#define log_debug2(...) ;
//#define log_debug2(...) log_debug(__VA_ARGS__)
+static int decimal_digits(unsigned n) {
+ return n > 1 ? ceil(log10(n)) : 1;
+}
+
struct ConstEvalAig
{
RTLIL::Module *module;
unsigned l1, l2, l3;
// Parse inputs
- int digits = ceil(log10(I));
+ int digits = decimal_digits(I);
for (unsigned i = 1; i <= I; ++i, ++line_count) {
if (!(f >> l1))
log_error("Line %u cannot be interpreted as an input!\n", line_count);
clk_wire->port_input = true;
clk_wire->port_output = false;
}
- digits = ceil(log10(L));
+ digits = decimal_digits(L);
for (unsigned i = 0; i < L; ++i, ++line_count) {
if (!(f >> l1 >> l2))
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
}
// Parse outputs
- digits = ceil(log10(O));
+ digits = decimal_digits(O);
for (unsigned i = 0; i < O; ++i, ++line_count) {
if (!(f >> l1))
log_error("Line %u cannot be interpreted as an output!\n", line_count);
std::string line;
// Parse inputs
- int digits = ceil(log10(I));
+ int digits = decimal_digits(I);
for (unsigned i = 1; i <= I; ++i) {
log_debug2("%d is an input\n", i);
RTLIL::Wire *wire = module->addWire(stringf("$i%0*d", digits, i));
clk_wire->port_input = true;
clk_wire->port_output = false;
}
- digits = ceil(log10(L));
+ digits = decimal_digits(L);
l1 = (I+1) * 2;
for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
if (!(f >> l2))
}
// Parse outputs
- digits = ceil(log10(O));
+ digits = decimal_digits(O);
for (unsigned i = 0; i < O; ++i, ++line_count) {
if (!(f >> l1))
log_error("Line %u cannot be interpreted as an output!\n", line_count);