arch, cpu: Add support for flattening misc register indexes.

With ARMv8 support the same misc register id  results in accessing different
registers depending on the current mode of the processor. This patch adds
the same orthogonality to the misc register file as the others (int, float, cc).
For all the othre ISAs this is currently a null-implementation.

Additionally, a system variable is added to all the ISA objects.

diff --git a/src/arch/alpha/AlphaISA.py b/src/arch/alpha/AlphaISA.py
index 64c9e4733dfffb8fc1fc905afe1354cf05bb1ed7..d853547043dbfff25e7a67ff93142d25b3907d26 100644 (file)
--- a/src/arch/alpha/AlphaISA.py
+++ b/src/arch/alpha/AlphaISA.py
@@ -35,9 +35,13 @@
 #
 # Authors: Andreas Sandberg
 
+from m5.params import *
+from m5.proxy import *
 from m5.SimObject import SimObject
 
 class AlphaISA(SimObject):
     type = 'AlphaISA'
     cxx_class = 'AlphaISA::ISA'
     cxx_header = "arch/alpha/isa.hh"
+
+    system = Param.System(Parent.any, "System this ISA object belongs to")

diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 9cfd840d9712dc511852082e3f5d6d361d8cfdcf..95dfdedd65416a9be72d4e659aad79cc43e88e89 100644 (file)
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -40,7 +40,7 @@ namespace AlphaISA
 {
 
 ISA::ISA(Params *p)
-    : SimObject(p)
+    : SimObject(p), system(p->system)
 {
     clear();
     initializeIprTable();

diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index d3049906634e3b3c724266e1123fcb3ea5d77eb7..35a26c108c42c3a88934412dcfc521773ef947ba 100644 (file)
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -39,6 +39,7 @@
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
 #include "sim/sim_object.hh"
+#include "sim/system.hh"
 
 struct AlphaISAParams;
 class BaseCPU;
@@ -55,6 +56,9 @@ namespace AlphaISA
         typedef AlphaISAParams Params;
 
       protected:
+        // Parent system
+        System *system;
+
         uint64_t fpcr;       // floating point condition codes
         uint64_t uniq;       // process-unique register
         bool lock_flag;      // lock flag for LL/SC
@@ -110,6 +114,12 @@ namespace AlphaISA
             return reg;
         }
 
+        int
+        flattenMiscIndex(int reg)
+        {
+            return reg;
+        }
+
         const Params *params() const;
 
         ISA(Params *p);

diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py
index bc969a9065751c0f30149550318f16deb5b22f10..22602ff0c869b88acf5f3435858f1b91d3de999b 100644 (file)
--- a/src/arch/mips/MipsISA.py
+++ b/src/arch/mips/MipsISA.py
@@ -37,11 +37,14 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
+from m5.proxy import *
 
 class MipsISA(SimObject):
     type = 'MipsISA'
     cxx_class = 'MipsISA::ISA'
     cxx_header = "arch/mips/isa.hh"
 
+    system = Param.System(Parent.any, "System this ISA object belongs to")
+
     num_threads = Param.UInt8(1, "Maximum number this ISA can handle")
     num_vpes = Param.UInt8(1, "Maximum number of vpes this ISA can handle")

diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index 891ed5e2f5cfad812b86469762f0b314a48093d1..164f10d5d03896312cee045ca5eee7dbba307cb2 100644 (file)
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -89,8 +89,7 @@ ISA::miscRegNames[NumMiscRegs] =
 };
 
 ISA::ISA(Params *p)
-    : SimObject(p),
-      numThreads(p->num_threads), numVpes(p->num_vpes)
+    : SimObject(p), numThreads(p->num_threads), numVpes(p->num_vpes)
 {
     miscRegFile.resize(NumMiscRegs);
     bankType.resize(NumMiscRegs);

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index c601cfc1eda74c442e963780acb5594316af777c..eddf75272915ed17919eb7f4afe2fa04e11bdcfc 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -184,6 +184,13 @@ namespace MipsISA
         {
             return reg;
         }
+
+        int
+        flattenMiscIndex(int reg)
+        {
+            return reg;
+        }
+
     };
 }
 

diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 7b59b2ad1179f6d297b87aaebd4aac3f00a8ddbb..028142b5077cff5ebac488ba34bee9767adca8a8 100644 (file)
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -105,6 +105,12 @@ class ISA : public SimObject
         return reg;
     }
 
+    int
+    flattenMiscIndex(int reg)
+    {
+        return reg;
+    }
+
     void startup(ThreadContext *tc) {}
 
     /// Explicitly import the otherwise hidden startup

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index e6f023bc0685c92c46dc8392d5d2c0e149eb6562..31cb09c7eb42be813a534fa5c8c9b2b5602f00b1 100644 (file)
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -177,7 +177,6 @@ class ISA : public SimObject
     using SimObject::startup;
 
   protected:
-
     bool isHyperPriv() { return hpstate.hpriv; }
     bool isPriv() { return hpstate.hpriv || pstate.priv; }
     bool isNonPriv() { return !isPriv(); }
@@ -213,6 +212,13 @@ class ISA : public SimObject
         return reg;
     }
 
+    int
+    flattenMiscIndex(int reg)
+    {
+        return reg;
+    }
+
+
     typedef SparcISAParams Params;
     const Params *params() const;
 

diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 5f36fd7adf87e9b437adc7f15f79ffd9183595ef..14c8e98c9ff8901c5d830039611f4e74d0ac3f05 100644 (file)
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -91,6 +91,12 @@ namespace X86ISA
             return reg;
         }
 
+        int
+        flattenMiscIndex(int reg)
+        {
+            return reg;
+        }
+
         void serialize(std::ostream &os);
         void unserialize(Checkpoint *cp, const std::string &section);
         void startup(ThreadContext *tc);

diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index c06e03fc6f26d04dcc60cdf521ead8976471697b..5c695c75044cd2d62b4eaa5cc564784ab6057988 100644 (file)
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -300,6 +300,7 @@ class CheckerThreadContext : public ThreadContext
     int flattenIntIndex(int reg) { return actualTC->flattenIntIndex(reg); }
     int flattenFloatIndex(int reg) { return actualTC->flattenFloatIndex(reg); }
     int flattenCCIndex(int reg) { return actualTC->flattenCCIndex(reg); }
+    int flattenMiscIndex(int reg) { return actualTC->flattenMiscIndex(reg); }
 
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }

diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 5e1c65f8fc7fd4b36baf2c7bfb9e6ae90036f3a2..b1a3610275681511b7293f1e4b324fed93834da3 100644 (file)
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -273,6 +273,9 @@ class InOrderThreadContext : public ThreadContext
     int flattenCCIndex(int reg)
     { return cpu->isa[thread->threadId()]->flattenCCIndex(reg); }
 
+    int flattenMiscIndex(int reg)
+    { return cpu->isa[thread->threadId()]->flattenMiscIndex(reg); }
+
     void activateContext(Cycles delay)
     { cpu->activateContext(thread->threadId(), delay); }
 

diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 88cf75f4f474bac081a7bc6d8e3d8dd08c793077..27f8e9561edd357025694bf99ebc94d3bce312fb 100755 (executable)
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -244,6 +244,7 @@ class O3ThreadContext : public ThreadContext
     virtual int flattenIntIndex(int reg);
     virtual int flattenFloatIndex(int reg);
     virtual int flattenCCIndex(int reg);
+    virtual int flattenMiscIndex(int reg);
 
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.

diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index c818260f4d2613f092e2706098cdbbd5a9ae30c2..43e9031359d2ac6daa4165654773b3cd099ce7fa 100755 (executable)
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -291,6 +291,13 @@ O3ThreadContext<Impl>::flattenCCIndex(int reg)
     return cpu->isa[thread->threadId()]->flattenCCIndex(reg);
 }
 
+template <class Impl>
+int
+O3ThreadContext<Impl>::flattenMiscIndex(int reg)
+{
+    return cpu->isa[thread->threadId()]->flattenMiscIndex(reg);
+}
+
 template <class Impl>
 void
 O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index fa0d20b0a2c6ac8891ea95e8f87648eddf6186b1..c5fae4e8efecd3d1678385b3c22b33a3dff1ec2f 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2011 ARM Limited
+ * Copyright (c) 2011-2012 ARM Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -415,6 +415,12 @@ class SimpleThread : public ThreadState
         return isa->flattenCCIndex(reg);
     }
 
+    int
+    flattenMiscIndex(int reg)
+    {
+        return isa->flattenMiscIndex(reg);
+    }
+
     unsigned readStCondFailures() { return storeCondFailures; }
 
     void setStCondFailures(unsigned sc_failures)

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index be18f680ff32ee718d48890ff537e1df90508c1e..efd3cc80092cef670824f657120a74d49d45a218 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -235,6 +235,7 @@ class ThreadContext
     virtual int flattenIntIndex(int reg) = 0;
     virtual int flattenFloatIndex(int reg) = 0;
     virtual int flattenCCIndex(int reg) = 0;
+    virtual int flattenMiscIndex(int reg) = 0;
 
     virtual uint64_t
     readRegOtherThread(int misc_reg, ThreadID tid)
@@ -451,6 +452,9 @@ class ProxyThreadContext : public ThreadContext
     int flattenCCIndex(int reg)
     { return actualTC->flattenCCIndex(reg); }
 
+    int flattenMiscIndex(int reg)
+    { return actualTC->flattenMiscIndex(reg); }
+
     unsigned readStCondFailures()
     { return actualTC->readStCondFailures(); }