update STATE format (bit error)

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index 1a2443a735b0c06c4dc39f0c1691bfb6801c2430..8d509ea858181d283be9115595805e7c2a0f6608 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -322,7 +322,7 @@ and seSTATE).
 
 The format of the STATE CSR is as follows:
 
-| (30..29 | (28..27) | (26..24) | (23..18) | (17..12) | (11..6) | (5...0) |
+| (29..28 | (27..26) | (25..24) | (23..18) | (17..12) | (11..6) | (5...0) |
 | ------- | -------- | -------- | -------- | -------- | ------- | ------- |
 | dsvoffs | ssvoffs  | subvl    | destoffs | srcoffs  | vl      | maxvl   |
 
@@ -2594,6 +2594,11 @@ Could the 8 bit Register VLIW format use regnum<<1 instead, only accessing regs
 
 --
 
+Expand the range of SUBVL and its associated svsrcoffs and svdestoffs by
+adding a 2nd STATE CSR (or extending STATE to 64 bits).  Future version?
+
+--
+
 TODO evaluate strncpy and strlen
 <https://groups.google.com/forum/m/#!msg/comp.arch/bGBeaNjAKvc/_vbqyxTUAQAJ>