# Condition Register SVP64 Operations
Condition Register Fields are only 4 bits wide: this presents some
-interesting conceptual challenges for SVP64, with respect to element
-width (which is clearly meaningless).
+interesting conceptual challenges for SVP64, oarticularly with respect to element
+width (which is clearly meaningless). Likewise, arithmetic saturation
+has no meaning. Consequently an alternative Mode Format is required.
-
-Note that these rules and
-the alternative mapping **only** applies to instructions that **only**
+This alternative mapping **only** applies to instructions that **only**
reference a CR Field or CR bit as the sole exclusive result. This section
**does not** apply to instructions which primarily produce arithmetic
results that also produce a CR Field (such as when Rc=1).
+Instructions that involve Rc=1 are definitively arithmetic in nature,
+where the corresponding Condition Register Field can be considered to
+be a "co-result". Thus, if the arithmetic result is Vectorised, so
+is the CR Field "co-result", which puts both firmly out of scope for
+this section.
SVP64 RM `MODE` (includes `ELWIDTH` bits) for CR-based operations:
| 4 | 5 | 19-20 | 21 | 22 23 | description |
| - | - | ----- | --- |---------|----------------- |
-|dz |VLi| 01 | inv | CR-bit | normal mode |
-|sz |VLi| 01 | inv | dz Rc1 | VLSET mode |
+|dz |VLi| 01 | inv | CR-bit | Ffirst 3-bit mode |
+|sz |VLi| 01 | inv | dz Rc1 | Ffirst 5-bit mode |
| / | / | 00 | 0 | dz sz | normal mode |
| / | / | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 |
| / | / | 00 | 1 | 1 CRM | parallel reduce mode (mapreduce), SUBVL=1 |
| / | / | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 |
| / | / | 10 | / | / / | RESERVED |
-|dz | / | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
-|sz | / | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
+|dz | / | 11 | inv | CR-bit | 3-bit pred-result CR sel |
+|sz | / | 11 | inv | dz RC1 | 5-bit pred-result z/nonz |
Fields:
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