global: switch to VexRiscv as the default CPU

VexRiscv can now replace LM32 for almost all usecases and we now have better
software support with RISC-V.

diff --git a/README b/README
index bee291c59004892ac608b75d1d16903afd614c6b..88357cb0fabef7b814b381cae2153664e23bae17 100644 (file)
--- a/README
+++ b/README
@@ -92,32 +92,21 @@ FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_10
 -----------------------------------------
 0. Install Python 3.5+ and FPGA vendor's development tools.
 
-1. Get litex_setup.py script and execute:
-   ./litex_setup.py init install
-   This will clone and install Migen, LiteX and LiteX's cores.
-   To update all repositories execute:
-   ./litex_setup.py update
-
-2. Compile and install binutils. Take the latest version from GNU.
-  mkdir build && cd build
-  ../configure --target=lm32-elf
-  make
-  make install
-
-3. (Optional, only if you want to use a lm32 CPU in you SoC)
-  Compile and install GCC. Take gcc-core and gcc-g++ from GNU
-  (version 4.5 or >=4.9).
-  rm -rf libstdc++-v3
-  mkdir build && cd build
-  ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
-    --disable-libssp
-  make
-  make install
-
-4. Build the target of your board...:
+1. Install Migen/LiteX and the LiteX's cores:
+  wget https://raw.githubusercontent.com/enjoy-digital/litex/master/litex_setup.py
+  ./litex_setup.py init install
+  Later, if you need to update all repositories:
+  ./litex_setup.py update
+
+2. Install a RISC-V toolchain:
+  wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz
+  tar -xvf riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6.tar.gz
+  export PATH=$PATH:$PWD/riscv64-unknown-elf-gcc-20171231-x86_64-linux-centos6/bin/
+
+3. Build the target of your board...:
   Go to boards/targets and execute the target you want to build
 
-5. ... and/or install Verilator and test LiteX on your computer:
+4. ... and/or install Verilator and test LiteX on your computer:
   Download and install Verilator: http://www.veripool.org/
   On Fedora:
       sudo dnf install libevent-devel json-c-devel
@@ -125,7 +114,7 @@ FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_10
       sudo apt install libevent-dev libjson-c-dev
   run: litex_sim
 
-6. Run a terminal program on the board's serial port at 115200 8-N-1.
+5. Run a terminal program on the board's serial port at 115200 8-N-1.
   You should get the BIOS prompt.
 
 [> Contact

diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py
index b8897d00b53fe8ce8abedbbdae90537f37aa0933..e0e10673dda69704c630db25439ddb9b4de216f0 100644 (file)
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@@ -141,7 +141,7 @@ class SoCCore(Module):
         "csr":      0x60000000,  # (default shadow @0xe0000000)
     }
     def __init__(self, platform, clk_freq,
-                cpu_type="lm32", cpu_reset_address=0x00000000, cpu_variant=None,
+                cpu_type="vexriscv", cpu_reset_address=0x00000000, cpu_variant=None,
                 integrated_rom_size=0, integrated_rom_init=[],
                 integrated_sram_size=4096,
                 integrated_main_ram_size=0, integrated_main_ram_init=[],

diff --git a/test/test_targets.py b/test/test_targets.py
index 06a6358223d56c3d9e9d1dc88e824a8817a5c894..73f0cc772900c1a57f5467f88b064a0d4f7c30d4 100644 (file)
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -18,53 +18,52 @@ def build_test(socs):
 
 
 class TestTargets(unittest.TestCase):
-    kwargs = {"cpu_type": "vexriscv"}
     # altera boards
     def test_de0nano(self):
         from litex.boards.targets.de0nano import BaseSoC
-        errors = build_test([BaseSoC(**self.kwargs)])
+        errors = build_test([BaseSoC()])
         self.assertEqual(errors, 0)
 
     # xilinx boards
     def test_minispartan6(self):
         from litex.boards.targets.minispartan6 import BaseSoC
-        errors = build_test([BaseSoC(**self.kwargs)])
+        errors = build_test([BaseSoC()])
         self.assertEqual(errors, 0)
 
     def test_arty(self):
         from litex.boards.targets.arty import BaseSoC, EthernetSoC
-        errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)])
+        errors = build_test([BaseSoC(), EthernetSoC()])
         self.assertEqual(errors, 0)
 
     def test_nexys4ddr(self):
         from litex.boards.targets.nexys4ddr import BaseSoC
-        errors = build_test([BaseSoC(**self.kwargs)])
+        errors = build_test([BaseSoC()])
         self.assertEqual(errors, 0)
 
     def test_nexys_video(self):
         from litex.boards.targets.nexys_video import BaseSoC, EthernetSoC
-        errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)])
+        errors = build_test([BaseSoC(), EthernetSoC()])
         self.assertEqual(errors, 0)
 
     def test_genesys2(self):
         from litex.boards.targets.genesys2 import BaseSoC, EthernetSoC
-        errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)])
+        errors = build_test([BaseSoC(), EthernetSoC()])
         self.assertEqual(errors, 0)
 
     def test_kc705(self):
         from litex.boards.targets.kc705 import BaseSoC, EthernetSoC
-        errors = build_test([BaseSoC(**self.kwargs), EthernetSoC(**self.kwargs)])
+        errors = build_test([BaseSoC(), EthernetSoC()])
         self.assertEqual(errors, 0)
 
     # lattice boards
     def test_versa_ecp5(self):
         from litex.boards.targets.versa_ecp5 import BaseSoC
-        errors = build_test([BaseSoC(**self.kwargs)])
+        errors = build_test([BaseSoC()])
         self.assertEqual(errors, 0)
 
     def test_versa_ulx3s(self):
         from litex.boards.targets.ulx3s import BaseSoC
-        errors = build_test([BaseSoC(**self.kwargs)])
+        errors = build_test([BaseSoC()])
         self.assertEqual(errors, 0)
 
     # build simple design for all platforms