main['GCC'] = CXX_version and CXX_version.find('g++') >= 0
main['SUNCC'] = CXX_V and CXX_V.find('Sun C++') >= 0
main['ICC'] = CXX_V and CXX_V.find('Intel') >= 0
-if main['GCC'] + main['SUNCC'] + main['ICC'] > 1:
+main['CLANG'] = CXX_V and CXX_V.find('clang') >= 0
+if main['GCC'] + main['SUNCC'] + main['ICC'] + main['CLANG'] > 1:
print 'Error: How can we have two at the same time?'
Exit(1)
main.Append(CCFLAGS=['-library=stlport4'])
main.Append(CCFLAGS=['-xar'])
#main.Append(CCFLAGS=['-instances=semiexplicit'])
+elif main['CLANG']:
+ clang_version_re = re.compile(".* version (\d+\.\d+)")
+ clang_version_match = clang_version_re.match(CXX_version)
+ if (clang_version_match):
+ clang_version = clang_version_match.groups()[0]
+ if compareVersions(clang_version, "2.9") < 0:
+ print 'Error: clang version 2.9 or newer required.'
+ print ' Installed version:', clang_version
+ Exit(1)
+ else:
+ print 'Error: Unable to determine clang version.'
+ Exit(1)
+
+ main.Append(CCFLAGS=['-pipe'])
+ main.Append(CCFLAGS=['-fno-strict-aliasing'])
+ main.Append(CCFLAGS=['-Wall', '-Wno-sign-compare', '-Wundef'])
+ main.Append(CCFLAGS=['-Wno-tautological-compare'])
+ main.Append(CCFLAGS=['-Wno-self-assign'])
else:
print 'Error: Don\'t know what compiler options to use for your compiler.'
print ' Please fix SConstruct and src/SConscript and try again.'
major,minor,dot = [int(x) for x in m4env['GCC_VERSION'].split('.')]
if major >= 4:
m4env.Append(CCFLAGS=['-Wno-pointer-sign'])
+if m4env['CLANG']:
+ m4env.Append(CCFLAGS=['-Wno-initializer-overrides', '-Wno-pointer-sign'])
m4env.Append(CCFLAGS=['-Wno-implicit'])
del m4env['CPPPATH']
swig_env.Append(CCFLAGS='-Wno-unused-label')
if compareVersions(env['GCC_VERSION'], '4.6.0') != -1:
swig_env.Append(CCFLAGS='-Wno-unused-but-set-variable')
+ if env['CLANG']:
+ swig_env.Append(CCFLAGS=['-Wno-unused-label'])
+
werror_env = new_env.Clone()
werror_env.Append(CCFLAGS='-Werror')
# Debug binary
ccflags = {}
-if env['GCC']:
+if env['GCC'] or env['CLANG']:
if sys.platform == 'sunos5':
ccflags['debug'] = '-gstabs+'
else:
: BaseTLB(p), size(p->size), nlu(0)
{
table = new TlbEntry[size];
- memset(table, 0, sizeof(TlbEntry[size]));
+ memset(table, 0, sizeof(TlbEntry) * size);
flushCache();
}
TLB::flushAll()
{
DPRINTF(TLB, "flushAll\n");
- memset(table, 0, sizeof(TlbEntry[size]));
+ memset(table, 0, sizeof(TlbEntry) * size);
flushCache();
lookupTable.clear();
nlu = 0;
namespace AlphaISA {
-class TlbEntry;
+struct TlbEntry;
class TLB : public BaseTLB
{
#include "arch/arm/utility.hh"
#include "base/trace.hh"
#include "cpu/static_inst.hh"
+#include "sim/byteswap.hh"
namespace ArmISA
{
VfpRoundZero = 3
};
+static inline float bitsToFp(uint64_t, float);
+static inline uint32_t fpToBits(float);
+
template <class fpType>
static inline bool
flushToZero(fpType &op)
// Basic instruction class constructor template.
def template BasicConstructor {{
- inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
+ %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s)
{
%(constructor)s;
if (!(condCode == COND_AL || condCode == COND_UC)) {
}
break;
case 11:
- if (opc1 >= 0 && opc1 <=7) {
+ if (opc1 <=7) {
switch (crm) {
case 0:
case 1:
memset(&mem, 0, sizeof(mem));
Fault fault = readMemTiming(xc, traceData, addr, mem, flags);
if (fault == NoFault) {
- mem = gtoh(mem);
+ mem = TheISA::gtoh(mem);
if (traceData)
traceData->setData(mem);
}
{
Fault fault = writeMemTiming(xc, traceData, mem, addr, flags, res);
if (fault == NoFault && res != NULL) {
- *res = gtoh((MemT)*res);
+ *res = TheISA::gtoh((MemT)*res);
}
return fault;
}
template <> FaultVals MipsFault<TlbRefillFault>::vals =
{ "TLB Refill Exception", 0x180, ExcCodeDummy };
-template <> FaultVals MipsFault<TlbModifiedFault>::vals =
+template <> MipsFaultBase::FaultVals MipsFault<TlbModifiedFault>::vals =
{ "TLB Modified Exception", 0x180, ExcCodeMod };
void
TlbFault<TlbModifiedFault>(asid, vaddr, vpn, false)
{}
- ExcCode code() const { return vals.code; }
+ ExcCode code() const { return MipsFault<TlbModifiedFault>::code(); }
};
} // namespace MipsISA
class Port;
-class X86ACPIRSDPParams;
+struct X86ACPIRSDPParams;
-class X86ACPISysDescTableParams;
-class X86ACPIRSDTParams;
-class X86ACPIXSDTParams;
+struct X86ACPISysDescTableParams;
+struct X86ACPIRSDTParams;
+struct X86ACPIXSDTParams;
namespace X86ISA
{
uint8_t
writeOutField(PortProxy* proxy, Addr addr, T val)
{
- T guestVal = X86ISA::htog(val);
+ uint64_t guestVal = X86ISA::htog(val);
proxy->writeBlob(addr, (uint8_t *)(&guestVal), sizeof(T));
uint8_t checkSum = 0;
class PortProxy;
// Config entry types
-class X86IntelMPBaseConfigEntryParams;
-class X86IntelMPExtConfigEntryParams;
+struct X86IntelMPBaseConfigEntryParams;
+struct X86IntelMPExtConfigEntryParams;
// General table structures
-class X86IntelMPConfigTableParams;
-class X86IntelMPFloatingPointerParams;
+struct X86IntelMPConfigTableParams;
+struct X86IntelMPFloatingPointerParams;
// Base entry types
-class X86IntelMPBusParams;
-class X86IntelMPIOAPICParams;
-class X86IntelMPIOIntAssignmentParams;
-class X86IntelMPLocalIntAssignmentParams;
-class X86IntelMPProcessorParams;
+struct X86IntelMPBusParams;
+struct X86IntelMPIOAPICParams;
+struct X86IntelMPIOIntAssignmentParams;
+struct X86IntelMPLocalIntAssignmentParams;
+struct X86IntelMPProcessorParams;
// Extended entry types
-class X86IntelMPAddrSpaceMappingParams;
-class X86IntelMPBusHierarchyParams;
-class X86IntelMPCompatAddrSpaceModParams;
+struct X86IntelMPAddrSpaceMappingParams;
+struct X86IntelMPBusHierarchyParams;
+struct X86IntelMPCompatAddrSpaceModParams;
namespace X86ISA
{
#include "sim/sim_object.hh"
class PortProxy;
-class X86SMBiosBiosInformationParams;
-class X86SMBiosSMBiosStructureParams;
-class X86SMBiosSMBiosTableParams;
+struct X86SMBiosBiosInformationParams;
+struct X86SMBiosSMBiosStructureParams;
+struct X86SMBiosSMBiosTableParams;
namespace X86ISA
{
#if USE_FAST_ALLOC
-#ifdef __GNUC__
-#pragma implementation
-#endif
-
void *FastAlloc::freeLists[Num_Buckets];
#if FAST_ALLOC_STATS
{
std::pair<iterator,iterator> p;
p = find(r);
- if (p.first->first.start == r.start && p.first->first.end == r.end ||
+ if ((p.first->first.start == r.start && p.first->first.end == r.end) ||
p.first == tree.end())
return tree.insert(std::make_pair<Range<T>,V>(r, d));
else
public:
HardBreakpoint(BaseRemoteGDB *_gdb, Addr addr);
- std::string name() { return gdb->name() + ".hwbkpt"; }
+ const std::string name() const { return gdb->name() + ".hwbkpt"; }
virtual void process(ThreadContext *tc);
};
// Treat all objects in an stl container as pointers to heap objects,
// calling delete on each one and zeroing the pointers along the way
-template <typename T, template <typename T, typename A> class C, typename A>
+template <template <typename T, typename A> class C, typename T, typename A>
void
deletePointers(C<T,A> &container)
{
// Write out all elements in an stl container as a space separated
// list enclosed in square brackets
-template <typename T, template <typename T, typename A> class C, typename A>
+template <template <typename T, typename A> class C, typename T, typename A>
std::ostream &
operator<<(std::ostream& out, const C<T,A> &vec)
{
}
void
-BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
+BaseCPU::takeOverFrom(BaseCPU *oldCPU)
{
+ Port *ic = getPort("icache_port");
+ Port *dc = getPort("dcache_port");
assert(threadContexts.size() == oldCPU->threadContexts.size());
_cpuId = oldCPU->cpuId();
#include "arch/interrupts.hh"
#endif
-class BaseCPUParams;
+struct BaseCPUParams;
class BranchPred;
class CheckerCPU;
class ThreadContext;
/// Notify the CPU that the indicated context is now active. The
/// delay parameter indicates the number of ticks to wait before
/// executing (typically 0 or 1).
- virtual void activateContext(int thread_num, int delay) {}
+ virtual void activateContext(ThreadID thread_num, int delay) {}
/// Notify the CPU that the indicated context is now suspended.
- virtual void suspendContext(int thread_num) {}
+ virtual void suspendContext(ThreadID thread_num) {}
/// Notify the CPU that the indicated context is now deallocated.
- virtual void deallocateContext(int thread_num) {}
+ virtual void deallocateContext(ThreadID thread_num) {}
/// Notify the CPU that the indicated context is now halted.
- virtual void haltContext(int thread_num) {}
+ virtual void haltContext(ThreadID thread_num) {}
/// Given a Thread Context pointer return the thread num
int findContext(ThreadContext *tc);
/// Take over execution from the given CPU. Used for warm-up and
/// sampling.
- virtual void takeOverFrom(BaseCPU *, Port *ic, Port *dc);
+ virtual void takeOverFrom(BaseCPU *);
/**
* Number of threads we're actually simulating (<= SMT_MAX_THREADS).
//
//
-struct OpDesc : public SimObject
+class OpDesc : public SimObject
{
+ public:
OpClass opClass;
unsigned opLat;
unsigned issueLat;
issueLat(p->issueLat) {};
};
-struct FUDesc : public SimObject
+class FUDesc : public SimObject
{
+ public:
std::vector<OpDesc *> opDescList;
unsigned number;
const char *
-InOrderCPU::TickEvent::description()
+InOrderCPU::TickEvent::description() const
{
return "InOrderCPU tick event";
}
const char *
-InOrderCPU::CPUEvent::description()
+InOrderCPU::CPUEvent::description() const
{
return "InOrderCPU event";
}
}
void
-InOrderCPU::haltContext(ThreadID tid, int delay)
+InOrderCPU::haltContext(ThreadID tid)
{
DPRINTF(InOrderCPU, "[tid:%i]: Calling Halt Context...\n", tid);
- scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid], delay);
+ scheduleCpuEvent(HaltThread, NoFault, tid, dummyInst[tid]);
activityRec.activity();
}
}
void
-InOrderCPU::suspendContext(ThreadID tid, int delay)
+InOrderCPU::suspendContext(ThreadID tid)
{
- scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid], delay);
+ scheduleCpuEvent(SuspendThread, NoFault, tid, dummyInst[tid]);
}
void
void process();
/** Returns the description of the tick event. */
- const char *description();
+ const char *description() const;
};
/** The tick event used for scheduling CPU ticks. */
void process();
/** Returns the description of the CPU event. */
- const char *description();
+ const char *description() const;
/** Schedule Event */
void scheduleEvent(int delay);
void deactivateThread(ThreadID tid);
/** Schedule a thread suspension on the CPU */
- void suspendContext(ThreadID tid, int delay = 0);
+ void suspendContext(ThreadID tid);
/** Suspend Thread, Remove from Active Threads List, Add to Suspend List */
void suspendThread(ThreadID tid);
/** Schedule a thread halt on the CPU */
- void haltContext(ThreadID tid, int delay = 0);
+ void haltContext(ThreadID tid);
/** Halt Thread, Remove from Active Thread List, Place Thread on Halted
* Threads List
}
const char *
-ResourceEvent::description()
+ResourceEvent::description() const
{
string desc = resource->name() + "-event:slot[" + to_string(slotIdx)
+ "]";
typedef ResourceRequest ResReq;
typedef ResourceRequest* ResReqPtr;
+class CacheRequest;
+typedef CacheRequest* CacheReqPtr;
+
class Resource {
public:
typedef ThePipeline::DynInstPtr DynInstPtr;
* if instruction is actually in resource before
* trying to do access.Needs to be defined for derived units.
*/
- virtual Fault doCacheAccess(DynInstPtr inst, uint64_t *res=NULL)
- { panic("doCacheAccess undefined for %s", name()); return NoFault; }
+ virtual void doCacheAccess(DynInstPtr inst, uint64_t *write_result = NULL,
+ CacheReqPtr split_req = NULL)
+ { panic("doCacheAccess undefined for %s", name()); }
/** Setup Squash to be sent out to pipeline and resource pool */
void setupSquash(DynInstPtr inst, int stage_num, ThreadID tid);
virtual void process();
/** Returns the description of the resource event. */
- const char *description();
+ const char *description() const;
/** Set slot idx for event */
void setSlot(int slot) { slotIdx = slot; }
int reqID;
- virtual void setRequest(DynInstPtr _inst, int stage_num,
+ void setRequest(DynInstPtr _inst, int stage_num,
int res_idx, int slot_num, unsigned _cmd);
virtual void clearRequest();
const char *
-ResourcePool::ResPoolEvent::description()
+ResourcePool::ResPoolEvent::description() const
{
return "Resource Pool event";
}
void process();
/** Returns the description of the resource event. */
- const char *description();
+ const char *description() const;
/** Schedule Event */
void scheduleEvent(int delay);
#include "params/InOrderCPU.hh"
#include "sim/sim_object.hh"
-class CacheRequest;
-typedef CacheRequest* CacheReqPtr;
-
class CacheReqPacket;
typedef CacheReqPacket* CacheReqPktPtr;
return;
thread->setStatus(ThreadContext::Suspended);
- cpu->suspendContext(thread->threadId(), delay);
+ cpu->suspendContext(thread->threadId());
}
void
return;
thread->setStatus(ThreadContext::Halted);
- cpu->haltContext(thread->threadId(), delay);
+ cpu->haltContext(thread->threadId());
}
{
size_t soFar = 0;
while (soFar < size) {
- size_t res = ::read(fd, (uint8_t *)ptr + soFar, size - soFar);
+ ssize_t res = ::read(fd, (uint8_t *)ptr + soFar, size - soFar);
if (res < 0)
panic("Read call failed! %s\n", strerror(errno));
else
#include "cpu/pred/tournament.hh"
#include "cpu/inst_seq.hh"
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
/**
* Basically a wrapper class to hold both the branch predictor
#include "cpu/inst_seq.hh"
#include "cpu/timebuf.hh"
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
template <class>
-class O3ThreadState;
+struct O3ThreadState;
/**
* DefaultCommit handles single threaded and SMT commit. Its width is
#include "debug/Activity.hh"
#endif
-class BaseCPUParams;
+struct BaseCPUParams;
using namespace TheISA;
using namespace std;
template <class Impl>
bool
-FullO3CPU<Impl>::deallocateContext(ThreadID tid, bool remove, int delay)
+FullO3CPU<Impl>::scheduleDeallocateContext(ThreadID tid, bool remove,
+ int delay)
{
// Schedule removal of thread data from CPU
if (delay){
FullO3CPU<Impl>::suspendContext(ThreadID tid)
{
DPRINTF(O3CPU,"[tid: %i]: Suspending Thread Context.\n", tid);
- bool deallocated = deallocateContext(tid, false, 1);
+ bool deallocated = scheduleDeallocateContext(tid, false, 1);
// If this was the last thread then unschedule the tick event.
if ((activeThreads.size() == 1 && !deallocated) ||
activeThreads.size() == 0)
{
//For now, this is the same as deallocate
DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
- deallocateContext(tid, true, 1);
+ scheduleDeallocateContext(tid, true, 1);
}
template <class Impl>
activityRec.reset();
- BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
+ BaseCPU::takeOverFrom(oldCPU);
fetch.takeOverFrom();
decode.takeOverFrom();
class MemObject;
class Process;
-class BaseCPUParams;
+struct BaseCPUParams;
class BaseO3CPU : public BaseCPU
{
/** Remove Thread from Active Threads List &&
* Possibly Remove Thread Context from CPU.
*/
- bool deallocateContext(ThreadID tid, bool remove, int delay = 1);
+ bool scheduleDeallocateContext(ThreadID tid, bool remove, int delay = 1);
/** Remove Thread from Active Threads List &&
* Remove Thread Context from CPU.
#include "base/statistics.hh"
#include "cpu/timebuf.hh"
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
/**
* DefaultDecode class handles both single threaded and SMT
#include "debug/Decode.hh"
#include "params/DerivO3CPU.hh"
-using namespace std;
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::list;
template<class Impl>
DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
#include "mem/port.hh"
#include "sim/eventq.hh"
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
/**
* DefaultFetch class handles both single threaded and SMT fetch. Its
}
void
-FUPool::takeOverFrom()
+FUPool::takeOver()
{
for (int i = 0; i < numFU; i++) {
unitBusy[i] = false;
#include <vector>
#include "cpu/op_class.hh"
-#include "cpu/sched_list.hh"
#include "params/FUPool.hh"
#include "sim/sim_object.hh"
void switchOut();
/** Takes over from another CPU's thread. */
- void takeOverFrom();
+ void takeOver();
};
#endif // __CPU_O3_FU_POOL_HH__
#include "cpu/timebuf.hh"
#include "debug/IEW.hh"
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
class FUPool;
/**
typedef typename CPUPol::RenameStruct RenameStruct;
typedef typename CPUPol::IssueStruct IssueStruct;
- friend class Impl::O3CPU;
- friend class CPUPol::IQ;
-
public:
/** Overall IEW stage status. Used to determine if the CPU can
* deschedule itself due to a lack of activity.
instQueue.takeOverFrom();
ldstQueue.takeOverFrom();
- fuPool->takeOverFrom();
+ fuPool->takeOver();
initStage();
cpu->activityThisCycle();
#include "cpu/timebuf.hh"
#include "sim/eventq.hh"
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
class FUPool;
class MemInterface;
// Typedef of iterator through the list of instructions.
typedef typename std::list<DynInstPtr>::iterator ListIt;
- friend class Impl::O3CPU;
-
/** FU completion event class. */
class FUCompletion : public Event {
private:
#include "params/DerivO3CPU.hh"
#include "sim/core.hh"
-using namespace std;
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::list;
template <class Impl>
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
#include "mem/port.hh"
#include "sim/sim_object.hh"
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
template <class Impl>
class LSQ {
#include "mem/packet.hh"
#include "mem/port.hh"
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
/**
* Class that implements the actual LQ and SQ for each specific
#include "cpu/o3/mem_dep_unit_impl.hh"
#include "cpu/o3/store_set.hh"
-// Force instantation of memory dependency unit using store sets and
-// O3CPUImpl.
-template class MemDepUnit<StoreSet, O3CPUImpl>;
-
#ifdef DEBUG
template <>
int
int
MemDepUnit<StoreSet, O3CPUImpl>::MemDepEntry::memdep_erase = 0;
#endif
+
+// Force instantation of memory dependency unit using store sets and
+// O3CPUImpl.
+template class MemDepUnit<StoreSet, O3CPUImpl>;
}
};
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
template <class Impl>
class InstructionQueue;
#include "config/the_isa.hh"
#include "cpu/timebuf.hh"
-class DerivO3CPUParams;
+struct DerivO3CPUParams;
/**
* DefaultRename handles both single threaded and SMT rename. Its
* @param initial_val Starting value for each counter.
*/
SatCounter(unsigned bits, uint8_t initial_val)
- : initialVal(initialVal), maxVal((1 << bits) - 1), counter(initial_val)
+ : initialVal(initial_val), maxVal((1 << bits) - 1),
+ counter(initial_val)
{
// Check to make sure initial value doesn't exceed the max
// counter value.
class ThreadContext;
/** Event for timing out quiesce instruction */
-struct EndQuiesceEvent : public Event
+class EndQuiesceEvent : public Event
{
+ public:
/** A pointer to the thread context that is quiesced */
ThreadContext *tc;
+++ /dev/null
-/*
- * Copyright (c) 2002-2005 The Regents of The University of Michigan
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Steve Raasch
- */
-
-#ifndef SCHED_LIST_HH
-#define SCHED_LIST_HH
-
-#include <list>
-
-#include "base/intmath.hh"
-#include "base/misc.hh"
-
-// Any types you use this class for must be covered here...
-namespace {
- void ClearEntry(int &i) { i = 0; };
- void ClearEntry(unsigned &i) { i = 0; };
- void ClearEntry(double &i) { i = 0; };
- template <class T> void ClearEntry(std::list<T> &l) { l.clear(); };
-};
-
-
-//
-// this is a special list type that allows the user to insert elements at a
-// specified positive offset from the "current" element, but only allow them
-// be extracted from the "current" element
-//
-
-
-template <class T>
-class SchedList
-{
- T *data_array;
- unsigned position;
- unsigned size;
- unsigned mask;
-
- public:
- SchedList(unsigned size);
- SchedList(void);
-
- void init(unsigned size);
-
- T &operator[](unsigned offset);
-
- void advance(void);
-
- void clear(void);
-};
-
-
-
-//
-// Constructor
-//
-template<class T>
-SchedList<T>::SchedList(unsigned _size)
-{
- size = _size;
-
- // size must be a power of two
- if (!isPowerOf2(size)) {
- panic("SchedList: size must be a power of two");
- }
-
- if (size < 2) {
- panic("SchedList: you don't want a list that small");
- }
-
- // calculate the bit mask for the modulo operation
- mask = size - 1;
-
- data_array = new T[size];
-
- if (!data_array) {
- panic("SchedList: could not allocate memory");
- }
-
- clear();
-}
-
-template<class T>
-SchedList<T>::SchedList(void)
-{
- data_array = 0;
- size = 0;
-}
-
-
-template<class T> void
-SchedList<T>::init(unsigned _size)
-{
- size = _size;
-
- if (!data_array) {
- // size must be a power of two
- if (size & (size-1)) {
- panic("SchedList: size must be a power of two");
- }
-
- if (size < 2) {
- panic("SchedList: you don't want a list that small");
- }
-
- // calculate the bit mask for the modulo operation
- mask = size - 1;
-
- data_array = new T[size];
-
- if (!data_array) {
- panic("SchedList: could not allocate memory");
- }
-
- clear();
- }
-}
-
-
-template<class T> void
-SchedList<T>::advance(void)
-{
- ClearEntry(data_array[position]);
-
- // position = (++position % size);
- position = ++position & mask;
-}
-
-
-template<class T> void
-SchedList<T>::clear(void)
-{
- for (unsigned i=0; i<size; ++i) {
- ClearEntry(data_array[i]);
- }
-
- position = 0;
-}
-
-
-template<class T> T&
-SchedList<T>::operator[](unsigned offset)
-{
- if (offset >= size) {
- panic("SchedList: can't access element beyond current pointer");
- }
-
- // unsigned p = (position + offset) % size;
- unsigned p = (position + offset) & mask;
-
- return data_array[p];
-}
-
-
-
-#endif
void
AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
{
- BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
+ BaseCPU::takeOverFrom(oldCPU);
assert(!tickEvent.scheduled());
void
-AtomicSimpleCPU::activateContext(int thread_num, int delay)
+AtomicSimpleCPU::activateContext(ThreadID thread_num, int delay)
{
DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
void
-AtomicSimpleCPU::suspendContext(int thread_num)
+AtomicSimpleCPU::suspendContext(ThreadID thread_num)
{
DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
- virtual void activateContext(int thread_num, int delay);
- virtual void suspendContext(int thread_num);
+ virtual void activateContext(ThreadID thread_num, int delay);
+ virtual void suspendContext(ThreadID thread_num);
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
}
void
-BaseSimpleCPU::deallocateContext(int thread_num)
+BaseSimpleCPU::deallocateContext(ThreadID thread_num)
{
// for now, these are equivalent
suspendContext(thread_num);
void
-BaseSimpleCPU::haltContext(int thread_num)
+BaseSimpleCPU::haltContext(ThreadID thread_num)
{
// for now, these are equivalent
suspendContext(thread_num);
class InstRecord;
}
-class BaseSimpleCPUParams;
+struct BaseSimpleCPUParams;
class BaseSimpleCPU : public BaseCPU
void postExecute();
void advancePC(Fault fault);
- virtual void deallocateContext(int thread_num);
- virtual void haltContext(int thread_num);
+ virtual void deallocateContext(ThreadID thread_num);
+ virtual void haltContext(ThreadID thread_num);
// statistics
virtual void regStats();
void
TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
{
- BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
+ BaseCPU::takeOverFrom(oldCPU);
// if any of this CPU's ThreadContexts are active, mark the CPU as
// running and schedule its tick event.
void
-TimingSimpleCPU::activateContext(int thread_num, int delay)
+TimingSimpleCPU::activateContext(ThreadID thread_num, int delay)
{
DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
void
-TimingSimpleCPU::suspendContext(int thread_num)
+TimingSimpleCPU::suspendContext(ThreadID thread_num)
{
DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
- virtual void activateContext(int thread_num, int delay);
- virtual void suspendContext(int thread_num);
+ virtual void activateContext(ThreadID thread_num, int delay);
+ virtual void suspendContext(ThreadID thread_num);
Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
class DynInst;
class Packet;
-class O3CPUImpl;
+struct O3CPUImpl;
template <class Impl> class BaseO3DynInst;
typedef BaseO3DynInst<O3CPUImpl> O3DynInst;
template <class Impl> class OzoneDynInst;
#include "params/TsunamiCChip.hh"
#include "sim/system.hh"
-using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
#include "mem/port.hh"
#include "sim/system.hh"
-using namespace std;
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::string;
+using std::ostream;
+
//Should this be AlphaISA?
using namespace TheISA;
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::vector;
+
using namespace AmbaDev;
// initialize clcd registers
pic = simout.create(csprintf("%s.framebuffer.bmp", sys->name()), true);
- dmaBuffer = new uint8_t[LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t)];
+ const int buffer_size = LcdMaxWidth * LcdMaxHeight * sizeof(uint32_t);
+ dmaBuffer = new uint8_t[buffer_size];
memset(lcdPalette, 0, sizeof(lcdPalette));
memset(cursorImage, 0, sizeof(cursorImage));
- memset(dmaBuffer, 0, sizeof(dmaBuffer));
+ memset(dmaBuffer, 0, buffer_size);
if (vncserver)
vncserver->setFramebufferAddr(dmaBuffer);
#include "params/Pl111.hh"
#include "sim/serialize.hh"
-using namespace std;
-
class Gic;
class VncServer;
class Bitmap;
EventWrapper<Pl111, &Pl111::fillFifo> fillFifoEvent;
/** DMA done event */
- vector<EventWrapper<Pl111, &Pl111::dmaDone> > dmaDoneEvent;
+
std::vector<EventWrapper<Pl111, &Pl111::dmaDone> > dmaDoneEvent;
/** Wrapper to create an event out of the interrupt */
EventWrapper<Pl111, &Pl111::generateInterrupt> intEvent;
#include "sim/system.hh"
using namespace CopyEngineReg;
-using namespace std;
CopyEngine::CopyEngine(const Params *p)
: PciDev(p)
: DiskImage(p), filename(p->image_file), child(p->child), table(NULL)
{
if (filename.empty()) {
- init(p->table_size);
+ initSectorTable(p->table_size);
} else {
if (!open(filename)) {
if (p->read_only)
fatal("could not open read-only file");
- init(p->table_size);
+ initSectorTable(p->table_size);
}
if (!p->read_only)
}
void
-CowDiskImage::init(int hash_size)
+CowDiskImage::initSectorTable(int hash_size)
{
table = new SectorTable(hash_size);
CowDiskImage(const Params *p);
~CowDiskImage();
- void init(int hash_size);
+ void initSectorTable(int hash_size);
bool open(const std::string &file);
void save();
void save(const std::string &file);
#include <string>
-#include "base/trace.hh"
#include "cpu/intr_control.hh"
#include "debug/IdeCtrl.hh"
#include "dev/ide_ctrl.hh"
#include "params/IdeController.hh"
#include "sim/byteswap.hh"
-using namespace std;
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::string;
// Bus master IDE registers
enum BMIRegOffset {
#include "params/NSGigE.hh"
#include "sim/system.hh"
+// clang complains about std::set being overloaded with Packet::set if
+// we open up the entire namespace std
+using std::min;
+using std::ostream;
+using std::string;
+
const char *NsRxStateStrings[] =
{
"rxIdle",
"dmaWriteWaiting"
};
-using namespace std;
using namespace Net;
using namespace TheISA;
// all these #if 0's are because i don't THINK the kernel needs to
// have these implemented. if there is a problem relating to one of
// these, you may need to add functionality in.
+
+// grouped together and #if 0'ed to avoid empty if body and make clang happy
+#if 0
if (reg & CFGR_TBI_EN) ;
if (reg & CFGR_MODE_1000) ;
- if (reg & CFGR_AUTO_1000)
- panic("CFGR_AUTO_1000 not implemented!\n");
-
if (reg & CFGR_PINT_DUPSTS ||
reg & CFGR_PINT_LNKSTS ||
reg & CFGR_PINT_SPDSTS)
if (reg & CFGR_MRM_DIS) ;
if (reg & CFGR_MWI_DIS) ;
- if (reg & CFGR_T64ADDR) ;
- // panic("CFGR_T64ADDR is read only register!\n");
-
- if (reg & CFGR_PCI64_DET)
- panic("CFGR_PCI64_DET is read only register!\n");
-
if (reg & CFGR_DATA64_EN) ;
if (reg & CFGR_M64ADDR) ;
if (reg & CFGR_PHY_RST) ;
if (reg & CFGR_PHY_DIS) ;
- if (reg & CFGR_EXTSTS_EN)
- extstsEnable = true;
- else
- extstsEnable = false;
-
if (reg & CFGR_REQALG) ;
if (reg & CFGR_SB) ;
if (reg & CFGR_POW) ;
if (reg & CFGR_BROM_DIS) ;
if (reg & CFGR_EXT_125) ;
if (reg & CFGR_BEM) ;
+
+ if (reg & CFGR_T64ADDR) ;
+ // panic("CFGR_T64ADDR is read only register!\n");
+#endif
+ if (reg & CFGR_AUTO_1000)
+ panic("CFGR_AUTO_1000 not implemented!\n");
+
+ if (reg & CFGR_PCI64_DET)
+ panic("CFGR_PCI64_DET is read only register!\n");
+
+ if (reg & CFGR_EXTSTS_EN)
+ extstsEnable = true;
+ else
+ extstsEnable = false;
break;
case MEAR:
eepromClk = reg & MEAR_EECLK;
// since phy is completely faked, MEAR_MD* don't matter
+
+// grouped together and #if 0'ed to avoid empty if body and make clang happy
+#if 0
if (reg & MEAR_MDIO) ;
if (reg & MEAR_MDDIR) ;
if (reg & MEAR_MDC) ;
+#endif
break;
case PTSCR:
#include "params/PciConfigAll.hh"
#include "sim/system.hh"
-using namespace std;
-
PciConfigAll::PciConfigAll(const Params *p)
: PioDevice(p)
{
#include "sim/byteswap.hh"
#include "sim/core.hh"
-using namespace std;
-
PciDev::PciConfigPort::PciConfigPort(PciDev *dev, int busid, int devid,
int funcid, Platform *p)
}
void
-PciDev::serialize(ostream &os)
+PciDev::serialize(std::ostream &os)
{
SERIALIZE_ARRAY(BARSize, sizeof(BARSize) / sizeof(BARSize[0]));
SERIALIZE_ARRAY(BARAddrs, sizeof(BARAddrs) / sizeof(BARAddrs[0]));
MSHRQueue_WriteBuffer
};
+ public:
/**
* Reasons for caches to be blocked.
*/
NUM_BLOCKED_CAUSES
};
- public:
/**
* Reasons for cache to request a bus.
*/
NUM_REQUEST_CAUSES
};
- private:
+ protected:
class CachePort : public SimpleTimingPort
{
}
};
- public: //Made public so coherence can get at it.
CachePort *cpuSidePort;
CachePort *memSidePort;
.flags(pdf)
;
- repl->regStats(name);
+ repl->regStatsWithSuffix(name);
if (PROFILE_IIC)
setAccess
}
void
-GenRepl::regStats(const string name)
+GenRepl::regStatsWithSuffix(const string name)
{
using namespace Stats;
* Register statistics.
* @param name The name to prepend to statistic descriptions.
*/
- virtual void regStats(const std::string name);
+ virtual void regStatsWithSuffix(const std::string name);
/**
* Update the tag pointer to when the tag moves.
* Register statistics.
* @param name The name to prepend to statistic descriptions.
*/
- virtual void regStats(const std::string name) = 0;
+ virtual void regStatsWithSuffix(const std::string name) = 0;
/**
* Update the tag pointer to when the tag moves.
#include "mem/request.hh"
#include "sim/core.hh"
-struct Packet;
+class Packet;
typedef Packet *PacketPtr;
typedef uint8_t* PacketDataPtr;
typedef std::list<PacketPtr> PacketList;
for (vector<Router_d*>::const_iterator i= m_router_ptr_vector.begin();
i != m_router_ptr_vector.end(); ++i) {
Router_d* router = safe_cast<Router_d*>(*i);
- int router_id=fault_model->declare_router(router->get_num_inports(),
- router->get_num_outports(),
- router->get_vc_per_vnet(),
- getBuffersPerDataVC(),
- getBuffersPerCtrlVC());
+ int router_id M5_VAR_USED =
+ fault_model->declare_router(router->get_num_inports(),
+ router->get_num_outports(),
+ router->get_vc_per_vnet(),
+ getBuffersPerDataVC(),
+ getBuffersPerCtrlVC());
assert(router_id == router->get_id());
router->printAggregateFaultProbability(cout);
router->printFaultVector(cout);
class DataBlock;
class CacheMemory;
-class RubySequencerParams;
+struct RubySequencerParams;
struct SequencerRequest
{
#include <string>
-struct EventQueue;
+class EventQueue;
''')
for param in params:
param.cxx_predecls(code)
void setOutputDir(const std::string &dir);
-struct Callback;
+class Callback;
void registerExitCallback(Callback *callback);
void doExitCleanup();
a_val = TheISA::htog(val);
}
-template class AuxVector<uint32_t>;
-template class AuxVector<uint64_t>;
+template struct AuxVector<uint32_t>;
+template struct AuxVector<uint64_t>;
Process::Process(ProcessParams * params)
: SimObject(params), system(params->system),
#include "sim/syscallreturn.hh"
class PageTable;
-class ProcessParams;
-class LiveProcessParams;
+struct ProcessParams;
+struct LiveProcessParams;
class SyscallDesc;
class System;
class ThreadContext;
{
AddrType data_ptr_swap;
for (std::vector<std::string>::size_type i = 0; i < strings.size(); ++i) {
- data_ptr_swap = htog(data_ptr);
+ data_ptr_swap = TheISA::htog(data_ptr);
memProxy->writeBlob(array_ptr, (uint8_t*)&data_ptr_swap,
sizeof(AddrType));
memProxy->writeString(data_ptr, strings[i].c_str());
public:
const string name() const;
void serialize(ostream &os);
- void unserialize(Checkpoint *cp);
+ void unserialize(Checkpoint *cp, const std::string §ion);
};
/// The one and only instance of the Globals class.
}
void
-Globals::unserialize(Checkpoint *cp)
+Globals::unserialize(Checkpoint *cp, const std::string §ion)
{
- const string §ion = name();
Tick tick;
paramIn(cp, section, "curTick", tick);
curTick(tick);
void
Serializable::unserializeGlobals(Checkpoint *cp)
{
- globals.unserialize(cp);
+ globals.unserialize(cp, globals.name());
}
void
}
void
-SimObject::setMemoryMode(State new_mode)
+SimObject::setMemoryMode(Enums::MemoryMode new_mode)
{
panic("setMemoryMode() should only be called on systems");
}
#include <string>
#include <vector>
+#include "enums/MemoryMode.hh"
#include "params/SimObject.hh"
#include "sim/eventq.hh"
#include "sim/serialize.hh"
// before the object will be done draining. Normally this should be 1
virtual unsigned int drain(Event *drain_event);
virtual void resume();
- virtual void setMemoryMode(State new_mode);
+ virtual void setMemoryMode(Enums::MemoryMode new_mode);
virtual void switchOut();
virtual void takeOverFrom(BaseCPU *cpu);
tgt->st_dev = 0xA;
else
tgt->st_dev = host->st_dev;
- tgt->st_dev = htog(tgt->st_dev);
+ tgt->st_dev = TheISA::htog(tgt->st_dev);
tgt->st_ino = host->st_ino;
- tgt->st_ino = htog(tgt->st_ino);
+ tgt->st_ino = TheISA::htog(tgt->st_ino);
tgt->st_mode = host->st_mode;
if (fakeTTY) {
// Claim to be a character device
tgt->st_mode &= ~S_IFMT; // Clear S_IFMT
tgt->st_mode |= S_IFCHR; // Set S_IFCHR
}
- tgt->st_mode = htog(tgt->st_mode);
+ tgt->st_mode = TheISA::htog(tgt->st_mode);
tgt->st_nlink = host->st_nlink;
- tgt->st_nlink = htog(tgt->st_nlink);
+ tgt->st_nlink = TheISA::htog(tgt->st_nlink);
tgt->st_uid = host->st_uid;
- tgt->st_uid = htog(tgt->st_uid);
+ tgt->st_uid = TheISA::htog(tgt->st_uid);
tgt->st_gid = host->st_gid;
- tgt->st_gid = htog(tgt->st_gid);
+ tgt->st_gid = TheISA::htog(tgt->st_gid);
if (fakeTTY)
tgt->st_rdev = 0x880d;
else
tgt->st_rdev = host->st_rdev;
- tgt->st_rdev = htog(tgt->st_rdev);
+ tgt->st_rdev = TheISA::htog(tgt->st_rdev);
tgt->st_size = host->st_size;
- tgt->st_size = htog(tgt->st_size);
+ tgt->st_size = TheISA::htog(tgt->st_size);
tgt->st_atimeX = host->st_atime;
- tgt->st_atimeX = htog(tgt->st_atimeX);
+ tgt->st_atimeX = TheISA::htog(tgt->st_atimeX);
tgt->st_mtimeX = host->st_mtime;
- tgt->st_mtimeX = htog(tgt->st_mtimeX);
+ tgt->st_mtimeX = TheISA::htog(tgt->st_mtimeX);
tgt->st_ctimeX = host->st_ctime;
- tgt->st_ctimeX = htog(tgt->st_ctimeX);
+ tgt->st_ctimeX = TheISA::htog(tgt->st_ctimeX);
// Force the block size to be 8k. This helps to ensure buffered io works
// consistently across different hosts.
tgt->st_blksize = 0x2000;
- tgt->st_blksize = htog(tgt->st_blksize);
+ tgt->st_blksize = TheISA::htog(tgt->st_blksize);
tgt->st_blocks = host->st_blocks;
- tgt->st_blocks = htog(tgt->st_blocks);
+ tgt->st_blocks = TheISA::htog(tgt->st_blocks);
}
// Same for stat64
convertStatBuf<target_stat, host_stat64>(tgt, host, fakeTTY);
#if defined(STAT_HAVE_NSEC)
tgt->st_atime_nsec = host->st_atime_nsec;
- tgt->st_atime_nsec = htog(tgt->st_atime_nsec);
+ tgt->st_atime_nsec = TheISA::htog(tgt->st_atime_nsec);
tgt->st_mtime_nsec = host->st_mtime_nsec;
- tgt->st_mtime_nsec = htog(tgt->st_mtime_nsec);
+ tgt->st_mtime_nsec = TheISA::htog(tgt->st_mtime_nsec);
tgt->st_ctime_nsec = host->st_ctime_nsec;
- tgt->st_ctime_nsec = htog(tgt->st_ctime_nsec);
+ tgt->st_ctime_nsec = TheISA::htog(tgt->st_ctime_nsec);
#else
tgt->st_atime_nsec = 0;
tgt->st_mtime_nsec = 0;
p->readBlob(tiov_base + i*sizeof(typename OS::tgt_iovec),
(uint8_t*)&tiov, sizeof(typename OS::tgt_iovec));
- hiov[i].iov_len = gtoh(tiov.iov_len);
+ hiov[i].iov_len = TheISA::gtoh(tiov.iov_len);
hiov[i].iov_base = new char [hiov[i].iov_len];
- p->readBlob(gtoh(tiov.iov_base), (uint8_t *)hiov[i].iov_base,
+ p->readBlob(TheISA::gtoh(tiov.iov_base), (uint8_t *)hiov[i].iov_base,
hiov[i].iov_len);
}
case OS::TGT_RLIMIT_STACK:
// max stack size in bytes: make up a number (8MB for now)
rlp->rlim_cur = rlp->rlim_max = 8 * 1024 * 1024;
- rlp->rlim_cur = htog(rlp->rlim_cur);
- rlp->rlim_max = htog(rlp->rlim_max);
+ rlp->rlim_cur = TheISA::htog(rlp->rlim_cur);
+ rlp->rlim_max = TheISA::htog(rlp->rlim_max);
break;
case OS::TGT_RLIMIT_DATA:
// max data segment size in bytes: make up a number
rlp->rlim_cur = rlp->rlim_max = 256 * 1024 * 1024;
- rlp->rlim_cur = htog(rlp->rlim_cur);
- rlp->rlim_max = htog(rlp->rlim_max);
+ rlp->rlim_cur = TheISA::htog(rlp->rlim_cur);
+ rlp->rlim_max = TheISA::htog(rlp->rlim_max);
break;
default:
struct timeval hostTimeval[2];
for (int i = 0; i < 2; ++i)
{
- hostTimeval[i].tv_sec = gtoh((*tp)[i].tv_sec);
- hostTimeval[i].tv_usec = gtoh((*tp)[i].tv_usec);
+ hostTimeval[i].tv_sec = TheISA::gtoh((*tp)[i].tv_sec);
+ hostTimeval[i].tv_usec = TheISA::gtoh((*tp)[i].tv_usec);
}
// Adjust path for current working directory
switch (who) {
case OS::TGT_RUSAGE_SELF:
getElapsedTime(rup->ru_utime.tv_sec, rup->ru_utime.tv_usec);
- rup->ru_utime.tv_sec = htog(rup->ru_utime.tv_sec);
- rup->ru_utime.tv_usec = htog(rup->ru_utime.tv_usec);
+ rup->ru_utime.tv_sec = TheISA::htog(rup->ru_utime.tv_sec);
+ rup->ru_utime.tv_usec = TheISA::htog(rup->ru_utime.tv_usec);
break;
case OS::TGT_RUSAGE_CHILDREN:
bufp->tms_cstime = 0;
// Convert to host endianness
- bufp->tms_utime = htog(bufp->tms_utime);
+ bufp->tms_utime = TheISA::htog(bufp->tms_utime);
// Write back
bufp.copyOut(tc->getMemProxy());
Addr taddr = (Addr)process->getSyscallArg(tc, index);
if(taddr != 0) {
typename OS::time_t t = sec;
- t = htog(t);
+ t = TheISA::htog(t);
SETranslatingPortProxy *p = tc->getMemProxy();
p->writeBlob(taddr, (uint8_t*)&t, (int)sizeof(typename OS::time_t));
}
projects / gem5.git / commitdiff