arch-arm: Fix mrc,mcr to cop14 disassemble

This patch fixes the disassemble for AArch32 mcr/mrc p14 instructions.

Change-Id: If5d7c2d7c726f040ae20053bf1d70f4405b34d0e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9681
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index a9acc21af94ae2507708dc06c32a7808c49f4348..4f1960b952f9450279dde61700dfd1c001d2ba4b 100644 (file)
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -177,9 +177,9 @@ let {{
           default:
             uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
             if (isRead) {
-                return new Mrc14(machInst, rt, (IntRegIndex)miscReg, iss);
+                return new Mrc14(machInst, rt, miscReg, iss);
             } else {
-                return new Mcr14(machInst, (IntRegIndex)miscReg, rt, iss);
+                return new Mcr14(machInst, miscReg, rt, iss);
             }
         }
     }

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 3aeee04568d9064de98f6ec14688a9a82de6dc02..f1c6acff38f2c01c54d76284d9d5346689543397 100644 (file)
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -875,11 +875,11 @@ let {{
     Dest = MiscOp1;
     '''
 
-    mrc14Iop = InstObjParams("mrc", "Mrc14", "RegRegImmOp",
+    mrc14Iop = InstObjParams("mrc", "Mrc14", "RegMiscRegImmOp",
                              { "code": mrc14code,
                                "predicate_test": predicateTest }, [])
-    header_output += RegRegImmOpDeclare.subst(mrc14Iop)
-    decoder_output += RegRegImmOpConstructor.subst(mrc14Iop)
+    header_output += RegMiscRegImmOpDeclare.subst(mrc14Iop)
+    decoder_output += RegMiscRegImmOpConstructor.subst(mrc14Iop)
     exec_output += PredOpExecute.subst(mrc14Iop)
 
 
@@ -899,12 +899,12 @@ let {{
     }
     MiscDest = Op1;
     '''
-    mcr14Iop = InstObjParams("mcr", "Mcr14", "RegRegImmOp",
+    mcr14Iop = InstObjParams("mcr", "Mcr14", "MiscRegRegImmOp",
                              { "code": mcr14code,
                                "predicate_test": predicateTest },
                                ["IsSerializeAfter","IsNonSpeculative"])
-    header_output += RegRegImmOpDeclare.subst(mcr14Iop)
-    decoder_output += RegRegImmOpConstructor.subst(mcr14Iop)
+    header_output += MiscRegRegImmOpDeclare.subst(mcr14Iop)
+    decoder_output += MiscRegRegImmOpConstructor.subst(mcr14Iop)
     exec_output += PredOpExecute.subst(mcr14Iop)
 
     mrc15code = '''