gpu-compute: No RF scheduling in case of SKIP or EMPTY

In case of flat memory instructions the status for the
LM pipe execution unit is set to SKIP or EMPTY, as the bus
between the VRF and the GM and LM pipe is shared. The
destination operands should not be scheduled for the LM pipe,
event if the wave is in the dispatch list. This can lead
to deadlock in the destination cache as DCEs are reused
and the slotsAvailableForBank count gets artificially
incremented.

Change-Id: I2230c53e3bc1032d2cccbe00fab62c99ab8de6cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29970
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

diff --git a/src/gpu-compute/schedule_stage.cc b/src/gpu-compute/schedule_stage.cc
index 0785aa03d8b0f2447c2d9173305ca33c4f481bda..e0600a623a357e66c0a74109e3ffd3a6c71420ff 100644 (file)
--- a/src/gpu-compute/schedule_stage.cc
+++ b/src/gpu-compute/schedule_stage.cc
@@ -236,9 +236,13 @@ void
 ScheduleStage::scheduleRfDestOperands()
 {
     for (int j = 0; j < computeUnit.numExeUnits(); ++j) {
-        if (!dispatchList->at(j).first) {
+        if (dispatchList->at(j).second == EMPTY ||
+            dispatchList->at(j).second == SKIP) {
             continue;
         }
+
+        assert(dispatchList->at(j).first);
+
         // get the wave on dispatch list and attempt to allocate write
         // resources in the RFs
         Wavefront *w = dispatchList->at(j).first;