return r;
}
-static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags)
+static void r600_state_pm4_with_flush(struct radeon_state *state, u32 flags, int bufs_are_cbs)
{
unsigned i, j, add, size;
for (i = 0; i < state->nreloc; i++) {
size = (state->bo[state->reloc_bo_id[i]]->size + 255) >> 8;
state->pm4[state->cpm4++] = PKT3(PKT3_SURFACE_SYNC, 3);
+ if (bufs_are_cbs)
+ flags |= S_0085F0_CB0_DEST_BASE_ENA(1 << i);
state->pm4[state->cpm4++] = flags;
state->pm4[state->cpm4++] = size;
state->pm4[state->cpm4++] = 0x00000000;
static int r600_state_pm4_shader(struct radeon_state *state)
{
- r600_state_pm4_with_flush(state, S_0085F0_SH_ACTION_ENA(1));
+ r600_state_pm4_with_flush(state, S_0085F0_SH_ACTION_ENA(1), 0);
return r600_state_pm4_generic(state);
}
if (!state->nbo)
return 0;
- r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1) |
- S_0085F0_CB0_DEST_BASE_ENA(1));
+ r600_state_pm4_with_flush(state, S_0085F0_CB_ACTION_ENA(1), 1);
return 0;
}
return 0;
r600_state_pm4_with_flush(state, S_0085F0_DB_ACTION_ENA(1) |
- S_0085F0_DB_DEST_BASE_ENA(1));
+ S_0085F0_DB_DEST_BASE_ENA(1), 0);
return 0;
}
fprintf(stderr, "%s need %d bo got %d\n", __func__, nbo, state->nbo);
return -EINVAL;
}
- r600_state_pm4_with_flush(state, flags);
+ r600_state_pm4_with_flush(state, flags, 0);
offset = regs[0].offset + soffset;
if (state->radeon->family >= CHIP_CEDAR)
nres = 8;