* ppc-opc.c (PPC440): Define.

	(powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci,
	icread instructions when PPC440.  Add dlmzb instruction.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6f5bd4b44cf8d0e9f934fdf079f1639706196ce2..02a6d172ec044ef28f8051e0c0aa3b271b2d3957 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2003-08-19  Alan Modra  <amodra@bigpond.net.au>
+
+       * ppc-opc.c (PPC440): Define.
+       (powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci,
+       icread instructions when PPC440.  Add dlmzb instruction.
+
 2003-08-14  Alan Modra  <amodra@bigpond.net.au>
 
        * dep-in.sed: Remove libintl.h.

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 0f04cfb8468bd77262304ce8d09d45433c55b3a7..7fd2977befcd2329233adb4f23be3066cd1ed9d4 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -1771,6 +1771,7 @@ extract_tbr (unsigned long insn,
 #define PPCONLY        PPC_OPCODE_PPC
 #define PPC403 PPC_OPCODE_403
 #define PPC405 PPC403
+#define PPC440 PPC_OPCODE_440
 #define PPC750 PPC
 #define PPC860 PPC
 #define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
@@ -1863,90 +1864,90 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "twi",     OP(3),    OP_MASK,        PPCCOM,         { TO, RA, SI } },
 { "ti",      OP(3),    OP_MASK,        PWRCOM,         { TO, RA, SI } },
 
-{ "macchw",    XO(4,172,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchw.",   XO(4,172,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwo",   XO(4,172,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwo.",  XO(4,172,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchws",   XO(4,236,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchws.",  XO(4,236,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwso",  XO(4,236,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwsu",  XO(4,204,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwsuo.",        XO(4,204,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwu",   XO(4,140,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwu.",  XO(4,140,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwuo",  XO(4,140,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhw",    XO(4,44,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhw.",   XO(4,44,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwo",   XO(4,44,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwo.",  XO(4,44,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhws",   XO(4,108,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhws.",  XO(4,108,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwso",  XO(4,108,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwsu",  XO(4,76,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwsu.", XO(4,76,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwsuo", XO(4,76,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwsuo.",        XO(4,76,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwu",   XO(4,12,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwu.",  XO(4,12,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwuo",  XO(4,12,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "machhwuo.", XO(4,12,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhw",    XO(4,428,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhw.",   XO(4,428,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwo",   XO(4,428,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwo.",  XO(4,428,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhws",   XO(4,492,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhws.",  XO(4,492,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwso",  XO(4,492,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwsu",  XO(4,460,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwsuo.",        XO(4,460,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwu",   XO(4,396,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwu.",  XO(4,396,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwuo",  XO(4,396,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "mulchw",    XRC(4,168,0),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulchw.",   XRC(4,168,1),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulchwu",   XRC(4,136,0),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulchwu.",  XRC(4,136,1),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulhhw",    XRC(4,40,0),   X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulhhw.",   XRC(4,40,1),   X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulhhwu",   XRC(4,8,0),    X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mulhhwu.",  XRC(4,8,1),    X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mullhw",    XRC(4,424,0),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mullhw.",   XRC(4,424,1),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mullhwu",   XRC(4,392,0),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "mullhwu.",  XRC(4,392,1),  X_MASK,  PPC405,         { RT, RA, RB } },
-{ "nmacchw",   XO(4,174,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchw.",  XO(4,174,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchwo",  XO(4,174,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchws",  XO(4,238,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmacchwso.",        XO(4,238,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhw",   XO(4,46,0,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhw.",  XO(4,46,0,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhwo",  XO(4,46,1,0),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhwo.", XO(4,46,1,1),  XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhws",  XO(4,110,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmachhwso.",        XO(4,110,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhw",   XO(4,430,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhw.",  XO(4,430,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhwo",  XO(4,430,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhws",  XO(4,494,0,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405,         { RT, RA, RB } },
-{ "nmaclhwso.",        XO(4,494,1,1), XO_MASK, PPC405,         { RT, RA, RB } },
+{ "macchw",    XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchw.",   XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwo",   XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwo.",  XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchws",   XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchws.",  XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwso",  XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsu",  XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwsuo.",        XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwu",   XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwu.",  XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwuo",  XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhw",    XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhw.",   XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwo",   XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwo.",  XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhws",   XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhws.",  XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwso",  XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsu",  XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsu.", XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsuo", XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwsuo.",        XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwu",   XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwu.",  XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwuo",  XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "machhwuo.", XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhw",    XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhw.",   XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwo",   XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwo.",  XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhws",   XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhws.",  XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwso",  XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsu",  XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwsuo.",        XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwu",   XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwu.",  XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwuo",  XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchw",    XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchw.",   XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchwu",   XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulchwu.",  XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhw",    XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhw.",   XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhwu",   XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mulhhwu.",  XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhw",    XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhw.",   XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhwu",   XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "mullhwu.",  XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchw",   XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchw.",  XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwo",  XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchws",  XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmacchwso.",        XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhw",   XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhw.",  XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwo",  XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwo.", XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhws",  XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmachhwso.",        XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhw",   XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhw.",  XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwo",  XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhws",  XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
+{ "nmaclhwso.",        XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
 { "mfvscr",  VX(4, 1540), VX_MASK,     PPCVEC,         { VD } },
 { "mtvscr",  VX(4, 1604), VX_MASK,     PPCVEC,         { VB } },
 { "vaddcuw", VX(4,  384), VX_MASK,     PPCVEC,         { VD, VA, VB } },
@@ -3314,6 +3315,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "mulhw",   XO(31,75,0,0), XO_MASK,   PPC,            { RT, RA, RB } },
 { "mulhw.",  XO(31,75,0,1), XO_MASK,   PPC,            { RT, RA, RB } },
 
+{ "dlmzb",   XRC(31,78,0),  X_MASK,    PPC403|PPC440,  { RA, RS, RB } },
+{ "dlmzb.",  XRC(31,78,1),  X_MASK,    PPC403|PPC440,  { RA, RS, RB } },
+
 { "mtsrd",   X(31,82), XRB_MASK|(1<<20), PPC64,        { SR, RS } },
 
 { "mfmsr",   X(31,83), XRARB_MASK,     COM,            { RT } },
@@ -3783,7 +3787,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "dstst",   XDSS(31,374,0), XDSS_MASK,        PPCVEC,         { RA, RB, STRM } },
 { "dststt",  XDSS(31,374,1), XDSS_MASK,        PPCVEC,         { RA, RB, STRM } },
 
-{ "dccci",   X(31,454),        XRT_MASK,       PPC403,         { RA, RB } },
+{ "dccci",   X(31,454),        XRT_MASK,       PPC403|PPC440,  { RA, RB } },
 
 { "abs",     XO(31,360,0,0), XORB_MASK, M601,          { RT, RA } },
 { "abs.",    XO(31,360,0,1), XORB_MASK, M601,          { RT, RA } },
@@ -4065,7 +4069,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "dcbie",   X(31,478),        XRT_MASK,       BOOKE64,        { RA, RB } },
 
-{ "dcread",  X(31,486),        X_MASK,         PPC403,         { RT, RA, RB }},
+{ "dcread",  X(31,486),        X_MASK,         PPC403|PPC440,  { RT, RA, RB }},
 
 { "mtpmr",   X(31,462),        X_MASK,         PPCPMR,         { PMR, RS }},
 
@@ -4288,7 +4292,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stduxe",  X(31,959),        X_MASK,         BOOKE64,        { RS, RAS, RB } },
 
-{ "iccci",   X(31,966),        XRT_MASK,       PPC403,         { RA, RB } },
+{ "iccci",   X(31,966),        XRT_MASK,       PPC403|PPC440,  { RA, RB } },
 
 { "tlbwe",   X(31,978),        X_MASK,         BOOKE,          { 0 } },
 
@@ -4305,7 +4309,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "extsw",   XRC(31,986,0), XRB_MASK,  PPC64 | BOOKE64,{ RA, RS } },
 { "extsw.",  XRC(31,986,1), XRB_MASK,  PPC64,          { RA, RS } },
 
-{ "icread",  X(31,998),        XRT_MASK,       PPC403,         { RA, RB } },
+{ "icread",  X(31,998),        XRT_MASK,       PPC403|PPC440,  { RA, RB } },
 
 { "icbie",   X(31,990),        XRT_MASK,       BOOKE64,        { RA, RB } },
 { "stfiwxe", X(31,991),        X_MASK,         BOOKE64,        { FRS, RA, RB } },