Add support for the MIPS eXtended Physical Address (XPA) ASE.

ChangeLog:

binutils/
	* doc/binutils.texi: Document the disassemble MIPS XPA instructions
	command line option.

gas/
	* config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
 	(md_longopts): Add xpa and no-xpa command line options.
 	(mips_ases): Add MIPS XPA ASE.
 	(mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
 	* doc/as.texinfo: Document the MIPS XPA command line options.
 	* doc/c-mips.texi: Document the MIPS XPA command line options,
 	and assembler directives.

gas/testsuite/
 	* gas/mips/mips.exp: Add xpa tests.
 	* gas/mips/xpa.s: New test.
 	* gas/mips/xpa.d: Likewise.

include/
 	* opcode/mips.h (ASE_XPA): New define.

opcodes/
 	* mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
 	to allow the MIPS XPA ASE.
 	(parse_mips_dis_option): Process the -Mxpa option.
 	* mips-opc.c (XPA): New define.
 	(mips_builtin_opcodes): Add MIPS XPA instructions and move the
 	locations of the ctc0 and cfc0 instructions.

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index fe2b6732c0168d57086a61d0a145298628d9c9fc..8449d08ea363a5f0c8f5827581f0e588ea1ab8d5 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * doc/binutils.texi: Document the disassemble MIPS XPA instructions
+       command line option.
+
 2014-04-22  Christian Svensson  <blue@cmd.nu>
 
        * readelf.c: Remove openrisc and or32 support.  Add support for or1k.

diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
index 5c95800f91c4cf37fdd20c24a676c511b5e35ac7..3375d3682e7795194fea4f0c7489d723754fa361 100644 (file)
--- a/binutils/doc/binutils.texi
+++ b/binutils/doc/binutils.texi
@@ -2132,6 +2132,9 @@ Disassemble MSA instructions.
 @item virt
 Disassemble the virtualization ASE instructions.
 
+@item xpa
+Disassemble the eXtended Physical Address (XPA) ASE instructions.
+
 @item gpr-names=@var{ABI}
 Print GPR (general-purpose register) names as appropriate
 for the specified ABI.  By default, GPR names are selected according to

diff --git a/gas/ChangeLog b/gas/ChangeLog
index dd67c862392e36094f6858f313fea9df1daa9e8a..5c5137a66127070da6910fe41aab6f9762c73ffd 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * config/tc-mips.c (options): Add OPTION_XPA and OPTION_NO_XPA.
+       (md_longopts): Add xpa and no-xpa command line options.
+       (mips_ases): Add MIPS XPA ASE.
+       (mips_cpu_info_table): Update p5600 entry to allow the XPA ASE.
+       * doc/as.texinfo: Document the MIPS XPA command line options.
+       * doc/c-mips.texi: Document the MIPS XPA command line options,
+       and assembler directives.
+
 2014-04-22  Sandra Loosemore  <sandra@codesourcery.com>
 
        * config/tc-nios2.c (nios2_consume_arg): Add case for 'E' to

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 47de8d386928588fb6309131352f1ba96ca02549..960169ee2528584648585d04a753b3ce8067639f 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1338,6 +1338,8 @@ enum options
     OPTION_NO_DSPR2,
     OPTION_EVA,
     OPTION_NO_EVA,
+    OPTION_XPA,
+    OPTION_NO_XPA,
     OPTION_MICROMIPS,
     OPTION_NO_MICROMIPS,
     OPTION_MCU,
@@ -1447,6 +1449,8 @@ struct option md_longopts[] =
   {"mno-virt", no_argument, NULL, OPTION_NO_VIRT},
   {"mmsa", no_argument, NULL, OPTION_MSA},
   {"mno-msa", no_argument, NULL, OPTION_NO_MSA},
+  {"mxpa", no_argument, NULL, OPTION_XPA},
+  {"mno-xpa", no_argument, NULL, OPTION_NO_XPA},
 
   /* Old-style architecture options.  Don't add more of these.  */
   {"m4650", no_argument, NULL, OPTION_M4650},
@@ -1599,7 +1603,11 @@ static const struct mips_ase mips_ases[] = {
 
   { "msa", ASE_MSA, ASE_MSA64,
     OPTION_MSA, OPTION_NO_MSA,
-    2, 2, 2, 2 }
+    2, 2, 2, 2 },
+
+  { "xpa", ASE_XPA, 0,
+    OPTION_XPA, OPTION_NO_XPA,
+    2, 2, -1, -1 }
 };
 
 /* The set of ASEs that require -mfp64.  */
@@ -17903,7 +17911,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "1004kf",         0, ASE_DSP | ASE_MT,     ISA_MIPS32R2, CPU_MIPS32R2 },
   { "1004kf1_1",      0, ASE_DSP | ASE_MT,     ISA_MIPS32R2, CPU_MIPS32R2 },
   /* P5600 with EVA and Virtualization ASEs, other ASEs are optional.  */
-  { "p5600",          0, ASE_VIRT | ASE_EVA,   ISA_MIPS32R2, CPU_MIPS32R2 },
+  { "p5600",          0, ASE_VIRT | ASE_EVA | ASE_XPA,         ISA_MIPS32R2, CPU_MIPS32R2 },
 
   /* MIPS 64 */
   { "5kc",            0, 0,                    ISA_MIPS64,   CPU_MIPS64 },
@@ -18161,6 +18169,9 @@ MIPS options:\n\
 -mmsa                  generate MSA instructions\n\
 -mno-msa               do not generate MSA instructions\n"));
   fprintf (stream, _("\
+-mxpa                  generate eXtended Physical Address (XPA) instructions\n\
+-mno-xpa               do not generate eXtended Physical Address (XPA) instructions\n"));
+  fprintf (stream, _("\
 -mvirt                 generate Virtualization instructions\n\
 -mno-virt              do not generate Virtualization instructions\n"));
   fprintf (stream, _("\

diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo
index 7432fbafd850a6c02a5511d52a2c833a24eeaed3..d16bbf6265e9d2e5bac6d47f97382f114f5c9df1 100644 (file)
--- a/gas/doc/as.texinfo
+++ b/gas/doc/as.texinfo
@@ -413,6 +413,7 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}.
    [@b{-mdsp}] [@b{-mno-dsp}]
    [@b{-mdspr2}] [@b{-mno-dspr2}]
    [@b{-mmsa}] [@b{-mno-msa}]
+   [@b{-mxpa}] [@b{-mno-xpa}]
    [@b{-mmt}] [@b{-mno-mt}]
    [@b{-mmcu}] [@b{-mno-mcu}]
    [@b{-minsn32}] [@b{-mno-insn32}]
@@ -1357,6 +1358,12 @@ Generate code for the MIPS SIMD Architecture Extension.
 This tells the assembler to accept MSA instructions.
 @samp{-mno-msa} turns off this option.
 
+@item -mxpa
+@itemx -mno-xpa
+Generate code for the MIPS eXtended Physical Address (XPA) Extension.
+This tells the assembler to accept XPA instructions.
+@samp{-mno-xpa} turns off this option.
+
 @item -mmt
 @itemx -mno-mt
 Generate code for the MT Application Specific Extension.

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 3778ae203ea5b1d719933900cf34deae9045dc3d..0c5e82d94d64cf10cc721f270db2530898329162 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -183,6 +183,12 @@ Generate code for the MIPS SIMD Architecture Extension.
 This tells the assembler to accept MSA instructions.
 @samp{-mno-msa} turns off this option.
 
+@item -mxpa
+@itemx -mno-xpa
+Generate code for the MIPS eXtended Physical Address (XPA) Extension.
+This tells the assembler to accept XPA instructions.
+@samp{-mno-xpa} turns off this option.
+
 @item -mvirt
 @itemx -mno-virt
 Generate code for the Virtualization Application Specific Extension.
@@ -879,6 +885,13 @@ from the Virtualization Application Specific Extension from that point
 on in the assembly.  The @code{.set novirt} directive prevents Virtualization
 instructions from being accepted.
 
+@cindex MIPS eXtended Physical Address (XPA) instruction generation override
+@kindex @code{.set xpa}
+@kindex @code{.set noxpa}
+The directive @code{.set xpa} makes the assembler accept instructions
+from the XPA Extension from that point on in the assembly.  The 
+@code{.set noxpa} directive prevents XPA instructions from being accepted.
+
 Traditional MIPS assemblers do not support these directives.
 
 @node MIPS Floating-Point

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 9b3d9c3312451971ab530a5c9a838d6ee764d45b..492450b38eae03a3781ec2b44b4604c48959010d 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * gas/mips/mips.exp: Add xpa tests.
+       * gas/mips/xpa.s: New test.
+       * gas/mips/xpa.d: Likewise.
+
 2014-04-22  Sandra Loosemore  <sandra@codesourcery.com>
 
        * gas/nios2/selftest.s: New.

diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 628f482813593a283165f08436d48f36e3708a89..b0d8ac2acbe0c6e8470393d8bce3fe525af317b9 100644 (file)
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -1170,6 +1170,8 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test_arches "msa-relax"   [mips_arch_list_matching mips32r2]
     run_dump_test_arches "msa-branch"  [mips_arch_list_matching mips32r2]
 
+    run_dump_test_arches "xpa"         [mips_arch_list_matching mips32r2 !micromips]
+
     run_dump_test "pcrel-1"
     run_dump_test "pcrel-2"
     run_list_test "pcrel-3" "" "Invalid cross-section PC-relative references"

diff --git a/gas/testsuite/gas/mips/xpa.d b/gas/testsuite/gas/mips/xpa.d
new file mode 100644 (file)
index 0000000..f1047c9
--- /dev/null
+++ b/gas/testsuite/gas/mips/xpa.d
@@ -0,0 +1,24 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -Mxpa,cp0-names=mips32r2
+#name: XPA instructions
+#as: -32 -mxpa
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 40420800     mfhc0   v0,c0_random
+[0-9a-f]+ <[^>]*> 40428000     mfhc0   v0,c0_config
+[0-9a-f]+ <[^>]*> 40420002     mfhc0   v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 40420007     mfhc0   v0,\$0,7
+[0-9a-f]+ <[^>]*> 40c20800     mthc0   v0,c0_random
+[0-9a-f]+ <[^>]*> 40c28000     mthc0   v0,c0_config
+[0-9a-f]+ <[^>]*> 40c20002     mthc0   v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 40c20007     mthc0   v0,\$0,7
+[0-9a-f]+ <[^>]*> 40620c00     mfhgc0  v0,c0_random
+[0-9a-f]+ <[^>]*> 40628400     mfhgc0  v0,c0_config
+[0-9a-f]+ <[^>]*> 40620402     mfhgc0  v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 40620407     mfhgc0  v0,\$0,7
+[0-9a-f]+ <[^>]*> 40620e00     mthgc0  v0,c0_random
+[0-9a-f]+ <[^>]*> 40628600     mthgc0  v0,c0_config
+[0-9a-f]+ <[^>]*> 40620602     mthgc0  v0,c0_mvpconf0
+[0-9a-f]+ <[^>]*> 40620607     mthgc0  v0,\$0,7
+       ...

diff --git a/gas/testsuite/gas/mips/xpa.s b/gas/testsuite/gas/mips/xpa.s
new file mode 100644 (file)
index 0000000..4d91f75
--- /dev/null
+++ b/gas/testsuite/gas/mips/xpa.s
@@ -0,0 +1,29 @@
+       .text
+       .set    noat
+       .set    noreorder
+       .set    nomacro
+test_xpa:
+
+       mfhc0   $2, $1
+       mfhc0   $2, $16
+       mfhc0   $2, $0, 2
+       mfhc0   $2, $0, 7
+
+       mthc0   $2, $1
+       mthc0   $2, $16
+       mthc0   $2, $0, 2
+       mthc0   $2, $0, 7
+       
+       mfhgc0  $2, $1
+       mfhgc0  $2, $16
+       mfhgc0  $2, $0, 2
+       mfhgc0  $2, $0, 7
+
+       mthgc0  $2, $1
+       mthgc0  $2, $16
+       mthgc0  $2, $0, 2
+       mthgc0  $2, $0, 7
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+       .align  2
+       .space  8

diff --git a/include/ChangeLog b/include/ChangeLog
index aeb73af747635aff57944c5e0382a26ad99c8a00..42a63999687f9d56bb1bce2c16e4a1569a0b2d95 100644 (file)
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,7 @@
+2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * opcode/mips.h (ASE_XPA): New define.
+
 2014-04-22  Christian Svensson  <blue@cmd.nu>
 
        * dis-asm.h: Remove openrisc and or32 support.  Add support for or1k.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 5cc9d244b7ce16cb7d0bfbf15c730e11c1d436f2..a5d2935385a05c42ccf8a0e8a3bef22e904e6522 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1155,6 +1155,8 @@ static const unsigned int mips_isa_table[] =
 /* MSA Extension  */
 #define ASE_MSA                        0x00000800
 #define ASE_MSA64              0x00001000
+/* eXtended Physical Address (XPA) Extension.  */
+#define ASE_XPA                        0x00002000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fda57ef1e49fc87ef2a9923f9562c7bc91aea340..62b96f2115bdda6ee00b824622a9cf31c4e4dd11 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2014-04-23  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
+       to allow the MIPS XPA ASE.
+       (parse_mips_dis_option): Process the -Mxpa option.
+       * mips-opc.c (XPA): New define.
+       (mips_builtin_opcodes): Add MIPS XPA instructions and move the
+       locations of the ctc0 and cfc0 instructions.
+
 2014-04-22  Christian Svensson  <blue@cmd.nu>
 
        * Makefile.am: Remove openrisc and or32 support.  Add support for or1k.

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 1de2ca3b20ecafead9957c87072ed25fe3254f90..0f8624efa2ca485335ada76955bcb1f7331ad8be 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -551,7 +551,7 @@ const struct mips_arch_choice mips_arch_choices[] =
   { "mips32r2",        1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
     ISA_MIPS32R2,
     (ASE_SMARTMIPS | ASE_DSP | ASE_DSPR2 | ASE_EVA | ASE_MIPS3D
-     | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA),
+     | ASE_MT | ASE_MCU | ASE_VIRT | ASE_MSA | ASE_XPA),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -566,7 +566,7 @@ const struct mips_arch_choice mips_arch_choices[] =
   { "mips64r2",        1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
     ISA_MIPS64R2,
     (ASE_MIPS3D | ASE_DSP | ASE_DSPR2 | ASE_DSP64 | ASE_EVA | ASE_MT
-     | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64),
+     | ASE_MCU | ASE_VIRT | ASE_VIRT64 | ASE_MSA | ASE_MSA64 | ASE_XPA),
     mips_cp0_names_mips3264r2,
     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
     mips_cp1_names_mips3264, mips_hwr_names_mips3264r2 },
@@ -810,6 +810,13 @@ parse_mips_dis_option (const char *option, unsigned int len)
        mips_ase |= ASE_VIRT64;
       return;
     }
+
+  if (CONST_STRNEQ (option, "xpa"))
+    {
+      mips_ase |= ASE_XPA;
+      return;
+    }
+  
   
   /* Look for the = that delimits the end of the option name.  */
   for (i = 0; i < len; i++)
@@ -2195,6 +2202,9 @@ with the -M switch (multiple options should be separated by commas):\n"));
   fprintf (stream, _("\n\
   virt            Recognize the virtualization ASE instructions.\n"));
 
+  fprintf (stream, _("\n\
+  xpa            Recognize the eXtended Physical Address (XPA) ASE instructions.\n"));
+
   fprintf (stream, _("\n\
   gpr-names=ABI            Print GPR names according to  specified ABI.\n\
                            Default: based on binary being disassembled.\n"));

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 8e26f48ccabb99fbe23d42121425e1a3d5cfc1b8..9181c3f54444e3dc320c8a452b9f1e56cb055769 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -359,6 +359,9 @@ decode_mips_operand (const char *p)
 #define MSA    ASE_MSA
 #define MSA64  ASE_MSA64
 
+/* eXtended Physical Address (XPA) support.  */
+#define XPA     ASE_XPA
+
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
    for arguments must apear in the correct order in this table for the
@@ -895,7 +898,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ceil.l.s",           "D,S",          0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I3_33,          0,      0 },
 {"ceil.w.d",           "D,S",          0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I2,             0,      SF },
 {"ceil.w.s",           "D,S",          0x4600000e, 0xffff003f, WR_1|RD_2|FP_S,         0,              I2,             0,      EE },
-{"cfc0",               "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
+/* cfc0 is at the bottom of the table.  */
 {"cfc1",               "t,G",          0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S,    0,              I1,             0,      0 },
 {"cfc1",               "t,S",          0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S,    0,              I1,             0,      0 },
 /* cfc2 is at the bottom of the table.  */
@@ -908,7 +911,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cins",               "t,r,+p,+S",    0x70000032, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"clo",                        "U,s",          0x70000021, 0xfc0007ff, WR_1|RD_2,      0,              I32|N55,        0,      0 },
 {"clz",                        "U,s",          0x70000020, 0xfc0007ff, WR_1|RD_2,      0,              I32|N55,        0,      0 },
-{"ctc0",               "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
+/* ctc0 is at the bottom of the table.  */
 {"ctc1",               "t,G",          0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S,    0,              I1,             0,      0 },
 {"ctc1",               "t,S",          0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S,    0,              I1,             0,      0 },
 /* ctc2 is at the bottom of the table.  */
@@ -1300,6 +1303,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfc0",               "t,G,H",        0x40000000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I32,            0,      0 },
 {"mfgc0",              "t,G",          0x40600000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              0,              IVIRT,  0 },
 {"mfgc0",              "t,G,H",        0x40600000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              0,              IVIRT,  0 },
+{"mfhc0",              "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I33,            XPA,    0 },
+{"mfhc0",              "t,G,H",        0x40400000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I33,            XPA,    0 },
+{"mfhgc0",             "t,G",          0x40600400, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I33,            IVIRT|XPA,      0 },
+{"mfhgc0",             "t,G,H",        0x40600400, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I33,            IVIRT|XPA,      0 },
 {"mfc1",               "t,S",          0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S,     0,              I1,             0,      0 },
 {"mfc1",               "t,G",          0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S,     0,              I1,             0,      0 },
 {"mfhc1",              "t,S",          0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D,     0,              I33,            0,      0 },
@@ -1393,6 +1400,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtc0",               "t,G,H",        0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I32,            0,      0 },
 {"mtgc0",              "t,G",          0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              0,              IVIRT,  0 },
 {"mtgc0",              "t,G,H",        0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              0,              IVIRT,  0 },
+{"mthc0",              "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              I33,            XPA,    0 },
+{"mthc0",              "t,G,H",        0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I33,            XPA,    0 },
+{"mthgc0",             "t,G",          0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              I33,            IVIRT|XPA,      0 },
+{"mthgc0",             "t,G,H",        0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I33,            IVIRT|XPA,      0 },
 {"mtc1",               "t,S",          0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S,     0,              I1,             0,      0 },
 {"mtc1",               "t,G",          0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S,     0,              I1,             0,      0 },
 {"mthc1",              "t,S",          0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D,     0,              I33,            0,      0 },
@@ -1954,6 +1965,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"zcb",                        "(b)",          0x7000071f, 0xfc1fffff, RD_1|SM,                0,              IOCT2,          0,      0 },
 {"zcbt",               "(b)",          0x7000075f, 0xfc1fffff, RD_1|SM,                0,              IOCT2,          0,      0 },
 
+/* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the 
+   mfhc0 and mthc0 XPA instructions, so they have been placed here 
+   to allow the XPA instructions to take precedence.  */
+{"ctc0",               "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
+{"cfc0",               "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
+
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
 {"bc2f",               "p",            0x49000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2 },