newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_TEX;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = aactx->texTemp;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = aactx->texTemp;
newInst.Instruction.NumSrcRegs = 2;
newInst.Instruction.Texture = TRUE;
- newInst.InstructionTexture.Texture = TGSI_TEXTURE_2D;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
- newInst.FullSrcRegisters[0].SrcRegister.Index = aactx->maxInput + 1;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_SAMPLER;
- newInst.FullSrcRegisters[1].SrcRegister.Index = aactx->freeSampler;
+ newInst.Texture.Texture = TGSI_TEXTURE_2D;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_INPUT;
+ newInst.Src[0].SrcRegister.Index = aactx->maxInput + 1;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_SAMPLER;
+ newInst.Src[1].SrcRegister.Index = aactx->freeSampler;
ctx->emit_instruction(ctx, &newInst);
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MOV;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_OUTPUT;
- newInst.FullDstRegisters[0].DstRegister.Index = aactx->colorOutput;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_XYZ;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_OUTPUT;
+ newInst.Dst[0].DstRegister.Index = aactx->colorOutput;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_XYZ;
newInst.Instruction.NumSrcRegs = 1;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = aactx->colorTemp;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = aactx->colorTemp;
ctx->emit_instruction(ctx, &newInst);
/* MUL alpha */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_OUTPUT;
- newInst.FullDstRegisters[0].DstRegister.Index = aactx->colorOutput;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_OUTPUT;
+ newInst.Dst[0].DstRegister.Index = aactx->colorOutput;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 2;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = aactx->colorTemp;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[1].SrcRegister.Index = aactx->texTemp;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = aactx->colorTemp;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[1].SrcRegister.Index = aactx->texTemp;
ctx->emit_instruction(ctx, &newInst);
/* END */
uint i;
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
- struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
+ struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (dst->DstRegister.File == TGSI_FILE_OUTPUT &&
dst->DstRegister.Index == aactx->colorOutput) {
dst->DstRegister.File = TGSI_FILE_TEMPORARY;
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_XY;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_XY;
newInst.Instruction.NumSrcRegs = 2;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
- newInst.FullSrcRegisters[0].SrcRegister.Index = texInput;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_INPUT;
- newInst.FullSrcRegisters[1].SrcRegister.Index = texInput;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_INPUT;
+ newInst.Src[0].SrcRegister.Index = texInput;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_INPUT;
+ newInst.Src[1].SrcRegister.Index = texInput;
ctx->emit_instruction(ctx, &newInst);
/* ADD t0.x, t0.x, t0.y; # x^2 + y^2 */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_ADD;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
newInst.Instruction.NumSrcRegs = 2;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[1].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[1].SrcRegister.SwizzleX = TGSI_SWIZZLE_Y;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = tmp0;
+ newInst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[1].SrcRegister.Index = tmp0;
+ newInst.Src[1].SrcRegister.SwizzleX = TGSI_SWIZZLE_Y;
ctx->emit_instruction(ctx, &newInst);
#if NORMALIZE /* OPTIONAL normalization of length */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_RSQ;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
newInst.Instruction.NumSrcRegs = 1;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = tmp0;
ctx->emit_instruction(ctx, &newInst);
/* RCP t0.x, t0.x; */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_RCP;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X;
newInst.Instruction.NumSrcRegs = 1;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = tmp0;
ctx->emit_instruction(ctx, &newInst);
#endif
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SGT;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
newInst.Instruction.NumSrcRegs = 2;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_INPUT;
- newInst.FullSrcRegisters[1].SrcRegister.Index = texInput;
- newInst.FullSrcRegisters[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = tmp0;
+ newInst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_INPUT;
+ newInst.Src[1].SrcRegister.Index = texInput;
+ newInst.Src[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
ctx->emit_instruction(ctx, &newInst);
/* KIL -tmp0.yyyy; # if -tmp0.y < 0, KILL */
newInst.Instruction.Opcode = TGSI_OPCODE_KIL;
newInst.Instruction.NumDstRegs = 0;
newInst.Instruction.NumSrcRegs = 1;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_Y;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_Y;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_Y;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_Y;
- newInst.FullSrcRegisters[0].SrcRegister.Negate = 1;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = tmp0;
+ newInst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_Y;
+ newInst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_Y;
+ newInst.Src[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_Y;
+ newInst.Src[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_Y;
+ newInst.Src[0].SrcRegister.Negate = 1;
ctx->emit_instruction(ctx, &newInst);
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SUB;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_Z;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_Z;
newInst.Instruction.NumSrcRegs = 2;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
- newInst.FullSrcRegisters[0].SrcRegister.Index = texInput;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_W;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_INPUT;
- newInst.FullSrcRegisters[1].SrcRegister.Index = texInput;
- newInst.FullSrcRegisters[1].SrcRegister.SwizzleZ = TGSI_SWIZZLE_Z;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_INPUT;
+ newInst.Src[0].SrcRegister.Index = texInput;
+ newInst.Src[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_W;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_INPUT;
+ newInst.Src[1].SrcRegister.Index = texInput;
+ newInst.Src[1].SrcRegister.SwizzleZ = TGSI_SWIZZLE_Z;
ctx->emit_instruction(ctx, &newInst);
/* RCP t0.z, t0.z; # t0.z = 1 / m */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_RCP;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_Z;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_Z;
newInst.Instruction.NumSrcRegs = 1;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_Z;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = tmp0;
+ newInst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_Z;
ctx->emit_instruction(ctx, &newInst);
/* SUB t0.y, 1, t0.x; # d = 1 - d */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SUB;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
newInst.Instruction.NumSrcRegs = 2;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
- newInst.FullSrcRegisters[0].SrcRegister.Index = texInput;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[1].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_INPUT;
+ newInst.Src[0].SrcRegister.Index = texInput;
+ newInst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[1].SrcRegister.Index = tmp0;
+ newInst.Src[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
ctx->emit_instruction(ctx, &newInst);
/* MUL t0.w, t0.y, t0.z; # coverage = d * m */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 2;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_Y;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[1].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[1].SrcRegister.SwizzleW = TGSI_SWIZZLE_Z;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = tmp0;
+ newInst.Src[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_Y;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[1].SrcRegister.Index = tmp0;
+ newInst.Src[1].SrcRegister.SwizzleW = TGSI_SWIZZLE_Z;
ctx->emit_instruction(ctx, &newInst);
/* SLE t0.y, t0.x, tex.z; # bool b = distance <= k */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_SLE;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_Y;
newInst.Instruction.NumSrcRegs = 2;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_INPUT;
- newInst.FullSrcRegisters[1].SrcRegister.Index = texInput;
- newInst.FullSrcRegisters[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_Z;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = tmp0;
+ newInst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_INPUT;
+ newInst.Src[1].SrcRegister.Index = texInput;
+ newInst.Src[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_Z;
ctx->emit_instruction(ctx, &newInst);
/* CMP t0.w, -t0.y, tex.w, t0.w;
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_CMP;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = tmp0;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = tmp0;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 3;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_Y;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_Y;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_Y;
- newInst.FullSrcRegisters[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_Y;
- newInst.FullSrcRegisters[0].SrcRegister.Negate = 1;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_INPUT;
- newInst.FullSrcRegisters[1].SrcRegister.Index = texInput;
- newInst.FullSrcRegisters[1].SrcRegister.SwizzleX = TGSI_SWIZZLE_W;
- newInst.FullSrcRegisters[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
- newInst.FullSrcRegisters[1].SrcRegister.SwizzleZ = TGSI_SWIZZLE_W;
- newInst.FullSrcRegisters[1].SrcRegister.SwizzleW = TGSI_SWIZZLE_W;
- newInst.FullSrcRegisters[2].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[2].SrcRegister.Index = tmp0;
- newInst.FullSrcRegisters[2].SrcRegister.SwizzleX = TGSI_SWIZZLE_W;
- newInst.FullSrcRegisters[2].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
- newInst.FullSrcRegisters[2].SrcRegister.SwizzleZ = TGSI_SWIZZLE_W;
- newInst.FullSrcRegisters[2].SrcRegister.SwizzleW = TGSI_SWIZZLE_W;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = tmp0;
+ newInst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_Y;
+ newInst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_Y;
+ newInst.Src[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_Y;
+ newInst.Src[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_Y;
+ newInst.Src[0].SrcRegister.Negate = 1;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_INPUT;
+ newInst.Src[1].SrcRegister.Index = texInput;
+ newInst.Src[1].SrcRegister.SwizzleX = TGSI_SWIZZLE_W;
+ newInst.Src[1].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
+ newInst.Src[1].SrcRegister.SwizzleZ = TGSI_SWIZZLE_W;
+ newInst.Src[1].SrcRegister.SwizzleW = TGSI_SWIZZLE_W;
+ newInst.Src[2].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[2].SrcRegister.Index = tmp0;
+ newInst.Src[2].SrcRegister.SwizzleX = TGSI_SWIZZLE_W;
+ newInst.Src[2].SrcRegister.SwizzleY = TGSI_SWIZZLE_W;
+ newInst.Src[2].SrcRegister.SwizzleZ = TGSI_SWIZZLE_W;
+ newInst.Src[2].SrcRegister.SwizzleW = TGSI_SWIZZLE_W;
ctx->emit_instruction(ctx, &newInst);
}
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MOV;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_OUTPUT;
- newInst.FullDstRegisters[0].DstRegister.Index = aactx->colorOutput;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_XYZ;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_OUTPUT;
+ newInst.Dst[0].DstRegister.Index = aactx->colorOutput;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_XYZ;
newInst.Instruction.NumSrcRegs = 1;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = aactx->colorTemp;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = aactx->colorTemp;
ctx->emit_instruction(ctx, &newInst);
/* MUL result.color.w, colorTemp, tmp0.w; */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_OUTPUT;
- newInst.FullDstRegisters[0].DstRegister.Index = aactx->colorOutput;
- newInst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_OUTPUT;
+ newInst.Dst[0].DstRegister.Index = aactx->colorOutput;
+ newInst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_W;
newInst.Instruction.NumSrcRegs = 2;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = aactx->colorTemp;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[1].SrcRegister.Index = aactx->tmp0;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = aactx->colorTemp;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[1].SrcRegister.Index = aactx->tmp0;
ctx->emit_instruction(ctx, &newInst);
}
else {
uint i;
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
- struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
+ struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (dst->DstRegister.File == TGSI_FILE_OUTPUT &&
dst->DstRegister.Index == aactx->colorOutput) {
dst->DstRegister.File = TGSI_FILE_TEMPORARY;
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_MUL;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = pctx->texTemp;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = pctx->texTemp;
newInst.Instruction.NumSrcRegs = 2;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_INPUT;
- newInst.FullSrcRegisters[0].SrcRegister.Index = wincoordInput;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_IMMEDIATE;
- newInst.FullSrcRegisters[1].SrcRegister.Index = pctx->numImmed;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_INPUT;
+ newInst.Src[0].SrcRegister.Index = wincoordInput;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_IMMEDIATE;
+ newInst.Src[1].SrcRegister.Index = pctx->numImmed;
ctx->emit_instruction(ctx, &newInst);
/* TEX texTemp, texTemp, sampler; */
newInst = tgsi_default_full_instruction();
newInst.Instruction.Opcode = TGSI_OPCODE_TEX;
newInst.Instruction.NumDstRegs = 1;
- newInst.FullDstRegisters[0].DstRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullDstRegisters[0].DstRegister.Index = pctx->texTemp;
+ newInst.Dst[0].DstRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Dst[0].DstRegister.Index = pctx->texTemp;
newInst.Instruction.NumSrcRegs = 2;
newInst.Instruction.Texture = TRUE;
- newInst.InstructionTexture.Texture = TGSI_TEXTURE_2D;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = pctx->texTemp;
- newInst.FullSrcRegisters[1].SrcRegister.File = TGSI_FILE_SAMPLER;
- newInst.FullSrcRegisters[1].SrcRegister.Index = pctx->freeSampler;
+ newInst.Texture.Texture = TGSI_TEXTURE_2D;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = pctx->texTemp;
+ newInst.Src[1].SrcRegister.File = TGSI_FILE_SAMPLER;
+ newInst.Src[1].SrcRegister.Index = pctx->freeSampler;
ctx->emit_instruction(ctx, &newInst);
/* KIL -texTemp; # if -texTemp < 0, KILL fragment */
newInst.Instruction.Opcode = TGSI_OPCODE_KIL;
newInst.Instruction.NumDstRegs = 0;
newInst.Instruction.NumSrcRegs = 1;
- newInst.FullSrcRegisters[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
- newInst.FullSrcRegisters[0].SrcRegister.Index = pctx->texTemp;
- newInst.FullSrcRegisters[0].SrcRegister.Negate = 1;
+ newInst.Src[0].SrcRegister.File = TGSI_FILE_TEMPORARY;
+ newInst.Src[0].SrcRegister.Index = pctx->texTemp;
+ newInst.Src[0].SrcRegister.Negate = 1;
ctx->emit_instruction(ctx, &newInst);
}
static boolean emit_ABS( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg neg = aos_get_internal(cp, IMM_NEGS);
struct x86_reg tmp = aos_get_xmm_reg(cp);
sse_mulps(cp->func, tmp, neg);
sse_maxps(cp->func, tmp, arg0);
- store_dest(cp, &op->FullDstRegisters[0], tmp);
+ store_dest(cp, &op->Dst[0], tmp);
return TRUE;
}
static boolean emit_ADD( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_addps(cp->func, dst, arg1);
- store_dest(cp, &op->FullDstRegisters[0], dst);
+ store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_COS( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- x87_fld_src(cp, &op->FullSrcRegisters[0], 0);
+ x87_fld_src(cp, &op->Src[0], 0);
x87_fcos(cp->func);
- x87_fstp_dest4(cp, &op->FullDstRegisters[0]);
+ x87_fstp_dest4(cp, &op->Dst[0]);
return TRUE;
}
*/
static boolean emit_DP3( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg tmp = aos_get_xmm_reg(cp);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_addss(cp->func, dst, tmp);
aos_release_xmm_reg(cp, tmp.idx);
- store_scalar_dest(cp, &op->FullDstRegisters[0], dst);
+ store_scalar_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_DP4( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg tmp = aos_get_xmm_reg(cp);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_addss(cp->func, dst, tmp);
aos_release_xmm_reg(cp, tmp.idx);
- store_scalar_dest(cp, &op->FullDstRegisters[0], dst);
+ store_scalar_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_DPH( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg tmp = aos_get_xmm_reg(cp);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_addss(cp->func, dst, tmp);
aos_release_xmm_reg(cp, tmp.idx);
- store_scalar_dest(cp, &op->FullDstRegisters[0], dst);
+ store_scalar_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_DST( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = aos_get_xmm_reg(cp);
struct x86_reg tmp = aos_get_xmm_reg(cp);
struct x86_reg ones = aos_get_internal(cp, IMM_ONES);
sse_mulps(cp->func, dst, tmp);
aos_release_xmm_reg(cp, tmp.idx);
- store_dest(cp, &op->FullDstRegisters[0], dst);
+ store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_LG2( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
x87_fld1(cp->func); /* 1 */
- x87_fld_src(cp, &op->FullSrcRegisters[0], 0); /* a0 1 */
+ x87_fld_src(cp, &op->Src[0], 0); /* a0 1 */
x87_fyl2x(cp->func); /* log2(a0) */
- x87_fstp_dest4(cp, &op->FullDstRegisters[0]);
+ x87_fstp_dest4(cp, &op->Dst[0]);
return TRUE;
}
#if 0
static boolean emit_EX2( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- x87_fld_src(cp, &op->FullSrcRegisters[0], 0);
+ x87_fld_src(cp, &op->Src[0], 0);
x87_emit_ex2(cp);
- x87_fstp_dest4(cp, &op->FullDstRegisters[0]);
+ x87_fstp_dest4(cp, &op->Dst[0]);
return TRUE;
}
#endif
static boolean emit_FLR( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg dst = get_dst_ptr(cp, &op->FullDstRegisters[0]);
- unsigned writemask = op->FullDstRegisters[0].DstRegister.WriteMask;
+ struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
+ unsigned writemask = op->Dst[0].DstRegister.WriteMask;
int i;
set_fpu_round_neg_inf( cp );
*/
for (i = 3; i >= 0; i--) {
if (writemask & (1<<i)) {
- x87_fld_src(cp, &op->FullSrcRegisters[0], i);
+ x87_fld_src(cp, &op->Src[0], i);
}
}
static boolean emit_RND( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg dst = get_dst_ptr(cp, &op->FullDstRegisters[0]);
- unsigned writemask = op->FullDstRegisters[0].DstRegister.WriteMask;
+ struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
+ unsigned writemask = op->Dst[0].DstRegister.WriteMask;
int i;
set_fpu_round_nearest( cp );
*/
for (i = 3; i >= 0; i--) {
if (writemask & (1<<i)) {
- x87_fld_src(cp, &op->FullSrcRegisters[0], i);
+ x87_fld_src(cp, &op->Src[0], i);
}
}
static boolean emit_FRC( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg dst = get_dst_ptr(cp, &op->FullDstRegisters[0]);
+ struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
struct x86_reg st0 = x86_make_reg(file_x87, 0);
struct x86_reg st1 = x86_make_reg(file_x87, 1);
- unsigned writemask = op->FullDstRegisters[0].DstRegister.WriteMask;
+ unsigned writemask = op->Dst[0].DstRegister.WriteMask;
int i;
set_fpu_round_neg_inf( cp );
*/
for (i = 3; i >= 0; i--) {
if (writemask & (1<<i)) {
- x87_fld_src(cp, &op->FullSrcRegisters[0], i);
+ x87_fld_src(cp, &op->Src[0], i);
}
}
static boolean emit_LIT( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
struct x86_reg ecx = x86_make_reg( file_REG32, reg_CX );
- unsigned writemask = op->FullDstRegisters[0].DstRegister.WriteMask;
+ unsigned writemask = op->Dst[0].DstRegister.WriteMask;
unsigned lit_count = cp->lit_count++;
struct x86_reg result, arg0;
unsigned i;
if (writemask != TGSI_WRITEMASK_XYZW)
result = x86_make_disp(cp->machine_EDX, Offset(struct aos_machine, tmp[0]));
else
- result = get_dst_ptr(cp, &op->FullDstRegisters[0]);
+ result = get_dst_ptr(cp, &op->Dst[0]);
- arg0 = fetch_src( cp, &op->FullSrcRegisters[0] );
+ arg0 = fetch_src( cp, &op->Src[0] );
if (arg0.file == file_XMM) {
struct x86_reg tmp = x86_make_disp(cp->machine_EDX,
Offset(struct aos_machine, tmp[1]));
if (writemask != TGSI_WRITEMASK_XYZW) {
store_dest( cp,
- &op->FullDstRegisters[0],
+ &op->Dst[0],
get_xmm_writable( cp, result ) );
}
#if 0
static boolean emit_inline_LIT( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg dst = get_dst_ptr(cp, &op->FullDstRegisters[0]);
- unsigned writemask = op->FullDstRegisters[0].DstRegister.WriteMask;
+ struct x86_reg dst = get_dst_ptr(cp, &op->Dst[0]);
+ unsigned writemask = op->Dst[0].DstRegister.WriteMask;
if (writemask & TGSI_WRITEMASK_YZ) {
struct x86_reg st1 = x86_make_reg(file_x87, 1);
*/
x87_fldz(cp->func); /* 1 0 */
#endif
- x87_fld_src(cp, &op->FullSrcRegisters[0], 1); /* a1 1 0 */
+ x87_fld_src(cp, &op->Src[0], 1); /* a1 1 0 */
x87_fcomi(cp->func, st2); /* a1 1 0 */
x87_fcmovb(cp->func, st1); /* a1' 1 0 */
x87_fstp(cp->func, st1); /* a1' 0 */
x87_fstp(cp->func, st1); /* a1' */
- x87_fld_src(cp, &op->FullSrcRegisters[0], 3); /* a3 a1' */
+ x87_fld_src(cp, &op->Src[0], 3); /* a3 a1' */
x87_fxch(cp->func, st1); /* a1' a3 */
/* a0' = max2(a0, 0):
*/
x87_fldz(cp->func); /* 0 r2 */
- x87_fld_src(cp, &op->FullSrcRegisters[0], 0); /* a0 0 r2 */
+ x87_fld_src(cp, &op->Src[0], 0); /* a0 0 r2 */
x87_fcomi(cp->func, st1);
x87_fcmovb(cp->func, st1); /* a0' 0 r2 */
static boolean emit_MAX( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_maxps(cp->func, dst, arg1);
- store_dest(cp, &op->FullDstRegisters[0], dst);
+ store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_MIN( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_minps(cp->func, dst, arg1);
- store_dest(cp, &op->FullDstRegisters[0], dst);
+ store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_MOV( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
/* potentially nothing to do */
- store_dest(cp, &op->FullDstRegisters[0], dst);
+ store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_MUL( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_mulps(cp->func, dst, arg1);
- store_dest(cp, &op->FullDstRegisters[0], dst);
+ store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_MAD( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
- struct x86_reg arg2 = fetch_src(cp, &op->FullSrcRegisters[2]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
+ struct x86_reg arg2 = fetch_src(cp, &op->Src[2]);
/* If we can't clobber old contents of arg0, get a temporary & copy
* it there, then clobber it...
sse_mulps(cp->func, arg0, arg1);
sse_addps(cp->func, arg0, arg2);
- store_dest(cp, &op->FullDstRegisters[0], arg0);
+ store_dest(cp, &op->Dst[0], arg0);
return TRUE;
}
static boolean emit_POW( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
#if 0
- x87_fld_src(cp, &op->FullSrcRegisters[1], 0); /* a1.x */
- x87_fld_src(cp, &op->FullSrcRegisters[0], 0); /* a0.x a1.x */
+ x87_fld_src(cp, &op->Src[1], 0); /* a1.x */
+ x87_fld_src(cp, &op->Src[0], 0); /* a0.x a1.x */
x87_fyl2x(cp->func); /* a1*log2(a0) */
x87_emit_ex2( cp ); /* 2^(a1*log2(a0)) */
- x87_fstp_dest4(cp, &op->FullDstRegisters[0]);
+ x87_fstp_dest4(cp, &op->Dst[0]);
#else
uint i;
x86_lea( cp->func, cp->stack_ESP, x86_make_disp(cp->stack_ESP, -8) );
- x87_fld_src( cp, &op->FullSrcRegisters[1], 0 );
+ x87_fld_src( cp, &op->Src[1], 0 );
x87_fstp( cp->func, x86_make_disp( cp->stack_ESP, 4 ) );
- x87_fld_src( cp, &op->FullSrcRegisters[0], 0 );
+ x87_fld_src( cp, &op->Src[0], 0 );
x87_fstp( cp->func, x86_make_disp( cp->stack_ESP, 0 ) );
/* tmp_EAX has been pushed & will be restored below */
*/
cp->func->x87_stack++;
- x87_fstp_dest4( cp, &op->FullDstRegisters[0] );
+ x87_fstp_dest4( cp, &op->Dst[0] );
#endif
return TRUE;
}
x86_lea( cp->func, cp->stack_ESP, x86_make_disp(cp->stack_ESP, -4) );
- x87_fld_src( cp, &op->FullSrcRegisters[0], 0 );
+ x87_fld_src( cp, &op->Src[0], 0 );
x87_fstp( cp->func, x86_make_disp( cp->stack_ESP, 0 ) );
/* tmp_EAX has been pushed & will be restored below */
*/
cp->func->x87_stack++;
- x87_fstp_dest4( cp, &op->FullDstRegisters[0] );
+ x87_fstp_dest4( cp, &op->Dst[0] );
return TRUE;
}
static boolean emit_RCP( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg dst = aos_get_xmm_reg(cp);
if (cp->have_sse2) {
sse_divss(cp->func, dst, arg0);
}
- store_scalar_dest(cp, &op->FullDstRegisters[0], dst);
+ store_scalar_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_RSQ( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
if (0) {
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg r = aos_get_xmm_reg(cp);
sse_rsqrtss(cp->func, r, arg0);
- store_scalar_dest(cp, &op->FullDstRegisters[0], r);
+ store_scalar_dest(cp, &op->Dst[0], r);
return TRUE;
}
else {
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg r = aos_get_xmm_reg(cp);
struct x86_reg neg_half = get_reg_ptr( cp, AOS_FILE_INTERNAL, IMM_RSQ );
sse_addss( cp->func, tmp, one_point_five ); /* 1.5 - .5 * a * r * r */
sse_mulss( cp->func, r, tmp ); /* r * (1.5 - .5 * a * r * r) */
- store_scalar_dest(cp, &op->FullDstRegisters[0], r);
+ store_scalar_dest(cp, &op->Dst[0], r);
aos_release_xmm_reg(cp, tmp.idx);
static boolean emit_SGE( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg ones = aos_get_internal(cp, IMM_ONES);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_cmpps(cp->func, dst, arg1, cc_NotLessThan);
sse_andps(cp->func, dst, ones);
- store_dest(cp, &op->FullDstRegisters[0], dst);
+ store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_SIN( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- x87_fld_src(cp, &op->FullSrcRegisters[0], 0);
+ x87_fld_src(cp, &op->Src[0], 0);
x87_fsin(cp->func);
- x87_fstp_dest4(cp, &op->FullDstRegisters[0]);
+ x87_fstp_dest4(cp, &op->Dst[0]);
return TRUE;
}
static boolean emit_SLT( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg ones = aos_get_internal(cp, IMM_ONES);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_cmpps(cp->func, dst, arg1, cc_LessThan);
sse_andps(cp->func, dst, ones);
- store_dest(cp, &op->FullDstRegisters[0], dst);
+ store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_SUB( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg dst = get_xmm_writable(cp, arg0);
sse_subps(cp->func, dst, arg1);
- store_dest(cp, &op->FullDstRegisters[0], dst);
+ store_dest(cp, &op->Dst[0], dst);
return TRUE;
}
static boolean emit_TRUNC( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
struct x86_reg tmp0 = aos_get_xmm_reg(cp);
sse2_cvttps2dq(cp->func, tmp0, arg0);
sse2_cvtdq2ps(cp->func, tmp0, tmp0);
- store_dest(cp, &op->FullDstRegisters[0], tmp0);
+ store_dest(cp, &op->Dst[0], tmp0);
return TRUE;
}
static boolean emit_XPD( struct aos_compilation *cp, const struct tgsi_full_instruction *op )
{
- struct x86_reg arg0 = fetch_src(cp, &op->FullSrcRegisters[0]);
- struct x86_reg arg1 = fetch_src(cp, &op->FullSrcRegisters[1]);
+ struct x86_reg arg0 = fetch_src(cp, &op->Src[0]);
+ struct x86_reg arg1 = fetch_src(cp, &op->Src[1]);
struct x86_reg tmp0 = aos_get_xmm_reg(cp);
struct x86_reg tmp1 = aos_get_xmm_reg(cp);
aos_release_xmm_reg(cp, tmp0.idx);
- store_dest(cp, &op->FullDstRegisters[0], tmp1);
+ store_dest(cp, &op->Dst[0], tmp1);
return TRUE;
}
continue;
for (i = 0; i < TGSI_FULL_MAX_DST_REGISTERS; i++) {
- if (parse.FullToken.FullInstruction.FullDstRegisters[i].DstRegister.File ==
+ if (parse.FullToken.FullInstruction.Dst[i].DstRegister.File ==
TGSI_FILE_OUTPUT)
{
- unsigned idx = parse.FullToken.FullInstruction.FullDstRegisters[i].DstRegister.Index;
+ unsigned idx = parse.FullToken.FullInstruction.Dst[i].DstRegister.Index;
cp->output_last_write[idx] = this_instruction;
}
}
inputs[3] = 0;
for (int i = 0; i < inst->Instruction.NumSrcRegs; ++i) {
- struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
+ struct tgsi_full_src_register *src = &inst->Src[i];
llvm::Value *val = 0;
llvm::Value *indIdx = 0;
/* store results */
for (int i = 0; i < inst->Instruction.NumDstRegs; ++i) {
- struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
+ struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (dst->DstRegister.File == TGSI_FILE_OUTPUT) {
storage->setOutputElement(dst->DstRegister.Index, out, dst->DstRegister.WriteMask);
std::vector< std::vector<llvm::Value*> > inputs(inst->Instruction.NumSrcRegs);
for (int i = 0; i < inst->Instruction.NumSrcRegs; ++i) {
- struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
+ struct tgsi_full_src_register *src = &inst->Src[i];
std::vector<llvm::Value*> val;
llvm::Value *indIdx = 0;
int swizzle = swizzleInt(src);
/* store results */
for (int i = 0; i < inst->Instruction.NumDstRegs; ++i) {
- struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
+ struct tgsi_full_dst_register *dst = &inst->Dst[i];
storage->store((enum tgsi_file_type)dst->DstRegister.File,
dst->DstRegister.Index, out, dst->DstRegister.WriteMask,
instr->getIRBuilder() );
unsigned i;
full_instruction.Instruction = tgsi_default_instruction();
- full_instruction.InstructionPredicate = tgsi_default_instruction_predicate();
- full_instruction.InstructionLabel = tgsi_default_instruction_label();
- full_instruction.InstructionTexture = tgsi_default_instruction_texture();
+ full_instruction.Predicate = tgsi_default_instruction_predicate();
+ full_instruction.Label = tgsi_default_instruction_label();
+ full_instruction.Texture = tgsi_default_instruction_texture();
for( i = 0; i < TGSI_FULL_MAX_DST_REGISTERS; i++ ) {
- full_instruction.FullDstRegisters[i] = tgsi_default_full_dst_register();
+ full_instruction.Dst[i] = tgsi_default_full_dst_register();
}
for( i = 0; i < TGSI_FULL_MAX_SRC_REGISTERS; i++ ) {
- full_instruction.FullSrcRegisters[i] = tgsi_default_full_src_register();
+ full_instruction.Src[i] = tgsi_default_full_src_register();
}
return full_instruction;
size++;
*instruction_predicate =
- tgsi_build_instruction_predicate(full_inst->InstructionPredicate.Index,
- full_inst->InstructionPredicate.Negate,
- full_inst->InstructionPredicate.SwizzleX,
- full_inst->InstructionPredicate.SwizzleY,
- full_inst->InstructionPredicate.SwizzleZ,
- full_inst->InstructionPredicate.SwizzleW,
+ tgsi_build_instruction_predicate(full_inst->Predicate.Index,
+ full_inst->Predicate.Negate,
+ full_inst->Predicate.SwizzleX,
+ full_inst->Predicate.SwizzleY,
+ full_inst->Predicate.SwizzleZ,
+ full_inst->Predicate.SwizzleW,
instruction,
header);
}
if( tgsi_compare_instruction_label(
- full_inst->InstructionLabel,
+ full_inst->Label,
tgsi_default_instruction_label() ) ) {
struct tgsi_instruction_label *instruction_label;
size++;
*instruction_label = tgsi_build_instruction_label(
- full_inst->InstructionLabel.Label,
+ full_inst->Label.Label,
prev_token,
instruction,
header );
}
if( tgsi_compare_instruction_texture(
- full_inst->InstructionTexture,
+ full_inst->Texture,
tgsi_default_instruction_texture() ) ) {
struct tgsi_instruction_texture *instruction_texture;
size++;
*instruction_texture = tgsi_build_instruction_texture(
- full_inst->InstructionTexture.Texture,
+ full_inst->Texture.Texture,
prev_token,
instruction,
header );
}
for( i = 0; i < full_inst->Instruction.NumDstRegs; i++ ) {
- const struct tgsi_full_dst_register *reg = &full_inst->FullDstRegisters[i];
+ const struct tgsi_full_dst_register *reg = &full_inst->Dst[i];
struct tgsi_dst_register *dst_register;
struct tgsi_token *prev_token;
}
for( i = 0; i < full_inst->Instruction.NumSrcRegs; i++ ) {
- const struct tgsi_full_src_register *reg = &full_inst->FullSrcRegisters[i];
+ const struct tgsi_full_src_register *reg = &full_inst->Src[i];
struct tgsi_src_register *src_register;
struct tgsi_token *prev_token;
}
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
- const struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
+ const struct tgsi_full_dst_register *dst = &inst->Dst[i];
if (!first_reg)
CHR( ',' );
}
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
- const struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
+ const struct tgsi_full_src_register *src = &inst->Src[i];
if (!first_reg)
CHR( ',' );
if (inst->Instruction.Texture) {
TXT( ", " );
- ENM( inst->InstructionTexture.Texture, texture_names );
+ ENM( inst->Texture.Texture, texture_names );
}
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_ENDLOOP:
case TGSI_OPCODE_CAL:
TXT( " :" );
- UID( inst->InstructionLabel.Label );
+ UID( inst->Label.Label );
break;
}
}
for( i = 0; i < inst->Instruction.NumDstRegs; i++ ) {
- struct tgsi_full_dst_register *dst = &inst->FullDstRegisters[i];
- struct tgsi_full_dst_register *fd = &fi->FullDstRegisters[i];
+ struct tgsi_full_dst_register *dst = &inst->Dst[i];
+ struct tgsi_full_dst_register *fd = &fi->Dst[i];
EOL();
TXT( "\nFile : " );
}
for( i = 0; i < inst->Instruction.NumSrcRegs; i++ ) {
- struct tgsi_full_src_register *src = &inst->FullSrcRegisters[i];
- struct tgsi_full_src_register *fs = &fi->FullSrcRegisters[i];
+ struct tgsi_full_src_register *src = &inst->Src[i];
+ struct tgsi_full_src_register *fs = &fi->Src[i];
EOL();
TXT( "\nFile : ");
#define TEMP_P0 TGSI_EXEC_TEMP_P0
#define IS_CHANNEL_ENABLED(INST, CHAN)\
- ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
+ ((INST).Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
#define IS_CHANNEL_ENABLED2(INST, CHAN)\
- ((INST).FullDstRegisters[1].DstRegister.WriteMask & (1 << (CHAN)))
+ ((INST).Dst[1].DstRegister.WriteMask & (1 << (CHAN)))
#define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)\
{
uint i, chan;
- uint writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
+ uint writemask = inst->Dst[0].DstRegister.WriteMask;
if (writemask == TGSI_WRITEMASK_X ||
writemask == TGSI_WRITEMASK_Y ||
writemask == TGSI_WRITEMASK_Z ||
/* loop over src regs */
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
- if ((inst->FullSrcRegisters[i].SrcRegister.File ==
- inst->FullDstRegisters[0].DstRegister.File) &&
- (inst->FullSrcRegisters[i].SrcRegister.Index ==
- inst->FullDstRegisters[0].DstRegister.Index)) {
+ if ((inst->Src[i].SrcRegister.File ==
+ inst->Dst[0].DstRegister.File) &&
+ (inst->Src[i].SrcRegister.Index ==
+ inst->Dst[0].DstRegister.Index)) {
/* loop over dest channels */
uint channelsWritten = 0x0;
FOR_EACH_ENABLED_CHANNEL(*inst, chan) {
/* check if we're reading a channel that's been written */
- uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->FullSrcRegisters[i], chan);
+ uint swizzle = tgsi_util_get_full_src_register_swizzle(&inst->Src[i], chan);
if (channelsWritten & (1 << swizzle)) {
return TRUE;
}
switch (chan_index) {
case CHAN_X:
- swizzle = inst->InstructionPredicate.SwizzleX;
+ swizzle = inst->Predicate.SwizzleX;
break;
case CHAN_Y:
- swizzle = inst->InstructionPredicate.SwizzleY;
+ swizzle = inst->Predicate.SwizzleY;
break;
case CHAN_Z:
- swizzle = inst->InstructionPredicate.SwizzleZ;
+ swizzle = inst->Predicate.SwizzleZ;
break;
case CHAN_W:
- swizzle = inst->InstructionPredicate.SwizzleW;
+ swizzle = inst->Predicate.SwizzleW;
break;
default:
assert(0);
return;
}
- assert(inst->InstructionPredicate.Index == 0);
+ assert(inst->Predicate.Index == 0);
- pred = &mach->Predicates[inst->InstructionPredicate.Index].xyzw[swizzle];
+ pred = &mach->Predicates[inst->Predicate.Index].xyzw[swizzle];
- if (inst->InstructionPredicate.Negate) {
+ if (inst->Predicate.Negate) {
for (i = 0; i < QUAD_SIZE; i++) {
if (pred->u[i]) {
execmask &= ~(1 << i);
}
#define FETCH(VAL,INDEX,CHAN)\
- fetch_source (mach, VAL, &inst->FullSrcRegisters[INDEX], CHAN)
+ fetch_source (mach, VAL, &inst->Src[INDEX], CHAN)
#define STORE(VAL,INDEX,CHAN)\
- store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN )
+ store_dest (mach, VAL, &inst->Dst[INDEX], inst, CHAN )
/**
/* unswizzle channel */
swizzle = tgsi_util_get_full_src_register_swizzle (
- &inst->FullSrcRegisters[0],
+ &inst->Src[0],
chan_index);
/* check if the component has not been already tested */
boolean biasLod,
boolean projected)
{
- const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
+ const uint unit = inst->Src[1].SrcRegister.Index;
union tgsi_exec_channel r[4];
uint chan_index;
float lodBias;
/* debug_printf("Sampler %u unit %u\n", sampler, unit); */
- switch (inst->InstructionTexture.Texture) {
+ switch (inst->Texture.Texture) {
case TGSI_TEXTURE_1D:
case TGSI_TEXTURE_SHADOW1D:
exec_txd(struct tgsi_exec_machine *mach,
const struct tgsi_full_instruction *inst)
{
- const uint unit = inst->FullSrcRegisters[3].SrcRegister.Index;
+ const uint unit = inst->Src[3].SrcRegister.Index;
union tgsi_exec_channel r[4];
uint chan_index;
* XXX: This is fake TXD -- the derivatives are not taken into account, yet.
*/
- switch (inst->InstructionTexture.Texture) {
+ switch (inst->Texture.Texture) {
case TGSI_TEXTURE_1D:
case TGSI_TEXTURE_SHADOW1D:
mach->FuncStack[mach->FuncStackTop++] = mach->FuncMask;
/* Finally, jump to the subroutine */
- *pc = inst->InstructionLabel.Label;
+ *pc = inst->Label.Label;
}
break;
copy_token(&inst->Instruction, &token);
if (inst->Instruction.Predicate) {
- next_token(ctx, &inst->InstructionPredicate);
+ next_token(ctx, &inst->Predicate);
}
if (inst->Instruction.Label) {
- next_token( ctx, &inst->InstructionLabel);
+ next_token( ctx, &inst->Label);
}
if (inst->Instruction.Texture) {
- next_token( ctx, &inst->InstructionTexture);
+ next_token( ctx, &inst->Texture);
}
assert( inst->Instruction.NumDstRegs <= TGSI_FULL_MAX_DST_REGISTERS );
for( i = 0; i < inst->Instruction.NumDstRegs; i++ ) {
- next_token( ctx, &inst->FullDstRegisters[i].DstRegister );
+ next_token( ctx, &inst->Dst[i].DstRegister );
/*
* No support for indirect or multi-dimensional addressing.
*/
- assert( !inst->FullDstRegisters[i].DstRegister.Dimension );
+ assert( !inst->Dst[i].DstRegister.Dimension );
- if( inst->FullDstRegisters[i].DstRegister.Indirect ) {
- next_token( ctx, &inst->FullDstRegisters[i].DstRegisterInd );
+ if( inst->Dst[i].DstRegister.Indirect ) {
+ next_token( ctx, &inst->Dst[i].DstRegisterInd );
/*
* No support for indirect or multi-dimensional addressing.
*/
- assert( !inst->FullDstRegisters[i].DstRegisterInd.Dimension );
- assert( !inst->FullDstRegisters[i].DstRegisterInd.Indirect );
+ assert( !inst->Dst[i].DstRegisterInd.Dimension );
+ assert( !inst->Dst[i].DstRegisterInd.Indirect );
}
}
for( i = 0; i < inst->Instruction.NumSrcRegs; i++ ) {
- next_token( ctx, &inst->FullSrcRegisters[i].SrcRegister );
+ next_token( ctx, &inst->Src[i].SrcRegister );
- if( inst->FullSrcRegisters[i].SrcRegister.Indirect ) {
- next_token( ctx, &inst->FullSrcRegisters[i].SrcRegisterInd );
+ if( inst->Src[i].SrcRegister.Indirect ) {
+ next_token( ctx, &inst->Src[i].SrcRegisterInd );
/*
* No support for indirect or multi-dimensional addressing.
*/
- assert( !inst->FullSrcRegisters[i].SrcRegisterInd.Indirect );
- assert( !inst->FullSrcRegisters[i].SrcRegisterInd.Dimension );
+ assert( !inst->Src[i].SrcRegisterInd.Indirect );
+ assert( !inst->Src[i].SrcRegisterInd.Dimension );
}
- if( inst->FullSrcRegisters[i].SrcRegister.Dimension ) {
- next_token( ctx, &inst->FullSrcRegisters[i].SrcRegisterDim );
+ if( inst->Src[i].SrcRegister.Dimension ) {
+ next_token( ctx, &inst->Src[i].SrcRegisterDim );
/*
* No support for multi-dimensional addressing.
*/
- assert( !inst->FullSrcRegisters[i].SrcRegisterDim.Dimension );
+ assert( !inst->Src[i].SrcRegisterDim.Dimension );
- if( inst->FullSrcRegisters[i].SrcRegisterDim.Indirect ) {
- next_token( ctx, &inst->FullSrcRegisters[i].SrcRegisterDimInd );
+ if( inst->Src[i].SrcRegisterDim.Indirect ) {
+ next_token( ctx, &inst->Src[i].SrcRegisterDimInd );
/*
* No support for indirect or multi-dimensional addressing.
*/
- assert( !inst->FullSrcRegisters[i].SrcRegisterInd.Indirect );
- assert( !inst->FullSrcRegisters[i].SrcRegisterInd.Dimension );
+ assert( !inst->Src[i].SrcRegisterInd.Indirect );
+ assert( !inst->Src[i].SrcRegisterInd.Dimension );
}
}
}
struct tgsi_full_instruction
{
struct tgsi_instruction Instruction;
- struct tgsi_instruction_predicate InstructionPredicate;
- struct tgsi_instruction_label InstructionLabel;
- struct tgsi_instruction_texture InstructionTexture;
- struct tgsi_full_dst_register FullDstRegisters[TGSI_FULL_MAX_DST_REGISTERS];
- struct tgsi_full_src_register FullSrcRegisters[TGSI_FULL_MAX_SRC_REGISTERS];
+ struct tgsi_instruction_predicate Predicate;
+ struct tgsi_instruction_label Label;
+ struct tgsi_instruction_texture Texture;
+ struct tgsi_full_dst_register Dst[TGSI_FULL_MAX_DST_REGISTERS];
+ struct tgsi_full_src_register Src[TGSI_FULL_MAX_SRC_REGISTERS];
};
union tgsi_full_token
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)
#define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
- ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
+ ((INST).Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
#define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
struct tgsi_full_instruction *inst, int src_reg, uint chan)
{
const const struct tgsi_full_src_register *src =
- &inst->FullSrcRegisters[src_reg];
+ &inst->Src[src_reg];
int vec;
uint i;
const struct tgsi_full_instruction *inst,
unsigned chan_index)
{
- const struct tgsi_full_dst_register *reg = &inst->FullDstRegisters[0];
+ const struct tgsi_full_dst_register *reg = &inst->Dst[0];
if (is_ppc_vec_temporary_dst(reg)) {
int vec = gen->temps_map[reg->DstRegister.Index][chan_index];
unsigned chan_index,
boolean free_vec)
{
- const struct tgsi_full_dst_register *reg = &inst->FullDstRegisters[0];
+ const struct tgsi_full_dst_register *reg = &inst->Dst[0];
switch (reg->DstRegister.File) {
case TGSI_FILE_OUTPUT:
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
check_register_usage(
ctx,
- inst->FullDstRegisters[i].DstRegister.File,
- inst->FullDstRegisters[i].DstRegister.Index,
+ inst->Dst[i].DstRegister.File,
+ inst->Dst[i].DstRegister.Index,
"destination",
FALSE );
}
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
check_register_usage(
ctx,
- inst->FullSrcRegisters[i].SrcRegister.File,
- inst->FullSrcRegisters[i].SrcRegister.Index,
+ inst->Src[i].SrcRegister.File,
+ inst->Src[i].SrcRegister.Index,
"source",
- (boolean)inst->FullSrcRegisters[i].SrcRegister.Indirect );
- if (inst->FullSrcRegisters[i].SrcRegister.Indirect) {
+ (boolean)inst->Src[i].SrcRegister.Indirect );
+ if (inst->Src[i].SrcRegister.Indirect) {
uint file;
int index;
- file = inst->FullSrcRegisters[i].SrcRegisterInd.File;
- index = inst->FullSrcRegisters[i].SrcRegisterInd.Index;
+ file = inst->Src[i].SrcRegisterInd.File;
+ index = inst->Src[i].SrcRegisterInd.Index;
check_register_usage(
ctx,
file,
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_BGNFOR:
case TGSI_OPCODE_ENDFOR:
- if (inst->FullDstRegisters[0].DstRegister.File != TGSI_FILE_LOOP ||
- inst->FullDstRegisters[0].DstRegister.Index != 0) {
+ if (inst->Dst[0].DstRegister.File != TGSI_FILE_LOOP ||
+ inst->Dst[0].DstRegister.Index != 0) {
report_error(ctx, "Destination register must be LOOP[0]");
}
break;
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_BGNFOR:
- if (inst->FullSrcRegisters[0].SrcRegister.File != TGSI_FILE_CONSTANT &&
- inst->FullSrcRegisters[0].SrcRegister.File != TGSI_FILE_IMMEDIATE) {
+ if (inst->Src[0].SrcRegister.File != TGSI_FILE_CONSTANT &&
+ inst->Src[0].SrcRegister.File != TGSI_FILE_IMMEDIATE) {
report_error(ctx, "Source register file must be either CONST or IMM");
}
break;
uint i;
for (i = 0; i < fullinst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *src =
- &fullinst->FullSrcRegisters[i];
+ &fullinst->Src[i];
if (src->SrcRegister.File == TGSI_FILE_INPUT) {
const int ind = src->SrcRegister.Index;
if (info->input_semantic_name[ind] == TGSI_SEMANTIC_FOG) {
struct tgsi_full_instruction *fullinst =
&parse.FullToken.FullInstruction;
const struct tgsi_full_src_register *src =
- &fullinst->FullSrcRegisters[0];
+ &fullinst->Src[0];
const struct tgsi_full_dst_register *dst =
- &fullinst->FullDstRegisters[0];
+ &fullinst->Dst[0];
/* Do a whole bunch of checks for a simple move */
if (fullinst->Instruction.Opcode != TGSI_OPCODE_MOV ||
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)
#define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
- ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
+ ((INST).Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
#define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
}
#define FETCH( FUNC, INST, XMM, INDEX, CHAN )\
- emit_fetch( FUNC, XMM, &(INST).FullSrcRegisters[INDEX], CHAN )
+ emit_fetch( FUNC, XMM, &(INST).Src[INDEX], CHAN )
/**
* Register store.
}
#define STORE( FUNC, INST, XMM, INDEX, CHAN )\
- emit_store( FUNC, XMM, &(INST).FullDstRegisters[INDEX], &(INST), CHAN )
+ emit_store( FUNC, XMM, &(INST).Dst[INDEX], &(INST), CHAN )
static void PIPE_CDECL
boolean lodbias,
boolean projected)
{
- const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
+ const uint unit = inst->Src[1].SrcRegister.Index;
struct x86_reg args[2];
unsigned count;
unsigned i;
assert(inst->Instruction.Texture);
- switch (inst->InstructionTexture.Texture) {
+ switch (inst->Texture.Texture) {
case TGSI_TEXTURE_1D:
count = 1;
break;
{
uint i;
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
- const struct tgsi_full_src_register *reg = &inst->FullSrcRegisters[i];
+ const struct tgsi_full_src_register *reg = &inst->Src[i];
if (reg->SrcRegister.File == TGSI_FILE_TEMPORARY &&
reg->SrcRegister.Indirect)
return TRUE;
}
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
- const struct tgsi_full_dst_register *reg = &inst->FullDstRegisters[i];
+ const struct tgsi_full_dst_register *reg = &inst->Dst[i];
if (reg->DstRegister.File == TGSI_FILE_TEMPORARY &&
reg->DstRegister.Indirect)
return TRUE;
case TGSI_OPCODE_KIL:
/* conditional kill */
- emit_kil( func, &inst->FullSrcRegisters[0] );
+ emit_kil( func, &inst->Src[0] );
break;
case TGSI_OPCODE_PK2H:
}
if (i < info->num_dst) {
- if (!parse_dst_operand( ctx, &inst.FullDstRegisters[i] ))
+ if (!parse_dst_operand( ctx, &inst.Dst[i] ))
return FALSE;
}
else if (i < info->num_dst + info->num_src) {
- if (!parse_src_operand( ctx, &inst.FullSrcRegisters[i - info->num_dst] ))
+ if (!parse_src_operand( ctx, &inst.Src[i - info->num_dst] ))
return FALSE;
}
else {
if (str_match_no_case( &ctx->cur, texture_names[j] )) {
if (!is_digit_alpha_underscore( ctx->cur )) {
inst.Instruction.Texture = 1;
- inst.InstructionTexture.Texture = j;
+ inst.Texture.Texture = j;
break;
}
}
return FALSE;
}
inst.Instruction.Label = 1;
- inst.InstructionLabel.Label = target;
+ inst.Label.Label = target;
}
advance = tgsi_build_full_instruction(
*/
for (i = 0; i < 4; ++i) {
inst = vl_inst3(TGSI_OPCODE_DP4, TGSI_FILE_OUTPUT, 0, TGSI_FILE_TEMPORARY, 0, TGSI_FILE_CONSTANT, i);
- inst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
+ inst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
inst = vl_inst2(TGSI_OPCODE_MOV, TGSI_FILE_TEMPORARY, 0, TGSI_FILE_TEMPORARY, 1);
- inst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
- inst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
- inst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
- inst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
+ inst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
+ inst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
+ inst.Src[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
+ inst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
inst = vl_inst2(TGSI_OPCODE_MOV, TGSI_FILE_TEMPORARY, 0, TGSI_FILE_TEMPORARY, 1);
- inst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
- inst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
- inst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
- inst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
+ inst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
+ inst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
+ inst.Src[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
+ inst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
inst = vl_inst2(TGSI_OPCODE_MOV, TGSI_FILE_TEMPORARY, 0, TGSI_FILE_TEMPORARY, 1);
- inst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
- inst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
- inst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
- inst.FullDstRegisters[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
+ inst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
+ inst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
+ inst.Src[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
+ inst.Dst[0].DstRegister.WriteMask = TGSI_WRITEMASK_X << i;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
}
/* lerp t1, c1.x, t1, t2 ; Blend past and future texels */
inst = vl_inst4(TGSI_OPCODE_LRP, TGSI_FILE_TEMPORARY, 1, TGSI_FILE_CONSTANT, 1, TGSI_FILE_TEMPORARY, 1, TGSI_FILE_TEMPORARY, 2);
- inst.FullSrcRegisters[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
- inst.FullSrcRegisters[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
- inst.FullSrcRegisters[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
- inst.FullSrcRegisters[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_X;
+ inst.Src[0].SrcRegister.SwizzleX = TGSI_SWIZZLE_X;
+ inst.Src[0].SrcRegister.SwizzleY = TGSI_SWIZZLE_X;
+ inst.Src[0].SrcRegister.SwizzleZ = TGSI_SWIZZLE_X;
+ inst.Src[0].SrcRegister.SwizzleW = TGSI_SWIZZLE_X;
ti += tgsi_build_full_instruction(&inst, &tokens[ti], header, max_tokens - ti);
/* add o0, t0, t1 ; Add past/future ref and differential to form final output */
inst.Instruction.Opcode = opcode;
inst.Instruction.NumDstRegs = 1;
- inst.FullDstRegisters[0].DstRegister.File = dst_file;
- inst.FullDstRegisters[0].DstRegister.Index = dst_index;
+ inst.Dst[0].DstRegister.File = dst_file;
+ inst.Dst[0].DstRegister.Index = dst_index;
inst.Instruction.NumSrcRegs = 1;
- inst.FullSrcRegisters[0].SrcRegister.File = src_file;
- inst.FullSrcRegisters[0].SrcRegister.Index = src_index;
+ inst.Src[0].SrcRegister.File = src_file;
+ inst.Src[0].SrcRegister.Index = src_index;
return inst;
}
inst.Instruction.Opcode = opcode;
inst.Instruction.NumDstRegs = 1;
- inst.FullDstRegisters[0].DstRegister.File = dst_file;
- inst.FullDstRegisters[0].DstRegister.Index = dst_index;
+ inst.Dst[0].DstRegister.File = dst_file;
+ inst.Dst[0].DstRegister.Index = dst_index;
inst.Instruction.NumSrcRegs = 2;
- inst.FullSrcRegisters[0].SrcRegister.File = src1_file;
- inst.FullSrcRegisters[0].SrcRegister.Index = src1_index;
- inst.FullSrcRegisters[1].SrcRegister.File = src2_file;
- inst.FullSrcRegisters[1].SrcRegister.Index = src2_index;
+ inst.Src[0].SrcRegister.File = src1_file;
+ inst.Src[0].SrcRegister.Index = src1_index;
+ inst.Src[1].SrcRegister.File = src2_file;
+ inst.Src[1].SrcRegister.Index = src2_index;
return inst;
}
inst.Instruction.Opcode = TGSI_OPCODE_TEX;
inst.Instruction.NumDstRegs = 1;
- inst.FullDstRegisters[0].DstRegister.File = dst_file;
- inst.FullDstRegisters[0].DstRegister.Index = dst_index;
+ inst.Dst[0].DstRegister.File = dst_file;
+ inst.Dst[0].DstRegister.Index = dst_index;
inst.Instruction.NumSrcRegs = 2;
inst.Instruction.Texture = 1;
- inst.InstructionTexture.Texture = tex;
- inst.FullSrcRegisters[0].SrcRegister.File = src1_file;
- inst.FullSrcRegisters[0].SrcRegister.Index = src1_index;
- inst.FullSrcRegisters[1].SrcRegister.File = src2_file;
- inst.FullSrcRegisters[1].SrcRegister.Index = src2_index;
+ inst.Texture.Texture = tex;
+ inst.Src[0].SrcRegister.File = src1_file;
+ inst.Src[0].SrcRegister.Index = src1_index;
+ inst.Src[1].SrcRegister.File = src2_file;
+ inst.Src[1].SrcRegister.Index = src2_index;
return inst;
}
inst.Instruction.Opcode = opcode;
inst.Instruction.NumDstRegs = 1;
- inst.FullDstRegisters[0].DstRegister.File = dst_file;
- inst.FullDstRegisters[0].DstRegister.Index = dst_index;
+ inst.Dst[0].DstRegister.File = dst_file;
+ inst.Dst[0].DstRegister.Index = dst_index;
inst.Instruction.NumSrcRegs = 3;
- inst.FullSrcRegisters[0].SrcRegister.File = src1_file;
- inst.FullSrcRegisters[0].SrcRegister.Index = src1_index;
- inst.FullSrcRegisters[1].SrcRegister.File = src2_file;
- inst.FullSrcRegisters[1].SrcRegister.Index = src2_index;
- inst.FullSrcRegisters[2].SrcRegister.File = src3_file;
- inst.FullSrcRegisters[2].SrcRegister.Index = src3_index;
+ inst.Src[0].SrcRegister.File = src1_file;
+ inst.Src[0].SrcRegister.Index = src1_index;
+ inst.Src[1].SrcRegister.File = src2_file;
+ inst.Src[1].SrcRegister.Index = src2_index;
+ inst.Src[2].SrcRegister.File = src3_file;
+ inst.Src[2].SrcRegister.Index = src3_index;
return inst;
}
#define FOR_EACH_ENABLED_CHANNEL(inst, ch) \
for (ch = 0; ch < 4; ch++) \
- if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << ch))
+ if (inst->Dst[0].DstRegister.WriteMask & (1 << ch))
static boolean
{
int ch = 0, src_reg, addr_reg;
- src_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
+ src_reg = get_src_reg(gen, ch, &inst->Src[0]);
addr_reg = get_address_reg(gen);
/* convert float to int */
int ch, src_reg[4], dst_reg[4];
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- src_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- dst_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ src_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ dst_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- if (is_register_src(gen, ch, &inst->FullSrcRegisters[0]) &&
- is_memory_dst(gen, ch, &inst->FullDstRegisters[0])) {
+ if (is_register_src(gen, ch, &inst->Src[0]) &&
+ is_memory_dst(gen, ch, &inst->Dst[0])) {
/* special-case: register to memory store */
- store_dest_reg(gen, src_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, src_reg[ch], ch, &inst->Dst[0]);
}
else {
spe_move(gen->f, dst_reg[ch], src_reg[ch]);
- store_dest_reg(gen, dst_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, dst_reg[ch], ch, &inst->Dst[0]);
}
}
/* Loop over Red/Green/Blue/Alpha channels, fetch src operands */
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- s2_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
- d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ s2_reg[ch] = get_src_reg(gen, ch, &inst->Src[1]);
+ d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
/* Loop over Red/Green/Blue/Alpha channels, do the op, store results */
/* Store the result (a no-op for TGSI_FILE_TEMPORARY dests) */
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
/* Free any intermediate temps we allocated */
int ch, s1_reg[4], s2_reg[4], s3_reg[4], d_reg[4];
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- s2_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
- s3_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
- d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ s2_reg[ch] = get_src_reg(gen, ch, &inst->Src[1]);
+ s3_reg[ch] = get_src_reg(gen, ch, &inst->Src[2]);
+ d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
spe_fma(gen->f, d_reg[ch], s1_reg[ch], s2_reg[ch], s3_reg[ch]);
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
return TRUE;
/* setup/get src/dst/temp regs */
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- s2_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
- s3_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
- d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ s2_reg[ch] = get_src_reg(gen, ch, &inst->Src[1]);
+ s3_reg[ch] = get_src_reg(gen, ch, &inst->Src[2]);
+ d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
tmp_reg[ch] = get_itemp(gen);
}
spe_fma(gen->f, d_reg[ch], tmp_reg[ch], s1_reg[ch], s3_reg[ch]);
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
return TRUE;
int ch, s1_reg[4], d_reg[4], tmp_reg[4];
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
tmp_reg[ch] = get_itemp(gen);
}
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
spe_load_uint(gen->f, bit31mask_reg, (1 << 31));
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
/* d = sign bit cleared in s1 */
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
int s2x_reg, s2y_reg, s2z_reg;
int t0_reg = get_itemp(gen), t1_reg = get_itemp(gen);
- s1x_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
- s2x_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
- s1y_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
- s2y_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
- s1z_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
- s2z_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
+ s1x_reg = get_src_reg(gen, CHAN_X, &inst->Src[0]);
+ s2x_reg = get_src_reg(gen, CHAN_X, &inst->Src[1]);
+ s1y_reg = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
+ s2y_reg = get_src_reg(gen, CHAN_Y, &inst->Src[1]);
+ s1z_reg = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
+ s2z_reg = get_src_reg(gen, CHAN_Z, &inst->Src[1]);
/* t0 = x0 * x1 */
spe_fm(gen->f, t0_reg, s1x_reg, s2x_reg);
spe_fa(gen->f, t0_reg, t0_reg, t1_reg);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
spe_move(gen->f, d_reg, t0_reg);
- store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg, ch, &inst->Dst[0]);
}
free_itemps(gen);
int s1x_reg, s1y_reg, s1z_reg, s1w_reg;
int t0_reg = get_itemp(gen), t1_reg = get_itemp(gen);
- s0x_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
- s1x_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
- s0y_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
- s1y_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
- s0z_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
- s1z_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
- s0w_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[0]);
- s1w_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[1]);
+ s0x_reg = get_src_reg(gen, CHAN_X, &inst->Src[0]);
+ s1x_reg = get_src_reg(gen, CHAN_X, &inst->Src[1]);
+ s0y_reg = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
+ s1y_reg = get_src_reg(gen, CHAN_Y, &inst->Src[1]);
+ s0z_reg = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
+ s1z_reg = get_src_reg(gen, CHAN_Z, &inst->Src[1]);
+ s0w_reg = get_src_reg(gen, CHAN_W, &inst->Src[0]);
+ s1w_reg = get_src_reg(gen, CHAN_W, &inst->Src[1]);
/* t0 = x0 * x1 */
spe_fm(gen->f, t0_reg, s0x_reg, s1x_reg);
spe_fa(gen->f, t0_reg, t0_reg, t1_reg);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
spe_move(gen->f, d_reg, t0_reg);
- store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg, ch, &inst->Dst[0]);
}
free_itemps(gen);
{
/* XXX rewrite this function to look more like DP3/DP4 */
int ch;
- int s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
- int s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
+ int s1_reg = get_src_reg(gen, CHAN_X, &inst->Src[0]);
+ int s2_reg = get_src_reg(gen, CHAN_X, &inst->Src[1]);
int tmp_reg = get_itemp(gen);
/* t = x0 * x1 */
spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
- s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
- s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
+ s1_reg = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
+ s2_reg = get_src_reg(gen, CHAN_Y, &inst->Src[1]);
/* t = y0 * y1 + t */
spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
- s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
- s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
+ s1_reg = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
+ s2_reg = get_src_reg(gen, CHAN_Z, &inst->Src[1]);
/* t = z0 * z1 + t */
spe_fma(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
- s2_reg = get_src_reg(gen, CHAN_W, &inst->FullSrcRegisters[1]);
+ s2_reg = get_src_reg(gen, CHAN_W, &inst->Src[1]);
/* t = w1 + t */
spe_fa(gen->f, tmp_reg, s2_reg, tmp_reg);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
spe_move(gen->f, d_reg, tmp_reg);
- store_dest_reg(gen, tmp_reg, ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, tmp_reg, ch, &inst->Dst[0]);
}
free_itemps(gen);
int src_reg[3];
int t0_reg = get_itemp(gen), t1_reg = get_itemp(gen);
- src_reg[0] = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
- src_reg[1] = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
- src_reg[2] = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
+ src_reg[0] = get_src_reg(gen, CHAN_X, &inst->Src[0]);
+ src_reg[1] = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
+ src_reg[2] = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
/* t0 = x * x */
spe_fm(gen->f, t0_reg, src_reg[0], src_reg[0]);
spe_fi(gen->f, t1_reg, t0_reg, t1_reg);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
/* dst = src[ch] * t1 */
spe_fm(gen->f, d_reg, src_reg[ch], t1_reg);
- store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg, ch, &inst->Dst[0]);
}
free_itemps(gen);
static boolean
emit_XPD(struct codegen *gen, const struct tgsi_full_instruction *inst)
{
- int s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
- int s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
+ int s1_reg = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
+ int s2_reg = get_src_reg(gen, CHAN_Y, &inst->Src[1]);
int tmp_reg = get_itemp(gen);
/* t = z0 * y1 */
spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
- s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
- s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
+ s1_reg = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
+ s2_reg = get_src_reg(gen, CHAN_Z, &inst->Src[1]);
/* t = y0 * z1 - t */
spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
- if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << CHAN_X)) {
- store_dest_reg(gen, tmp_reg, CHAN_X, &inst->FullDstRegisters[0]);
+ if (inst->Dst[0].DstRegister.WriteMask & (1 << CHAN_X)) {
+ store_dest_reg(gen, tmp_reg, CHAN_X, &inst->Dst[0]);
}
- s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
- s2_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[1]);
+ s1_reg = get_src_reg(gen, CHAN_X, &inst->Src[0]);
+ s2_reg = get_src_reg(gen, CHAN_Z, &inst->Src[1]);
/* t = x0 * z1 */
spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
- s1_reg = get_src_reg(gen, CHAN_Z, &inst->FullSrcRegisters[0]);
- s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
+ s1_reg = get_src_reg(gen, CHAN_Z, &inst->Src[0]);
+ s2_reg = get_src_reg(gen, CHAN_X, &inst->Src[1]);
/* t = z0 * x1 - t */
spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
- if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << CHAN_Y)) {
- store_dest_reg(gen, tmp_reg, CHAN_Y, &inst->FullDstRegisters[0]);
+ if (inst->Dst[0].DstRegister.WriteMask & (1 << CHAN_Y)) {
+ store_dest_reg(gen, tmp_reg, CHAN_Y, &inst->Dst[0]);
}
- s1_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[0]);
- s2_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[1]);
+ s1_reg = get_src_reg(gen, CHAN_Y, &inst->Src[0]);
+ s2_reg = get_src_reg(gen, CHAN_X, &inst->Src[1]);
/* t = y0 * x1 */
spe_fm(gen->f, tmp_reg, s1_reg, s2_reg);
- s1_reg = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[0]);
- s2_reg = get_src_reg(gen, CHAN_Y, &inst->FullSrcRegisters[1]);
+ s1_reg = get_src_reg(gen, CHAN_X, &inst->Src[0]);
+ s2_reg = get_src_reg(gen, CHAN_Y, &inst->Src[1]);
/* t = x0 * y1 - t */
spe_fms(gen->f, tmp_reg, s1_reg, s2_reg, tmp_reg);
- if (inst->FullDstRegisters[0].DstRegister.WriteMask & (1 << CHAN_Z)) {
- store_dest_reg(gen, tmp_reg, CHAN_Z, &inst->FullDstRegisters[0]);
+ if (inst->Dst[0].DstRegister.WriteMask & (1 << CHAN_Z)) {
+ store_dest_reg(gen, tmp_reg, CHAN_Z, &inst->Dst[0]);
}
free_itemps(gen);
one_reg = get_const_one_reg(gen);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- s2_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
- d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ s2_reg[ch] = get_src_reg(gen, ch, &inst->Src[1]);
+ d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
int ch;
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- int s1_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- int s2_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
- int s3_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[2]);
- int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ int s1_reg = get_src_reg(gen, ch, &inst->Src[0]);
+ int s2_reg = get_src_reg(gen, ch, &inst->Src[1]);
+ int s3_reg = get_src_reg(gen, ch, &inst->Src[2]);
+ int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
int zero_reg = get_itemp(gen);
spe_zero(gen->f, zero_reg);
spe_fcgt(gen->f, d_reg, zero_reg, s1_reg);
spe_selb(gen->f, d_reg, s3_reg, s2_reg, d_reg);
- store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg, ch, &inst->Dst[0]);
free_itemps(gen);
}
int ch, s1_reg[4], d_reg[4];
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
/* Convert float to int */
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
one_reg = get_const_one_reg(gen);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
tmp_reg[ch] = get_itemp(gen);
}
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
one_reg = get_const_one_reg(gen);
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
tmp_reg[ch] = get_itemp(gen);
}
/* store result */
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
if (scalar) {
for (a = 0; a < num_args; a++) {
- s_regs[a] = get_src_reg(gen, CHAN_X, &inst->FullSrcRegisters[a]);
+ s_regs[a] = get_src_reg(gen, CHAN_X, &inst->Src[a]);
}
/* we'll call the function, put the return value in this register,
* then replicate it across all write-enabled components in d_reg.
if (!scalar) {
for (a = 0; a < num_args; a++) {
- s_regs[a] = get_src_reg(gen, ch, &inst->FullSrcRegisters[a]);
+ s_regs[a] = get_src_reg(gen, ch, &inst->Src[a]);
}
}
- d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
if (!scalar || !func_called) {
/* for a scalar function, we'll really only call the function once */
spe_move(gen->f, d_reg, retval_reg);
}
- store_dest_reg(gen, d_reg, ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg, ch, &inst->Dst[0]);
free_itemps(gen);
}
emit_TEX(struct codegen *gen, const struct tgsi_full_instruction *inst)
{
const uint target = inst->InstructionExtTexture.Texture;
- const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
+ const uint unit = inst->Src[1].SrcRegister.Index;
uint addr;
int ch;
int coord_regs[4], d_regs[4];
return FALSE;
}
- assert(inst->FullSrcRegisters[1].SrcRegister.File == TGSI_FILE_SAMPLER);
+ assert(inst->Src[1].SrcRegister.File == TGSI_FILE_SAMPLER);
spe_comment(gen->f, -4, "CALL tex:");
/* get src/dst reg info */
for (ch = 0; ch < 4; ch++) {
- coord_regs[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- d_regs[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ coord_regs[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ d_regs[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
}
{
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_regs[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_regs[ch], ch, &inst->Dst[0]);
free_itemps(gen);
}
/* get src regs */
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s_regs[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
+ s_regs[ch] = get_src_reg(gen, ch, &inst->Src[0]);
}
/* test if any src regs are < 0 */
int ch, s0_reg[4], s1_reg[4], d_reg[4], tmp_reg[4];
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- s0_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- s1_reg[ch] = get_src_reg(gen, ch, &inst->FullSrcRegisters[1]);
- d_reg[ch] = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ s0_reg[ch] = get_src_reg(gen, ch, &inst->Src[0]);
+ s1_reg[ch] = get_src_reg(gen, ch, &inst->Src[1]);
+ d_reg[ch] = get_dst_reg(gen, ch, &inst->Dst[0]);
tmp_reg[ch] = get_itemp(gen);
}
}
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- store_dest_reg(gen, d_reg[ch], ch, &inst->FullDstRegisters[0]);
+ store_dest_reg(gen, d_reg[ch], ch, &inst->Dst[0]);
}
free_itemps(gen);
/* update conditional execution mask with the predicate register */
int tmp_reg = get_itemp(gen);
- int s1_reg = get_src_reg(gen, channel, &inst->FullSrcRegisters[0]);
+ int s1_reg = get_src_reg(gen, channel, &inst->Src[0]);
/* tmp = (s1_reg == 0) */
spe_ceqi(gen->f, tmp_reg, s1_reg, 0);
int ch;
FOR_EACH_ENABLED_CHANNEL(inst, ch) {
- int s_reg = get_src_reg(gen, ch, &inst->FullSrcRegisters[0]);
- int d_reg = get_dst_reg(gen, ch, &inst->FullDstRegisters[0]);
+ int s_reg = get_src_reg(gen, ch, &inst->Src[0]);
+ int d_reg = get_dst_reg(gen, ch, &inst->Dst[0]);
int t1_reg = get_itemp(gen);
int t2_reg = get_itemp(gen);
for (CHAN = 0; CHAN < 4; CHAN++)
#define IS_CHANNEL_ENABLED(INST, CHAN)\
- ((INST).FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
+ ((INST).Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
#define IS_CHANNEL_ENABLED2(INST, CHAN)\
- ((INST).FullDstRegisters[1].DstRegister.WriteMask & (1 << (CHAN)))
+ ((INST).Dst[1].DstRegister.WriteMask & (1 << (CHAN)))
#define FOR_EACH_ENABLED_CHANNEL(INST, CHAN)\
FOR_EACH_CHANNEL( CHAN )\
}
#define FETCH(VAL,INDEX,CHAN)\
- fetch_source (mach, VAL, &inst->FullSrcRegisters[INDEX], CHAN)
+ fetch_source (mach, VAL, &inst->Src[INDEX], CHAN)
#define STORE(VAL,INDEX,CHAN)\
- store_dest (mach, VAL, &inst->FullDstRegisters[INDEX], inst, CHAN )
+ store_dest (mach, VAL, &inst->Dst[INDEX], inst, CHAN )
/**
/* unswizzle channel */
swizzle = tgsi_util_get_full_src_register_swizzle (
- &inst->FullSrcRegisters[0],
+ &inst->Src[0],
chan_index);
/* check if the component has not been already tested */
const struct tgsi_full_instruction *inst,
boolean biasLod, boolean projected)
{
- const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
+ const uint unit = inst->Src[1].SrcRegister.Index;
union spu_exec_channel r[8];
uint chan_index;
float lodBias;
get_result_flags(const struct tgsi_full_instruction *inst)
{
const uint writeMask
- = inst->FullDstRegisters[0].DstRegister.WriteMask;
+ = inst->Dst[0].DstRegister.WriteMask;
uint flags = 0x0;
if (inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE)
const struct tgsi_full_instruction *inst,
uint opcode)
{
- uint texture = inst->InstructionTexture.Texture;
- uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
+ uint texture = inst->Texture.Texture;
+ uint unit = inst->Src[1].SrcRegister.Index;
uint tex = translate_tex_src_target( p, texture );
uint sampler = i915_emit_decl(p, REG_TYPE_S, unit, tex);
- uint coord = src_vector( p, &inst->FullSrcRegisters[0]);
+ uint coord = src_vector( p, &inst->Src[0]);
i915_emit_texld( p,
- get_result_vector( p, &inst->FullDstRegisters[0] ),
+ get_result_vector( p, &inst->Dst[0] ),
get_result_flags( inst ),
sampler,
coord,
assert(numArgs <= 3);
- arg1 = (numArgs < 1) ? 0 : src_vector( p, &inst->FullSrcRegisters[0] );
- arg2 = (numArgs < 2) ? 0 : src_vector( p, &inst->FullSrcRegisters[1] );
- arg3 = (numArgs < 3) ? 0 : src_vector( p, &inst->FullSrcRegisters[2] );
+ arg1 = (numArgs < 1) ? 0 : src_vector( p, &inst->Src[0] );
+ arg2 = (numArgs < 2) ? 0 : src_vector( p, &inst->Src[1] );
+ arg3 = (numArgs < 3) ? 0 : src_vector( p, &inst->Src[2] );
i915_emit_arith( p,
opcode,
- get_result_vector( p, &inst->FullDstRegisters[0]),
+ get_result_vector( p, &inst->Dst[0]),
get_result_flags( inst ), 0,
arg1,
arg2,
/* transpose first two registers */
inst2 = *inst;
- inst2.FullSrcRegisters[0] = inst->FullSrcRegisters[1];
- inst2.FullSrcRegisters[1] = inst->FullSrcRegisters[0];
+ inst2.Src[0] = inst->Src[1];
+ inst2.Src[1] = inst->Src[0];
emit_simple_arith(p, &inst2, opcode, numArgs);
}
switch (inst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
+ src0 = src_vector(p, &inst->Src[0]);
i915_emit_arith(p,
A0_MAX,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
src0, negate(src0, 1, 1, 1, 1), 0);
break;
break;
case TGSI_OPCODE_CMP:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
- src1 = src_vector(p, &inst->FullSrcRegisters[1]);
- src2 = src_vector(p, &inst->FullSrcRegisters[2]);
+ src0 = src_vector(p, &inst->Src[0]);
+ src1 = src_vector(p, &inst->Src[1]);
+ src2 = src_vector(p, &inst->Src[2]);
i915_emit_arith(p, A0_CMP,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst),
0, src0, src2, src1); /* NOTE: order of src2, src1 */
break;
case TGSI_OPCODE_COS:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
+ src0 = src_vector(p, &inst->Src[0]);
tmp = i915_get_utemp(p);
i915_emit_arith(p,
i915_emit_arith(p,
A0_DP4,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(tmp, ONE, Z, Y, X),
i915_emit_const4fv(p, cos_constants), 0);
break;
case TGSI_OPCODE_DPH:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
- src1 = src_vector(p, &inst->FullSrcRegisters[1]);
+ src0 = src_vector(p, &inst->Src[0]);
+ src1 = src_vector(p, &inst->Src[1]);
i915_emit_arith(p,
A0_DP4,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, X, Y, Z, ONE), src1, 0);
break;
case TGSI_OPCODE_DST:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
- src1 = src_vector(p, &inst->FullSrcRegisters[1]);
+ src0 = src_vector(p, &inst->Src[0]);
+ src1 = src_vector(p, &inst->Src[1]);
/* result[0] = 1 * 1;
* result[1] = a[1] * b[1];
*/
i915_emit_arith(p,
A0_MUL,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, ONE, Y, Z, ONE),
swizzle(src1, ONE, Y, ONE, W), 0);
break;
case TGSI_OPCODE_EX2:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
+ src0 = src_vector(p, &inst->Src[0]);
i915_emit_arith(p,
A0_EXP,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, X, X, X, X), 0, 0);
break;
case TGSI_OPCODE_KIL:
/* kill if src[0].x < 0 || src[0].y < 0 ... */
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
+ src0 = src_vector(p, &inst->Src[0]);
tmp = i915_get_utemp(p);
i915_emit_texld(p,
break;
case TGSI_OPCODE_LG2:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
+ src0 = src_vector(p, &inst->Src[0]);
i915_emit_arith(p,
A0_LOG,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, X, X, X, X), 0, 0);
break;
case TGSI_OPCODE_LIT:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
+ src0 = src_vector(p, &inst->Src[0]);
tmp = i915_get_utemp(p);
/* tmp = max( a.xyzw, a.00zw )
swizzle(tmp, Y, Y, Y, Y), 0, 0);
i915_emit_arith(p, A0_CMP,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
negate(swizzle(tmp, ONE, ONE, X, ONE), 0, 0, 1, 0),
swizzle(tmp, ONE, X, ZERO, ONE),
break;
case TGSI_OPCODE_LRP:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
- src1 = src_vector(p, &inst->FullSrcRegisters[1]);
- src2 = src_vector(p, &inst->FullSrcRegisters[2]);
+ src0 = src_vector(p, &inst->Src[0]);
+ src1 = src_vector(p, &inst->Src[1]);
+ src2 = src_vector(p, &inst->Src[2]);
flags = get_result_flags(inst);
tmp = i915_get_utemp(p);
flags & A0_DEST_CHANNEL_ALL, 0, src1, src0, src2);
i915_emit_arith(p, A0_MAD,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
flags, 0, negate(src2, 1, 1, 1, 1), src0, tmp);
break;
break;
case TGSI_OPCODE_MIN:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
- src1 = src_vector(p, &inst->FullSrcRegisters[1]);
+ src0 = src_vector(p, &inst->Src[0]);
+ src1 = src_vector(p, &inst->Src[1]);
tmp = i915_get_utemp(p);
flags = get_result_flags(inst);
i915_emit_arith(p,
A0_MOV,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
flags, 0, negate(tmp, 1, 1, 1, 1), 0, 0);
break;
break;
case TGSI_OPCODE_POW:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
- src1 = src_vector(p, &inst->FullSrcRegisters[1]);
+ src0 = src_vector(p, &inst->Src[0]);
+ src1 = src_vector(p, &inst->Src[1]);
tmp = i915_get_utemp(p);
flags = get_result_flags(inst);
i915_emit_arith(p,
A0_EXP,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
flags, 0, swizzle(tmp, X, X, X, X), 0, 0);
break;
break;
case TGSI_OPCODE_RCP:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
+ src0 = src_vector(p, &inst->Src[0]);
i915_emit_arith(p,
A0_RCP,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, X, X, X, X), 0, 0);
break;
case TGSI_OPCODE_RSQ:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
+ src0 = src_vector(p, &inst->Src[0]);
i915_emit_arith(p,
A0_RSQ,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, X, X, X, X), 0, 0);
break;
case TGSI_OPCODE_SCS:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
+ src0 = src_vector(p, &inst->Src[0]);
tmp = i915_get_utemp(p);
/*
swizzle(tmp, X, Y, X, Y),
swizzle(tmp, X, X, ONE, ONE), 0);
- writemask = inst->FullDstRegisters[0].DstRegister.WriteMask;
+ writemask = inst->Dst[0].DstRegister.WriteMask;
if (writemask & TGSI_WRITEMASK_Y) {
uint tmp1;
i915_emit_arith(p,
A0_DP4,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
A0_DEST_CHANNEL_Y, 0,
swizzle(tmp1, W, Z, Y, X),
i915_emit_const4fv(p, sin_constants), 0);
i915_emit_arith(p,
A0_DP4,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
A0_DEST_CHANNEL_X, 0,
swizzle(tmp, ONE, Z, Y, X),
i915_emit_const4fv(p, cos_constants), 0);
break;
case TGSI_OPCODE_SIN:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
+ src0 = src_vector(p, &inst->Src[0]);
tmp = i915_get_utemp(p);
i915_emit_arith(p,
i915_emit_arith(p,
A0_DP4,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(tmp, W, Z, Y, X),
i915_emit_const4fv(p, sin_constants), 0);
break;
case TGSI_OPCODE_SUB:
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
- src1 = src_vector(p, &inst->FullSrcRegisters[1]);
+ src0 = src_vector(p, &inst->Src[0]);
+ src1 = src_vector(p, &inst->Src[1]);
i915_emit_arith(p,
A0_ADD,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
src0, negate(src1, 1, 1, 1, 1), 0);
break;
* result.z = src0.x * src1.y - src0.y * src1.x;
* result.w = undef;
*/
- src0 = src_vector(p, &inst->FullSrcRegisters[0]);
- src1 = src_vector(p, &inst->FullSrcRegisters[1]);
+ src0 = src_vector(p, &inst->Src[0]);
+ src1 = src_vector(p, &inst->Src[1]);
tmp = i915_get_utemp(p);
i915_emit_arith(p,
i915_emit_arith(p,
A0_MAD,
- get_result_vector(p, &inst->FullDstRegisters[0]),
+ get_result_vector(p, &inst->Dst[0]),
get_result_flags(inst), 0,
swizzle(src0, Y, Z, X, ONE),
swizzle(src1, Z, X, Y, ONE),
for (CHAN = 0; CHAN < NUM_CHANNELS; CHAN++)
#define IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
- ((INST)->FullDstRegisters[0].DstRegister.WriteMask & (1 << (CHAN)))
+ ((INST)->Dst[0].DstRegister.WriteMask & (1 << (CHAN)))
#define IF_IS_DST0_CHANNEL_ENABLED( INST, CHAN )\
if (IS_DST0_CHANNEL_ENABLED( INST, CHAN ))
unsigned index,
const unsigned chan_index )
{
- const struct tgsi_full_src_register *reg = &inst->FullSrcRegisters[index];
+ const struct tgsi_full_src_register *reg = &inst->Src[index];
unsigned swizzle = tgsi_util_get_full_src_register_swizzle( reg, chan_index );
LLVMValueRef res;
unsigned chan_index,
LLVMValueRef value)
{
- const struct tgsi_full_dst_register *reg = &inst->FullDstRegisters[index];
+ const struct tgsi_full_dst_register *reg = &inst->Dst[index];
switch( inst->Instruction.Saturate ) {
case TGSI_SAT_NONE:
boolean projected,
LLVMValueRef *texel)
{
- const uint unit = inst->FullSrcRegisters[1].SrcRegister.Index;
+ const uint unit = inst->Src[1].SrcRegister.Index;
LLVMValueRef lodbias;
LLVMValueRef oow;
LLVMValueRef coords[3];
unsigned num_coords;
unsigned i;
- switch (inst->InstructionTexture.Texture) {
+ switch (inst->Texture.Texture) {
case TGSI_TEXTURE_1D:
num_coords = 1;
break;
struct lp_build_tgsi_soa_context *bld,
const struct tgsi_full_instruction *inst )
{
- const struct tgsi_full_src_register *reg = &inst->FullSrcRegisters[0];
+ const struct tgsi_full_src_register *reg = &inst->Src[0];
LLVMValueRef terms[NUM_CHANNELS];
LLVMValueRef mask;
unsigned chan_index;
{
uint i;
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
- const struct tgsi_full_src_register *reg = &inst->FullSrcRegisters[i];
+ const struct tgsi_full_src_register *reg = &inst->Src[i];
if (reg->SrcRegister.File == TGSI_FILE_TEMPORARY &&
reg->SrcRegister.Indirect)
return TRUE;
}
for (i = 0; i < inst->Instruction.NumDstRegs; i++) {
- const struct tgsi_full_dst_register *reg = &inst->FullDstRegisters[i];
+ const struct tgsi_full_dst_register *reg = &inst->Dst[i];
if (reg->DstRegister.File == TGSI_FILE_TEMPORARY &&
reg->DstRegister.Indirect)
return TRUE;
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
- fsrc = &finst->FullSrcRegisters[i];
+ fsrc = &finst->Src[i];
if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(vpc, fsrc);
}
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
- fsrc = &finst->FullSrcRegisters[i];
+ fsrc = &finst->Src[i];
switch (fsrc->SrcRegister.File) {
case TGSI_FILE_INPUT:
if (ai == -1 || ai == fsrc->SrcRegister.Index) {
}
}
- dst = tgsi_dst(vpc, &finst->FullDstRegisters[0]);
- mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
+ dst = tgsi_dst(vpc, &finst->Dst[0]);
+ mask = tgsi_mask(finst->Dst[0].DstRegister.WriteMask);
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
- fsrc = &finst->FullSrcRegisters[i];
+ fsrc = &finst->Src[i];
if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(fpc, fsrc);
}
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
- fsrc = &finst->FullSrcRegisters[i];
+ fsrc = &finst->Src[i];
switch (fsrc->SrcRegister.File) {
case TGSI_FILE_INPUT:
}
}
- dst = tgsi_dst(fpc, &finst->FullDstRegisters[0]);
- mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
+ dst = tgsi_dst(fpc, &finst->Dst[0]);
+ mask = tgsi_mask(finst->Dst[0].DstRegister.WriteMask);
sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
switch (finst->Instruction.Opcode) {
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
- fsrc = &finst->FullSrcRegisters[i];
+ fsrc = &finst->Src[i];
if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(vpc, fsrc);
}
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
- fsrc = &finst->FullSrcRegisters[i];
+ fsrc = &finst->Src[i];
switch (fsrc->SrcRegister.File) {
case TGSI_FILE_INPUT:
if (ai == -1 || ai == fsrc->SrcRegister.Index) {
}
}
- dst = tgsi_dst(vpc, &finst->FullDstRegisters[0]);
- mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
+ dst = tgsi_dst(vpc, &finst->Dst[0]);
+ mask = tgsi_mask(finst->Dst[0].DstRegister.WriteMask);
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
- fsrc = &finst->FullSrcRegisters[i];
+ fsrc = &finst->Src[i];
if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(fpc, fsrc);
}
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
- fsrc = &finst->FullSrcRegisters[i];
+ fsrc = &finst->Src[i];
switch (fsrc->SrcRegister.File) {
case TGSI_FILE_INPUT:
}
}
- dst = tgsi_dst(fpc, &finst->FullDstRegisters[0]);
- mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
+ dst = tgsi_dst(fpc, &finst->Dst[0]);
+ mask = tgsi_mask(finst->Dst[0].DstRegister.WriteMask);
sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE);
switch (finst->Instruction.Opcode) {
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
- fsrc = &finst->FullSrcRegisters[i];
+ fsrc = &finst->Src[i];
if (fsrc->SrcRegister.File == TGSI_FILE_TEMPORARY) {
src[i] = tgsi_src(vpc, fsrc);
}
for (i = 0; i < finst->Instruction.NumSrcRegs; i++) {
const struct tgsi_full_src_register *fsrc;
- fsrc = &finst->FullSrcRegisters[i];
+ fsrc = &finst->Src[i];
switch (fsrc->SrcRegister.File) {
case TGSI_FILE_INPUT:
}
}
- dst = tgsi_dst(vpc, &finst->FullDstRegisters[0]);
- mask = tgsi_mask(finst->FullDstRegisters[0].DstRegister.WriteMask);
+ dst = tgsi_dst(vpc, &finst->Dst[0]);
+ mask = tgsi_mask(finst->Dst[0].DstRegister.WriteMask);
switch (finst->Instruction.Opcode) {
case TGSI_OPCODE_ABS:
const struct tgsi_full_dst_register *fdst;
finst = &p.FullToken.FullInstruction;
- fdst = &finst->FullDstRegisters[0];
+ fdst = &finst->Dst[0];
if (fdst->DstRegister.File == TGSI_FILE_ADDRESS) {
if (fdst->DstRegister.Index > high_addr)
for (s = 0; s < insn->Instruction.NumSrcRegs; ++s) {
if (s == i)
continue;
- if ((insn->FullSrcRegisters[s].SrcRegister.Index ==
- insn->FullSrcRegisters[i].SrcRegister.Index) &&
- (insn->FullSrcRegisters[s].SrcRegister.File ==
- insn->FullSrcRegisters[i].SrcRegister.File))
+ if ((insn->Src[s].SrcRegister.Index ==
+ insn->Src[i].SrcRegister.Index) &&
+ (insn->Src[s].SrcRegister.File ==
+ insn->Src[i].SrcRegister.File))
return FALSE;
}
static unsigned
nv50_tgsi_src_mask(const struct tgsi_full_instruction *insn, int c)
{
- unsigned x, mask = insn->FullDstRegisters[0].DstRegister.WriteMask;
+ unsigned x, mask = insn->Dst[0].DstRegister.WriteMask;
switch (insn->Instruction.Opcode) {
case TGSI_OPCODE_COS:
const struct tgsi_instruction_texture *tex;
assert(insn->Instruction.Texture);
- tex = &insn->InstructionTexture;
+ tex = &insn->Texture;
mask = 0x7;
if (insn->Instruction.Opcode == TGSI_OPCODE_TXP)
unsigned mask, sat, unit;
int i, c;
- mask = inst->FullDstRegisters[0].DstRegister.WriteMask;
+ mask = inst->Dst[0].DstRegister.WriteMask;
sat = inst->Instruction.Saturate == TGSI_SAT_ZERO_ONE;
memset(src, 0, sizeof(src));
for (c = 0; c < 4; c++) {
if ((mask & (1 << c)) && !pc->r_dst[c])
- dst[c] = tgsi_dst(pc, c, &inst->FullDstRegisters[0]);
+ dst[c] = tgsi_dst(pc, c, &inst->Dst[0]);
else
dst[c] = pc->r_dst[c];
rdst[c] = dst[c];
}
for (i = 0; i < inst->Instruction.NumSrcRegs; i++) {
- const struct tgsi_full_src_register *fs = &inst->FullSrcRegisters[i];
+ const struct tgsi_full_src_register *fs = &inst->Src[i];
unsigned src_mask;
boolean neg_supp;
break;
case TGSI_OPCODE_TEX:
emit_tex(pc, dst, mask, src[0], unit,
- inst->InstructionTexture.Texture, FALSE);
+ inst->Texture.Texture, FALSE);
break;
case TGSI_OPCODE_TXP:
emit_tex(pc, dst, mask, src[0], unit,
- inst->InstructionTexture.Texture, TRUE);
+ inst->Texture.Texture, TRUE);
break;
case TGSI_OPCODE_TRUNC:
for (c = 0; c < 4; c++) {
const struct tgsi_dst_register *dst;
unsigned i, c, k, mask;
- dst = &insn->FullDstRegisters[0].DstRegister;
+ dst = &insn->Dst[0].DstRegister;
mask = dst->WriteMask;
if (dst->File == TGSI_FILE_TEMPORARY)
}
for (i = 0; i < insn->Instruction.NumSrcRegs; i++) {
- src = &insn->FullSrcRegisters[i];
+ src = &insn->Src[i];
if (src->SrcRegister.File == TGSI_FILE_TEMPORARY)
reg = pc->temp;
nv50_tgsi_scan_swizzle(const struct tgsi_full_instruction *insn,
unsigned rdep[4])
{
- const struct tgsi_full_dst_register *fd = &insn->FullDstRegisters[0];
+ const struct tgsi_full_dst_register *fd = &insn->Dst[0];
const struct tgsi_full_src_register *fs;
unsigned i, deqs = 0;
unsigned chn, mask = nv50_tgsi_src_mask(insn, i);
boolean neg_supp = negate_supported(insn, i);
- fs = &insn->FullSrcRegisters[i];
+ fs = &insn->Src[i];
if (fs->SrcRegister.File != fd->DstRegister.File ||
fs->SrcRegister.Index != fd->DstRegister.Index)
continue;
const struct tgsi_full_dst_register *fd;
unsigned i, deqs, rdep[4], m[4];
- fd = &tok->FullInstruction.FullDstRegisters[0];
+ fd = &tok->FullInstruction.Dst[0];
deqs = nv50_tgsi_scan_swizzle(&insn, rdep);
if (is_scalar_op(insn.Instruction.Opcode)) {
for (i = 0; i < 4; ++i) {
assert(pc->r_dst[m[i]] == NULL);
- insn.FullDstRegisters[0].DstRegister.WriteMask =
+ insn.Dst[0].DstRegister.WriteMask =
fd->DstRegister.WriteMask & (1 << m[i]);
- if (!insn.FullDstRegisters[0].DstRegister.WriteMask)
+ if (!insn.Dst[0].DstRegister.WriteMask)
continue;
if (deqs & (1 << i))
dst->U.I.SaturateMode = translate_saturate(src->Instruction.Saturate);
if (src->Instruction.NumDstRegs)
- transform_dstreg(ttr, &dst->U.I.DstReg, &src->FullDstRegisters[0]);
+ transform_dstreg(ttr, &dst->U.I.DstReg, &src->Dst[0]);
for(i = 0; i < src->Instruction.NumSrcRegs; ++i) {
- if (src->FullSrcRegisters[i].SrcRegister.File == TGSI_FILE_SAMPLER)
- dst->U.I.TexSrcUnit = src->FullSrcRegisters[i].SrcRegister.Index;
+ if (src->Src[i].SrcRegister.File == TGSI_FILE_SAMPLER)
+ dst->U.I.TexSrcUnit = src->Src[i].SrcRegister.Index;
else
- transform_srcreg(ttr, &dst->U.I.SrcReg[i], &src->FullSrcRegisters[i]);
+ transform_srcreg(ttr, &dst->U.I.SrcReg[i], &src->Src[i]);
}
/* Texturing. */
if (src->Instruction.Texture)
- transform_texture(dst, src->InstructionTexture);
+ transform_texture(dst, src->Texture);
}
static void handle_immediate(struct tgsi_to_rc * ttr, struct tgsi_full_immediate * imm)
const struct tgsi_full_instruction *insn,
unsigned idx )
{
- const struct tgsi_full_dst_register *reg = &insn->FullDstRegisters[idx];
+ const struct tgsi_full_dst_register *reg = &insn->Dst[idx];
SVGA3dShaderDestToken dest;
switch (reg->DstRegister.File) {
const struct tgsi_full_instruction *insn)
{
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
struct src_register src1 = get_fake_arl_const( emit );
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
SVGA3dShaderDestToken tmp = get_temp( emit );
const struct tgsi_full_instruction *insn)
{
const struct src_register src = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
struct src_register zero = get_zero_immediate( emit );
SVGA3dShaderInstToken if_token = inst_token( SVGA3DOP_IFC );
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* FRC TMP, SRC */
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
- emit, &insn->FullSrcRegisters[1] );
+ emit, &insn->Src[1] );
const struct src_register src2 = translate_src_register(
- emit, &insn->FullSrcRegisters[2] );
+ emit, &insn->Src[2] );
/* CMP DST, SRC0, SRC2, SRC1 */
return submit_op3( emit, inst_token( SVGA3DOP_CMP ), dst, src0, src2, src1);
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
- emit, &insn->FullSrcRegisters[1] );
+ emit, &insn->Src[1] );
SVGA3dShaderDestToken temp = get_temp( emit );
int i;
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
- emit, &insn->FullSrcRegisters[1] );
+ emit, &insn->Src[1] );
SVGA3dShaderDestToken temp = get_temp( emit );
struct src_register temp_src0, temp_src1;
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
struct src_register src1 = translate_src_register(
- emit, &insn->FullSrcRegisters[1] );
+ emit, &insn->Src[1] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* DP3 TMP, SRC1, SRC2 */
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* DP3 TMP, SRC, SRC */
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* SCS TMP SRC */
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* SCS TMP SRC */
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
SVGA3dShaderDestToken temp = get_temp( emit );
/* SCS TMP SRC */
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
struct src_register src1 = translate_src_register(
- emit, &insn->FullSrcRegisters[1] );
+ emit, &insn->Src[1] );
src1 = negate(src1);
const struct tgsi_full_instruction *insn )
{
SVGA3dShaderInstToken inst;
- const struct tgsi_full_src_register *reg = &insn->FullSrcRegisters[0];
+ const struct tgsi_full_src_register *reg = &insn->Src[0];
struct src_register src0;
inst = inst_token( SVGA3DOP_TEXKILL );
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
struct src_register src1 = translate_src_register(
- emit, &insn->FullSrcRegisters[1] );
+ emit, &insn->Src[1] );
return emit_select( emit, compare, dst, src0, src1 );
}
return FALSE;
}
- src0 = translate_src_register( emit, &insn->FullSrcRegisters[0] );
- src1 = translate_src_register( emit, &insn->FullSrcRegisters[1] );
+ src0 = translate_src_register( emit, &insn->Src[0] );
+ src1 = translate_src_register( emit, &insn->Src[1] );
if (emit->key.fkey.tex[src1.base.num].unnormalized) {
struct src_register wh = get_tex_dimensions( emit, src1.base.num );
break;
}
- src0 = translate_src_register( emit, &insn->FullSrcRegisters[0] );
- src1 = translate_src_register( emit, &insn->FullSrcRegisters[1] );
- src2 = translate_src_register( emit, &insn->FullSrcRegisters[2] );
+ src0 = translate_src_register( emit, &insn->Src[0] );
+ src1 = translate_src_register( emit, &insn->Src[1] );
+ src2 = translate_src_register( emit, &insn->Src[2] );
return submit_op3( emit, inst, dst, src0, src1, src2 );
}
SVGA3dShaderDestToken dst =
translate_dst_register( emit, insn, 0 );
struct src_register src0 =
- translate_src_register( emit, &insn->FullSrcRegisters[0] );
+ translate_src_register( emit, &insn->Src[0] );
struct src_register src1 =
- translate_src_register( emit, &insn->FullSrcRegisters[1] );
+ translate_src_register( emit, &insn->Src[1] );
SVGA3dShaderDestToken tex_result;
inst = inst_token( opcode );
dst = translate_dst_register( emit, insn, 0 );
- src = translate_src_register( emit, &insn->FullSrcRegisters[0] );
+ src = translate_src_register( emit, &insn->Src[0] );
src = scalar( src, TGSI_SWIZZLE_X );
return submit_op1( emit, inst, dst, src );
unsigned opcode,
const struct tgsi_full_instruction *insn )
{
- const struct tgsi_full_src_register *src = insn->FullSrcRegisters;
+ const struct tgsi_full_src_register *src = insn->Src;
SVGA3dShaderInstToken inst;
SVGA3dShaderDestToken dst;
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
struct src_register src1 = translate_src_register(
- emit, &insn->FullSrcRegisters[1] );
+ emit, &insn->Src[1] );
boolean need_tmp = FALSE;
/* POW can only output to a temporary */
- if (insn->FullDstRegisters[0].DstRegister.File != TGSI_FILE_TEMPORARY)
+ if (insn->Dst[0].DstRegister.File != TGSI_FILE_TEMPORARY)
need_tmp = TRUE;
/* POW src1 must not be the same register as dst */
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
- emit, &insn->FullSrcRegisters[1] );
+ emit, &insn->Src[1] );
boolean need_dst_tmp = FALSE;
/* XPD can only output to a temporary */
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
SVGA3dShaderDestToken tmp;
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
- emit, &insn->FullSrcRegisters[1] );
+ emit, &insn->Src[1] );
const struct src_register src2 = translate_src_register(
- emit, &insn->FullSrcRegisters[2] );
+ emit, &insn->Src[2] );
boolean need_dst_tmp = FALSE;
/* The dst reg must not be the same as src0 or src2 */
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
SVGA3dShaderDestToken tmp;
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
const struct src_register src1 = translate_src_register(
- emit, &insn->FullSrcRegisters[1] );
+ emit, &insn->Src[1] );
struct src_register zero = get_zero_immediate( emit );
boolean need_tmp = FALSE;
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 =
- translate_src_register( emit, &insn->FullSrcRegisters[0] );
+ translate_src_register( emit, &insn->Src[0] );
struct src_register zero = get_zero_immediate( emit );
SVGA3dShaderDestToken fraction;
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
SVGA3dShaderDestToken tmp = get_temp( emit );
const struct src_register src0 = translate_src_register(
- emit, &insn->FullSrcRegisters[0] );
+ emit, &insn->Src[0] );
struct src_register zero = get_zero_immediate( emit );
/* tmp = pow(src.y, src.w)
inst = inst_token( SVGA3DOP_EXP );
dst = translate_dst_register( emit, insn, 0 );
- src0 = translate_src_register( emit, &insn->FullSrcRegisters[0] );
+ src0 = translate_src_register( emit, &insn->Src[0] );
src0 = scalar( src0, TGSI_SWIZZLE_X );
if (dst.mask != TGSI_WRITEMASK_XYZW) {
{
SVGA3dShaderDestToken dst = translate_dst_register( emit, insn, 0 );
struct src_register src0 =
- translate_src_register( emit, &insn->FullSrcRegisters[0] );
+ translate_src_register( emit, &insn->Src[0] );
struct src_register zero = get_zero_immediate( emit );
SVGA3dShaderDestToken abs_tmp;
struct src_register abs_src0;
static boolean emit_call( struct svga_shader_emitter *emit,
const struct tgsi_full_instruction *insn )
{
- unsigned position = insn->InstructionLabel.Label;
+ unsigned position = insn->Label.Label;
unsigned i;
for (i = 0; i < emit->nr_labels; i++) {
const struct tgsi_full_instruction *insn,
int current_arl)
{
- if (insn->FullSrcRegisters[0].SrcRegister.Indirect &&
- insn->FullSrcRegisters[0].SrcRegisterInd.File == TGSI_FILE_ADDRESS) {
- const struct tgsi_full_src_register *reg = &insn->FullSrcRegisters[0];
+ if (insn->Src[0].SrcRegister.Indirect &&
+ insn->Src[0].SrcRegisterInd.File == TGSI_FILE_ADDRESS) {
+ const struct tgsi_full_src_register *reg = &insn->Src[0];
if (reg->SrcRegister.Index < 0) {
pre_parse_add_indirect(emit, reg->SrcRegister.Index, current_arl);
}
}
- if (insn->FullSrcRegisters[1].SrcRegister.Indirect &&
- insn->FullSrcRegisters[1].SrcRegisterInd.File == TGSI_FILE_ADDRESS) {
- const struct tgsi_full_src_register *reg = &insn->FullSrcRegisters[1];
+ if (insn->Src[1].SrcRegister.Indirect &&
+ insn->Src[1].SrcRegisterInd.File == TGSI_FILE_ADDRESS) {
+ const struct tgsi_full_src_register *reg = &insn->Src[1];
if (reg->SrcRegister.Index < 0) {
pre_parse_add_indirect(emit, reg->SrcRegister.Index, current_arl);
}
}
- if (insn->FullSrcRegisters[2].SrcRegister.Indirect &&
- insn->FullSrcRegisters[2].SrcRegisterInd.File == TGSI_FILE_ADDRESS) {
- const struct tgsi_full_src_register *reg = &insn->FullSrcRegisters[2];
+ if (insn->Src[2].SrcRegister.Indirect &&
+ insn->Src[2].SrcRegisterInd.File == TGSI_FILE_ADDRESS) {
+ const struct tgsi_full_src_register *reg = &insn->Src[2];
if (reg->SrcRegister.Index < 0) {
pre_parse_add_indirect(emit, reg->SrcRegister.Index, current_arl);
}
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