Added bool constructors to SigBit and SigSpec

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 2f2f7c7047e4fd12aeaffff614906226dead532e..f5dbafe1615f30bcddfe070f70ea7f7e2ecb678b 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -2188,6 +2188,16 @@ RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
        check();
 }
 
+RTLIL::SigSpec::SigSpec(bool bit)
+{
+       cover("kernel.rtlil.sigspec.init.bool");
+
+       width_ = 0;
+       hash_ = 0;
+       append_bit(bit);
+       check();
+}
+
 void RTLIL::SigSpec::pack() const
 {
        RTLIL::SigSpec *that = (RTLIL::SigSpec*)this;

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index a488d3a6b788813a16d1153dc6e21779430c1578..0157f3b7cd6b1321e2c02c3475b7992f4e03f0e5 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -899,6 +899,7 @@ struct RTLIL::SigBit
 
        SigBit() : wire(NULL), data(RTLIL::State::S0) { }
        SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
+       SigBit(bool bit) : wire(NULL), data(bit ? RTLIL::S1 : RTLIL::S0) { }
        SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
        SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); }
        SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; }
@@ -982,6 +983,7 @@ public:
        SigSpec(std::vector<RTLIL::SigChunk> chunks);
        SigSpec(std::vector<RTLIL::SigBit> bits);
        SigSpec(std::set<RTLIL::SigBit> bits);
+       SigSpec(bool bit);
 
        SigSpec(RTLIL::SigSpec &&other) {
                width_ = other.width_;