-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
# are not connected using addTwoLevelCacheHierarchy. Use the
# same clock as the CPUs, and set the L1-to-L2 bus width to 32
# bytes (256 bits).
- system.l2 = l2_cache_class(clock=options.cpu_clock,
+ system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
size=options.l2_size,
assoc=options.l2_assoc,
block_size=options.cacheline_size)
- system.tol2bus = CoherentBus(clock = options.cpu_clock, width = 32)
+ system.tol2bus = CoherentBus(clk_domain = system.cpu_clk_domain,
+ width = 32)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
testsys.cpu[i].max_insts_any_thread = int(options.fast_forward)
switch_cpus[i].system = testsys
switch_cpus[i].workload = testsys.cpu[i].workload
- switch_cpus[i].clock = testsys.cpu[i].clock
+ switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
# simulation period
if options.maxinsts:
switch_cpus[i].max_insts_any_thread = options.maxinsts
for i in xrange(np):
repeat_switch_cpus[i].system = testsys
repeat_switch_cpus[i].workload = testsys.cpu[i].workload
- repeat_switch_cpus[i].clock = testsys.cpu[i].clock
+ repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
if options.maxinsts:
repeat_switch_cpus[i].max_insts_any_thread = options.maxinsts
switch_cpus_1[i].system = testsys
switch_cpus[i].workload = testsys.cpu[i].workload
switch_cpus_1[i].workload = testsys.cpu[i].workload
- switch_cpus[i].clock = testsys.cpu[i].clock
- switch_cpus_1[i].clock = testsys.cpu[i].clock
+ switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
+ switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain
# if restoring, make atomic cpu simulate only a few instructions
if options.checkpoint_restore != None:
-# Copyright (c) 2010-2012 ARM Limited
+# Copyright (c) 2010-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# system under test can be any CPU
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-TestCPUClass.clock = options.cpu_clock
-DriveCPUClass.clock = options.cpu_clock
-
# Match the memories with the CPUs, the driver system always simple,
# and based on the options for the test system
DriveMemClass = SimpleMemory
else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
-test_sys.clock = options.sys_clock
+# Create a source clock for the system and set the clock period
+test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+
+# Create a source clock for the CPUs and set the clock period
+test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
if options.kernel is not None:
test_sys.kernel = binary(options.kernel)
test_sys.init_param = options.init_param
-test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
+# For now, assign all the CPUs to the same clock domain
+test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
+ for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM()
drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
DriveMemClass, bm[1])
- drive_sys.clock = options.sys_clock
+ # Create a source clock for the system and set the clock period
+ drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
+
+ # Create a source clock for the CPUs and set the clock period
+ drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
- drive_sys.cpu = DriveCPUClass(cpu_id=0)
+ drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
+ cpu_id=0)
drive_sys.cpu.createThreads()
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
system = System(funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(latency = "100ns"))
-system.clock = options.sys_clock
+system.clk_domain = SrcClockDomain(clock = options.sys_clock)
def make_level(spec, prototypes, attach_obj, attach_port):
fanout = spec[0]
parent = attach_obj # use attach obj as config parent too
if len(spec) > 1 and (fanout > 1 or options.force_bus):
port = getattr(attach_obj, attach_port)
- new_bus = CoherentBus(clock="500MHz", width=16)
+ new_bus = CoherentBus(width=16)
if (port.role == 'MASTER'):
new_bus.slave = port
attach_port = "master"
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
-system = System(physmem = SimpleMemory())
-system.clock = options.sys_clock
+system = System(physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
+
#
# Create the ruby random tester
#
Ruby.create_system(options, system)
+# Since Ruby runs at an independent frequency, create a seperate clock
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for ruby_port in system.ruby._cpu_ruby_ports:
sys.exit(1)
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-CPUClass.clock = options.cpu_clock
-
TestMemClass = Simulation.setMemClass(options)
if buildEnv['TARGET_ISA'] == "alpha":
else:
fatal("incapable of building non-alpha or non-x86 full system!")
-system.clock = options.sys_clock
+system.clk_domain = SrcClockDomain(clock = options.sys_clock)
if options.kernel is not None:
system.kernel = binary(options.kernel)
system.readfile = options.script
system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
+
+# Create a source clock for the CPUs and set the clock period
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+
Ruby.create_system(options, system, system.piobus, system._dma_ports)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the correct ruby system ports
#
+ cpu.clk_domain = system.cpu_clk_domain
cpu.createThreads()
cpu.createInterruptController()
cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
- physmem = SimpleMemory())
-system.clock = options.sys_clock
+ physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
if options.num_dmas > 0:
dmas = [ MemTest(atomic = False,
dma_ports.append(dma.test)
Ruby.create_system(options, system, dma_ports = dma_ports)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
#
# The tester is most effective when randomization is turned on and
# artifical delay is randomly inserted on messages
# create the desired simulated system
system = System(cpu = cpus,
- physmem = SimpleMemory())
-system.clock = options.sys_clock
+ physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
Ruby.create_system(options, system)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
i = 0
for ruby_port in system.ruby._cpu_ruby_ports:
#
# actually used by the rubytester, but is included to support the
# M5 memory size == Ruby memory size checks
#
-system = System(tester = tester, physmem = SimpleMemory())
-system.clock = options.sys_clock
+system = System(tester = tester, physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
Ruby.create_system(options, system)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
tester.num_cpus = len(system.ruby._cpu_ruby_ports)
-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012-2013 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
-CPUClass.clock = options.cpu_clock
CPUClass.numThreads = numThreads
MemClass = Simulation.setMemClass(options)
np = options.num_cpus
system = System(cpu = [CPUClass(cpu_id=i) for i in xrange(np)],
physmem = MemClass(range=AddrRange("512MB")),
- mem_mode = test_mem_mode)
-system.clock = options.sys_clock
+ mem_mode = test_mem_mode,
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
+
+# Create a separate clock domain for the CPUs
+system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
+
+# All cpus belong to a common cpu_clk_domain, therefore running at a common
+# frequency.
+for cpu in system.cpu:
+ cpu.clk_domain = system.cpu_clk_domain
# Sanity check
if options.fastmem:
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
+ # Run each of the ruby memory controllers at a ratio of the frequency of
+ # the ruby system
+ # clk_divider value is a fix to pass regression.
+ ruby_system.memctrl_clk_domain = DerivedClockDomain(
+ clk_domain=ruby_system.clk_domain,
+ clk_divider=3)
+
for i in xrange(options.num_dirs):
#
# Create the Ruby objects associated with the directory controller
#
- mem_cntrl = RubyMemoryControl(version = i,
- ruby_system = ruby_system)
+ mem_cntrl = RubyMemoryControl(
+ clk_domain = ruby_system.memctrl_clk_domain,
+ version = i,
+ ruby_system = ruby_system)
dir_size = MemorySize('0B')
dir_size.value = mem_module_size
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
+ # Run each of the ruby memory controllers at a ratio of the frequency of
+ # the ruby system.
+ # clk_divider value is a fix to pass regression.
+ ruby_system.memctrl_clk_domain = DerivedClockDomain(
+ clk_domain=ruby_system.clk_domain,
+ clk_divider=3)
+
for i in xrange(options.num_dirs):
#
# Create the Ruby objects associated with the directory controller
#
- mem_cntrl = RubyMemoryControl(version = i,
- ruby_system = ruby_system)
+ mem_cntrl = RubyMemoryControl(
+ clk_domain = ruby_system.memctrl_clk_domain,
+ version = i,
+ ruby_system = ruby_system)
dir_size = MemorySize('0B')
dir_size.value = mem_module_size
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
+ # Run each of the ruby memory controllers at a ratio of the frequency of
+ # the ruby system.
+ # clk_divider value is a fix to pass regression.
+ ruby_system.memctrl_clk_domain = DerivedClockDomain(
+ clk_domain=ruby_system.clk_domain,
+ clk_divider=3)
+
for i in xrange(options.num_dirs):
#
# Create the Ruby objects associated with the directory controller
#
- mem_cntrl = RubyMemoryControl(version = i,
- ruby_system = ruby_system)
+ mem_cntrl = RubyMemoryControl(
+ clk_domain = ruby_system.memctrl_clk_domain,
+ version = i,
+ ruby_system = ruby_system)
dir_size = MemorySize('0B')
dir_size.value = mem_module_size
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
+ # Run each of the ruby memory controllers at a ratio of the frequency of
+ # the ruby system
+ # clk_divider value is a fix to pass regression.
+ ruby_system.memctrl_clk_domain = DerivedClockDomain(
+ clk_domain=ruby_system.clk_domain,
+ clk_divider=3)
+
for i in xrange(options.num_dirs):
#
# Create the Ruby objects associated with the directory controller
#
- mem_cntrl = RubyMemoryControl(version = i,
- ruby_system = ruby_system)
+ mem_cntrl = RubyMemoryControl(
+ clk_domain = ruby_system.memctrl_clk_domain,
+ version = i,
+ ruby_system = ruby_system)
dir_size = MemorySize('0B')
dir_size.value = mem_module_size
else:
pf_start_bit = block_size_bits
+ # Run each of the ruby memory controllers at a ratio of the frequency of
+ # the ruby system
+ # clk_divider value is a fix to pass regression.
+ ruby_system.memctrl_clk_domain = DerivedClockDomain(
+ clk_domain=ruby_system.clk_domain,
+ clk_divider=3)
+
for i in xrange(options.num_dirs):
#
# Create the Ruby objects associated with the directory controller
#
- mem_cntrl = RubyMemoryControl(version = i,
- ruby_system = ruby_system)
+ mem_cntrl = RubyMemoryControl(
+ clk_domain = ruby_system.memctrl_clk_domain,
+ version = i,
+ ruby_system = ruby_system)
dir_size = MemorySize('0B')
dir_size.value = mem_module_size
system.memories.unproxy(system)))
mem_module_size = phys_mem_size / options.num_dirs
+ # Run each of the ruby memory controllers at a ratio of the frequency of
+ # the ruby system.
+ # clk_divider value is a fix to pass regression.
+ ruby_system.memctrl_clk_domain = DerivedClockDomain(
+ clk_domain=ruby_system.clk_domain,
+ clk_divider=3)
+
for i in xrange(options.num_dirs):
#
# Create the Ruby objects associated with the directory controller
#
- mem_cntrl = RubyMemoryControl(version = i,
- ruby_system = ruby_system)
+ mem_cntrl = RubyMemoryControl(
+ clk_domain = ruby_system.memctrl_clk_domain,
+ version = i,
+ ruby_system = ruby_system)
dir_size = MemorySize('0B')
dir_size.value = mem_module_size
def create_system(options, system, piobus = None, dma_ports = []):
- system.ruby = RubySystem(clock = options.ruby_clock,
- stats_filename = options.ruby_stats,
+ system.ruby = RubySystem(stats_filename = options.ruby_stats,
no_mem_vec = options.use_map)
ruby = system.ruby
system_type = 34
system_rev = 1 << 10
- boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+ boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock.frequency,
"boot processor frequency")
class FreebsdAlphaSystem(AlphaSystem):
system_type = 34
system_rev = 1 << 10
- boot_cpu_frequency = Param.Frequency(Self.cpu[0].clock.frequency,
+ boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock.frequency,
"boot processor frequency")
class BareIronMipsSystem(MipsSystem):
from ExeTracer import ExeTracer
from MemObject import MemObject
from BranchPredictor import BranchPredictor
+from ClockDomain import *
default_tracer = ExeTracer()
elif buildEnv['TARGET_ISA'] == 'alpha':
self.interrupts = AlphaInterrupts()
elif buildEnv['TARGET_ISA'] == 'x86':
- self.interrupts = X86LocalApic(clock = Parent.clock * 16,
+ self.apic_clk_domain = DerivedClockDomain(clk_domain =
+ Parent.clk_domain,
+ clk_divider = 16)
+ self.interrupts = X86LocalApic(clk_domain = self.apic_clk_domain,
pio_addr=0x2000000000000000)
_localApic = self.interrupts
elif buildEnv['TARGET_ISA'] == 'mips':
params->max_insts_all_threads = 0;
params->max_loads_any_thread = 0;
params->max_loads_all_threads = 0;
- params->clock = clock;
+ params->clk_domain = clk_domain;
// Hack to touch all parameters. Consider not deriving Checker
// from BaseCPU..it's not really a CPU in the end.
Counter temp;
params->exitOnError = exitOnError;
params->updateOnError = updateOnError;
params->warnOnlyOnLoadError = warnOnlyOnLoadError;
- params->clock = clock;
+ params->clk_domain = clk_domain;
params->tracer = tracer;
// Hack to touch all parameters. Consider not deriving Checker
// from BaseCPU..it's not really a CPU in the end.
"Number of enteries in the rx descriptor cache")
tx_desc_cache_size = Param.Int(64,
"Number of enteries in the rx descriptor cache")
- # Override the default clock
- clock = '500MHz'
VendorID = 0x8086
SubsystemID = 0x1008
SubsystemVendorID = 0x8086
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
- # Override the default clock
- clock = '500MHz'
-
dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
dma_write_delay = Param.Latency('0us', "fixed delay for dma writes")
cxx_header = "mem/ruby/system/RubyMemoryControl.hh"
version = Param.Int("");
- # Override the default clock
- clock = '400MHz'
banks_per_rank = Param.Int(8, "");
ranks_per_dimm = Param.Int(2, "");
dimms_per_channel = Param.Int(2, "");
--- /dev/null
+# Copyright (c) 2013 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Vasileios Spiliopoulos
+# Akash Bagdia
+
+from m5.params import *
+from m5.SimObject import SimObject
+
+# Abstract clock domain
+class ClockDomain(SimObject):
+ type = 'ClockDomain'
+ cxx_header = "sim/clock_domain.hh"
+ abstract = True
+
+# Source clock domain with an actual clock
+class SrcClockDomain(ClockDomain):
+ type = 'SrcClockDomain'
+ cxx_header = "sim/clock_domain.hh"
+ clock = Param.Clock("Clock period")
+
+# Derived clock domain with a parent clock domain and a frequency
+# divider
+class DerivedClockDomain(ClockDomain):
+ type = 'DerivedClockDomain'
+ cxx_header = "sim/clock_domain.hh"
+ clk_domain = Param.ClockDomain("Parent clock domain")
+ clk_divider = Param.Unsigned(1, "Frequency divider")
abstract = True
cxx_header = "sim/clocked_object.hh"
- # Clock period of this object, with the default value being the
- # clock period of the parent object, unproxied at instantiation
- # time
- clock = Param.Clock(Parent.clock, "Clock speed")
+ # The clock domain this clocked object belongs to, inheriting the
+ # parent's clock domain by default
+ clk_domain = Param.ClockDomain(Parent.clk_domain, "Clock domain")
SimObject('ClockedObject.py')
SimObject('Root.py')
SimObject('InstTracer.py')
+SimObject('ClockDomain.py')
Source('arguments.cc')
Source('async.cc')
Source('simulate.cc')
Source('stat_control.cc')
Source('syscall_emul.cc')
+Source('clock_domain.cc')
if env['TARGET_ISA'] != 'no':
SimObject('Process.py')
DebugFlag('Timer')
DebugFlag('VtoPhys')
DebugFlag('WorkItems')
+DebugFlag('ClockDomain')
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Vasileios Spiliopoulos
+ * Akash Bagdia
+ * Andreas Hansson
+ */
+
+#include "debug/ClockDomain.hh"
+#include "params/ClockDomain.hh"
+#include "params/DerivedClockDomain.hh"
+#include "params/SrcClockDomain.hh"
+#include "sim/clock_domain.hh"
+
+SrcClockDomain::SrcClockDomain(const Params *p) : ClockDomain(p)
+{
+ clockPeriod(p->clock);
+}
+
+void
+SrcClockDomain::clockPeriod(Tick clock_period)
+{
+ if (clock_period == 0) {
+ fatal("%s has a clock period of zero\n", name());
+ }
+
+ _clockPeriod = clock_period;
+
+ DPRINTF(ClockDomain,
+ "Setting clock period to %d ticks for source clock %s\n",
+ _clockPeriod, name());
+
+ // inform any derived clocks they need to updated their period
+ for (auto c = children.begin(); c != children.end(); ++c) {
+ (*c)->updateClockPeriod();
+ }
+}
+
+SrcClockDomain *
+SrcClockDomainParams::create()
+{
+ return new SrcClockDomain(this);
+}
+
+DerivedClockDomain::DerivedClockDomain(const Params *p) :
+ ClockDomain(p),
+ parent(*p->clk_domain),
+ clockDivider(p->clk_divider)
+{
+ // Ensure that clock divider setting works as frequency divider and never
+ // work as frequency multiplier
+ if (clockDivider < 1) {
+ fatal("Clock divider param cannot be less than 1");
+ }
+
+ // let the parent keep track of this derived domain so that it can
+ // propagate changes
+ parent.addDerivedDomain(this);
+
+ // update our clock period based on the parents clock
+ updateClockPeriod();
+}
+
+void
+DerivedClockDomain::updateClockPeriod()
+{
+ // recalculate the clock period, relying on the fact that changes
+ // propagate downwards in the tree
+ _clockPeriod = parent.clockPeriod() * clockDivider;
+
+ DPRINTF(ClockDomain,
+ "Setting clock period to %d ticks for derived clock %s\n",
+ _clockPeriod, name());
+
+ // inform any derived clocks
+ for (auto c = children.begin(); c != children.end(); ++c) {
+ (*c)->updateClockPeriod();
+ }
+}
+
+DerivedClockDomain *
+DerivedClockDomainParams::create()
+{
+ return new DerivedClockDomain(this);
+}
--- /dev/null
+/*
+ * Copyright (c) 2013 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Vasileios Spiliopoulos
+ * Akash Bagdia
+ */
+
+/**
+ * @file
+ * ClockDomain declarations.
+ */
+
+#ifndef __SIM_CLOCK_DOMAIN_HH__
+#define __SIM_CLOCK_DOMAIN_HH__
+
+#include "base/statistics.hh"
+#include "params/ClockDomain.hh"
+#include "params/DerivedClockDomain.hh"
+#include "params/SrcClockDomain.hh"
+#include "sim/sim_object.hh"
+
+/**
+ * Forward declaration
+ */
+class DerivedClockDomain;
+
+/**
+ * The ClockDomain provides clock to group of clocked objects bundled
+ * under the same clock domain. The clock domains provide support for
+ * a hierarchial structure with source and derived domains.
+ */
+class ClockDomain : public SimObject
+{
+
+ protected:
+
+ /**
+ * Pre-computed clock period in ticks. This is populated by the
+ * inheriting classes based on how their period is determined.
+ */
+ Tick _clockPeriod;
+
+ /**
+ * Pointers to potential derived clock domains so we can propagate
+ * changes.
+ */
+ std::vector<DerivedClockDomain*> children;
+
+ public:
+
+ typedef ClockDomainParams Params;
+ ClockDomain(const Params *p) : SimObject(p), _clockPeriod(0) {}
+
+ /**
+ * Get the clock period.
+ *
+ * @return Clock period in ticks
+ */
+ inline Tick clockPeriod() const { return _clockPeriod; }
+
+ /**
+ * Add a derived domain.
+ *
+ * @param Derived domain to add as a child
+ */
+ void addDerivedDomain(DerivedClockDomain *clock_domain)
+ { children.push_back(clock_domain); }
+
+};
+
+/**
+ * The source clock domains provides the notion of a clock domain that is
+ * connected to a tunable clock source. It maintains the clock period and
+ * provides methods for setting/getting the clock.
+ */
+class SrcClockDomain : public ClockDomain
+{
+
+ public:
+
+ typedef SrcClockDomainParams Params;
+ SrcClockDomain(const Params *p);
+
+ /**
+ * Set new clock value
+ * @param clock The new clock period in ticks
+ */
+ void clockPeriod(Tick clock_period);
+
+};
+
+/**
+ * The derived clock domains provides the notion of a clock domain
+ * that is connected to a parent clock domain that can either be a
+ * source clock domain or a derived clock domain. It maintains the
+ * clock divider and provides methods for getting the clock.
+ */
+class DerivedClockDomain: public ClockDomain
+{
+
+ public:
+
+ typedef DerivedClockDomainParams Params;
+ DerivedClockDomain(const Params *p);
+
+ /**
+ * Called by the parent clock domain to propagate changes. This
+ * also involves propagating the change further to any children of
+ * the derived domain itself.
+ */
+ void updateClockPeriod();
+
+ private:
+
+ /**
+ * Reference to the parent clock domain this clock domain derives
+ * its clock period from
+ */
+ ClockDomain &parent;
+
+ /**
+ * Local clock divider of the domain
+ */
+ const uint64_t clockDivider;
+};
+
+#endif
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include "base/misc.hh"
#include "params/ClockedObject.hh"
#include "sim/core.hh"
+#include "sim/clock_domain.hh"
#include "sim/sim_object.hh"
/**
// optimise for the common case and see if the tick should be
// advanced by a single clock period
- tick += clock;
+ tick += clockPeriod();
++cycle;
// see if we are done at this point
// if not, we have to recalculate the cycle and tick, we
// perform the calculations in terms of relative cycles to
// allow changes to the clock period in the future
- Cycles elapsedCycles(divCeil(curTick() - tick, clock));
+ Cycles elapsedCycles(divCeil(curTick() - tick, clockPeriod()));
cycle += elapsedCycles;
- tick += elapsedCycles * clock;
+ tick += elapsedCycles * clockPeriod();
}
- // Clock period in ticks
- Tick clock;
+ /**
+ * The clock domain this clocked object belongs to
+ */
+ ClockDomain &clockDomain;
protected:
/**
- * Create a clocked object and set the clock based on the
+ * Create a clocked object and set the clock domain based on the
* parameters.
*/
ClockedObject(const ClockedObjectParams* p) :
- SimObject(p), tick(0), cycle(0), clock(p->clock)
+ SimObject(p), tick(0), cycle(0), clockDomain(*p->clk_domain)
{
- if (clock == 0) {
- fatal("%s has a clock period of zero\n", name());
- }
}
/**
*/
void resetClock() const
{
- Cycles elapsedCycles(divCeil(curTick(), clock));
+ Cycles elapsedCycles(divCeil(curTick(), clockPeriod()));
cycle = elapsedCycles;
- tick = elapsedCycles * clock;
+ tick = elapsedCycles * clockPeriod();
}
public:
update();
// figure out when this future cycle is
- return tick + clock * cycles;
+ return tick + clockPeriod() * cycles;
}
/**
Tick nextCycle() const
{ return clockEdge(Cycles(1)); }
- inline uint64_t frequency() const { return SimClock::Frequency / clock; }
+ inline uint64_t frequency() const
+ {
+ return SimClock::Frequency / clockPeriod();
+ }
- inline Tick clockPeriod() const { return clock; }
+ inline Tick clockPeriod() const
+ {
+ return clockDomain.clockPeriod();
+ }
inline Cycles ticksToCycles(Tick t) const
- { return Cycles(t / clock); }
+ { return Cycles(t / clockPeriod()); }
};
self.num_cpus = num_cpus
self.checker = checker
- def create_cpus(self):
+ def create_cpus(self, cpu_clk_domain):
"""Return a list of CPU objects to add to a system."""
- cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
+ cpus = [ self.cpu_class(clk_domain = cpu_clk_domain,
+ cpu_id=i)
for i in range(self.num_cpus) ]
if self.checker:
for c in cpus:
Returns:
A bus that CPUs should use to connect to the shared cache.
"""
- system.toL2Bus = CoherentBus(clock='2GHz')
- system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
+ system.toL2Bus = CoherentBus(clk_domain=system.cpu_clk_domain)
+ system.l2c = L2Cache(clk_domain=system.cpu_clk_domain,
+ size='4MB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
system.l2c.mem_side = system.membus.slave
return system.toL2Bus
Arguments:
system -- System to initialize.
"""
- system.clock = '1GHz'
- system.cpu = self.create_cpus()
+ self.create_clk_src(system)
+ system.cpu = self.create_cpus(system.cpu_clk_domain)
if _have_kvm_support and \
any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
for cpu in system.cpu:
self.init_cpu(system, cpu, sha_bus)
+ def create_clk_src(self,system):
+ # Create system clock domain. This provides clock value to every
+ # clocked object that lies beneath it unless explicitly overwritten
+ # by a different clock domain.
+ system.clk_domain = SrcClockDomain(clock = '1GHz')
+
+ # Create a seperate clock domain for components that should
+ # run at CPUs frequency
+ system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+
@abstractmethod
def create_system(self):
"""Create an return an initialized system."""
BaseFSSystem.__init__(self, **kwargs)
self.cpu_classes = tuple(cpu_classes)
- def create_cpus(self):
- cpus = [ cclass(cpu_id=0, clock='2GHz', switched_out=True)
+ def create_cpus(self, cpu_clk_domain):
+ cpus = [ cclass(clk_domain = cpu_clk_domain,
+ cpu_id=0,
+ switched_out=True)
for cclass in self.cpu_classes ]
cpus[0].switched_out = False
return cpus
nb_cores = 8
# ruby does not support atomic, functional, or uncacheable accesses
-cpus = [ MemTest(clock = '2GHz', atomic=False, percent_functional=50,
+cpus = [ MemTest(atomic=False, percent_functional=50,
percent_uncacheable=0, suppress_func_warnings=True) \
for i in xrange(nb_cores) ]
system = System(cpu = cpus,
funcmem = SimpleMemory(in_addr_map = False),
physmem = SimpleMemory(null = True),
- funcbus = NoncoherentBus())
-system.clock = options.sys_clock
+ funcbus = NoncoherentBus(),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+
+# All cpus are associated with cpu_clk_domain
+for cpu in cpus:
+ cpu.clk_domain = system.cpu_clk_domain
Ruby.create_system(options, system)
+# Create a separate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
#MAX CORES IS 8 with the fals sharing method
nb_cores = 8
-cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
+cpus = [ MemTest() for i in xrange(nb_cores) ]
# system simulated
system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
funcbus = NoncoherentBus(),
physmem = SimpleMemory(),
- membus = CoherentBus(width=16))
-system.clock = '1GHz'
+ membus = CoherentBus(width=16),
+ clk_domain = SrcClockDomain(clock = '1GHz'))
-# l2cache & bus
-system.toL2Bus = CoherentBus(clock="2GHz", width=16)
-system.l2c = L2Cache(clock = '2GHz', size='64kB', assoc=8)
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
+
+system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16)
+system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
system.l2c.cpu_side = system.toL2Bus.master
# connect l2c to membus
# add L1 caches
for cpu in cpus:
+ # All cpus are associated with cpu_clk_domain
+ cpu.clk_domain = system.cpu_clk_domain
cpu.l1c = L1Cache(size = '32kB', assoc = 4)
cpu.l1c.cpu_side = cpu.test
cpu.l1c.mem_side = system.toL2Bus.slave
# system simulated
system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
- mem_mode = "timing")
-system.clock = '1GHz'
+ mem_mode = "timing",
+ clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
for cpu in cpus:
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus)
- cpu.clock = '2GHz'
+ # All cpus are associated with cpu_clk_domain
+ cpu.clk_domain = system.cpu_clk_domain
# connect memory to membus
system.physmem.port = system.membus.master
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1)
cpu = DerivO3CPU(cpu_id=0)
-cpu.clock = '2GHz'
system = System(cpu = cpu,
physmem = ruby_memory,
membus = CoherentBus(),
- mem_mode = "timing")
-system.clock = '1GHz'
+ mem_mode = "timing",
+ clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
+
system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
#the system
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
- mdesc=mdesc, Ruby=True)
+ mdesc=mdesc, Ruby=True,
+
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
+
Ruby.create_system(options, system, system.piobus, system._dma_ports)
+# Create a seperate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
for (i, cpu) in enumerate(system.cpu):
# create the interrupt controller
cpu.createInterruptController()
cpu.interrupts.pio = system.piobus.master
cpu.interrupts.int_master = system.piobus.slave
cpu.interrupts.int_slave = system.piobus.master
- cpu.clock = '2GHz'
# Set access_phys_mem to True for ruby port
system.ruby._cpu_ruby_ports[i].access_phys_mem = True
tester = RubyTester(check_flush = check_flush, checks_to_complete = 100,
wakeup_frequency = 10, num_cpus = options.num_cpus)
-system = System(tester = tester, physmem = SimpleMemory(null = True))
-system.clock = options.sys_clock
+system = System(tester = tester, physmem = SimpleMemory(null = True),
+ clk_domain = SrcClockDomain(clock = options.sys_clock))
Ruby.create_system(options, system)
+# Create a separate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = '1GHz')
+
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
#
ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
# system simulated
-system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus())
-system.clock = '1GHz'
+system = System(cpu = cpus, physmem = ruby_memory, membus = CoherentBus(),
+ clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
# add L1 caches
for cpu in cpus:
cpu.connectAllPorts(system.membus)
- cpu.clock = '2GHz'
+ # All cpus are associated with cpu_clk_domain
+ cpu.clk_domain = system.cpu_clk_domain
# connect memory to membus
system.physmem.port = system.membus.master
options.num_cpus = nb_cores
# system simulated
-system = System(cpu = cpus, physmem = SimpleMemory())
-system.clock = options.sys_clock
+system = System(cpu = cpus, physmem = SimpleMemory(),
+ clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
Ruby.create_system(options, system)
+# Create a separate clock domain for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(system.cpu):
options.num_cpus = 1
cpu = TimingSimpleCPU(cpu_id=0)
-system = System(cpu = cpu, physmem = SimpleMemory(null = True))
-system.clock = options.sys_clock
+system = System(cpu = cpu, physmem = SimpleMemory(null = True),
+ clk_domain = SrcClockDomain(clock = '1GHz'))
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
Ruby.create_system(options, system)
+# Create a separate clock for Ruby
+system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock)
+
assert(len(system.ruby._cpu_ruby_ports) == 1)
# create the interrupt controller
# system simulated
system = System(cpu = cpu, physmem = DDR3_1600_x64(),
- membus = NoncoherentBus(width = 16))
-system.clock = '1GHz'
+ membus = NoncoherentBus(width = 16),
+ clk_domain = SrcClockDomain(clock = '1GHz'))
# add a communication monitor
system.monitor = CommMonitor()
# system simulated
system = System(cpu = cpu, physmem = SimpleMemory(),
- membus = NoncoherentBus(width = 16))
-system.clock = '1GHz'
+ membus = NoncoherentBus(width = 16),
+ clk_domain = SrcClockDomain(clock = '1GHz'))
# add a communication monitor, and also trace all the packets
system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")
test_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
SysConfig('netperf-stream-client.rcS'))
-test_sys.clock = '1GHz'
+
+# Create the system clock domain
+test_sys.clk_domain = SrcClockDomain(clock = '1GHz')
+
test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
test_sys.cpu.createInterruptController()
test_sys.cpu.connectAllPorts(test_sys.membus)
-test_sys.cpu.clock = '2GHz'
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+test_sys.cpu.clk_domain = SrcClockDomain(clock = '2GHz')
+
+# Create a separate clock domain for Ethernet
+test_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz')
+
# In contrast to the other (one-system) Tsunami configurations we do
# not have an IO cache but instead rely on an IO bridge for accesses
# from masters on the IO bus to the memory bus
drive_sys = makeLinuxAlphaSystem('atomic', SimpleMemory,
SysConfig('netperf-server.rcS'))
-drive_sys.clock = '1GHz'
+# Create the system clock domain
+drive_sys.clk_domain = SrcClockDomain(clock = '1GHz')
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus)
-drive_sys.cpu.clock = '4GHz'
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+drive_sys.cpu.clk_domain = SrcClockDomain(clock = '4GHz')
+
+# Create a separate clock domain for Ethernet
+drive_sys.tsunami.ethernet.clk_domain = SrcClockDomain(clock = '500MHz')
+
drive_sys.iobridge = Bridge(delay='50ns', ranges = drive_sys.mem_ranges)
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave
projects / gem5.git / commitdiff