iris: bit of SBA code

genxml MOCS is stupid, addresses are hard news at 11

diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h
index 109e5b95e7e7a46c8213f1a1cdd14df677454f2f..d502682c7f625357f3c6d399e995d5511ecbbf32 100644 (file)
--- a/src/gallium/drivers/iris/iris_context.h
+++ b/src/gallium/drivers/iris/iris_context.h
@@ -71,6 +71,7 @@ enum iris_dirty {
    IRIS_DIRTY_GS                       = (1ull << 31),
    IRIS_DIRTY_FS                       = (1ull << 32),
    IRIS_DIRTY_CS                       = (1ull << 33),
+   IRIS_DIRTY_STATE_BASE_ADDRESS       = (1ull << 34),
 };
 
 struct iris_depth_stencil_alpha_state;
@@ -140,6 +141,9 @@ void iris_init_resource_functions(struct pipe_context *ctx);
 void iris_init_state_functions(struct pipe_context *ctx);
 void iris_init_query_functions(struct pipe_context *ctx);
 
+void iris_setup_state_base_address(struct iris_context *ice,
+                                   struct iris_batch *batch,
+                                   struct iris_bo *instruction_bo);
 void iris_upload_render_state(struct iris_context *ice,
                               struct iris_batch *batch,
                               const struct pipe_draw_info *draw);

diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index 03c42b7d7770e99dc4734a561991aec5d57b35c5..a24ffab51a3322653b79ae52216e12aac1036e9c 100644 (file)
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -248,6 +248,12 @@ translate_fill_mode(unsigned pipe_polymode)
    return map[pipe_polymode];
 }
 
+static struct iris_address
+ro_bo(struct brw_bo *bo, uint32_t offset)
+{
+   return (struct iris_address) { .bo = bo, .offset = offset };
+}
+
 static void
 iris_upload_initial_gpu_state(struct iris_context *ice,
                               struct iris_batch *batch)
@@ -1260,6 +1266,52 @@ iris_set_stream_output_targets(struct pipe_context *ctx,
 {
 }
 
+void
+iris_setup_state_base_address(struct iris_context *ice,
+                              struct iris_batch *batch,
+                              struct iris_bo *instruction_bo)
+{
+   if (ice->state.dirty & IRIS_DIRTY_STATE_BASE_ADDRESS)
+      ice->state.dirty &= ~IRIS_DIRTY_STATE_BASE_ADDRESS;
+      
+   /* XXX: PIPE_CONTROLs */
+
+#if 0
+   iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
+      sba.GeneralStateMemoryObjectControlState            = MOCS_WB;
+      sba.StatelessDataPortAccessMemoryObjectControlState = MOCS_WB;
+      sba.SurfaceStateMemoryObjectControlState            = MOCS_WB;
+      sba.DynamicStateMemoryObjectControlState            = MOCS_WB;
+      sba.IndirectObjectMemoryObjectControlState          = MOCS_WB;
+      sba.InstructionMemoryObjectControlState             = MOCS_WB;
+      sba.BindlessSurfaceStateMemoryObjectControlState    = MOCS_WB;
+
+      sba.GeneralStateBaseAddressModifyEnable   = true;
+      sba.SurfaceStateBaseAddressModifyEnable   = true;
+      sba.DynamicStateBaseAddressModifyEnable   = true;
+      sba.IndirectObjectBaseAddressModifyEnable = true;
+      sba.InstructionBaseAddressModifyEnable    = true;
+      sba.GeneralStateBufferSizeModifyEnable    = true;
+      sba.DynamicStateBufferSizeModifyEnable    = true;
+      sba.BindlessSurfaceStateBaseAddressModifyEnable = true;
+      sba.IndirectObjectBufferSizeModifyEnable  = true;
+      sba.InstructionBuffersizeModifyEnable     = true;
+
+      sba.SurfaceStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
+      sba.DynamicStateBaseAddress = ro_bo(batch->statebuf.bo, 0);
+      sba.IndirectObjectBaseAddress = 0;
+      sba.InstructionBaseAddress = ro_bo(instruction_bo, 0);
+      sba.BindlessSurfaceStateBaseAddress = 0;
+
+      sba.GeneralStateBufferSize = 0xfffff000;
+      sba.DynamicStateBufferSize = ALIGN(MAX_STATE_SIZE, 4096);
+      sba.IndirectObjectBufferSize = 0xfffff000;
+      sba.InstructionBufferSize = ALIGN(ice->shaders.cache.bo->size, 4096);
+      sba.BindlessSurfaceStateSize = 0;
+   }
+#endif
+}
+
 void
 iris_upload_render_state(struct iris_context *ice,
                          struct iris_batch *batch,