x86: also correctly support TEST opcode aliases

Opcodes F6/1 and F7/1 are aliases of F6/0 and F7/0 in all modes. This
complements commit 8b89fe14b5 ("X86: Decode opcode 0x82 as opcode 0x80
in 32-bit mode"), just that here 64-bit mode is also covered.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 5340f8b952bda93e54ccb1ebb8691f2b206684ca..c40140fa87093d1745395f0f133e4aaa5dd51557 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2017-02-24  Jan Beulich  <jbeulich@suse.com>
+
+       * testsuite/gas/i386/opcode.s: Add alternative TEST forms.
+       * testsuite/gas/i386/x86-64-opcode.s: Likewise.
+       * testsuite/gas/i386/opcode.d: Adjust accordingly.
+       * testsuite/gas/i386/opcode-intel.d: Likewise.
+       * testsuite/gas/i386/x86-64-opcode.d: Likewise.
+       * testsuite/gas/i386/ilp32/x86-64-opcode.d: Likewise.
+
 2017-02-24  Sheldon Lobo  <sheldon.lobo@oracle.com>
 
        Test cases for the architecture level aware SPARC ASI work.

diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d b/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d
index 5515f9f619dfa07e8d891073564d0559ee58339d..53893b30c2a65ca89ebac9b5c2fa599be174fe3b 100644 (file)
--- a/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/ilp32/x86-64-opcode.d
@@ -302,4 +302,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    0f 07                   sysret 
 [      ]*[a-f0-9]+:    0f 01 f8                swapgs 
 [      ]*[a-f0-9]+:    66 68 22 22             pushw  \$0x2222
+[      ]*[a-f0-9]+:    f6 c9 01                test   \$(0x)?0*1,%cl
+[      ]*[a-f0-9]+:    66 f7 c9 02 00          test   \$(0x)?0*2,%cx
+[      ]*[a-f0-9]+:    f7 c9 04 00 00 00       test   \$(0x)?0*4,%ecx
+[      ]*[a-f0-9]+:    48 f7 c9 08 00 00 00    test   \$(0x)?0*8,%rcx
 #pass

diff --git a/gas/testsuite/gas/i386/opcode-intel.d b/gas/testsuite/gas/i386/opcode-intel.d
index e924bf940ea859a96d752d2a8a04d25770bf5e2c..404758c2bfce01265285b52d7c08a0ae61d30bbd 100644 (file)
--- a/gas/testsuite/gas/i386/opcode-intel.d
+++ b/gas/testsuite/gas/i386/opcode-intel.d
@@ -601,4 +601,7 @@ Disassembly of section .text:
  +[a-f0-9]+:   82 f3 01                xor    bl,0x1
  +[a-f0-9]+:   82 fb 01                cmp    bl,0x1
  +[a-f0-9]+:   62 f3 7d 08 15 e8 ab    vpextrw eax,xmm5,0xab
+ +[a-f0-9]+:   f6 c9 01                test   cl,(0x)?0*1
+ +[a-f0-9]+:   66 f7 c9 02 00          test   cx,(0x)?0*2
+ +[a-f0-9]+:   f7 c9 04 00 00 00       test   ecx,(0x)?0*4
 #pass

diff --git a/gas/testsuite/gas/i386/opcode.d b/gas/testsuite/gas/i386/opcode.d
index dd898281f44362fcc699c6267aab57a16be38227..c7dc41076a4739108debbfb93819e2fd93fece4c 100644 (file)
--- a/gas/testsuite/gas/i386/opcode.d
+++ b/gas/testsuite/gas/i386/opcode.d
@@ -600,4 +600,7 @@ Disassembly of section .text:
  +[a-f0-9]+:   82 f3 01                xor    \$0x1,%bl
  +[a-f0-9]+:   82 fb 01                cmp    \$0x1,%bl
  +[a-f0-9]+:   62 f3 7d 08 15 e8 ab    vpextrw \$0xab,%xmm5,%eax
+ +[a-f0-9]+:   f6 c9 01                test   \$(0x)?0*1,%cl
+ +[a-f0-9]+:   66 f7 c9 02 00          test   \$(0x)?0*2,%cx
+ +[a-f0-9]+:   f7 c9 04 00 00 00       test   \$(0x)?0*4,%ecx
 #pass

diff --git a/gas/testsuite/gas/i386/opcode.s b/gas/testsuite/gas/i386/opcode.s
index 101085a660e4ae05d3e0cd753ee516e74f63b5c2..64357b53b5b57f8ba3f4c9d5f60c7dc2dda21c2c 100644 (file)
--- a/gas/testsuite/gas/i386/opcode.s
+++ b/gas/testsuite/gas/i386/opcode.s
@@ -600,3 +600,7 @@ foo:
        .byte 0x82, 0xfb, 0x01
 
        .byte 0x62, 0xf3, 0x7d, 0x08, 0x15, 0xe8, 0xab
+
+       .byte 0xf6, 0xc9, 0x01
+       .byte 0x66, 0xf7, 0xc9, 0x02, 0x00
+       .byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00

diff --git a/gas/testsuite/gas/i386/x86-64-opcode.d b/gas/testsuite/gas/i386/x86-64-opcode.d
index d29c2abfbf0dbe715fab438e0955fe17310f1048..a6087e0c455078440d8462fbe354f2b9c7161247 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-opcode.d
+++ b/gas/testsuite/gas/i386/x86-64-opcode.d
@@ -301,4 +301,8 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    0f 07                   sysret 
 [      ]*[a-f0-9]+:    0f 01 f8                swapgs 
 [      ]*[a-f0-9]+:    66 68 22 22             pushw  \$0x2222
+[      ]*[a-f0-9]+:    f6 c9 01                test   \$(0x)?0*1,%cl
+[      ]*[a-f0-9]+:    66 f7 c9 02 00          test   \$(0x)?0*2,%cx
+[      ]*[a-f0-9]+:    f7 c9 04 00 00 00       test   \$(0x)?0*4,%ecx
+[      ]*[a-f0-9]+:    48 f7 c9 08 00 00 00    test   \$(0x)?0*8,%rcx
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-opcode.s b/gas/testsuite/gas/i386/x86-64-opcode.s
index f271da5e1f21585de5203517efee84b625337be4..ffc8b9479bebdb3e53a8e4fd49660dbc1acc6f86 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-opcode.s
+++ b/gas/testsuite/gas/i386/x86-64-opcode.s
@@ -427,3 +427,8 @@
         swapgs                       #  --  --  -- --   0F 01 f8
 
        pushw $0x2222
+
+       .byte 0xf6, 0xc9, 0x01
+       .byte 0x66, 0xf7, 0xc9, 0x02, 0x00
+       .byte 0xf7, 0xc9, 0x04, 0x00, 0x00, 0x00
+       .byte 0x48, 0xf7, 0xc9, 0x08, 0x00, 0x00, 0x00

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 61d35a13ee218ceb12be674698eb8c587a9d609f..2bbe8b8c50006baaf318464bdb705ec9a2da7ae6 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-02-24  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
+
 2017-02-23  Sheldon Lobo <sheldon.lobo@oracle.com>
 
        Add support for associating SPARC ASIs with an architecture level.

diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 108f0e3b236581f236911cb6667683618ba35b8e..2b61d4a10087152b13c0d9632d5f28e5d289d7b8 100644 (file)
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3511,7 +3511,7 @@ static const struct dis386 reg_table[][8] = {
   /* REG_F6 */
   {
     { "testA", { Eb, Ib }, 0 },
-    { Bad_Opcode },
+    { "testA", { Eb, Ib }, 0 },
     { "notA",  { Ebh1 }, 0 },
     { "negA",  { Ebh1 }, 0 },
     { "mulA",  { Eb }, 0 },    /* Don't print the implicit %al register,  */
@@ -3522,7 +3522,7 @@ static const struct dis386 reg_table[][8] = {
   /* REG_F7 */
   {
     { "testQ", { Ev, Iv }, 0 },
-    { Bad_Opcode },
+    { "testQ", { Ev, Iv }, 0 },
     { "notQ",  { Evh1 }, 0 },
     { "negQ",  { Evh1 }, 0 },
     { "mulQ",  { Ev }, 0 },    /* Don't print the implicit register.  */