config: Fix 'learning gem5' configs after SMT push

This patch updates the 'learning gem5' example scripts to match the
recent push of the SMT patches.

diff --git a/configs/learning_gem5/part1/simple.py b/configs/learning_gem5/part1/simple.py
index 8e3fed65850d6fc057cda125b94f7335ee27971c..1249a846444ebcb82ff14d7f75e2f582762ac856 100644 (file)
--- a/configs/learning_gem5/part1/simple.py
+++ b/configs/learning_gem5/part1/simple.py
@@ -70,9 +70,9 @@ system.cpu.createInterruptController()
 # For x86 only, make sure the interrupts are connected to the memory
 # Note: these are directly connected to the memory bus and are not cached
 if m5.defines.buildEnv['TARGET_ISA'] == "x86":
-    system.cpu.interrupts.pio = system.membus.master
-    system.cpu.interrupts.int_master = system.membus.slave
-    system.cpu.interrupts.int_slave = system.membus.master
+    system.cpu.interrupts[0].pio = system.membus.master
+    system.cpu.interrupts[0].int_master = system.membus.slave
+    system.cpu.interrupts[0].int_slave = system.membus.master
 
 # Create a DDR3 memory controller and connect it to the membus
 system.mem_ctrl = DDR3_1600_x64()

diff --git a/configs/learning_gem5/part1/two_level.py b/configs/learning_gem5/part1/two_level.py
index edaeafe79600ab1ec4fd2054e46e12faada3d0da..de012b30e235af2a54fc8e44bff880676b79e4cd 100644 (file)
--- a/configs/learning_gem5/part1/two_level.py
+++ b/configs/learning_gem5/part1/two_level.py
@@ -120,9 +120,9 @@ system.cpu.createInterruptController()
 # For x86 only, make sure the interrupts are connected to the memory
 # Note: these are directly connected to the memory bus and are not cached
 if m5.defines.buildEnv['TARGET_ISA'] == "x86":
-    system.cpu.interrupts.pio = system.membus.master
-    system.cpu.interrupts.int_master = system.membus.slave
-    system.cpu.interrupts.int_slave = system.membus.master
+    system.cpu.interrupts[0].pio = system.membus.master
+    system.cpu.interrupts[0].int_master = system.membus.slave
+    system.cpu.interrupts[0].int_slave = system.membus.master
 
 # Connect the system up to the membus
 system.system_port = system.membus.slave