i965: Totally switch around how we handle nonzero baselevel-first_level.

This has no effect currently, because intel_finalize_mipmap_tree() always
makes mt->first_level == tObj->BaseLevel.

The change I made before to handle it
(b1080cfbdb0a084122fcd662cd27b4748c5598fd) got very close to working, but
after fixing some unrelated bugs in the series, it still left
tex-miplevel-selection producing errors when testing textureLod().  The
problem is that for explicit LODs, the sampler's LOD clamping is ignored,
and only the surface's MIP clamping is respected.  So we need to use
surface mip clamping, which applies on top of the sampler's mip clamping,
so the sampler change gets backed out.

Now actually tested with a non-regressing series producing a non-zero
computed baselevel.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
index 568dcb5e65dadcdce3be56f5b6310f43476e5696..b716d613090fc047bc9b6f55cf7f08189d87255c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c
@@ -202,8 +202,6 @@ static void brw_update_sampler_state(struct brw_context *brw,
    struct gl_context *ctx = &brw->ctx;
    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
    struct gl_texture_object *texObj = texUnit->_Current;
-   struct intel_texture_image *intel_image =
-      intel_texture_image(texObj->Image[0][texObj->BaseLevel]);
    struct gl_sampler_object *gl_sampler = _mesa_get_samplerobj(ctx, unit);
    bool using_nearest = false;
 
@@ -322,13 +320,10 @@ static void brw_update_sampler_state(struct brw_context *brw,
    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 
-   int baselevel = texObj->BaseLevel - intel_image->mt->first_level;
-   sampler->ss0.base_level = U_FIXED(baselevel, 1);
+   sampler->ss0.base_level = U_FIXED(0, 1);
 
-   sampler->ss1.max_lod = U_FIXED(CLAMP(baselevel +
-                                        gl_sampler->MaxLod, 0, 13), 6);
-   sampler->ss1.min_lod = U_FIXED(CLAMP(baselevel +
-                                        gl_sampler->MinLod, 0, 13), 6);
+   sampler->ss1.max_lod = U_FIXED(CLAMP(gl_sampler->MaxLod, 0, 13), 6);
+   sampler->ss1.min_lod = U_FIXED(CLAMP(gl_sampler->MinLod, 0, 13), 6);
 
    /* On Gen6+, the sampler can handle non-normalized texture
     * rectangle coordinates natively

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 066df9d42255799bb43954eabac86e7096103778..4c3eb69716722610273a0d81018d0da2b6c353fe 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -279,7 +279,7 @@ brw_update_texture_surface(struct gl_context *ctx,
 
    surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */
 
-   surf[2] = ((intelObj->_MaxLevel - mt->first_level) << BRW_SURFACE_LOD_SHIFT |
+   surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT |
              (mt->logical_width0 - 1) << BRW_SURFACE_WIDTH_SHIFT |
              (mt->logical_height0 - 1) << BRW_SURFACE_HEIGHT_SHIFT);
 
@@ -288,7 +288,8 @@ brw_update_texture_surface(struct gl_context *ctx,
              (intelObj->mt->region->pitch - 1) <<
              BRW_SURFACE_PITCH_SHIFT);
 
-   surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples);
+   surf[4] = (brw_get_surface_num_multisamples(intelObj->mt->num_samples) |
+              SET_FIELD(tObj->BaseLevel - mt->first_level, BRW_SURFACE_MIN_LOD));
 
    surf[5] = mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
 

diff --git a/src/mesa/drivers/dri/i965/gen7_sampler_state.c b/src/mesa/drivers/dri/i965/gen7_sampler_state.c
index d796fb504992e7a5643b1a49bc9ab8d9083b85d7..968c410345e1b261a785591848d8d1a0a54f55db 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sampler_state.c
@@ -41,8 +41,6 @@ gen7_update_sampler_state(struct brw_context *brw, int unit, int ss_index,
    struct gl_context *ctx = &brw->ctx;
    struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
    struct gl_texture_object *texObj = texUnit->_Current;
-   struct intel_texture_image *intel_image =
-      intel_texture_image(texObj->Image[0][texObj->BaseLevel]);
    struct gl_sampler_object *gl_sampler = _mesa_get_samplerobj(ctx, unit);
    bool using_nearest = false;
 
@@ -153,13 +151,10 @@ gen7_update_sampler_state(struct brw_context *brw, int unit, int ss_index,
    sampler->ss0.lod_preclamp = 1; /* OpenGL mode */
    sampler->ss0.default_color_mode = 0; /* OpenGL/DX10 mode */
 
-   int baselevel = texObj->BaseLevel - intel_image->mt->first_level;
-   sampler->ss0.base_level = U_FIXED(baselevel, 1);
+   sampler->ss0.base_level = U_FIXED(0, 1);
 
-   sampler->ss1.max_lod = U_FIXED(CLAMP(baselevel +
-                                        gl_sampler->MaxLod, 0, 13), 8);
-   sampler->ss1.min_lod = U_FIXED(CLAMP(baselevel +
-                                        gl_sampler->MinLod, 0, 13), 8);
+   sampler->ss1.max_lod = U_FIXED(CLAMP(gl_sampler->MaxLod, 0, 13), 8);
+   sampler->ss1.min_lod = U_FIXED(CLAMP(gl_sampler->MinLod, 0, 13), 8);
 
    /* The sampler can handle non-normalized texture rectangle coordinates
     * natively

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index f0d87ebd4532fab0acfcc64687ca25eff11441f3..89c0055e16c2be5a5f1c9a4790bd1d82d96a8511 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -348,8 +348,10 @@ gen7_update_texture_surface(struct gl_context *ctx,
    surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout);
 
    surf[5] = (SET_FIELD(GEN7_MOCS_L3, GEN7_SURFACE_MOCS) |
+              SET_FIELD(tObj->BaseLevel - mt->first_level,
+                        GEN7_SURFACE_MIN_LOD) |
               /* mip count */
-              (intelObj->_MaxLevel - mt->first_level));
+              (intelObj->_MaxLevel - tObj->BaseLevel));
 
    if (brw->is_haswell) {
       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style