Fix TODOs

diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg
index bcf966a8a042fa990e31e8e9cbd0bb5f6bcbe98a..6b6151564acba25d6f5944116da1e96ec85cc0b2 100644 (file)
--- a/passes/pmgen/xilinx_dsp.pmg
+++ b/passes/pmgen/xilinx_dsp.pmg
@@ -103,11 +103,6 @@ code sigA sigB sigC sigD sigM clock
        }
        else
                sigM = P;
-       // TODO: Check if necessary
-       // This sigM could have no users if downstream $add
-       //   is narrower than $mul result, for example
-       if (sigM.empty())
-               reject;
 
        clock = port(dsp, \CLK, SigBit());
 endcode
@@ -159,16 +154,6 @@ match preAdd
        optional
 endmatch
 
-code sigA sigD
-       // TODO: Check if this is necessary?
-       if (preAdd) {
-               sigA = port(preAdd, \A);
-               sigD = port(preAdd, \B);
-               if (GetSize(sigA) < GetSize(sigD))
-                       std::swap(sigA, sigD);
-       }
-endcode
-
 // (4) If pre-adder was present, find match 'A' input for A2REG
 //     If pre-adder was not present, move ADREG to A2REG
 //     Then match 'A' input for A1REG

diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg
index 38a5a8d24c0375e889462610284d0127e3c79e10..5697ee7370b305b828df94124cba5cfbc0589365 100644 (file)
--- a/passes/pmgen/xilinx_dsp_CREG.pmg
+++ b/passes/pmgen/xilinx_dsp_CREG.pmg
@@ -79,11 +79,6 @@ endcode
 //     (attached to at most two $mux cells that implement clock-enable or
 //      reset functionality, using a subpattern discussed below)
 code argQ ffC ffCcemux ffCrstmux ffCcepol ffCrstpol sigC clock
-       // TODO: Any downside to allowing this?
-       // If this DSP implements an accumulator, do not attempt to match
-       if (sigC == sigP)
-               reject;
-
        argQ = sigC;
        subpattern(in_dffe);
        if (dff) {