use max_count of 16 and clean up

diff --git a/lib/sata/__init__.py b/lib/sata/__init__.py
index b347a324f819bedc32407303182e0dad6b5481ad..de72c7ef440e07e772a84a738ae340f08224df95 100644 (file)
--- a/lib/sata/__init__.py
+++ b/lib/sata/__init__.py
@@ -4,7 +4,7 @@ from lib.sata.transport import SATATransport
 from lib.sata.command import SATACommand
 
 class SATACON(Module):
-       def __init__(self, phy, sector_size=512, max_count=8):
+       def __init__(self, phy, sector_size=512, max_count=16):
                self.sector_size = sector_size
                self.max_count = max_count
 
@@ -12,6 +12,6 @@ class SATACON(Module):
 
                self.link = SATALink(phy)
                self.transport = SATATransport(self.link)
-               self.command = SATACommand(self.transport, sector_size=sector_size, max_count=max_count)
+               self.command = SATACommand(self.transport, sector_size, max_count)
                self.sink, self.source = self.command.sink, self.command.source
 

diff --git a/lib/sata/command/__init__.py b/lib/sata/command/__init__.py
index 97522b99729fa2d7b1ddb728654de0bdb390a84f..9c7e35cf81c273cf87542c6e378cd471d90eca3e 100644 (file)
--- a/lib/sata/command/__init__.py
+++ b/lib/sata/command/__init__.py
@@ -102,7 +102,7 @@ class SATACommandRX(Module):
                ###
 
                cmd_fifo = SyncFIFO(command_rx_cmd_description(32), 2) # Note: ideally depth=1
-               data_fifo = InsertReset(SyncFIFO(command_rx_data_description(32), sector_size*max_count//4, buffered=True))
+               data_fifo = InsertReset(SyncFIFO(command_rx_data_description(32), (sector_size*max_count//4), buffered=True))
                self.submodules += cmd_fifo, data_fifo
 
                def test_type(name):

diff --git a/platforms/kc705.py b/platforms/kc705.py
index 46ebe3673b1f1b2140a0e7ee835099f1ccdeb94d..0dcf075db8acad2e03f6842500c9d3b99157054f 100644 (file)
--- a/platforms/kc705.py
+++ b/platforms/kc705.py
@@ -128,9 +128,9 @@ def Platform(*args, toolchain="vivado", programmer="xc3sprog", **kwargs):
                        except ConstraintError:
                                pass
                        self.add_platform_command("""
-create_clock -name sys_clk -period 5 [get_nets sys_clk]
-create_clock -name sata_rx_clk -period 3.33 [get_nets sata_rx_clk]
-create_clock -name sata_tx_clk -period 3.33 [get_nets sata_tx_clk]
+create_clock -name sys_clk -period 10 [get_nets sys_clk]
+create_clock -name sata_rx_clk -period 6.66 [get_nets sata_rx_clk]
+create_clock -name sata_tx_clk -period 6.66 [get_nets sata_tx_clk]
 
 set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_rx_clk]
 set_false_path -from [get_clocks sys_clk] -to [get_clocks sata_tx_clk]

diff --git a/targets/test.py b/targets/test.py
index b50e19ba4fbf08b9a4a678fe022dccd7888dfa0d..0b6c5a6cedc2bfb40817d93e71560abfb5ad880b 100644 (file)
--- a/targets/test.py
+++ b/targets/test.py
@@ -166,8 +166,8 @@ class TestDesign(UART2WB, AutoCSR):
                UART2WB.__init__(self, platform, clk_freq)
                self.crg = _CRG(platform)
 
-               self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, host=True, speed="SATA2")
-               self.sata_con = SATACON(self.sata_phy, sector_size=512, max_count=8)
+               self.sata_phy = SATAPHY(platform.request("sata_host"), clk_freq, speed="SATA2")
+               self.sata_con = SATACON(self.sata_phy)
 
                self.bist = SATABIST(self.sata_con)