[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning

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+Date: Wed, 29 Apr 2020 08:59:42 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: dep_changed
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: ALU (including IEEE754 16/32/64-bit FPU)
+X-Bugzilla-Version: unspecified
+X-Bugzilla-Keywords: 
+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
+X-Bugzilla-Status: CONFIRMED
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+Message-ID: <bug-132-13-rjPbJdYB54@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning
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