(no commit message)

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index 70ab38d9b0ba6ed07d7c804d094b38c916097718..10b0ebac6f09fc8938240c8fb486bea5f425a90b 100644 (file)
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -163,8 +163,6 @@ into a type of `cmp`.  The CR is stored (and the CR.eq bit tested
 against the `inv` field).
 If the CR.eq bit is equal to `inv` then the Vector is truncated and
 the loop ends.
-Note that when RC1=1 the result elements are never stored, only the CR
-Fields.
 
 VLi is only available as an option when `Rc=0` (or for instructions
 which do not have Rc). When set, the current element is always