soc/integration/soc_sdram: round port.data_width/l2_size to nearest power of 2 when...

With ECC configurations, native port data_width is not necessarily a power of 2.

diff --git a/litex/soc/integration/soc_sdram.py b/litex/soc/integration/soc_sdram.py
index 432de0b26791636f25de0fba4abed490566ee43e..5a80256d8c24c85eda22b76c86ac1a46674c569e 100644 (file)
--- a/litex/soc/integration/soc_sdram.py
+++ b/litex/soc/integration/soc_sdram.py
@@ -1,3 +1,5 @@
+from math import log2
+
 from migen import *
 from migen.genlib.record import *
 
@@ -76,7 +78,9 @@ class SoCSDRAM(SoCCore):
 
         if self.l2_size:
             port = self.sdram.crossbar.get_port()
-            l2_cache = wishbone.Cache(self.l2_size//4, self._wb_sdram, wishbone.Interface(port.dw))
+            port.data_width = 2**int(log2(port.data_width)) # Round to nearest power of 2
+            l2_size         = 2**int(log2(self.l2_size))    # Round to nearest power of 2
+            l2_cache = wishbone.Cache(l2_size//4, self._wb_sdram, wishbone.Interface(port.data_width))
             # XXX Vivado ->2018.2 workaround, Vivado is not able to map correctly our L2 cache.
             # Issue is reported to Xilinx, Remove this if ever fixed by Xilinx...
             from litex.build.xilinx.vivado import XilinxVivadoToolchain