(no commit message)

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 4d74d1fff3bf2496efa2325e46d6634c887cc07d..e89ad5e94281592248bd257636f14668118c99cb 100644 (file)
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -10,10 +10,10 @@ Use of setvl results in changes to the MVL, VL and STATE SPRs. see [[sv/sprs]]
 
 # Format
 
-| 0..5 |6..10|11..15|16.20|21.22.23.24..25|26.....30|31|  name   |
-|------|-----|------|-----|---------------|---------|--|---------|
-| 19   | RT  | RA   |     | XO[0:4]       | XO[5:9] |Rc| XL-Form |
-| 19   | RT  | RA   |imm  | imm //  vs ms | NNNNN   |Rc| setvl   |
+| 0.5|6.10|11.15|16.20|21.....24..25|26.....30|31|  name   |
+|----|----|-----|-----|-------------|---------|--|---------|
+| 19 | RT | RA  |     | XO[0:4]     | XO[5:9] |Rc| XL-Form |
+| 19 | RT | RA  |imm  | i //  vs ms | NNNNN   |Rc| setvl   |
 
 Note that imm spans 7 bits (16 to 22), and that bit 22 is reserved and must be zero.  Setting bit 22 causes an illegal exception.