Remove Constant

diff --git a/milkymist/asmicon/bankmachine.py b/milkymist/asmicon/bankmachine.py
index a2f37a4f66b2a2566a7d549b825f8ed00722658f..2806f046675f5a022a752ef631f95e1ac717f1c2 100644 (file)
--- a/milkymist/asmicon/bankmachine.py
+++ b/milkymist/asmicon/bankmachine.py
@@ -31,7 +31,7 @@ class _AddressSlicer:
                if isinstance(address, int):
                        return (address & (2**self._b1 - 1)) << self.address_align
                else:
-                       return Cat(Constant(0, BV(self.address_align)), address[:self._b1])
+                       return Cat(Replicate(0, self.address_align), address[:self._b1])
 
 class _Selector:
        def __init__(self, slicer, bankn, slots):

diff --git a/milkymist/asmicon/multiplexer.py b/milkymist/asmicon/multiplexer.py
index ac4b2265c9070751984fcd013cc6560c83f23b7d..f8effcaf5bcf9ed257b1dbc0220cb518aef4b005 100644 (file)
--- a/milkymist/asmicon/multiplexer.py
+++ b/milkymist/asmicon/multiplexer.py
@@ -71,7 +71,7 @@ class _Steerer:
                sync = []
                def stb_and(cmd, attr):
                        if not hasattr(cmd, "stb"):
-                               return Constant(0)
+                               return 0
                        else:
                                return cmd.stb & getattr(cmd, attr)
                for phase, sel in zip(self.dfi.phases, self.sel):

diff --git a/milkymist/uart/__init__.py b/milkymist/uart/__init__.py
index e59a2b793b0a7b555b8e0e1b4e7b2d6f5844a923..0dfa1dd3275288bafde8baa9242e60b512bce279 100644 (file)
--- a/milkymist/uart/__init__.py
+++ b/milkymist/uart/__init__.py
@@ -21,7 +21,7 @@ class UART:
                enable16 = Signal()
                enable16_counter = Signal(BV(16))
                comb = [
-                       enable16.eq(enable16_counter == Constant(0, BV(16)))
+                       enable16.eq(enable16_counter == 0)
                ]
                sync = [
                        enable16_counter.eq(enable16_counter - 1),
@@ -43,7 +43,7 @@ class UART:
                                self.tx.eq(0)
                        ).Elif(enable16 & tx_busy,
                                tx_count16.eq(tx_count16 + 1),
-                               If(tx_count16 == Constant(0, BV(4)),
+                               If(tx_count16 == 0,
                                        tx_bitcount.eq(tx_bitcount + 1),
                                        If(tx_bitcount == 8,
                                                self.tx.eq(1)

diff --git a/top.py b/top.py
index 16bc91227f34cd890f844ee365d5476f8ddd6610..f29f24afe5796488a58ab2c622a525bd26b674f2 100644 (file)
--- a/top.py
+++ b/top.py
@@ -97,14 +97,13 @@ def get():
                        cpu0.ibus,
                        cpu0.dbus
                ], [
-                       (binc("000"), norflash0.bus),
-                       (binc("001"), sram0.bus),
-                       (binc("011"), minimac0.membus),
-                       (binc("10"), wishbone2asmi0.wishbone),
-                       (binc("11"), wishbone2csr0.wishbone)
+                       (lambda a: a[26:29] == 0, norflash0.bus),
+                       (lambda a: a[26:29] == 1, sram0.bus),
+                       (lambda a: a[26:29] == 3, minimac0.membus),
+                       (lambda a: a[27:29] == 2, wishbone2asmi0.wishbone),
+                       (lambda a: a[27:29] == 3, wishbone2csr0.wishbone)
                ],
-               register=True,
-               offset=1)
+               register=True)
        
        #
        # CSR