enable $bits() and $size() functions only when the SystemVerilog flag is enabled...

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 0cde34dc51dc5577dd816cfeea89e6a8fc23ec5d..5b7e48361664405ef28fc776cf8ac00f33bb260c 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1870,7 +1870,7 @@ skip_dynamic_range_lvalue_expansion:;
                                goto apply_newNode;
                        }
 
-                       if (str == "\\$size" || str == "\\$bits")
+                       if (VERILOG_FRONTEND::sv_mode && (str == "\\$size" || str == "\\$bits"))
                        {
                                if (children.size() != 1)
                                        log_error("System function %s got %d arguments, expected 1 at %s:%d.\n",