add srcoffs and destoffs sv state, alter CSRs

remove SVREALVL, replace with SVSTATE

diff --git a/riscv/encoding.h b/riscv/encoding.h
index 980a792963c742be4d5262b8511f4af46711c67f..19b28c4f6d67ed21fd8223e06516ccf5022840d4 100644 (file)
--- a/riscv/encoding.h
+++ b/riscv/encoding.h
@@ -909,7 +909,7 @@
 #define CSR_SVPREDCFG6 0x4ce
 #define CSR_SVPREDCFG7 0x4cf
 #define CSR_SVVL 0x4f0
-#define CSR_SVREALVL 0x4f1
+#define CSR_SVSTATE 0x4f1
 #define CSR_SVMVL 0x4f2
 #define CSR_MVENDORID 0xf11
 #define CSR_MARCHID 0xf12
@@ -1260,7 +1260,7 @@ DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_R
 #endif
 #ifdef DECLARE_CSR
 DECLARE_CSR(svvl, CSR_SVVL)
-DECLARE_CSR(svrealvl, CSR_SVREALVL)
+DECLARE_CSR(svstate, CSR_SVSTATE)
 DECLARE_CSR(svmvl, CSR_SVMVL)
 DECLARE_CSR(svregcfg0, CSR_SVREGCFG0)
 DECLARE_CSR(svregcfg1, CSR_SVREGCFG1)

diff --git a/riscv/processor.cc b/riscv/processor.cc
index a53ab1e859ee610a0214330846ea173b1b0a4387..a57f8e6261a0f3b11e50389ea174e9d824ce5735 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -341,8 +341,12 @@ void processor_t::set_csr(int which, reg_t val)
       state.mvl = std::min(val, (uint64_t)63); // limited to XLEN width
       fprintf(stderr, "set MVL %lx\n", state.mvl);
       break;
-    case CSR_SVREALVL:
-      state.vl = std::min(val, state.mvl); // limited to MVL
+    case CSR_SVSTATE:
+      // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs
+      set_csr(CSR_SVMVL, get_field(val, 0x1f));
+      set_csr(CSR_SVVL , get_field(val, 0x1f<<6));
+      state.srcoffs = std::min(get_field(val, 0x1f<<12), state.vl);
+      state.destoffs = std::min(get_field(val, 0x1f<<18), state.vl);
       break;
     case CSR_SVVL:
       state.vl = std::min(state.mvl, val);
@@ -677,8 +681,10 @@ reg_t processor_t::get_csr(int which)
   {
 #ifdef SPIKE_SIMPLEV
     case CSR_SVVL:
-    case CSR_SVREALVL:
       return state.vl;
+    case CSR_SVSTATE:
+      return state.vl            | (state.mvl<<6) |
+             (state.srcoffs<<12) | (state.destoffs<<18) ;
     case CSR_SVMVL:
       return state.mvl;
     case CSR_SVREGCFG0:

diff --git a/riscv/processor.h b/riscv/processor.h
index 1c89da08cf06235694ea402a1b675533ebe11feb..2e87d5e25cd02f3d392bd4461ec1d539906038d2 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -129,6 +129,8 @@ struct state_t
 #ifdef SPIKE_SIMPLEV
   uint64_t vl;
   uint64_t mvl;
+  uint64_t destoffs; // destination loop element offset
+  uint64_t srcoffs;  // source loop element offset (used in twin-predication)
   sv_reg_csr_entry sv_csrs[SV_CSR_SZ];
   sv_reg_entry     sv_int_tb[NXPR];
   sv_reg_entry     sv_fp_tb[NFPR];