ARM: Get rid of a few more unused operands.

diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index 8b4175f9c8ba2f5768575d959d19c969b037dc80..af325b57adaba0c6f3d1d3f93427d486b8234fc1 100644 (file)
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -832,7 +832,6 @@ decode COND_CODE default Unknown::unknown() {
                 // ARM System Call (SoftWare Interrupt)
                 1: swi({{ if (testPredicate(Cpsr, condCode))
                           {
-                              //xc->syscall(R7);
                               xc->syscall(IMMED_23_0);
                           }
                 }});

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index be4ec6e0305755abf917abed9f11ffcadc45ff66..c056d41f2c6b36598ff56545ad6f27dbd4be498b 100644 (file)
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -48,12 +48,9 @@ def operands {{
     'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
 
     'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
-    'R0': ('IntReg', 'uw', '0', 'IsInteger', 5),
-    'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
     'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 5),
     'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 6),
     'LR': ('IntReg', 'uw', '14', 'IsInteger', 6),
-    'Ignore': ('IntReg', 'uw', '16', 'IsInteger', 99),
 
     #General Purpose Floating Point Reg Operands
     'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),