nir/range-analysis: Use types to provide better ranges from bcsel and mov

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
All Gen7+ platforms had similar results. (Ice Lake shown)
total instructions in shared programs: 16328255 -> 16315391 (-0.08%)
instructions in affected programs: 218318 -> 205454 (-5.89%)
helped: 988
HURT: 0
helped stats (abs) min: 1 max: 72 x̄: 13.02 x̃: 10
helped stats (rel) min: 0.33% max: 16.04% x̄: 6.27% x̃: 4.88%
95% mean confidence interval for instructions value: -13.69 -12.35
95% mean confidence interval for instructions %-change: -6.55% -5.99%
Instructions are helped.

total cycles in shared programs: 363683977 -> 363615417 (-0.02%)
cycles in affected programs: 1475193 -> 1406633 (-4.65%)
helped: 923
HURT: 36
helped stats (abs) min: 1 max: 624 x̄: 75.78 x̃: 48
helped stats (rel) min: 0.08% max: 13.89% x̄: 5.20% x̃: 5.08%
HURT stats (abs)   min: 1 max: 179 x̄: 38.58 x̃: 4
HURT stats (rel)   min: 0.06% max: 16.56% x̄: 3.33% x̃: 0.29%
95% mean confidence interval for cycles value: -75.88 -67.10
95% mean confidence interval for cycles %-change: -5.10% -4.66%
Cycles are helped.

Sandy Bridge
total instructions in shared programs: 10785779 -> 10785654 (<.01%)
instructions in affected programs: 13855 -> 13730 (-0.90%)
helped: 67
HURT: 0
helped stats (abs) min: 1 max: 15 x̄: 1.87 x̃: 1
helped stats (rel) min: 0.20% max: 3.45% x̄: 0.97% x̃: 0.78%
95% mean confidence interval for instructions value: -2.47 -1.26
95% mean confidence interval for instructions %-change: -1.13% -0.81%
Instructions are helped.

total cycles in shared programs: 153704799 -> 153704481 (<.01%)
cycles in affected programs: 101509 -> 101191 (-0.31%)
helped: 38
HURT: 13
helped stats (abs) min: 1 max: 38 x̄: 12.53 x̃: 16
helped stats (rel) min: 0.07% max: 2.69% x̄: 0.87% x̃: 0.53%
HURT stats (abs)   min: 1 max: 36 x̄: 12.15 x̃: 7
HURT stats (rel)   min: 0.06% max: 2.53% x̄: 0.73% x̃: 0.44%
95% mean confidence interval for cycles value: -10.24 -2.24
95% mean confidence interval for cycles %-change: -0.75% -0.17%
Cycles are helped.

LOST:   2
GAINED: 0

No shader-db change on Iron Lake or GM45.

diff --git a/src/compiler/nir/nir_range_analysis.c b/src/compiler/nir/nir_range_analysis.c
index e1f3eb14bceeef93887a745aa4901f3958eaa239..758d427f599d8c78678e9bcfd64db219efdda5a9 100644 (file)
--- a/src/compiler/nir/nir_range_analysis.c
+++ b/src/compiler/nir/nir_range_analysis.c
@@ -498,22 +498,9 @@ analyze_expression(const nir_alu_instr *instr, unsigned src,
 
    case nir_op_bcsel: {
       const struct ssa_result_range left =
-         analyze_expression(alu, 1, ht, nir_alu_src_type(alu, 1));
+         analyze_expression(alu, 1, ht, use_type);
       const struct ssa_result_range right =
-         analyze_expression(alu, 2, ht, nir_alu_src_type(alu, 2));
-
-      /* If either source is a constant load that is not zero, punt.  The type
-       * will always be uint regardless of the actual type.  We can't even
-       * decide if the value is non-zero because -0.0 is 0x80000000, and that
-       * will (possibly incorrectly) be considered non-zero.
-       */
-      /* FINISHME: We could do better, but it would require having the expected
-       * FINISHME: type passed in.
-       */
-      if ((nir_src_is_const(alu->src[1].src) && left.range != eq_zero) ||
-          (nir_src_is_const(alu->src[2].src) && right.range != eq_zero)) {
-         return (struct ssa_result_range){unknown, false};
-      }
+         analyze_expression(alu, 2, ht, use_type);
 
       r.is_integral = left.is_integral && right.is_integral;
 
@@ -800,17 +787,9 @@ analyze_expression(const nir_alu_instr *instr, unsigned src,
       };
       break;
 
-   case nir_op_mov: {
-      const struct ssa_result_range left =
-         analyze_expression(alu, 0, ht, nir_alu_src_type(alu, 0));
-
-      /* See commentary in nir_op_bcsel for the reasons this is necessary. */
-      if (nir_src_is_const(alu->src[0].src) && left.range != eq_zero)
-         return (struct ssa_result_range){unknown, false};
-
-      r = left;
+   case nir_op_mov:
+      r = analyze_expression(alu, 0, ht, use_type);
       break;
-   }
 
    case nir_op_fneg:
       r = analyze_expression(alu, 0, ht, nir_alu_src_type(alu, 0));