x86: correct VMOVSH attributes

Both forms were missing VexW0 (thus allowing Evex.W=1 to be encoded by
suitable means, which would cause #UD). The memory operand form further
was using the wrong Masking value, thus allowing zeroing-masking to be
encoded for the store form (which would again cause #UD).

diff --git a/gas/testsuite/gas/i386/evex-wig.s b/gas/testsuite/gas/i386/evex-wig.s
index df73c78eb4f9b4d38d11532f0d074c02d2ee085d..de8c16c7c2078172c26a4c671373b2157179a6ca 100644 (file)
--- a/gas/testsuite/gas/i386/evex-wig.s
+++ b/gas/testsuite/gas/i386/evex-wig.s
@@ -62,6 +62,18 @@ _start:
        {evex} vpinsrw $0, %eax, %xmm0, %xmm0
        {evex} vpinsrw $0, 2(%eax), %xmm0, %xmm0
 
+       vmovss %xmm0, %xmm0, %xmm0{%k7}
+       vmovss (%eax), %xmm0{%k7}
+       vmovss %xmm0, (%eax){%k7}
+
+       vmovsd %xmm0, %xmm0, %xmm0{%k7}
+       vmovsd (%eax), %xmm0{%k7}
+       vmovsd %xmm0, (%eax){%k7}
+
+       vmovsh %xmm0, %xmm0, %xmm0{%k7}
+       vmovsh (%eax), %xmm0{%k7}
+       vmovsh %xmm0, (%eax){%k7}
+
        vpmovsxbd       %xmm5, %zmm6{%k7}        # AVX512
        vpmovsxbd       %xmm5, %zmm6{%k7}{z}     # AVX512
        vpmovsxbd       (%ecx), %zmm6{%k7}       # AVX512

diff --git a/gas/testsuite/gas/i386/evex-wig1-intel.d b/gas/testsuite/gas/i386/evex-wig1-intel.d
index 0bf2be8fc9b06f67cfcd75b61a853f66895ae401..202c4f5c024ad58ddef51997d03b4519e99b00d4 100644 (file)
--- a/gas/testsuite/gas/i386/evex-wig1-intel.d
+++ b/gas/testsuite/gas/i386/evex-wig1-intel.d
@@ -45,6 +45,15 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    62 f3 fd 08 22 40 01 00         vpinsrd xmm0,xmm0,DWORD PTR \[eax\+0x4\],0x0
 [      ]*[a-f0-9]+:    62 f1 fd 08 c4 c0 00    vpinsrw xmm0,xmm0,eax,0x0
 [      ]*[a-f0-9]+:    62 f1 fd 08 c4 40 01 00         vpinsrw xmm0,xmm0,WORD PTR \[eax\+0x2\],0x0
+[      ]*[a-f0-9]+:    62 f1 7e 0f 10 c0       vmovss xmm0\{k7\},xmm0,xmm0
+[      ]*[a-f0-9]+:    62 f1 7e 0f 10 00       vmovss xmm0\{k7\},DWORD PTR \[eax\]
+[      ]*[a-f0-9]+:    62 f1 7e 0f 11 00       vmovss DWORD PTR \[eax\]\{k7\},xmm0
+[      ]*[a-f0-9]+:    62 f1 ff 0f 10 c0       vmovsd xmm0\{k7\},xmm0,xmm0
+[      ]*[a-f0-9]+:    62 f1 ff 0f 10 00       vmovsd xmm0\{k7\},QWORD PTR \[eax\]
+[      ]*[a-f0-9]+:    62 f1 ff 0f 11 00       vmovsd QWORD PTR \[eax\]\{k7\},xmm0
+[      ]*[a-f0-9]+:    62 f5 7e 0f 10 c0       vmovsh xmm0\{k7\},xmm0,xmm0
+[      ]*[a-f0-9]+:    62 f5 7e 0f 10 00       vmovsh xmm0\{k7\},WORD PTR \[eax\]
+[      ]*[a-f0-9]+:    62 f5 7e 0f 11 00       vmovsh WORD PTR \[eax\]\{k7\},xmm0
 [      ]*[a-f0-9]+:    62 f2 fd 4f 21 f5       vpmovsxbd zmm6\{k7\},xmm5
 [      ]*[a-f0-9]+:    62 f2 fd cf 21 f5       vpmovsxbd zmm6\{k7\}\{z\},xmm5
 [      ]*[a-f0-9]+:    62 f2 fd 4f 21 31       vpmovsxbd zmm6\{k7\},XMMWORD PTR \[ecx\]

diff --git a/gas/testsuite/gas/i386/evex-wig1.d b/gas/testsuite/gas/i386/evex-wig1.d
index def41b32868619a731a127af93f9bd53f3c9d21f..0a9a534d95750a5007bec504e0e9ff79d3bad221 100644 (file)
--- a/gas/testsuite/gas/i386/evex-wig1.d
+++ b/gas/testsuite/gas/i386/evex-wig1.d
@@ -45,6 +45,15 @@ Disassembly of section .text:
 [      ]*[a-f0-9]+:    62 f3 fd 08 22 40 01 00         vpinsrd \$0x0,0x4\(%eax\),%xmm0,%xmm0
 [      ]*[a-f0-9]+:    62 f1 fd 08 c4 c0 00    vpinsrw \$0x0,%eax,%xmm0,%xmm0
 [      ]*[a-f0-9]+:    62 f1 fd 08 c4 40 01 00         vpinsrw \$0x0,0x2\(%eax\),%xmm0,%xmm0
+[      ]*[a-f0-9]+:    62 f1 7e 0f 10 c0       vmovss %xmm0,%xmm0,%xmm0\{%k7\}
+[      ]*[a-f0-9]+:    62 f1 7e 0f 10 00       vmovss \(%eax\),%xmm0\{%k7\}
+[      ]*[a-f0-9]+:    62 f1 7e 0f 11 00       vmovss %xmm0,\(%eax\)\{%k7\}
+[      ]*[a-f0-9]+:    62 f1 ff 0f 10 c0       vmovsd %xmm0,%xmm0,%xmm0\{%k7\}
+[      ]*[a-f0-9]+:    62 f1 ff 0f 10 00       vmovsd \(%eax\),%xmm0\{%k7\}
+[      ]*[a-f0-9]+:    62 f1 ff 0f 11 00       vmovsd %xmm0,\(%eax\)\{%k7\}
+[      ]*[a-f0-9]+:    62 f5 7e 0f 10 c0       vmovsh %xmm0,%xmm0,%xmm0\{%k7\}
+[      ]*[a-f0-9]+:    62 f5 7e 0f 10 00       vmovsh \(%eax\),%xmm0\{%k7\}
+[      ]*[a-f0-9]+:    62 f5 7e 0f 11 00       vmovsh %xmm0,\(%eax\)\{%k7\}
 [      ]*[a-f0-9]+:    62 f2 fd 4f 21 f5       vpmovsxbd %xmm5,%zmm6\{%k7\}
 [      ]*[a-f0-9]+:    62 f2 fd cf 21 f5       vpmovsxbd %xmm5,%zmm6\{%k7\}\{z\}
 [      ]*[a-f0-9]+:    62 f2 fd 4f 21 31       vpmovsxbd \(%ecx\),%zmm6\{%k7\}

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 859412e410b2977905a50b95bc42ca52bd6fcaca..b788f80379778506adf1d7a5dffab502f0c1369a 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3684,8 +3684,8 @@ vmaxsh, 0xf35f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|V
 vminph, 0x5d, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
 vminsh, 0xf35d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
 
-vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3|EVexMap5|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM }
-vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
+vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|MaskingMorZ|EVexMap5|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM }
+vmovsh, 0xf310, None, CpuAVX512_FP16, D|Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
 
 vmovw, 0x666e, None, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM }
 vmovw, 0x667e, None, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32 }

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 6066e5fb36f1fd8991aa8a0359bcc3c5b5c7c4fe..b43da35365848ab60631e6a435065ce044087ac1 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -58553,8 +58553,8 @@ const insn_template i386_optab[] =
          1, 0, 0, 0, 0, 0 } } } },
   { "vmovsh", 0x10, 2, None,
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 5, 2, 0, 0,
-      0, 4, 3, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 5, 2, 0, 0,
+      0, 4, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -58568,7 +58568,7 @@ const insn_template i386_optab[] =
          1, 0, 0, 0, 0, 0 } } } },
   { "vmovsh", 0x10, 3, None,
     { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0,
-      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 5, 2, 0, 0,
+      0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 5, 2, 0, 0,
       0, 4, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
     { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,