* coff-h8300.c: Add and adjust comments about relaxation.

	* elf32-h8300.c: Likewise.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 8360a56f9f79ca34f43f5f5d18694518740d226e..2330758524db047f3af8d8c522500ccb2a79f02a 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,8 @@
+2004-01-19  Kazu Hirata  <kazu@cs.umass.edu>
+
+       * coff-h8300.c: Add and adjust comments about relaxation.
+       * elf32-h8300.c: Likewise.
+
 2004-01-16  Kazu Hirata  <kazu@cs.umass.edu>
 
        * coff-h8300.c: Fix comment typos.

diff --git a/bfd/coff-h8300.c b/bfd/coff-h8300.c
index b99a6e99f7367ad3a0c91d39f64100b7286f5f3a..bd798a64b65c90b50e2586ce781823fb456d83d3 100644 (file)
--- a/bfd/coff-h8300.c
+++ b/bfd/coff-h8300.c
@@ -776,8 +776,15 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
       src_address += 4;
       break;
 
-    /* A 16-bit absolute relocation that was formerly a 24-/32-bit
-       absolute relocation.  */
+      /* This is a 24-/32-bit absolute address in one of the following
+        instructions:
+
+          "band", "bclr", "biand", "bild", "bior", "bist", "bixor",
+          "bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and
+          "mov.[bwl]"
+
+        We may relax this into an 16-bit absolute address if it's in
+        the right range.  */
     case R_MOVL2:
       value = bfd_coff_reloc16_get_value (reloc, link_info, input_section);
       value = bfd_h8300_pad_address (abfd, value);
@@ -788,8 +795,9 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
          /* Insert the 16-bit value into the proper location.  */
          bfd_put_16 (abfd, value, data + dst_address);
 
-         /* Fix the opcode.  For all the move insns, we simply
-            need to turn off bit 0x20 in the previous byte.  */
+         /* Fix the opcode.  For all the instructions that belong to
+            this relaxation, we simply need to turn off bit 0x20 in
+            the previous byte.  */
          data[dst_address - 1] &= ~0x20;
          dst_address += 2;
          src_address += 4;
@@ -834,7 +842,7 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
          bfd_put_8 (abfd, 0x55, data + dst_address - 1);
          break;
        case 0x5a:
-         /* jmp ->bra */
+         /* jmp -> bra */
          bfd_put_8 (abfd, 0x40, data + dst_address - 1);
          break;
 
@@ -877,12 +885,15 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
        {
        case 0x58:
          /* bCC:16 -> bCC:8 */
-         /* Get the condition code from the original insn.  */
+         /* Get the second byte of the original insn, which contains
+            the condition code.  */
          tmp = data[dst_address - 1];
+
+         /* Compute the fisrt byte of the relaxed instruction.  The
+            original sequence 0x58 0xX0 is relaxed to 0x4X, where X
+            represents the condition code.  */
          tmp &= 0xf0;
          tmp >>= 4;
-
-         /* Now or in the high nibble of the opcode.  */
          tmp |= 0x40;
 
          /* Write it.  */

diff --git a/bfd/elf32-h8300.c b/bfd/elf32-h8300.c
index 81d1da83e01d2bcdf75f9ea654c8395e7bc7322b..1a176214f014cbc112473c4d55be444923299c6b 100644 (file)
--- a/bfd/elf32-h8300.c
+++ b/bfd/elf32-h8300.c
@@ -666,6 +666,9 @@ elf32_h8_merge_private_bfd_data (bfd *ibfd, bfd *obfd)
      mov.b:16       ->    mov.b:8                2 bytes
      mov.b:24/32     ->    mov.b:8                4 bytes
 
+     bset:24/32             ->    bset:16                2 bytes
+     (also applicable to other bit manipulation instructions)
+
      mov.[bwl]:24/32 ->    mov.[bwl]:16           2 bytes */
 
 static bfd_boolean
@@ -919,8 +922,10 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
                  }
 
                if (code == 0x5e)
+                 /* This is jsr.  */
                  bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 1);
                else if (code == 0x5a)
+                 /* This is jmp.  */
                  bfd_put_8 (abfd, 0x40, contents + irel->r_offset - 1);
                else
                  abort ();
@@ -975,14 +980,21 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
                if (code == 0x58)
                  {
                    /* bCC:16 -> bCC:8 */
-                   /* Get the condition code from the original insn.  */
+                   /* Get the second byte of the original insn, which
+                      contains the condition code.  */
                    code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
+
+                   /* Compute the fisrt byte of the relaxed
+                      instruction.  The original sequence 0x58 0xX0
+                      is relaxed to 0x4X, where X represents the
+                      condition code.  */
                    code &= 0xf0;
                    code >>= 4;
                    code |= 0x40;
                    bfd_put_8 (abfd, code, contents + irel->r_offset - 2);
                  }
                else if (code == 0x5c)
+                 /* This is bsr.  */
                  bfd_put_8 (abfd, 0x55, contents + irel->r_offset - 2);
                else
                  abort ();
@@ -1179,11 +1191,17 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
              }
          }
 
-       /* Fall through.  */
+         /* Fall through.  */
+
+         /* This is a 24-/32-bit absolute address in one of the
+            following instructions:
+
+              "band", "bclr", "biand", "bild", "bior", "bist",
+              "bixor", "bld", "bnot", "bor", "bset", "bst", "btst",
+              "bxor", and "mov.[bwl]"
 
-       /* This is a 24-/32-bit absolute address in a "mov" insn,
-          which may become a 16-bit absolute address if it is in the
-          right range.  */
+            We may relax this into an 16-bit absolute address if it's
+            in the right range.  */
        case R_H8_DIR32A16:
          {
            bfd_vma value;
@@ -1202,7 +1220,9 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
                /* Get the opcode.  */
                code = bfd_get_8 (abfd, contents + irel->r_offset - 1);
 
-               /* We just need to turn off bit 0x20.  */
+               /* Fix the opcode.  For all the instructions that
+                  belong to this relaxation, we simply need to turn
+                  off bit 0x20 in the previous byte.  */
                code &= ~0x20;
 
                bfd_put_8 (abfd, code, contents + irel->r_offset - 1);