#include "brw_wm.h"
#include "isl/isl.h"
-/**
- * Convert an swizzle enumeration (i.e. SWIZZLE_X) to one of the Gen7.5+
- * "Shader Channel Select" enumerations (i.e. HSW_SCS_RED). The mappings are
- *
- * SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_W, SWIZZLE_ZERO, SWIZZLE_ONE
- * 0 1 2 3 4 5
- * 4 5 6 7 0 1
- * SCS_RED, SCS_GREEN, SCS_BLUE, SCS_ALPHA, SCS_ZERO, SCS_ONE
- *
- * which is simply adding 4 then modding by 8 (or anding with 7).
- */
-static unsigned
-swizzle_to_scs(unsigned swizzle)
-{
- return (swizzle + 4) & 7;
-}
-
static uint32_t
surface_tiling_resource_mode(uint32_t tr_mode)
{
return GEN8_SURFACE_AUX_MODE_MCS;
}
-static void
-gen8_emit_texture_surface_state(struct brw_context *brw,
- struct intel_mipmap_tree *mt,
- GLenum target,
- unsigned min_layer, unsigned max_layer,
- unsigned min_level, unsigned max_level,
- unsigned format,
- unsigned swizzle,
- uint32_t *surf_offset, int surf_index,
- bool rw, bool for_gather)
-{
- const unsigned depth = max_layer - min_layer;
- struct intel_mipmap_tree *aux_mt = mt->mcs_mt;
- uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
- unsigned tiling_mode, pitch;
- const unsigned tr_mode = surface_tiling_resource_mode(mt->tr_mode);
- const uint32_t surf_type = translate_tex_target(target);
- uint32_t aux_mode = gen8_get_aux_mode(brw, mt);
-
- if (mt->format == MESA_FORMAT_S_UINT8) {
- tiling_mode = GEN8_SURFACE_TILING_W;
- pitch = 2 * mt->pitch;
- } else {
- tiling_mode = gen8_surface_tiling_mode(mt->tiling);
- pitch = mt->pitch;
- }
-
- /* Prior to Gen9, MCS is not uploaded for single-sampled surfaces because
- * the color buffer should always have been resolved before it is used as
- * a texture so there is no need for it. On Gen9 it will be uploaded when
- * the surface is losslessly compressed (CCS_E).
- * However, sampling engine is not capable of re-interpreting the
- * underlying color buffer in non-compressible formats when the surface
- * is configured as compressed. Therefore state upload has made sure the
- * buffer is in resolved state allowing the surface to be configured as
- * non-compressed.
- */
- if (mt->num_samples <= 1 &&
- (aux_mode != GEN9_SURFACE_AUX_MODE_CCS_E ||
- !isl_format_supports_lossless_compression(
- brw->intelScreen->devinfo, format))) {
- assert(!mt->mcs_mt ||
- mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED);
- aux_mt = NULL;
- aux_mode = GEN8_SURFACE_AUX_MODE_NONE;
- }
-
- uint32_t *surf = gen8_allocate_surface_state(brw, surf_offset, surf_index);
-
- surf[0] = SET_FIELD(surf_type, BRW_SURFACE_TYPE) |
- format << BRW_SURFACE_FORMAT_SHIFT |
- gen8_vertical_alignment(brw, mt, surf_type) |
- gen8_horizontal_alignment(brw, mt, surf_type) |
- tiling_mode;
-
- if (surf_type == BRW_SURFACE_CUBE) {
- surf[0] |= BRW_SURFACE_CUBEFACE_ENABLES;
- }
-
- /* From the CHV PRM, Volume 2d, page 321 (RENDER_SURFACE_STATE dword 0
- * bit 9 "Sampler L2 Bypass Mode Disable" Programming Notes):
- *
- * This bit must be set for the following surface types: BC2_UNORM
- * BC3_UNORM BC5_UNORM BC5_SNORM BC7_UNORM
- */
- if ((brw->gen >= 9 || brw->is_cherryview) &&
- (format == BRW_SURFACEFORMAT_BC2_UNORM ||
- format == BRW_SURFACEFORMAT_BC3_UNORM ||
- format == BRW_SURFACEFORMAT_BC5_UNORM ||
- format == BRW_SURFACEFORMAT_BC5_SNORM ||
- format == BRW_SURFACEFORMAT_BC7_UNORM))
- surf[0] |= GEN8_SURFACE_SAMPLER_L2_BYPASS_DISABLE;
-
- if (mt->target != GL_TEXTURE_3D)
- surf[0] |= GEN8_SURFACE_IS_ARRAY;
-
- surf[1] = SET_FIELD(mocs_wb, GEN8_SURFACE_MOCS) | mt->qpitch >> 2;
-
- surf[2] = SET_FIELD(mt->logical_width0 - 1, GEN7_SURFACE_WIDTH) |
- SET_FIELD(mt->logical_height0 - 1, GEN7_SURFACE_HEIGHT);
-
- surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) | (pitch - 1);
-
- surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout) |
- SET_FIELD(min_layer, GEN7_SURFACE_MIN_ARRAY_ELEMENT) |
- SET_FIELD(depth - 1, GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT);
-
- surf[5] = SET_FIELD(min_level - mt->first_level, GEN7_SURFACE_MIN_LOD) |
- (max_level - min_level - 1); /* mip count */
-
- if (brw->gen >= 9) {
- surf[5] |= SET_FIELD(tr_mode, GEN9_SURFACE_TRMODE);
- /* Disable Mip Tail by setting a large value. */
- surf[5] |= SET_FIELD(15, GEN9_SURFACE_MIP_TAIL_START_LOD);
- }
-
- if (aux_mt) {
- uint32_t tile_w, tile_h;
- assert(aux_mt->tiling == I915_TILING_Y);
- intel_get_tile_dims(aux_mt->tiling, aux_mt->tr_mode,
- aux_mt->cpp, &tile_w, &tile_h);
- surf[6] = SET_FIELD(aux_mt->qpitch / 4, GEN8_SURFACE_AUX_QPITCH) |
- SET_FIELD((aux_mt->pitch / tile_w) - 1,
- GEN8_SURFACE_AUX_PITCH) |
- aux_mode;
- }
-
- gen8_emit_fast_clear_color(brw, mt, surf);
- surf[7] |=
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 0)), GEN7_SURFACE_SCS_R) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 1)), GEN7_SURFACE_SCS_G) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 2)), GEN7_SURFACE_SCS_B) |
- SET_FIELD(swizzle_to_scs(GET_SWZ(swizzle, 3)), GEN7_SURFACE_SCS_A);
-
- *((uint64_t *) &surf[8]) = mt->bo->offset64 + mt->offset; /* reloc */
-
- if (aux_mt) {
- *((uint64_t *) &surf[10]) = aux_mt->bo->offset64;
- drm_intel_bo_emit_reloc(brw->batch.bo, *surf_offset + 10 * 4,
- aux_mt->bo, 0,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
- }
-
- /* Emit relocation to surface contents */
- drm_intel_bo_emit_reloc(brw->batch.bo,
- *surf_offset + 8 * 4,
- mt->bo,
- mt->offset,
- I915_GEM_DOMAIN_SAMPLER,
- (rw ? I915_GEM_DOMAIN_SAMPLER : 0));
-}
-
-static void
-gen8_update_texture_surface(struct gl_context *ctx,
- unsigned unit,
- uint32_t *surf_offset,
- bool for_gather,
- uint32_t plane)
-{
- struct brw_context *brw = brw_context(ctx);
- struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
-
- if (obj->Target == GL_TEXTURE_BUFFER) {
- brw_update_buffer_texture_surface(ctx, unit, surf_offset);
-
- } else {
- struct gl_texture_image *firstImage = obj->Image[0][obj->BaseLevel];
- struct intel_texture_object *intel_obj = intel_texture_object(obj);
- struct intel_mipmap_tree *mt = intel_obj->mt;
-
- if (plane > 0) {
- if (mt->plane[plane - 1] == NULL)
- return;
- mt = mt->plane[plane - 1];
- }
-
- struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
- /* If this is a view with restricted NumLayers, then our effective depth
- * is not just the miptree depth.
- */
- const unsigned depth = (obj->Immutable && obj->Target != GL_TEXTURE_3D ?
- obj->NumLayers : mt->logical_depth0);
-
- /* Handling GL_ALPHA as a surface format override breaks 1.30+ style
- * texturing functions that return a float, as our code generation always
- * selects the .x channel (which would always be 0).
- */
- const bool alpha_depth = obj->DepthMode == GL_ALPHA &&
- (firstImage->_BaseFormat == GL_DEPTH_COMPONENT ||
- firstImage->_BaseFormat == GL_DEPTH_STENCIL);
- const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
- brw_get_texture_swizzle(&brw->ctx, obj));
-
- mesa_format mesa_fmt = plane == 0 ? intel_obj->_Format : mt->format;
- unsigned format = translate_tex_format(brw, mesa_fmt,
- sampler->sRGBDecode);
-
- if (obj->StencilSampling && firstImage->_BaseFormat == GL_DEPTH_STENCIL) {
- mt = mt->stencil_mt;
- format = BRW_SURFACEFORMAT_R8_UINT;
- }
-
- const int surf_index = surf_offset - &brw->wm.base.surf_offset[0];
-
- gen8_emit_texture_surface_state(brw, mt, obj->Target,
- obj->MinLayer, obj->MinLayer + depth,
- obj->MinLevel + obj->BaseLevel,
- obj->MinLevel + intel_obj->_MaxLevel + 1,
- format, swizzle, surf_offset,
- surf_index, false, for_gather);
- }
-}
-
/**
* Creates a null surface.
*
void
gen8_init_vtable_surface_functions(struct brw_context *brw)
{
- brw->vtbl.update_texture_surface = gen8_update_texture_surface;
+ brw->vtbl.update_texture_surface = brw_update_texture_surface;
brw->vtbl.update_renderbuffer_surface = gen8_update_renderbuffer_surface;
brw->vtbl.emit_null_surface_state = gen8_emit_null_surface_state;
- brw->vtbl.emit_texture_surface_state = gen8_emit_texture_surface_state;
brw->vtbl.emit_buffer_surface_state = gen8_emit_buffer_surface_state;
}
projects / mesa.git / commitdiff