add rv64ud sv fadd test, shows flaw in loop for 3-arg operands

diff --git a/isa/Makefile b/isa/Makefile
index a3a5ee59308bdad38e63a50bf865018822f73b56..4411cceb2ea9ba24724bf80ba847c1de4408d9cb 100644 (file)
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -14,6 +14,7 @@ include $(src_dir)/rv64um/Makefrag
 include $(src_dir)/rv64ua/Makefrag
 include $(src_dir)/rv64uf/Makefrag
 include $(src_dir)/rv64ud/Makefrag
+include $(src_dir)/rv64ud/Makefrag.sv
 include $(src_dir)/rv64si/Makefrag
 include $(src_dir)/rv64mi/Makefrag
 endif

diff --git a/isa/macros/simplev/sv_test_macros.h b/isa/macros/simplev/sv_test_macros.h
index 97bb950816249fde85fd3eff7892f3479196a271..23feaa1c287a3372aa7ad1ba049b3289dda37797 100644 (file)
--- a/isa/macros/simplev/sv_test_macros.h
+++ b/isa/macros/simplev/sv_test_macros.h
@@ -26,6 +26,19 @@
         la      x1, from; \
         lw      reg, offs(x1)
 
+#define SV_FLD_DATA( reg, from, offs ) \
+        la      x1, from; \
+        fld     reg, offs(x1)
+
 #define TEST_SV_IMM( reg, imm ) \
         li      x1, imm; \
         bne     reg, x1, fail
+
+#define TEST_SV_FD( flags, freg, from, offs ) \
+        fsflags x2, x0; \
+        li      x1, flags; \
+        bne     x2, x1, fail; \
+        la      x1, from; \
+        ld      x1, offs(x1); \
+        fmv.x.d x2, freg; \
+        bne     x2, x1, fail

diff --git a/isa/rv64ud/Makefrag.sv b/isa/rv64ud/Makefrag.sv
new file mode 100644 (file)
index 0000000..6407239
--- /dev/null
+++ b/isa/rv64ud/Makefrag.sv
@@ -0,0 +1,11 @@
+#=======================================================================
+# Makefrag for rv64ud tests
+#-----------------------------------------------------------------------
+
+rv64ud_sv_tests = \
+       sv_fadd \
+
+rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sv_tests))
+rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sv_tests))
+
+spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests)

diff --git a/isa/rv64ud/sv_fadd.S b/isa/rv64ud/sv_fadd.S
new file mode 100644 (file)
index 0000000..f456119
--- /dev/null
+++ b/isa/rv64ud/sv_fadd.S
@@ -0,0 +1,70 @@
+#include "riscv_test.h"
+#include "sv_test_macros.h"
+
+RVTEST_RV64UF
+
+
+# SV test: vector-vector fadd
+#
+# sets up x3 and x4 with data, sets VL to 2, and carries out
+# an "add 1 to x3".  which actually means "add 1 to x3 *AND* add 1 to x4"
+
+# Test code region.
+RVTEST_CODE_BEGIN   # Start of test code.
+
+        SV_FLD_DATA( f1, testdata   , 0)
+        SV_FLD_DATA( f2, testdata+8 , 0)
+        SV_FLD_DATA( f3, testdata+16, 0)
+        SV_FLD_DATA( f4, testdata+24, 0)
+        SV_FLD_DATA( f5, testdata+32, 0)
+        SV_FLD_DATA( f6, testdata+40, 0)
+        SV_FLD_DATA( f7, testdata+48, 0)
+        SV_FLD_DATA( f8, testdata+56, 0)
+
+        SET_SV_MVL(2)
+        SET_SV_CSR(0, 2, 0, 2, 1, 0)
+        SET_SV_VL(2)
+
+        fadd.d f2, f2, f6;
+
+        CLR_SV_CSRS()
+        SET_SV_VL(0)
+        SET_SV_MVL(0)
+
+        TEST_SV_FD(0, f1, testdata+64, 0) 
+        TEST_SV_FD(0, f2, testdata+72, 0) 
+        TEST_SV_FD(0, f3, testdata+80, 0) 
+        TEST_SV_FD(0, f4, testdata+88, 0) 
+
+        RVTEST_PASS           # Signal success.
+fail:
+        RVTEST_FAIL
+RVTEST_CODE_END     # End of test code.
+
+# Input data section.
+# This section is optional, and this data is NOT saved in the output.
+.data
+        .align 3
+testdata:
+        .double 1001.0
+        .double 41.0
+        .double 42.0
+        .double 1002.0
+        .double 1001.0
+        .double 1.0
+        .double 2.0
+        .double 1002.0
+        .double 1001.0
+        .double 42.0
+        .double 44.0
+        .double 1002.0
+
+# Output data section.
+RVTEST_DATA_BEGIN   # Start of test output data region.
+        .align 3
+result:
+        .dword -1
+        .dword -1
+        .dword -1
+RVTEST_DATA_END     # End of test output data region.
+