i965: Add and use a getter for the clear color

It returns both the inline clear color and a clear address which points
to the indirect clear color buffer (or NULL if unused/non-existent).
This getter allows CNL to sample from fast-cleared sRGB textures
correctly by doing the needed sRGB-decode on the clear color (inline)
and making the indirect clear color buffer unused.

v2 (Rafael):
* Have a more detailed commit message.
* Add a comment on the sRGB conversion process.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c
index 37fca5e9d3184f07a4e74e69067c69735054dfeb..ba14136edc6dea2d2523ffcb80b3f72317db087f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -166,7 +166,11 @@ blorp_surf_for_miptree(struct brw_context *brw,
       /* We only really need a clear color if we also have an auxiliary
        * surface.  Without one, it does nothing.
        */
-      surf->clear_color = mt->fast_clear_color;
+      surf->clear_color =
+         intel_miptree_get_clear_color(devinfo, mt, mt->surf.format,
+                                       !is_render_target, (struct brw_bo **)
+                                       &surf->clear_color_addr.buffer,
+                                       &surf->clear_color_addr.offset);
 
       surf->aux_surf = &mt->aux_buf->surf;
       surf->aux_addr = (struct blorp_address) {
@@ -176,13 +180,6 @@ blorp_surf_for_miptree(struct brw_context *brw,
 
       surf->aux_addr.buffer = mt->aux_buf->bo;
       surf->aux_addr.offset = mt->aux_buf->offset;
-
-      if (devinfo->gen >= 10) {
-         surf->clear_color_addr = (struct blorp_address) {
-            .buffer = mt->aux_buf->clear_color_bo,
-            .offset = mt->aux_buf->clear_color_offset,
-         };
-      }
    } else {
       surf->aux_addr = (struct blorp_address) {
          .buffer = NULL,

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 7cbd2d42ae52cf94f11dbedbd204147b180c097c..96c93a7e5bf706b6278899108ffc0ab9f0c10660 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -166,9 +166,10 @@ brw_emit_surface_state(struct brw_context *brw,
       /* We only really need a clear color if we also have an auxiliary
        * surface.  Without one, it does nothing.
        */
-      clear_bo = mt->aux_buf->clear_color_bo;
-      clear_offset = mt->aux_buf->clear_color_offset;
-      clear_color = mt->fast_clear_color;
+      clear_color =
+         intel_miptree_get_clear_color(devinfo, mt, view.format,
+                                       view.usage & ISL_SURF_USAGE_TEXTURE_BIT,
+                                       &clear_bo, &clear_offset);
    }
 
    void *state = brw_state_batch(brw,

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 139f3f0c1947e0152d576cdcb02a62fef5fae3f3..b00368f8f9f7fc2425afbd6720f742d8a83e6f18 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -46,6 +46,9 @@
 #include "main/texcompress_etc.h"
 #include "main/teximage.h"
 #include "main/streaming-load-memcpy.h"
+
+#include "util/format_srgb.h"
+
 #include "x86/common_x86_asm.h"
 
 #define FILE_DEBUG_FLAG DEBUG_MIPTREE
@@ -3803,3 +3806,34 @@ intel_miptree_set_depth_clear_value(struct brw_context *brw,
    }
    return false;
 }
+
+union isl_color_value
+intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
+                              const struct intel_mipmap_tree *mt,
+                              enum isl_format view_format, bool sampling,
+                              struct brw_bo **clear_color_bo,
+                              uint32_t *clear_color_offset)
+{
+   assert(mt->aux_buf);
+
+   if (devinfo->gen == 10 && isl_format_is_srgb(view_format) && sampling) {
+      /* The gen10 sampler doesn't gamma-correct the clear color. In this case,
+       * we switch to using the inline clear color and do the sRGB color
+       * conversion process defined in the OpenGL spec. The red, green, and
+       * blue channels take part in gamma correction, while the alpha channel
+       * is unchanged.
+       */
+      union isl_color_value srgb_decoded_value = mt->fast_clear_color;
+      for (unsigned i = 0; i < 3; i++) {
+         srgb_decoded_value.f32[i] =
+            util_format_srgb_to_linear_float(mt->fast_clear_color.f32[i]);
+      }
+      *clear_color_bo = 0;
+      *clear_color_offset = 0;
+      return srgb_decoded_value;
+   } else {
+      *clear_color_bo = mt->aux_buf->clear_color_bo;
+      *clear_color_offset = mt->aux_buf->clear_color_offset;
+      return mt->fast_clear_color;
+   }
+}

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 241832f686f4429e7242cbab6771363f425547ae..e99ea44b8099775e3d522ba7eb28627343e2610c 100644 (file)
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -736,6 +736,14 @@ intel_miptree_set_clear_color(struct brw_context *brw,
                               struct intel_mipmap_tree *mt,
                               const union gl_color_union *color);
 
+/* Get a clear color suitable for filling out an ISL surface state. */
+union isl_color_value
+intel_miptree_get_clear_color(const struct gen_device_info *devinfo,
+                              const struct intel_mipmap_tree *mt,
+                              enum isl_format view_format, bool sampling,
+                              struct brw_bo **clear_color_bo,
+                              uint32_t *clear_color_offset);
+
 bool
 intel_miptree_set_depth_clear_value(struct brw_context *brw,
                                     struct intel_mipmap_tree *mt,