IBM Z: Rename mode attr tointvec to TOINTVEC

Just a preparation to add a lower-case tointvec.

gcc/ChangeLog:

	* config/s390/vector.md: Rename tointvec to TOINTVEC.
	* config/s390/vx-builtins.md: Likewise.

diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md
index 31d323930b203785ea4f348bb74009c3a73f23d7..58b8999f2db783f60369e5dbc4fbbae0ea67c40c 100644 (file)
--- a/gcc/config/s390/vector.md
+++ b/gcc/config/s390/vector.md
@@ -137,7 +137,7 @@
 
 ; Resulting mode of a vector comparison.  For floating point modes an
 ; integer vector mode with the same element size is picked.
-(define_mode_attr tointvec [(V1QI "V1QI") (V2QI "V2QI") (V4QI "V4QI") (V8QI "V8QI") (V16QI "V16QI")
+(define_mode_attr TOINTVEC [(V1QI "V1QI") (V2QI "V2QI") (V4QI "V4QI") (V8QI "V8QI") (V16QI "V16QI")
                            (V1HI "V1HI") (V2HI "V2HI") (V4HI "V4HI") (V8HI "V8HI")
                            (V1SI "V1SI") (V2SI "V2SI") (V4SI "V4SI")
                            (V1DI "V1DI") (V2DI "V2DI")
@@ -697,12 +697,12 @@
 (define_expand "vcond_mask_<mode><mode>"
   [(set (match_operand:V 0 "register_operand" "")
        (if_then_else:V
-        (eq (match_operand:<tointvec> 3 "register_operand" "")
+        (eq (match_operand:<TOINTVEC> 3 "register_operand" "")
             (match_dup 4))
         (match_operand:V 2 "register_operand" "")
         (match_operand:V 1 "register_operand" "")))]
   "TARGET_VX"
-  "operands[4] = CONST0_RTX (<tointvec>mode);")
+  "operands[4] = CONST0_RTX (<TOINTVEC>mode);")
 
 
 ; We only have HW support for byte vectors.  The middle-end is
@@ -1586,8 +1586,8 @@
 
 ; vfcesb, vfcedb, wfcexb: non-signaling "==" comparison (a == b)
 (define_insn "*vec_cmpeq<mode>_quiet_nocc"
-  [(set (match_operand:<tointvec>         0 "register_operand" "=v")
-       (eq:<tointvec> (match_operand:VFT 1 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>         0 "register_operand" "=v")
+       (eq:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v")
                       (match_operand:VFT 2 "register_operand" "v")))]
   "TARGET_VX"
   "<vw>fce<sdx>b\t%v0,%v1,%v2"
@@ -1595,45 +1595,45 @@
 
 ; vfchsb, vfchdb, wfchxb: non-signaling > comparison (!(b u>= a))
 (define_insn "vec_cmpgt<mode>_quiet_nocc"
-  [(set (match_operand:<tointvec>            0 "register_operand" "=v")
-       (not:<tointvec>
-        (unge:<tointvec> (match_operand:VFT 2 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>            0 "register_operand" "=v")
+       (not:<TOINTVEC>
+        (unge:<TOINTVEC> (match_operand:VFT 2 "register_operand" "v")
                          (match_operand:VFT 1 "register_operand" "v"))))]
   "TARGET_VX"
   "<vw>fch<sdx>b\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])
 
 (define_expand "vec_cmplt<mode>_quiet_nocc"
-  [(set (match_operand:<tointvec>            0 "register_operand" "=v")
-       (not:<tointvec>
-        (unge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>            0 "register_operand" "=v")
+       (not:<TOINTVEC>
+        (unge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v")
                          (match_operand:VFT 2 "register_operand" "v"))))]
   "TARGET_VX")
 
 ; vfchesb, vfchedb, wfchexb: non-signaling >= comparison (!(a u< b))
 (define_insn "vec_cmpge<mode>_quiet_nocc"
-  [(set (match_operand:<tointvec>            0 "register_operand" "=v")
-       (not:<tointvec>
-        (unlt:<tointvec> (match_operand:VFT 1 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>            0 "register_operand" "=v")
+       (not:<TOINTVEC>
+        (unlt:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v")
                          (match_operand:VFT 2 "register_operand" "v"))))]
   "TARGET_VX"
   "<vw>fche<sdx>b\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])
 
 (define_expand "vec_cmple<mode>_quiet_nocc"
-  [(set (match_operand:<tointvec>            0 "register_operand" "=v")
-       (not:<tointvec>
-        (unlt:<tointvec> (match_operand:VFT 2 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>            0 "register_operand" "=v")
+       (not:<TOINTVEC>
+        (unlt:<TOINTVEC> (match_operand:VFT 2 "register_operand" "v")
                          (match_operand:VFT 1 "register_operand" "v"))))]
   "TARGET_VX")
 
 ; vfkesb, vfkedb, wfkexb: signaling == comparison ((a >= b) & (b >= a))
 (define_insn "*vec_cmpeq<mode>_signaling_nocc"
-  [(set (match_operand:<tointvec>          0 "register_operand" "=v")
-       (and:<tointvec>
-        (ge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>          0 "register_operand" "=v")
+       (and:<TOINTVEC>
+        (ge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v")
                        (match_operand:VFT 2 "register_operand" "v"))
-        (ge:<tointvec> (match_dup         2)
+        (ge:<TOINTVEC> (match_dup         2)
                        (match_dup         1))))]
   "TARGET_VXE"
   "<vw>fke<sdx>b\t%v0,%v1,%v2"
@@ -1641,16 +1641,16 @@
 
 ; vfkhsb, vfkhdb, wfkhxb: signaling > comparison (a > b)
 (define_insn "*vec_cmpgt<mode>_signaling_nocc"
-  [(set (match_operand:<tointvec>         0 "register_operand" "=v")
-       (gt:<tointvec> (match_operand:VFT 1 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>         0 "register_operand" "=v")
+       (gt:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v")
                       (match_operand:VFT 2 "register_operand" "v")))]
   "TARGET_VXE"
   "<vw>fkh<sdx>b\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])
 
 (define_insn "*vec_cmpgt<mode>_signaling_finite_nocc"
-  [(set (match_operand:<tointvec>         0 "register_operand" "=v")
-       (gt:<tointvec> (match_operand:VFT 1 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>         0 "register_operand" "=v")
+       (gt:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v")
                       (match_operand:VFT 2 "register_operand" "v")))]
   "TARGET_NONSIGNALING_VECTOR_COMPARE_OK"
   "<vw>fch<sdx>b\t%v0,%v1,%v2"
@@ -1658,16 +1658,16 @@
 
 ; vfkhesb, vfkhedb, wfkhexb: signaling >= comparison (a >= b)
 (define_insn "*vec_cmpge<mode>_signaling_nocc"
-  [(set (match_operand:<tointvec>         0 "register_operand" "=v")
-       (ge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>         0 "register_operand" "=v")
+       (ge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v")
                       (match_operand:VFT 2 "register_operand" "v")))]
   "TARGET_VXE"
   "<vw>fkhe<sdx>b\t%v0,%v1,%v2"
   [(set_attr "op_type" "VRR")])
 
 (define_insn "*vec_cmpge<mode>_signaling_finite_nocc"
-  [(set (match_operand:<tointvec>         0 "register_operand" "=v")
-       (ge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>         0 "register_operand" "=v")
+       (ge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v")
                       (match_operand:VFT 2 "register_operand" "v")))]
   "TARGET_NONSIGNALING_VECTOR_COMPARE_OK"
   "<vw>fche<sdx>b\t%v0,%v1,%v2"
@@ -1679,84 +1679,84 @@
 
 ; UNGT a u> b -> !!(b u< a)
 (define_expand "vec_cmpungt<mode>"
-  [(set (match_operand:<tointvec>            0 "register_operand" "=v")
-       (not:<tointvec>
-        (unlt:<tointvec> (match_operand:VFT 2 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>            0 "register_operand" "=v")
+       (not:<TOINTVEC>
+        (unlt:<TOINTVEC> (match_operand:VFT 2 "register_operand" "v")
                          (match_operand:VFT 1 "register_operand" "v"))))
    (set (match_dup                           0)
-       (not:<tointvec> (match_dup           0)))]
+       (not:<TOINTVEC> (match_dup           0)))]
   "TARGET_VX")
 
 ; UNGE a u>= b -> !!(a u>= b)
 (define_expand "vec_cmpunge<mode>"
-  [(set (match_operand:<tointvec>            0 "register_operand" "=v")
-       (not:<tointvec>
-        (unge:<tointvec> (match_operand:VFT 1 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>            0 "register_operand" "=v")
+       (not:<TOINTVEC>
+        (unge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v")
                          (match_operand:VFT 2 "register_operand" "v"))))
    (set (match_dup                           0)
-       (not:<tointvec> (match_dup           0)))]
+       (not:<TOINTVEC> (match_dup           0)))]
   "TARGET_VX")
 
 ; UNEQ a u== b -> !(!(a u>= b) | !(b u>= a))
 (define_expand "vec_cmpuneq<mode>"
-  [(set (match_operand:<tointvec>            0 "register_operand" "=v")
-       (not:<tointvec>
-        (unge:<tointvec> (match_operand:VFT 1 "register_operand"  "v")
+  [(set (match_operand:<TOINTVEC>            0 "register_operand" "=v")
+       (not:<TOINTVEC>
+        (unge:<TOINTVEC> (match_operand:VFT 1 "register_operand"  "v")
                          (match_operand:VFT 2 "register_operand"  "v"))))
    (set (match_dup                           3)
-       (not:<tointvec>
-        (unge:<tointvec> (match_dup         2)
+       (not:<TOINTVEC>
+        (unge:<TOINTVEC> (match_dup         2)
                          (match_dup         1))))
    (set (match_dup                           0)
-       (ior:<tointvec> (match_dup           0)
+       (ior:<TOINTVEC> (match_dup           0)
                        (match_dup           3)))
    (set (match_dup                           0)
-       (not:<tointvec> (match_dup           0)))]
+       (not:<TOINTVEC> (match_dup           0)))]
   "TARGET_VX"
 {
-  operands[3] = gen_reg_rtx (<tointvec>mode);
+  operands[3] = gen_reg_rtx (<TOINTVEC>mode);
 })
 
 ; LTGT a <> b -> a > b | b > a
 (define_expand "vec_cmpltgt<mode>"
-  [(set (match_operand:<tointvec>         0 "register_operand" "=v")
-       (gt:<tointvec> (match_operand:VFT 1 "register_operand"  "v")
+  [(set (match_operand:<TOINTVEC>         0 "register_operand" "=v")
+       (gt:<TOINTVEC> (match_operand:VFT 1 "register_operand"  "v")
                    (match_operand:VFT 2 "register_operand"  "v")))
-   (set (match_dup 3) (gt:<tointvec> (match_dup 2) (match_dup 1)))
-   (set (match_dup 0) (ior:<tointvec> (match_dup 0) (match_dup 3)))]
+   (set (match_dup 3) (gt:<TOINTVEC> (match_dup 2) (match_dup 1)))
+   (set (match_dup 0) (ior:<TOINTVEC> (match_dup 0) (match_dup 3)))]
   "TARGET_VXE"
 {
-  operands[3] = gen_reg_rtx (<tointvec>mode);
+  operands[3] = gen_reg_rtx (<TOINTVEC>mode);
 })
 
 ; ORDERED (a, b): !(a u< b) | !(a u>= b)
 (define_expand "vec_cmpordered<mode>"
-  [(set (match_operand:<tointvec>            0 "register_operand" "=v")
-       (not:<tointvec>
-        (unlt:<tointvec> (match_operand:VFT 1 "register_operand" "v")
+  [(set (match_operand:<TOINTVEC>            0 "register_operand" "=v")
+       (not:<TOINTVEC>
+        (unlt:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v")
                          (match_operand:VFT 2 "register_operand" "v"))))
    (set (match_dup                           3)
-       (not:<tointvec>
-        (unge:<tointvec> (match_dup         1)
+       (not:<TOINTVEC>
+        (unge:<TOINTVEC> (match_dup         1)
                          (match_dup         2))))
    (set (match_dup                           0)
-       (ior:<tointvec> (match_dup           0)
+       (ior:<TOINTVEC> (match_dup           0)
                        (match_dup           3)))]
   "TARGET_VX"
 {
-  operands[3] = gen_reg_rtx (<tointvec>mode);
+  operands[3] = gen_reg_rtx (<TOINTVEC>mode);
 })
 
 ; UNORDERED (a, b): !ORDERED (a, b)
 (define_expand "vec_cmpunordered<mode>"
-  [(match_operand:<tointvec> 0 "register_operand" "=v")
+  [(match_operand:<TOINTVEC> 0 "register_operand" "=v")
    (match_operand:VFT        1 "register_operand" "v")
    (match_operand:VFT        2 "register_operand" "v")]
   "TARGET_VX"
 {
   emit_insn (gen_vec_cmpordered<mode> (operands[0], operands[1], operands[2]));
   emit_insn (gen_rtx_SET (operands[0],
-            gen_rtx_NOT (<tointvec>mode, operands[0])));
+            gen_rtx_NOT (<TOINTVEC>mode, operands[0])));
   DONE;
 })
 
@@ -1835,7 +1835,7 @@
 (define_split
   [(set (match_operand:V 0 "register_operand" "")
        (if_then_else:V
-        (eq (match_operand:<tointvec> 3 "register_operand" "")
+        (eq (match_operand:<TOINTVEC> 3 "register_operand" "")
             (match_operand:V 4 "const0_operand" ""))
         (match_operand:V 1 "const0_operand" "")
         (match_operand:V 2 "all_ones_operand" "")))]
@@ -1849,7 +1849,7 @@
 (define_split
   [(set (match_operand:V 0 "register_operand" "")
        (if_then_else:V
-        (eq (match_operand:<tointvec> 3 "register_operand" "")
+        (eq (match_operand:<TOINTVEC> 3 "register_operand" "")
             (match_operand:V 4 "const0_operand" ""))
         (match_operand:V 1 "all_ones_operand" "")
         (match_operand:V 2 "const0_operand" "")))]
@@ -1863,7 +1863,7 @@
 (define_split
   [(set (match_operand:V 0 "register_operand" "")
        (if_then_else:V
-        (ne (match_operand:<tointvec> 3 "register_operand" "")
+        (ne (match_operand:<TOINTVEC> 3 "register_operand" "")
             (match_operand:V 4 "const0_operand" ""))
         (match_operand:V 1 "all_ones_operand" "")
         (match_operand:V 2 "const0_operand" "")))]
@@ -1877,7 +1877,7 @@
 (define_split
   [(set (match_operand:V 0 "register_operand" "")
        (if_then_else:V
-        (ne (match_operand:<tointvec> 3 "register_operand" "")
+        (ne (match_operand:<TOINTVEC> 3 "register_operand" "")
             (match_operand:V 4 "const0_operand" ""))
         (match_operand:V 1 "const0_operand" "")
         (match_operand:V 2 "all_ones_operand" "")))]
@@ -1891,8 +1891,8 @@
 (define_insn "*vec_sel0<mode>"
   [(set (match_operand:V 0 "register_operand" "=v")
        (if_then_else:V
-        (eq (match_operand:<tointvec> 3 "register_operand" "v")
-            (match_operand:<tointvec> 4 "const0_operand" ""))
+        (eq (match_operand:<TOINTVEC> 3 "register_operand" "v")
+            (match_operand:<TOINTVEC> 4 "const0_operand" ""))
         (match_operand:V 1 "register_operand" "v")
         (match_operand:V 2 "register_operand" "v")))]
   "TARGET_VX"
@@ -1903,8 +1903,8 @@
 (define_insn "*vec_sel0<mode>"
   [(set (match_operand:V 0 "register_operand" "=v")
        (if_then_else:V
-        (eq (not:<tointvec> (match_operand:<tointvec> 3 "register_operand" "v"))
-            (match_operand:<tointvec> 4 "const0_operand" ""))
+        (eq (not:<TOINTVEC> (match_operand:<TOINTVEC> 3 "register_operand" "v"))
+            (match_operand:<TOINTVEC> 4 "const0_operand" ""))
         (match_operand:V 1 "register_operand" "v")
         (match_operand:V 2 "register_operand" "v")))]
   "TARGET_VX"
@@ -1915,8 +1915,8 @@
 (define_insn "*vec_sel1<mode>"
   [(set (match_operand:V 0 "register_operand" "=v")
        (if_then_else:V
-        (eq (match_operand:<tointvec> 3 "register_operand" "v")
-            (match_operand:<tointvec> 4 "all_ones_operand" ""))
+        (eq (match_operand:<TOINTVEC> 3 "register_operand" "v")
+            (match_operand:<TOINTVEC> 4 "all_ones_operand" ""))
         (match_operand:V 1 "register_operand" "v")
         (match_operand:V 2 "register_operand" "v")))]
   "TARGET_VX"
@@ -1927,8 +1927,8 @@
 (define_insn "*vec_sel1<mode>"
   [(set (match_operand:V 0 "register_operand" "=v")
        (if_then_else:V
-        (eq (not:<tointvec> (match_operand:<tointvec> 3 "register_operand" "v"))
-            (match_operand:<tointvec> 4 "all_ones_operand" ""))
+        (eq (not:<TOINTVEC> (match_operand:<TOINTVEC> 3 "register_operand" "v"))
+            (match_operand:<TOINTVEC> 4 "all_ones_operand" ""))
         (match_operand:V 1 "register_operand" "v")
         (match_operand:V 2 "register_operand" "v")))]
   "TARGET_VX"

diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md
index 010db4d1115679723b5c594eb764151590c94a61..2bbed197e7391862299956e662941a5ff82f2f0d 100644 (file)
--- a/gcc/config/s390/vx-builtins.md
+++ b/gcc/config/s390/vx-builtins.md
@@ -76,7 +76,7 @@
 (define_insn "vec_gather_element<mode>"
   [(set (match_operand:V_HW_32_64                     0 "register_operand"  "=v")
        (unspec:V_HW_32_64 [(match_operand:V_HW_32_64 1 "register_operand"   "0")
-                           (match_operand:<tointvec> 2 "register_operand"   "v")
+                           (match_operand:<TOINTVEC> 2 "register_operand"   "v")
                            (match_operand:BLK        3 "memory_operand"     "R")
                            (match_operand:QI         4 "const_mask_operand" "C")]
                           UNSPEC_VEC_GATHER))]
@@ -477,7 +477,7 @@
 (define_insn "vec_scatter_element<mode>_<non_vec_int>"
   [(set (mem:<non_vec>
         (plus:<non_vec_int> (unspec:<non_vec_int>
-                             [(match_operand:<tointvec> 1 "register_operand"   "v")
+                             [(match_operand:<TOINTVEC> 1 "register_operand"   "v")
                               (match_operand:QI         3 "const_mask_operand" "C")]
                              UNSPEC_VEC_EXTRACT)
                             (match_operand:DI           2 "address_operand"   "ZQ")))
@@ -492,7 +492,7 @@
 ; multiplexing here in the expander.
 (define_expand "vec_scatter_element<V_HW_32_64:mode>"
   [(match_operand:V_HW_32_64 0 "register_operand" "")
-   (match_operand:<tointvec> 1 "register_operand" "")
+   (match_operand:<TOINTVEC> 1 "register_operand" "")
    (match_operand 2 "address_operand" "")
    (match_operand:QI 3 "const_mask_operand" "")]
   "TARGET_VX"
@@ -813,8 +813,8 @@
 })
 
 (define_expand "vec_cmp<fpcmp:code><mode>"
-  [(set (match_operand:<tointvec>              0 "register_operand" "=v")
-       (fpcmp:<tointvec> (match_operand:VF_HW 1 "register_operand"  "v")
+  [(set (match_operand:<TOINTVEC>              0 "register_operand" "=v")
+       (fpcmp:<TOINTVEC> (match_operand:VF_HW 1 "register_operand"  "v")
                       (match_operand:VF_HW 2 "register_operand"  "v")))]
   "TARGET_VX"
 {
@@ -1050,7 +1050,7 @@
 (define_expand "vec_slb<mode>"
   [(set (match_operand:V_HW 0 "register_operand"                     "")
        (unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "")
-                     (match_operand:<tointvec> 2 "register_operand" "")]
+                     (match_operand:<TOINTVEC> 2 "register_operand" "")]
                     UNSPEC_VEC_SLB))]
   "TARGET_VX"
 {
@@ -1121,7 +1121,7 @@
 (define_insn "vec_srab<mode>"
   [(set (match_operand:V_HW 0 "register_operand"                    "=v")
        (unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "v")
-                     (match_operand:<tointvec> 2 "register_operand" "v")]
+                     (match_operand:<TOINTVEC> 2 "register_operand" "v")]
                     UNSPEC_VEC_SRAB))]
   "TARGET_VX"
   "vsrab\t%v0,%v1,%v2"
@@ -1146,7 +1146,7 @@
 (define_expand "vec_srb<mode>"
   [(set (match_operand:V_HW 0 "register_operand"                     "")
        (unspec:V_HW [(match_operand:V_HW 1 "register_operand"       "")
-                     (match_operand:<tointvec> 2 "register_operand" "")]
+                     (match_operand:<TOINTVEC> 2 "register_operand" "")]
                     UNSPEC_VEC_SRLB))]
   "TARGET_VX"
 {
@@ -1229,7 +1229,7 @@
 (define_expand "vec_test_mask_int<mode>"
   [(set (reg:CCRAW CC_REGNUM)
        (unspec:CCRAW [(match_operand:V_HW 1 "register_operand" "")
-                      (match_operand:<tointvec> 2 "register_operand" "")]
+                      (match_operand:<TOINTVEC> 2 "register_operand" "")]
                      UNSPEC_VEC_TEST_MASK))
    (set (match_operand:SI 0 "register_operand" "")
        (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
@@ -1238,7 +1238,7 @@
 (define_insn "*vec_test_mask<mode>"
   [(set (reg:CCRAW CC_REGNUM)
        (unspec:CCRAW [(match_operand:V_HW 0 "register_operand" "v")
-                      (match_operand:<tointvec> 1 "register_operand" "v")]
+                      (match_operand:<TOINTVEC> 1 "register_operand" "v")]
                      UNSPEC_VEC_TEST_MASK))]
   "TARGET_VX"
   "vtm\t%v0,%v1"
@@ -1946,7 +1946,7 @@
        (unspec:CCRAW [(match_operand:VF_HW 1 "register_operand"  "v")
                       (match_operand:HI    2 "const_int_operand" "J")]
                      UNSPEC_VEC_VFTCICC))
-   (clobber (match_scratch:<tointvec> 0 "=v"))]
+   (clobber (match_scratch:<TOINTVEC> 0 "=v"))]
   "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'J', \"J\")"
   "<vw>ftci<sdx>b\t%v0,%v1,%x2"
   [(set_attr "op_type" "VRR")])
@@ -1957,7 +1957,7 @@
          (unspec:CCRAW [(match_operand:VF_HW 0 "register_operand")
                         (match_operand:HI    1 "const_int_operand")]
                        UNSPEC_VEC_VFTCICC))
-     (clobber (scratch:<tointvec>))])
+     (clobber (scratch:<TOINTVEC>))])
    (set (match_operand:SI 2 "register_operand" "")
        (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))]
   "TARGET_VX && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[1]), 'J', \"J\")")
@@ -2083,7 +2083,7 @@
   [(set (reg:VFCMP CC_REGNUM)
        (compare:VFCMP (match_operand:VF_HW 0 "register_operand" "v")
                       (match_operand:VF_HW 1 "register_operand" "v")))
-   (clobber (match_scratch:<tointvec> 2 "=v"))]
+   (clobber (match_scratch:<TOINTVEC> 2 "=v"))]
   "TARGET_VX"
   "<vw>fc<asm_fcmp><sdx>bs\t%v2,%v0,%v1"
   [(set_attr "op_type" "VRR")])
@@ -2094,8 +2094,8 @@
     [(set (reg:CCVEQ CC_REGNUM)
          (compare:CCVEQ (match_operand:VF_HW 1 "register_operand"  "v")
                         (match_operand:VF_HW 2 "register_operand"  "v")))
-     (set (match_operand:<tointvec> 0 "register_operand" "=v")
-         (eq:<tointvec> (match_dup 1) (match_dup 2)))])
+     (set (match_operand:<TOINTVEC> 0 "register_operand" "=v")
+         (eq:<TOINTVEC> (match_dup 1) (match_dup 2)))])
    (set (match_operand:SI 3 "memory_operand" "")
        (unspec:SI [(reg:CCVEQ CC_REGNUM)] UNSPEC_CC_TO_INT))]
   "TARGET_VX")
@@ -2105,8 +2105,8 @@
     [(set (reg:CCVFH CC_REGNUM)
          (compare:CCVFH (match_operand:VF_HW 1 "register_operand"  "v")
                         (match_operand:VF_HW 2 "register_operand"  "v")))
-     (set (match_operand:<tointvec> 0 "register_operand" "=v")
-         (gt:<tointvec> (match_dup 1) (match_dup 2)))])
+     (set (match_operand:<TOINTVEC> 0 "register_operand" "=v")
+         (gt:<TOINTVEC> (match_dup 1) (match_dup 2)))])
    (set (match_operand:SI 3 "memory_operand" "")
        (unspec:SI [(reg:CCVIH CC_REGNUM)] UNSPEC_CC_TO_INT))]
   "TARGET_VX")
@@ -2116,8 +2116,8 @@
     [(set (reg:CCVFHE CC_REGNUM)
          (compare:CCVFHE (match_operand:VF_HW 1 "register_operand"  "v")
                          (match_operand:VF_HW 2 "register_operand"  "v")))
-     (set (match_operand:<tointvec> 0 "register_operand" "=v")
-         (ge:<tointvec> (match_dup 1) (match_dup 2)))])
+     (set (match_operand:<TOINTVEC> 0 "register_operand" "=v")
+         (ge:<TOINTVEC> (match_dup 1) (match_dup 2)))])
    (set (match_operand:SI 3 "memory_operand" "")
        (unspec:SI [(reg:CCVFHE CC_REGNUM)] UNSPEC_CC_TO_INT))]
   "TARGET_VX")
@@ -2131,8 +2131,8 @@
   [(set (reg:CCVEQ CC_REGNUM)
        (compare:CCVEQ (match_operand:VF_HW 0 "register_operand"  "v")
                       (match_operand:VF_HW 1 "register_operand"  "v")))
-   (set (match_operand:<tointvec>              2 "register_operand" "=v")
-       (eq:<tointvec> (match_dup 0) (match_dup 1)))]
+   (set (match_operand:<TOINTVEC>              2 "register_operand" "=v")
+       (eq:<TOINTVEC> (match_dup 0) (match_dup 1)))]
   "TARGET_VX"
   "<vw>fce<sdx>bs\t%v2,%v0,%v1"
   [(set_attr "op_type" "VRR")])
@@ -2142,8 +2142,8 @@
   [(set (reg:CCVFH CC_REGNUM)
        (compare:CCVFH (match_operand:VF_HW 0 "register_operand"  "v")
                       (match_operand:VF_HW 1 "register_operand"  "v")))
-   (set (match_operand:<tointvec>              2 "register_operand" "=v")
-       (gt:<tointvec> (match_dup 0) (match_dup 1)))]
+   (set (match_operand:<TOINTVEC>              2 "register_operand" "=v")
+       (gt:<TOINTVEC> (match_dup 0) (match_dup 1)))]
   "TARGET_VX"
   "<vw>fch<sdx>bs\t%v2,%v0,%v1"
   [(set_attr "op_type" "VRR")])
@@ -2153,8 +2153,8 @@
   [(set (reg:CCVFHE CC_REGNUM)
        (compare:CCVFHE (match_operand:VF_HW 0 "register_operand"  "v")
                        (match_operand:VF_HW 1 "register_operand"  "v")))
-   (set (match_operand:<tointvec>            2 "register_operand" "=v")
-       (ge:<tointvec> (match_dup 0) (match_dup 1)))]
+   (set (match_operand:<TOINTVEC>            2 "register_operand" "=v")
+       (ge:<TOINTVEC> (match_dup 0) (match_dup 1)))]
   "TARGET_VX"
   "<vw>fche<sdx>bs\t%v2,%v0,%v1"
   [(set_attr "op_type" "VRR")])