aarch64-simd-builtins.def (bswap): Use CF2 rather than CF10 so 2 is appended on the...

2014-12-05  Andrew Pinski  <apinski@cavium.com>

        * config/aarch64/aarch64-simd-builtins.def (bswap): Use CF2 rather
        than CF10 so 2 is appended on the code.
        * config/aarch64/aarch64-simd.md (bswap<mode>): Rename to ...
        (bswap<mode>2): This so it matches for the optabs.

From-SVN: r218435

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d0375513a23beccc6ae5c255668ab7e2f4ae1534..48e713b4ef264d3cc6b4504ba75dba73b1299970 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2014-12-05  Andrew Pinski  <apinski@cavium.com>
+
+       * config/aarch64/aarch64-simd-builtins.def (bswap): Use CF2 rather
+       than CF10 so 2 is appended on the code.
+       * config/aarch64/aarch64-simd.md (bswap<mode>): Rename to ...
+       (bswap<mode>2): This so it matches for the optabs.
+
 2014-12-05  Thomas Preud'homme  <thomas.preudhomme@arm.com>
 
        * regrename.c (find_best_rename_reg): Rename to ...

diff --git a/gcc/config/aarch64/aarch64-simd-builtins.def b/gcc/config/aarch64/aarch64-simd-builtins.def
index 4eb70ff629f9e3f317c4518046b1e0e88277ef88..503fa2c6b610d7526a631cbc5706fffb2b9b07c4 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd-builtins.def
+++ b/gcc/config/aarch64/aarch64-simd-builtins.def
@@ -317,7 +317,7 @@
   VAR1 (UNOP, floatunsv4si, 2, v4sf)
   VAR1 (UNOP, floatunsv2di, 2, v2df)
 
-  VAR5 (UNOPU, bswap, 10, v4hi, v8hi, v2si, v4si, v2di)
+  VAR5 (UNOPU, bswap, 2, v4hi, v8hi, v2si, v4si, v2di)
 
   BUILTIN_VB (UNOP, rbit, 0)
 

diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 0ec132345a5b5d5cc68450fa38f73e727ba45d01..4995e4dfe94c287bfd859641de31f0c9bbdef6cc 100644 (file)
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -287,7 +287,7 @@
   [(set_attr "type" "neon_mul_<Vetype><q>")]
 )
 
-(define_insn "bswap<mode>"
+(define_insn "bswap<mode>2"
   [(set (match_operand:VDQHSD 0 "register_operand" "=w")
         (bswap:VDQHSD (match_operand:VDQHSD 1 "register_operand" "w")))]
   "TARGET_SIMD"
@@ -309,7 +309,7 @@
         (ctz:VS (match_operand:VS 1 "register_operand")))]
   "TARGET_SIMD"
   {
-     emit_insn (gen_bswap<mode> (operands[0], operands[1]));
+     emit_insn (gen_bswap<mode>2 (operands[0], operands[1]));
      rtx op0_castsi2qi = simplify_gen_subreg(<VS:VSI2QI>mode, operands[0],
                                             <MODE>mode, 0);
      emit_insn (gen_aarch64_rbit<VS:vsi2qi> (op0_castsi2qi, op0_castsi2qi));