(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 6aa54155bc47bfe1e15a3e1663405402a36aef39..fefe531720d20828007999107bd3c57122150a0a 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -129,7 +129,8 @@ Brief description of fields:
 
 * **sz=1** if predication is enabled and `sz=1` and a predicate
   element bit is zero, `SNZ` will
-  be substituted in place of the CR bit selected by `BI`.
+  be substituted in place of the CR bit selected by `BI`,
+  as the Condition tested.
   Contrast this with
   normal SVP64 `sz=1` behaviour, where *only* a zero is put in
   place of masked-out predicate bits.