Signed-off-by: Clifford Wolf <clifford@clifford.at>
if (str == endptr)
len_in_bits = -1;
- // The "<bits>'s?[bodhBODH]<digits>" syntax
+ // The "<bits>'[sS]?[bodhBODH]<digits>" syntax
if (*endptr == '\'')
{
std::vector<RTLIL::State> data;
bool is_signed = false;
bool is_unsized = len_in_bits < 0;
- if (*(endptr+1) == 's') {
+ if (*(endptr+1) == 's' || *(endptr+1) == 'S') {
is_signed = true;
endptr++;
}
return TOK_CONSTVAL;
}
-[0-9]*[ \t]*\'s?[bodhBODH]*[ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
+[0-9]*[ \t]*\'[sS]?[bodhBODH][ \t\r\n]*[0-9a-fA-FzxZX?_]+ {
frontend_verilog_yylval.string = new std::string(yytext);
return TOK_CONSTVAL;
}