opt_lut: leave intact LUTs with cascade feeding module outputs.

diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc
index 4207fbdb9d31f850071bdabae41521d9407e727e..ba2cc6ee7b96ea51fc688276a2cb7d081a10b1c0 100644 (file)
--- a/passes/opt/opt_lut.cc
+++ b/passes/opt/opt_lut.cc
@@ -225,6 +225,12 @@ struct OptLutWorker
 
                                        log("Found %s.%s (cell A) feeding %s.%s (cell B).\n", log_id(module), log_id(lutA), log_id(module), log_id(lutB));
 
+                                       if (index.query_is_output(lutA->getPort("\\Y")))
+                                       {
+                                               log("  Not combining LUTs (cascade connection feeds module output).\n");
+                                               continue;
+                                       }
+
                                        pool<SigBit> lutA_inputs;
                                        pool<SigBit> lutB_inputs;
                                        for (auto &bit : lutA_input)

diff --git a/tests/opt/opt_lut_port.il b/tests/opt/opt_lut_port.il
new file mode 100644 (file)
index 0000000..7eb7189
--- /dev/null
+++ b/tests/opt/opt_lut_port.il
@@ -0,0 +1,18 @@
+module $1
+  wire width 4 input 2 \_0_
+  wire output 4 \_1_
+  wire input 3 \_2_
+  wire output 1 \o
+  cell $lut \_3_
+    parameter \LUT 16'0011000000000011
+    parameter \WIDTH 4
+    connect \A { \_0_ [3] \o 2'00 }
+    connect \Y \_1_
+  end
+  cell $lut \_4_
+    parameter \LUT 4'0001
+    parameter \WIDTH 4
+    connect \A { 3'000 \_2_ }
+    connect \Y \o
+  end
+end

diff --git a/tests/opt/opt_lut_port.ys b/tests/opt/opt_lut_port.ys
new file mode 100644 (file)
index 0000000..51dfd98
--- /dev/null
+++ b/tests/opt/opt_lut_port.ys
@@ -0,0 +1,2 @@
+read_ilang opt_lut_port.il
+select -assert-count 2 t:$lut