config: Remove redundant explicit setting of default clocks

This patch removes the explicit setting of the clock period for
certain instances of CoherentBus, NonCoherentBus and IOCache where the
specified clock is same as the default value of the system clock. As
all the values used are the defaults, there are no performance
changes. There are similar cases where the toL2Bus is set to use the
parent CPU clock which is already the default behaviour.

The main motivation for these simplifications is to ease the
introduction of clock domains.

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 4fedf12db2a1f72ff5a8d8e5ae64922453340b0c..b17266e54cbb89e5a96eb07c000d0faaa8114fa0 100644 (file)
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -134,8 +134,8 @@ if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
     test_sys.vm = KvmVM()
 
 if options.caches or options.l2cache:
-    test_sys.iocache = IOCache(clock = '1GHz',
-                               addr_ranges = test_sys.mem_ranges)
+    # By default the IOCache runs at the system clock
+    test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
     test_sys.iocache.cpu_side = test_sys.iobus.master
     test_sys.iocache.mem_side = test_sys.membus.slave
 else:

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index f52c6b11f8c518f04f886ec1c792725d8f532e1a..e7613c5bb7493bb938e477cf0c6ed0ff369c9792 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -281,10 +281,10 @@ class BaseCPU(MemObject):
 
     def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
         self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
-        # Override the default bus clock of 1 GHz and uses the CPU
-        # clock for the L1-to-L2 bus, and also set a width of 32 bytes
-        # (256-bits), which is four times that of the default bus.
-        self.toL2Bus = CoherentBus(clock = Parent.clock, width = 32)
+        # Set a width of 32 bytes (256-bits), which is four times that
+        # of the default bus. The clock of the CPU is inherited by
+        # default.
+        self.toL2Bus = CoherentBus(width = 32)
         self.connectCachedPorts(self.toL2Bus)
         self.l2cache = l2c
         self.toL2Bus.master = self.l2cache.cpu_side

diff --git a/src/dev/CopyEngine.py b/src/dev/CopyEngine.py
index 68332e0a0dd84e51806d30293eba566bb3bca54e..d56294d669880ec7e5bbbbd69ad408bfcf91f5d5 100644 (file)
--- a/src/dev/CopyEngine.py
+++ b/src/dev/CopyEngine.py
@@ -53,8 +53,6 @@ class CopyEngine(PciDevice):
     ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
     XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
 
-    # Override the default clock
-    clock = '500MHz'
     latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
     latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
 

diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index ab994b6f0355bed3ffd977a0a9f42d13cf37c523..5c2768fb92aa4eaf1b3ca8aab2f221ac7036e2e4 100644 (file)
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -118,8 +118,6 @@ class CpuLocalTimer(BasicPioDevice):
     gic = Param.BaseGic(Parent.any, "Gic to use for interrupting")
     int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
     int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
-    # Override the default clock
-    clock = '1GHz'
 
 class PL031(AmbaIntDevice):
     type = 'PL031'

diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py
index ba261cc36a8c27b96bfc7e283a729ff7170ac16c..29e395404b8af4609080eae82ea739f8e55d00d5 100644 (file)
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -36,7 +36,6 @@ class RubySystem(ClockedObject):
     random_seed = Param.Int(1234, "random seed used by the simulation");
     randomization = Param.Bool(False,
         "insert random delays on message enqueue times");
-    clock = '1GHz'
     block_size_bytes = Param.UInt32(64,
         "default cache block size; must be a power of two");
     mem_size = Param.MemorySize("total memory size of the system");

diff --git a/tests/configs/base_config.py b/tests/configs/base_config.py
index 29aec35e723242a18c747c814252b919d5b44392..60ba3166577dbbfee1c22c7678d536ab8c7da252 100644 (file)
--- a/tests/configs/base_config.py
+++ b/tests/configs/base_config.py
@@ -161,8 +161,8 @@ class BaseFSSystem(BaseSystem):
     def init_system(self, system):
         BaseSystem.init_system(self, system)
 
-        #create the iocache
-        system.iocache = IOCache(clock='1GHz', addr_ranges=system.mem_ranges)
+        # create the iocache, which by default runs at the system clock
+        system.iocache = IOCache(addr_ranges=system.mem_ranges)
         system.iocache.cpu_side = system.iobus.master
         system.iocache.mem_side = system.membus.slave
 

diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 55c086d69ebc87498c40bb05bfec7420f8dd12d7..379b1e4217cab4417619583ef827f5a55d8c98bb 100644 (file)
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -39,7 +39,7 @@ cpus = [ MemTest(clock = '2GHz') for i in xrange(nb_cores) ]
 system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
                 funcbus = NoncoherentBus(),
                 physmem = SimpleMemory(),
-                membus = CoherentBus(clock="1GHz", width=16))
+                membus = CoherentBus(width=16))
 
 # l2cache & bus
 system.toL2Bus = CoherentBus(clock="2GHz", width=16)

diff --git a/tests/configs/tgen-simple-dram.py b/tests/configs/tgen-simple-dram.py
index 407852682658c02cae3c051636d5a1e47be3f5cf..b57817c95e78b037e095cea4c5ac283bdba01641 100644 (file)
--- a/tests/configs/tgen-simple-dram.py
+++ b/tests/configs/tgen-simple-dram.py
@@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
 
 # system simulated
 system = System(cpu = cpu, physmem = DDR3_1600_x64(),
-                membus = NoncoherentBus(clock="1GHz", width = 16))
+                membus = NoncoherentBus(width = 16))
 
 # add a communication monitor
 system.monitor = CommMonitor()

diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py
index d402e557c318606709d8602a159923565b7512fe..200834ec3e6a905a5e329539759621b924b26eba 100644 (file)
--- a/tests/configs/tgen-simple-mem.py
+++ b/tests/configs/tgen-simple-mem.py
@@ -49,7 +49,7 @@ cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg")
 
 # system simulated
 system = System(cpu = cpu, physmem = SimpleMemory(),
-                membus = NoncoherentBus(clock="1GHz", width = 16))
+                membus = NoncoherentBus(width = 16))
 
 # add a communication monitor, and also trace all the packets
 system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz")