shuffle things around a bit for sv, put rv32/64_name back to like they were

decided to move sv to its own template file, and make a bit more use
of macro pre-processing

diff --git a/riscv/insn_template.cc b/riscv/insn_template.cc
index 46a5321f3565e91de4841be2914b532e33df0b32..9bfda57b48d62be046946e9d21321821db803ab5 100644 (file)
--- a/riscv/insn_template.cc
+++ b/riscv/insn_template.cc
@@ -3,24 +3,43 @@
 #include "insn_template.h"
 
 #ifdef SPIKE_SIMPLEV
+
+/* transfer the sed/awk processing through to insn_template_sv.cc
+ * however it's been noted that the rv32_xx and rv64_xx functions
+ * are absolutely identical, so to avoid duplicating them, the
+ * exact same template is included *twice*... with macro #defines
+ * to indicate the size (32/64).
+ * 
+ * the messy-looking INCLUDEFILE, INSCODE and INSN #defines are
+ * here because the sed/awk processing from Makefile is *not*
+ * a macro pre-processor, it's an *actual* hard-substitution.
+ * so below, #define INSN NAME is substituted with "#define INSN add"
+ * when add.cc is created from this template, etc.  the use of the
+ * weird macro names is to avoid e.g. #define INSOPCODE OPCODE being
+ * substituted as "#define INSadd add" during the awk/sed processing.
+ */
+#define INSN NAME
+#define INCLUDEFILE "insns/NAME.h"
+#define INSNCODE OPCODE
 #include "sv_decode.h"
-#endif
+#define FN rv32_NAME
+#define ISASZ 32
+#include "insn_template_sv.cc"
+#undef ISASZ
+#undef FN
+#define ISASZ 64
+#define FN rv64_NAME
+#include "insn_template_sv.cc"
 
-reg_t rv32_NAME(processor_t* p, insn_t s_insn, reg_t pc)
+#else
+
+reg_t rv32_NAME(processor_t* p, insn_t insn, reg_t pc)
 {
   int xlen = 32;
   reg_t npc = sext_xlen(pc + insn_length(OPCODE));
   insn_bits_t bits = s_insn.bits();
-#ifdef SPIKE_SIMPLEV
-  int voffs = 0;
-  sv_insn_t insn(bits, voffs);
-  #include "insns/NAME.h"
-  trace_opcode(p, OPCODE, s_insn);
-#else
-  insn_t insn(bits);
   #include "insns/NAME.h"
   trace_opcode(p, OPCODE, s_insn);
-#endif
   return npc;
 }
 
@@ -29,15 +48,10 @@ reg_t rv64_NAME(processor_t* p, insn_t s_insn, reg_t pc)
   int xlen = 64;
   reg_t npc = sext_xlen(pc + insn_length(OPCODE));
   insn_bits_t bits = s_insn.bits();
-#ifdef SPIKE_SIMPLEV
-  int voffs = 0;
-  sv_insn_t insn(bits, voffs);
-  #include "insns/NAME.h"
-  trace_opcode(p, OPCODE, s_insn);
-#else
   insn_t insn(bits);
   #include "insns/NAME.h"
   trace_opcode(p, OPCODE, s_insn);
-#endif
   return npc;
 }
+#endif
+

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
new file mode 100644 (file)
index 0000000..b83f877
--- /dev/null
+++ b/riscv/insn_template_sv.cc
@@ -0,0 +1,14 @@
+// See LICENSE for license details.
+
+reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
+{
+  int xlen = ISASZ;
+  reg_t npc = sext_xlen(pc + insn_length(INSNCODE));
+  insn_bits_t bits = s_insn.bits();
+  int voffs = 0;
+  sv_insn_t insn(bits, voffs);
+  #include INCLUDEFILE
+  trace_opcode(p, INSNCODE, s_insn);
+  return npc;
+}
+