X(AST_ARGUMENT)
X(AST_RANGE)
X(AST_CONSTANT)
+ X(AST_REALVALUE)
X(AST_CELLTYPE)
X(AST_IDENTIFIER)
X(AST_PREFIX)
fprintf(f, "%zd'b %s", bits.size(), RTLIL::Const(bits).as_string().c_str());
break;
+ case AST_REALVALUE:
+ fprintf(f, "%e", realvalue);
+ break;
+
case AST_BLOCK:
if (children.size() == 1) {
children[0]->dumpVlog(f, indent);
AST_ARGUMENT,
AST_RANGE,
AST_CONSTANT,
+ AST_REALVALUE,
AST_CELLTYPE,
AST_IDENTIFIER,
AST_PREFIX,
bool is_input, is_output, is_reg, is_signed, is_string, range_valid;
int port_id, range_left, range_right;
uint32_t integer;
+ double realvalue;
// this is set by simplify and used during RTLIL generation
AstNode *id2ast;
return TOK_CONST;
}
+[0-9][0-9_]*\.[0-9][0-9_]*([eE][-+]?[0-9_]+)? {
+ frontend_verilog_yylval.string = new std::string(yytext);
+ return TOK_REAL;
+}
+
+[0-9][0-9_]*[eE][-+]?[0-9_]+ {
+ frontend_verilog_yylval.string = new std::string(yytext);
+ return TOK_REAL;
+}
+
\" { BEGIN(STRING); }
<STRING>\\. { yymore(); }
<STRING>\" {
%{
#include <list>
-#include <assert.h>
+#include <string.h>
#include "verilog_frontend.h"
#include "kernel/log.h"
bool boolean;
}
-%token <string> TOK_STRING TOK_ID TOK_CONST TOK_PRIMITIVE
+%token <string> TOK_STRING TOK_ID TOK_CONST TOK_REAL TOK_PRIMITIVE
%token ATTR_BEGIN ATTR_END DEFATTR_BEGIN DEFATTR_END
%token TOK_MODULE TOK_ENDMODULE TOK_PARAMETER TOK_LOCALPARAM TOK_DEFPARAM
%token TOK_INPUT TOK_OUTPUT TOK_INOUT TOK_WIRE TOK_REG
frontend_verilog_yyerror("Missing details for module port `%s'.",
port_stubs.begin()->first.c_str());
ast_stack.pop_back();
- assert(ast_stack.size() == 0);
+ log_assert(ast_stack.size() == 0);
};
module_para_opt:
log_error("Value conversion failed: `%s'\n", $1->c_str());
delete $1;
} |
+ TOK_REAL {
+ $$ = new AstNode(AST_REALVALUE);
+ char *p = strdup($1->c_str()), *q;
+ for (int i = 0, j = 0; !p[j]; j++)
+ if (p[j] != '_')
+ p[i++] = p[j], p[i] = 0;
+ $$->realvalue = strtod(p, &q);
+ log_assert(*q == 0);
+ delete $1;
+ free(p);
+ } |
TOK_STRING {
$$ = AstNode::mkconst_str(*$1);
delete $1;