i965: get outputs written from nir info

This is a step towards dropping the GLSL IR version of
do_set_program_inouts() in i965 and moving towards native nir support.

This is important because we want to eventually convert to nir and
use its optimisations passes before we can call this GLSL IR pass.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_gs.c b/src/mesa/drivers/dri/i965/brw_gs.c
index a898260eeda8d7150370db70df26a3eb70e8c9f6..12bc706e9f2647be1fd5e538955b9c824f325576 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -134,7 +134,7 @@ brw_codegen_gs_prog(struct brw_context *brw,
                                &prog_data.base.base,
                                compiler->scalar_stage[MESA_SHADER_GEOMETRY]);
 
-   GLbitfield64 outputs_written = gp->program.Base.OutputsWritten;
+   uint64_t outputs_written = gp->program.Base.nir->info.outputs_written;
 
    prog_data.base.cull_distance_mask =
       ((1 << gp->program.Base.CullDistanceArraySize) - 1) <<

diff --git a/src/mesa/drivers/dri/i965/brw_tcs.c b/src/mesa/drivers/dri/i965/brw_tcs.c
index 84188612a1f750105a2a2dd093a0c468bbdccc0e..0b691397a2db7da95caf63daba9783830bf5c5bc 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tcs.c
+++ b/src/mesa/drivers/dri/i965/brw_tcs.c
@@ -328,8 +328,10 @@ brw_tcs_populate_key(struct brw_context *brw,
    memset(key, 0, sizeof(*key));
 
    if (brw->tess_ctrl_program) {
-      per_vertex_slots |= brw->tess_ctrl_program->Base.OutputsWritten;
-      per_patch_slots |= brw->tess_ctrl_program->Base.PatchOutputsWritten;
+      per_vertex_slots |=
+         brw->tess_ctrl_program->Base.nir->info.outputs_written;
+      per_patch_slots |=
+         brw->tess_ctrl_program->Base.nir->info.patch_outputs_written;
    }
 
    if (brw->gen < 8 || !tcp)
@@ -424,8 +426,8 @@ brw_tcs_precompile(struct gl_context *ctx,
       key.tes_primitive_mode = GL_TRIANGLES;
    }
 
-   key.outputs_written = prog->OutputsWritten;
-   key.patch_outputs_written = prog->PatchOutputsWritten;
+   key.outputs_written = prog->nir->info.outputs_written;
+   key.patch_outputs_written = prog->nir->info.patch_outputs_written;
 
    success = brw_codegen_tcs_prog(brw, shader_prog, btcp, &key);
 

diff --git a/src/mesa/drivers/dri/i965/brw_tes.c b/src/mesa/drivers/dri/i965/brw_tes.c
index 2c43a3e058f3b90f91f19e246959a94e2dedc20f..d1f56bde6061e67f9b1d99b1e25b8c15e9a8d73c 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_tes.c
+++ b/src/mesa/drivers/dri/i965/brw_tes.c
@@ -250,8 +250,10 @@ brw_tes_populate_key(struct brw_context *brw,
     * be stored in the Patch URB Entry as well.
     */
    if (brw->tess_ctrl_program) {
-      per_vertex_slots |= brw->tess_ctrl_program->Base.OutputsWritten;
-      per_patch_slots |= brw->tess_ctrl_program->Base.PatchOutputsWritten;
+      per_vertex_slots |=
+         brw->tess_ctrl_program->Base.nir->info.outputs_written;
+      per_patch_slots |=
+         brw->tess_ctrl_program->Base.nir->info.patch_outputs_written;
    }
 
    /* Ignore gl_TessLevelInner/Outer - we treat them as system values,
@@ -318,8 +320,8 @@ brw_tes_precompile(struct gl_context *ctx,
    if (shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]) {
       struct gl_program *tcp =
          shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]->Program;
-      key.inputs_read |= tcp->OutputsWritten;
-      key.patch_inputs_read |= tcp->PatchOutputsWritten;
+      key.inputs_read |= tcp->nir->info.outputs_written;
+      key.patch_inputs_read |= tcp->nir->info.patch_outputs_written;
    }
 
    /* Ignore gl_TessLevelInner/Outer - they're system values. */

diff --git a/src/mesa/drivers/dri/i965/brw_vs.c b/src/mesa/drivers/dri/i965/brw_vs.c
index bd194ca226e468a4524b1b1eec8a8f959c276431..aa1ae2851610bd86fc6b7069656fbec1cc9de76a 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vs.c
+++ b/src/mesa/drivers/dri/i965/brw_vs.c
@@ -149,8 +149,9 @@ brw_codegen_vs_prog(struct brw_context *brw,
                                  &prog_data.base.base);
    }
 
-   GLbitfield64 outputs_written =
-      brw_vs_outputs_written(brw, key, vp->program.Base.OutputsWritten);
+   uint64_t outputs_written =
+      brw_vs_outputs_written(brw, key,
+                             vp->program.Base.nir->info.outputs_written);
    prog_data.inputs_read = vp->program.Base.InputsRead;
 
    if (key->copy_edgeflag) {
@@ -339,8 +340,9 @@ brw_vs_populate_key(struct brw_context *brw,
       }
    }
 
-   if (prog->OutputsWritten & (VARYING_BIT_COL0 | VARYING_BIT_COL1 |
-                               VARYING_BIT_BFC0 | VARYING_BIT_BFC1)) {
+   if (prog->nir->info.outputs_written &
+       (VARYING_BIT_COL0 | VARYING_BIT_COL1 | VARYING_BIT_BFC0 |
+        VARYING_BIT_BFC1)) {
       /* _NEW_LIGHT | _NEW_BUFFERS */
       key->clamp_vertex_color = ctx->Light._ClampVertexColor;
    }
@@ -399,8 +401,9 @@ brw_vs_precompile(struct gl_context *ctx,
    brw_setup_tex_for_precompile(brw, &key.tex, prog);
    key.program_string_id = bvp->id;
    key.clamp_vertex_color =
-      (prog->OutputsWritten & (VARYING_BIT_COL0 | VARYING_BIT_COL1 |
-                               VARYING_BIT_BFC0 | VARYING_BIT_BFC1));
+      (prog->nir->info.outputs_written &
+       (VARYING_BIT_COL0 | VARYING_BIT_COL1 | VARYING_BIT_BFC0 |
+        VARYING_BIT_BFC1));
 
    success = brw_codegen_vs_prog(brw, shader_prog, bvp, &key);
 

diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c
index 6dcfb8003f05fa3dab3ce8f5a5fa8499d2883b1b..d5f3b22ff74b98e88495c11d7f945aa2a7b68450 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -453,8 +453,10 @@ brw_wm_populate_key(struct brw_context *brw, struct brw_wm_prog_key *key)
          lookup |= IZ_PS_KILL_ALPHATEST_BIT;
       }
 
-      if (fp->program.Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
+      if (fp->program.Base.nir->info.outputs_written &
+          BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
          lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
+      }
 
       /* _NEW_DEPTH */
       if (ctx->Depth.Test)
@@ -602,11 +604,13 @@ brw_fs_precompile(struct gl_context *ctx,
 
    memset(&key, 0, sizeof(key));
 
+   uint64_t outputs_written = fp->Base.nir->info.outputs_written;
+
    if (brw->gen < 6) {
       if (fp->Base.nir->info.fs.uses_discard)
          key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT;
 
-      if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
+      if (outputs_written & BITFIELD64_BIT(FRAG_RESULT_DEPTH))
          key.iz_lookup |= IZ_PS_COMPUTES_DEPTH_BIT;
 
       /* Just assume depth testing. */
@@ -620,7 +624,7 @@ brw_fs_precompile(struct gl_context *ctx,
 
    brw_setup_tex_for_precompile(brw, &key.tex, &fp->Base);
 
-   key.nr_color_regions = _mesa_bitcount_64(fp->Base.OutputsWritten &
+   key.nr_color_regions = _mesa_bitcount_64(outputs_written &
          ~(BITFIELD64_BIT(FRAG_RESULT_DEPTH) |
            BITFIELD64_BIT(FRAG_RESULT_STENCIL) |
            BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK)));

diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 624cd945b889acc9fe3d7fc71091fedf975eabe1..5008c91c0389d5252d5c321905a6b0d437b04887 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -37,6 +37,7 @@
 #include "brw_state.h"
 #include "brw_defines.h"
 #include "brw_wm.h"
+#include "compiler/nir/nir.h"
 
 /***********************************************************************
  * WM unit - fragment programs and rasterization
@@ -53,11 +54,11 @@ brw_color_buffer_write_enabled(struct brw_context *brw)
    /* _NEW_BUFFERS */
    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
       struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
+      uint64_t outputs_written = fp->Base.nir->info.outputs_written;
 
       /* _NEW_COLOR */
-      if (rb &&
-         (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
-          fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
+      if (rb && (outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR) ||
+                outputs_written & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) &&
          (ctx->Color.ColorMask[i][0] ||
           ctx->Color.ColorMask[i][1] ||
           ctx->Color.ColorMask[i][2] ||
@@ -167,7 +168,7 @@ brw_upload_wm_unit(struct brw_context *brw)
 
    /* BRW_NEW_FRAGMENT_PROGRAM */
    wm->wm5.program_uses_depth = prog_data->uses_src_depth;
-   wm->wm5.program_computes_depth = (fp->Base.OutputsWritten &
+   wm->wm5.program_computes_depth = (fp->Base.nir->info.outputs_written &
                                     BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0;
    /* _NEW_BUFFERS
     * Override for NULL depthbuffer case, required by the Pixel Shader Computed