BaseCPU::GlobalStats::GlobalStats(::Stats::Group *parent)
: ::Stats::Group(parent),
- simInsts(this, "sim_insts", "Number of instructions simulated"),
- simOps(this, "sim_ops", "Number of ops (including micro ops) simulated"),
- hostInstRate(this, "host_inst_rate",
- "Simulator instruction rate (inst/s)"),
- hostOpRate(this, "host_op_rate",
- "Simulator op (including micro ops) rate (op/s)")
+ ADD_STAT(simInsts, "Number of instructions simulated"),
+ ADD_STAT(simOps, "Number of ops (including micro ops) simulated"),
+ ADD_STAT(hostInstRate, "Simulator instruction rate (inst/s)"),
+ ADD_STAT(hostOpRate, "Simulator op (including micro ops) rate (op/s)")
{
simInsts
.functor(BaseCPU::numSimulatedInsts)
AbstractMemory::MemStats::MemStats(AbstractMemory &_mem)
: Stats::Group(&_mem), mem(_mem),
- bytesRead(this, "bytes_read",
- "Number of bytes read from this memory"),
- bytesInstRead(this, "bytes_inst_read",
- "Number of instructions bytes read from this memory"),
- bytesWritten(this, "bytes_written",
- "Number of bytes written to this memory"),
- numReads(this, "num_reads",
- "Number of read requests responded to by this memory"),
- numWrites(this, "num_writes",
- "Number of write requests responded to by this memory"),
- numOther(this, "num_other",
- "Number of other requests responded to by this memory"),
- bwRead(this, "bw_read",
- "Total read bandwidth from this memory (bytes/s)"),
- bwInstRead(this, "bw_inst_read",
- "Instruction read bandwidth from this memory (bytes/s)"),
- bwWrite(this, "bw_write",
- "Write bandwidth from this memory (bytes/s)"),
- bwTotal(this, "bw_total",
- "Total bandwidth to/from this memory (bytes/s)")
+ ADD_STAT(bytesRead, "Number of bytes read from this memory"),
+ ADD_STAT(bytesInstRead,
+ "Number of instructions bytes read from this memory"),
+ ADD_STAT(bytesWritten, "Number of bytes written to this memory"),
+ ADD_STAT(numReads, "Number of read requests responded to by this memory"),
+ ADD_STAT(numWrites,
+ "Number of write requests responded to by this memory"),
+ ADD_STAT(numOther, "Number of other requests responded to by this memory"),
+ ADD_STAT(bwRead, "Total read bandwidth from this memory (bytes/s)"),
+ ADD_STAT(bwInstRead,
+ "Instruction read bandwidth from this memory (bytes/s)"),
+ ADD_STAT(bwWrite, "Write bandwidth from this memory (bytes/s)"),
+ ADD_STAT(bwTotal, "Total bandwidth to/from this memory (bytes/s)")
{
}
BaseCache::CacheStats::CacheStats(BaseCache &c)
: Stats::Group(&c), cache(c),
- demandHits(this, "demand_hits", "number of demand (read+write) hits"),
-
- overallHits(this, "overall_hits", "number of overall hits"),
- demandMisses(this, "demand_misses",
- "number of demand (read+write) misses"),
- overallMisses(this, "overall_misses", "number of overall misses"),
- demandMissLatency(this, "demand_miss_latency",
- "number of demand (read+write) miss cycles"),
- overallMissLatency(this, "overall_miss_latency",
- "number of overall miss cycles"),
- demandAccesses(this, "demand_accesses",
- "number of demand (read+write) accesses"),
- overallAccesses(this, "overall_accesses",
- "number of overall (read+write) accesses"),
- demandMissRate(this, "demand_miss_rate",
- "miss rate for demand accesses"),
- overallMissRate(this, "overall_miss_rate",
- "miss rate for overall accesses"),
- demandAvgMissLatency(this, "demand_avg_miss_latency",
- "average overall miss latency"),
- overallAvgMissLatency(this, "overall_avg_miss_latency",
- "average overall miss latency"),
- blocked_cycles(this, "blocked_cycles",
- "number of cycles access was blocked"),
- blocked_causes(this, "blocked", "number of cycles access was blocked"),
- avg_blocked(this, "avg_blocked_cycles",
- "average number of cycles each access was blocked"),
- unusedPrefetches(this, "unused_prefetches",
- "number of HardPF blocks evicted w/o reference"),
- writebacks(this, "writebacks", "number of writebacks"),
- demandMshrHits(this, "demand_mshr_hits",
- "number of demand (read+write) MSHR hits"),
- overallMshrHits(this, "overall_mshr_hits",
- "number of overall MSHR hits"),
- demandMshrMisses(this, "demand_mshr_misses",
- "number of demand (read+write) MSHR misses"),
- overallMshrMisses(this, "overall_mshr_misses",
- "number of overall MSHR misses"),
- overallMshrUncacheable(this, "overall_mshr_uncacheable_misses",
- "number of overall MSHR uncacheable misses"),
- demandMshrMissLatency(this, "demand_mshr_miss_latency",
- "number of demand (read+write) MSHR miss cycles"),
- overallMshrMissLatency(this, "overall_mshr_miss_latency",
- "number of overall MSHR miss cycles"),
- overallMshrUncacheableLatency(this, "overall_mshr_uncacheable_latency",
- "number of overall MSHR uncacheable cycles"),
- demandMshrMissRate(this, "demand_mshr_miss_rate",
- "mshr miss rate for demand accesses"),
- overallMshrMissRate(this, "overall_mshr_miss_rate",
- "mshr miss rate for overall accesses"),
- demandAvgMshrMissLatency(this, "demand_avg_mshr_miss_latency",
- "average overall mshr miss latency"),
- overallAvgMshrMissLatency(this, "overall_avg_mshr_miss_latency",
- "average overall mshr miss latency"),
- overallAvgMshrUncacheableLatency(
- this, "overall_avg_mshr_uncacheable_latency",
- "average overall mshr uncacheable latency"),
- replacements(this, "replacements", "number of replacements"),
-
- dataExpansions(this, "data_expansions", "number of data expansions"),
- dataContractions(this, "data_contractions", "number of data contractions"),
+ ADD_STAT(demandHits, "number of demand (read+write) hits"),
+ ADD_STAT(overallHits, "number of overall hits"),
+ ADD_STAT(demandMisses, "number of demand (read+write) misses"),
+ ADD_STAT(overallMisses, "number of overall misses"),
+ ADD_STAT(demandMissLatency, "number of demand (read+write) miss cycles"),
+ ADD_STAT(overallMissLatency, "number of overall miss cycles"),
+ ADD_STAT(demandAccesses, "number of demand (read+write) accesses"),
+ ADD_STAT(overallAccesses, "number of overall (read+write) accesses"),
+ ADD_STAT(demandMissRate, "miss rate for demand accesses"),
+ ADD_STAT(overallMissRate, "miss rate for overall accesses"),
+ ADD_STAT(demandAvgMissLatency, "average overall miss latency"),
+ ADD_STAT(overallAvgMissLatency, "average overall miss latency"),
+ ADD_STAT(blockedCycles, "number of cycles access was blocked"),
+ ADD_STAT(blockedCauses, "number of cycles access was blocked"),
+ ADD_STAT(avgBlocked,"average number of cycles each access was blocked"),
+ ADD_STAT(unusedPrefetches,
+ "number of HardPF blocks evicted w/o reference"),
+ ADD_STAT(writebacks, "number of writebacks"),
+ ADD_STAT(demandMshrHits, "number of demand (read+write) MSHR hits"),
+ ADD_STAT(overallMshrHits, "number of overall MSHR hits"),
+ ADD_STAT(demandMshrMisses, "number of demand (read+write) MSHR misses"),
+ ADD_STAT(overallMshrMisses, "number of overall MSHR misses"),
+ ADD_STAT(overallMshrUncacheable,
+ "number of overall MSHR uncacheable misses"),
+ ADD_STAT(demandMshrMissLatency,
+ "number of demand (read+write) MSHR miss cycles"),
+ ADD_STAT(overallMshrMissLatency, "number of overall MSHR miss cycles"),
+ ADD_STAT(overallMshrUncacheableLatency,
+ "number of overall MSHR uncacheable cycles"),
+ ADD_STAT(demandMshrMissRate, "mshr miss rate for demand accesses"),
+ ADD_STAT(overallMshrMissRate, "mshr miss rate for overall accesses"),
+ ADD_STAT(demandAvgMshrMissLatency, "average overall mshr miss latency"),
+ ADD_STAT(overallAvgMshrMissLatency, "average overall mshr miss latency"),
+ ADD_STAT(overallAvgMshrUncacheableLatency,
+ "average overall mshr uncacheable latency"),
+ ADD_STAT(replacements, "number of replacements"),
+ ADD_STAT(dataExpansions, "number of data expansions"),
+ ADD_STAT(dataContractions, "number of data contractions"),
cmd(MemCmd::NUM_MEM_CMDS)
{
for (int idx = 0; idx < MemCmd::NUM_MEM_CMDS; ++idx)
overallAvgMissLatency.subname(i, system->getRequestorName(i));
}
- blocked_cycles.init(NUM_BLOCKED_CAUSES);
- blocked_cycles
+ blockedCycles.init(NUM_BLOCKED_CAUSES);
+ blockedCycles
.subname(Blocked_NoMSHRs, "no_mshrs")
.subname(Blocked_NoTargets, "no_targets")
;
- blocked_causes.init(NUM_BLOCKED_CAUSES);
- blocked_causes
+ blockedCauses.init(NUM_BLOCKED_CAUSES);
+ blockedCauses
.subname(Blocked_NoMSHRs, "no_mshrs")
.subname(Blocked_NoTargets, "no_targets")
;
- avg_blocked
+ avgBlocked
.subname(Blocked_NoMSHRs, "no_mshrs")
.subname(Blocked_NoTargets, "no_targets")
;
- avg_blocked = blocked_cycles / blocked_causes;
+ avgBlocked = blockedCycles / blockedCauses;
unusedPrefetches.flags(nozero);
Stats::Formula overallAvgMissLatency;
/** The total number of cycles blocked for each blocked cause. */
- Stats::Vector blocked_cycles;
+ Stats::Vector blockedCycles;
/** The number of times this cache blocked for each blocked cause. */
- Stats::Vector blocked_causes;
+ Stats::Vector blockedCauses;
/** The average number of cycles blocked for each blocked cause. */
- Stats::Formula avg_blocked;
+ Stats::Formula avgBlocked;
/** The number of times a HW-prefetched block is evicted w/o
* reference. */
{
uint8_t flag = 1 << cause;
if (blocked == 0) {
- stats.blocked_causes[cause]++;
+ stats.blockedCauses[cause]++;
blockedCycle = curCycle();
cpuSidePort.setBlocked();
}
blocked &= ~flag;
DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
if (blocked == 0) {
- stats.blocked_cycles[cause] += curCycle() - blockedCycle;
+ stats.blockedCycles[cause] += curCycle() - blockedCycle;
cpuSidePort.clearBlocked();
}
}
Base::BaseStats::BaseStats(Base& _compressor)
: Stats::Group(&_compressor), compressor(_compressor),
- compressions(this, "compressions",
- "Total number of compressions"),
- failedCompressions(this, "failed_compressions",
- "Total number of failed compressions"),
- compressionSize(this, "compression_size",
- "Number of blocks that were compressed to this power of two size"),
- compressionSizeBits(this, "compression_size_bits",
- "Total compressed data size, in bits"),
- avgCompressionSizeBits(this, "avg_compression_size_bits",
- "Average compression size, in bits"),
- decompressions(this, "total_decompressions",
- "Total number of decompressions")
+ ADD_STAT(compressions, "Total number of compressions"),
+ ADD_STAT(failedCompressions, "Total number of failed compressions"),
+ ADD_STAT(compressionSize, "Number of blocks that were compressed to this "
+ "power of two size"),
+ ADD_STAT(compressionSizeBits, "Total compressed data size, in bits"),
+ ADD_STAT(avgCompressionSizeBits, "Average compression size, in bits"),
+ ADD_STAT(decompressions, "Total number of decompressions")
{
}
BaseDictionaryCompressor::DictionaryStats::DictionaryStats(
BaseStats& base_group, BaseDictionaryCompressor& _compressor)
: Stats::Group(&base_group), compressor(_compressor),
- patterns(this, "pattern",
- "Number of data entries that were compressed to this pattern")
+ ADD_STAT(patterns,
+ "Number of data entries that were compressed to this pattern")
{
}
Multi::MultiStats::MultiStats(BaseStats& base_group, Multi& _compressor)
: Stats::Group(&base_group), compressor(_compressor),
- ranks(this, "ranks",
- "Number of times each compressor had the nth best compression")
+ ADD_STAT(ranks,
+ "Number of times each compressor had the nth best compression")
{
}
: Stats::Group(&_tags),
tags(_tags),
- tagsInUse(this, "tagsinuse",
- "Cycle average of tags in use"),
- totalRefs(this, "total_refs",
- "Total number of references to valid blocks."),
- sampledRefs(this, "sampled_refs",
- "Sample count of references to valid blocks."),
- avgRefs(this, "avg_refs",
- "Average number of references to valid blocks."),
- warmupCycle(this, "warmup_cycle",
- "Cycle when the warmup percentage was hit."),
- occupancies(this, "occ_blocks",
- "Average occupied blocks per requestor"),
- avgOccs(this, "occ_percent",
- "Average percentage of cache occupancy"),
- occupanciesTaskId(this, "occ_task_id_blocks",
- "Occupied blocks per task id"),
- ageTaskId(this, "age_task_id_blocks", "Occupied blocks per task id"),
- percentOccsTaskId(this, "occ_task_id_percent",
- "Percentage of cache occupancy per task id"),
- tagAccesses(this, "tag_accesses", "Number of tag accesses"),
- dataAccesses(this, "data_accesses", "Number of data accesses")
+ ADD_STAT(tagsInUse, "Cycle average of tags in use"),
+ ADD_STAT(totalRefs, "Total number of references to valid blocks."),
+ ADD_STAT(sampledRefs, "Sample count of references to valid blocks."),
+ ADD_STAT(avgRefs, "Average number of references to valid blocks."),
+ ADD_STAT(warmupCycle, "Cycle when the warmup percentage was hit."),
+ ADD_STAT(occupancies, "Average occupied blocks per requestor"),
+ ADD_STAT(avgOccs, "Average percentage of cache occupancy"),
+ ADD_STAT(occupanciesTaskId, "Occupied blocks per task id"),
+ ADD_STAT(ageTaskId, "Occupied blocks per task id"),
+ ADD_STAT(percentOccsTaskId, "Percentage of cache occupancy per task id"),
+ ADD_STAT(tagAccesses, "Number of tag accesses"),
+ ADD_STAT(dataAccesses, "Number of data accesses")
{
}
SectorTags::SectorTagsStats::SectorTagsStats(BaseTagStats &base_group,
SectorTags& _tags)
: Stats::Group(&base_group), tags(_tags),
- evictionsReplacement(this, "evictions_replacement",
- "Number of blocks evicted due to a replacement")
+ ADD_STAT(evictionsReplacement,
+ "Number of blocks evicted due to a replacement")
{
}
pointOfCoherency(p.point_of_coherency),
pointOfUnification(p.point_of_unification),
- snoops(this, "snoops", "Total snoops (count)"),
- snoopTraffic(this, "snoopTraffic", "Total snoop traffic (bytes)"),
- snoopFanout(this, "snoop_fanout", "Request fanout histogram")
+ ADD_STAT(snoops, "Total snoops (count)"),
+ ADD_STAT(snoopTraffic, "Total snoop traffic (bytes)"),
+ ADD_STAT(snoopFanout, "Request fanout histogram")
{
// create the ports based on the size of the memory-side port and
// CPU-side port vector ports, and the presence of the default port,
void
AbstractController::init()
{
- stats.m_delayHistogram.init(10);
+ stats.delayHistogram.init(10);
uint32_t size = Network::getNumberOfVirtualNetworks();
for (uint32_t i = 0; i < size; i++) {
- stats.m_delayVCHistogram.push_back(new Stats::Histogram(this));
- stats.m_delayVCHistogram[i]->init(10);
+ stats.delayVCHistogram.push_back(new Stats::Histogram(this));
+ stats.delayVCHistogram[i]->init(10);
}
if (getMemReqQueue()) {
void
AbstractController::resetStats()
{
- stats.m_delayHistogram.reset();
+ stats.delayHistogram.reset();
uint32_t size = Network::getNumberOfVirtualNetworks();
for (uint32_t i = 0; i < size; i++) {
- stats.m_delayVCHistogram[i]->reset();
+ stats.delayVCHistogram[i]->reset();
}
}
void
AbstractController::profileMsgDelay(uint32_t virtualNetwork, Cycles delay)
{
- assert(virtualNetwork < stats.m_delayVCHistogram.size());
- stats.m_delayHistogram.sample(delay);
- stats.m_delayVCHistogram[virtualNetwork]->sample(delay);
+ assert(virtualNetwork < stats.delayVCHistogram.size());
+ stats.delayHistogram.sample(delay);
+ stats.delayVCHistogram[virtualNetwork]->sample(delay);
}
void
AbstractController::
ControllerStats::ControllerStats(Stats::Group *parent)
: Stats::Group(parent),
- m_fully_busy_cycles(this, "fully_busy_cycles",
- "cycles for which number of transistions == max "
- "transitions"),
- m_delayHistogram(this, "delay_histogram")
+ ADD_STAT(fullyBusyCycles,
+ "cycles for which number of transistions == max transitions"),
+ ADD_STAT(delayHistogram, "delay_histogram")
{
- m_fully_busy_cycles
+ fullyBusyCycles
.flags(Stats::nozero);
- m_delayHistogram
+ delayHistogram
.flags(Stats::nozero);
}
MachineID getMachineID() const { return m_machineID; }
RequestorID getRequestorId() const { return m_id; }
- Stats::Histogram& getDelayHist() { return stats.m_delayHistogram; }
+ Stats::Histogram& getDelayHist() { return stats.delayHistogram; }
Stats::Histogram& getDelayVCHist(uint32_t index)
- { return *(stats.m_delayVCHistogram[index]); }
+ { return *(stats.delayVCHistogram[index]); }
bool respondsTo(Addr addr)
{
{
auto iter = m_inTrans.find(addr);
assert(iter != m_inTrans.end());
- stats.m_inTransLatHist[iter->second.transaction]
+ stats.inTransLatHist[iter->second.transaction]
[iter->second.state]
[(unsigned)finalState]->sample(
ticksToCycles(curTick() - iter->second.time));
{
auto iter = m_outTrans.find(addr);
assert(iter != m_outTrans.end());
- stats.m_outTransLatHist[iter->second.transaction]->sample(
+ stats.outTransLatHist[iter->second.transaction]->sample(
ticksToCycles(curTick() - iter->second.time));
m_outTrans.erase(iter);
}
// Initialized by the SLICC compiler for all combinations of event and
// states. Only histograms with samples will appear in the stats
std::vector<std::vector<std::vector<Stats::Histogram*>>>
- m_inTransLatHist;
+ inTransLatHist;
// Initialized by the SLICC compiler for all events.
// Only histograms with samples will appear in the stats.
- std::vector<Stats::Histogram*> m_outTransLatHist;
+ std::vector<Stats::Histogram*> outTransLatHist;
//! Counter for the number of cycles when the transitions carried out
//! were equal to the maximum allowed
- Stats::Scalar m_fully_busy_cycles;
+ Stats::Scalar fullyBusyCycles;
//! Histogram for profiling delay for the messages this controller
//! cares for
- Stats::Histogram m_delayHistogram;
- std::vector<Stats::Histogram *> m_delayVCHistogram;
+ Stats::Histogram delayHistogram;
+ std::vector<Stats::Histogram *> delayVCHistogram;
} stats;
};
std::string stat_name =
"outTransLatHist." + ${ident}_Event_to_string(event);
Stats::Histogram* t = new Stats::Histogram(&stats, stat_name.c_str());
- stats.m_outTransLatHist.push_back(t);
+ stats.outTransLatHist.push_back(t);
t->init(5);
t->flags(Stats::pdf | Stats::total |
Stats::oneline | Stats::nozero);
}
for (${ident}_Event event = ${ident}_Event_FIRST;
event < ${ident}_Event_NUM; ++event) {
- stats.m_inTransLatHist.emplace_back();
+ stats.inTransLatHist.emplace_back();
for (${ident}_State initial_state = ${ident}_State_FIRST;
initial_state < ${ident}_State_NUM; ++initial_state) {
- stats.m_inTransLatHist.back().emplace_back();
+ stats.inTransLatHist.back().emplace_back();
for (${ident}_State final_state = ${ident}_State_FIRST;
final_state < ${ident}_State_NUM; ++final_state) {
std::string stat_name = "inTransLatHist." +
${ident}_State_to_string(final_state);
Stats::Histogram* t =
new Stats::Histogram(&stats, stat_name.c_str());
- stats.m_inTransLatHist.back().back().push_back(t);
+ stats.inTransLatHist.back().back().push_back(t);
t->init(5);
t->flags(Stats::pdf | Stats::total |
Stats::oneline | Stats::nozero);
assert(counter <= m_transitions_per_cycle);
if (counter == m_transitions_per_cycle) {
// Count how often we are fully utilized
- stats.m_fully_busy_cycles++;
+ stats.fullyBusyCycles++;
// Wakeup in another cycle and try again
scheduleEvent(Cycles(1));
gotAllAddrRanges(false), defaultPortID(InvalidPortID),
useDefaultRange(p.use_default_range),
- transDist(this, "trans_dist", "Transaction distribution"),
- pktCount(this, "pkt_count",
- "Packet count per connected requestor and responder (bytes)"),
- pktSize(this, "pkt_size", "Cumulative packet size per connected "
- "requestor and responder (bytes)")
+ ADD_STAT(transDist, "Transaction distribution"),
+ ADD_STAT(pktCount,
+ "Packet count per connected requestor and responder (bytes)"),
+ ADD_STAT(pktSize, "Cumulative packet size per connected requestor and "
+ "responder (bytes)")
{
}
Root::RootStats::RootStats()
: Stats::Group(nullptr),
- simSeconds(this, "sim_seconds", "Number of seconds simulated"),
- simTicks(this, "sim_ticks", "Number of ticks simulated"),
- finalTick(this, "final_tick",
- "Number of ticks from beginning of simulation "
- "(restored from checkpoints and never reset)"),
- simFreq(this, "sim_freq", "Frequency of simulated ticks"),
- hostSeconds(this, "host_seconds", "Real time elapsed on the host"),
- hostTickRate(this, "host_tick_rate", "Simulator tick rate (ticks/s)"),
- hostMemory(this, "host_mem_usage", "Number of bytes of host memory used"),
+ ADD_STAT(simSeconds, "Number of seconds simulated"),
+ ADD_STAT(simTicks, "Number of ticks simulated"),
+ ADD_STAT(finalTick, "Number of ticks from beginning of simulation "
+ "(restored from checkpoints and never reset)"),
+ ADD_STAT(simFreq, "Frequency of simulated ticks"),
+ ADD_STAT(hostSeconds, "Real time elapsed on the host"),
+ ADD_STAT(hostTickRate, "Simulator tick rate (ticks/s)"),
+ ADD_STAT(hostMemory, "Number of bytes of host memory used"),
statTime(true),
startTick(0)
struct WorkloadStats : public Stats::Group
{
- Stats::Scalar arm;
- Stats::Scalar quiesce;
+ struct InstStats: public Stats::Group
+ {
+ Stats::Scalar arm;
+ Stats::Scalar quiesce;
+
+ InstStats(Stats::Group *parent) : Stats::Group(parent, "inst"),
+ ADD_STAT(arm, "number of arm instructions executed"),
+ ADD_STAT(quiesce, "number of quiesce instructions executed")
+ {}
+
+ } instStats;
WorkloadStats(Workload *workload) : Stats::Group(workload),
- arm(this, "inst.arm", "number of arm instructions executed"),
- quiesce(this, "inst.quiesce",
- "number of quiesce instructions executed")
+ instStats(workload)
{}
} stats;
Workload(const WorkloadParams &_params) : SimObject(_params), stats(this)
{}
- void recordQuiesce() { stats.quiesce++; }
- void recordArm() { stats.arm++; }
+ void recordQuiesce() { stats.instStats.quiesce++; }
+ void recordArm() { stats.instStats.arm++; }
System *system = nullptr;