renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index a748ca05dded4841ed2c5314d73e709d2135536e..fa1c284dc4eaba2f204946b26efdf8422203ee01 100644 (file)
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -133,7 +133,7 @@ struct Smt2Worker
 
        std::string get_bool(RTLIL::SigSpec sig, const char *state_name = "state")
        {
-               return get_bool(sig.to_single_sigbit(), state_name);
+               return get_bool(sig.as_bit(), state_name);
        }
 
        std::string get_bv(RTLIL::SigSpec sig, const char *state_name = "state")
@@ -216,7 +216,7 @@ struct Smt2Worker
 
        void export_gate(RTLIL::Cell *cell, std::string expr)
        {
-               RTLIL::SigBit bit = sigmap(cell->getPort("\\Y").to_single_sigbit());
+               RTLIL::SigBit bit = sigmap(cell->getPort("\\Y").as_bit());
                std::string processed_expr;
 
                for (char ch : expr) {

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 6f150c1e2ebbc75834a4874c4c920a312604625a..5f056f89ceac1f548603a5abe99d838e5b6f5f35 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -3197,6 +3197,17 @@ RTLIL::SigChunk RTLIL::SigSpec::as_chunk() const
        return chunks_[0];
 }
 
+RTLIL::SigBit RTLIL::SigSpec::as_bit() const
+{
+       cover("kernel.rtlil.sigspec.as_bit");
+
+       log_assert(width_ == 1);
+       if (packed())
+               return RTLIL::SigBit(*chunks_.begin());
+       else
+               return bits_[0];
+}
+
 bool RTLIL::SigSpec::match(std::string pattern) const
 {
        cover("kernel.rtlil.sigspec.match");
@@ -3284,18 +3295,6 @@ dict<RTLIL::SigBit, RTLIL::SigBit> RTLIL::SigSpec::to_sigbit_dict(const RTLIL::S
        return new_map;
 }
 
-RTLIL::SigBit RTLIL::SigSpec::to_single_sigbit() const
-{
-       cover("kernel.rtlil.sigspec.to_single_sigbit");
-
-       pack();
-       log_assert(width_ == 1);
-       for (auto &c : chunks_)
-               if (c.width)
-                       return RTLIL::SigBit(c);
-       log_abort();
-}
-
 static void sigspec_parse_split(std::vector<std::string> &tokens, const std::string &text, char sep)
 {
        size_t start = 0, end = 0;

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 43ef58068bdfd29e8074302ecda436f263822e3d..99dcb31168386d6f8acffc702e478c09ce7c29f9 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -690,6 +690,7 @@ public:
 
        bool is_wire() const;
        bool is_chunk() const;
+       inline bool is_bit() const { return width_ == 1; }
 
        bool is_fully_const() const;
        bool is_fully_zero() const;
@@ -704,6 +705,7 @@ public:
        RTLIL::Const as_const() const;
        RTLIL::Wire *as_wire() const;
        RTLIL::SigChunk as_chunk() const;
+       RTLIL::SigBit as_bit() const;
 
        bool match(std::string pattern) const;
 
@@ -712,7 +714,6 @@ public:
        std::vector<RTLIL::SigBit> to_sigbit_vector() const;
        std::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const;
        dict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const;
-       RTLIL::SigBit to_single_sigbit() const;
 
        static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str);
        static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str);

diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 4ce2ec11c997f860b7807bb4abc0968ac46a13cc..2556fb74037391ce2c184c00245cda2535f40a91 100644 (file)
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -64,7 +64,7 @@ struct SpliceWorker
                        return sliced_signals_cache.at(sig);
 
                int offset = 0;
-               int p = driven_bits_map.at(sig.extract(0, 1).to_single_sigbit()) - 1;
+               int p = driven_bits_map.at(sig.extract(0, 1).as_bit()) - 1;
                while (driven_bits.at(p) != RTLIL::State::Sm)
                        p--, offset++;
 

diff --git a/passes/equiv/equiv_induct.cc b/passes/equiv/equiv_induct.cc
index a536fe308a8390c45d0b658c6d1e5f11b26202f8..cdb951ec90519597a3abc05100d22791de4b2ac9 100644 (file)
--- a/passes/equiv/equiv_induct.cc
+++ b/passes/equiv/equiv_induct.cc
@@ -59,8 +59,8 @@ struct EquivInductWorker
                                cell_warn_cache.insert(cell);
                        }
                        if (cell->type == "$equiv") {
-                               SigBit bit_a = sigmap(cell->getPort("\\A")).to_single_sigbit();
-                               SigBit bit_b = sigmap(cell->getPort("\\B")).to_single_sigbit();
+                               SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
+                               SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
                                if (bit_a != bit_b) {
                                        int ez_a = satgen.importSigBit(bit_a, step);
                                        int ez_b = satgen.importSigBit(bit_b, step);
@@ -137,8 +137,8 @@ struct EquivInductWorker
 
                for (auto cell : workset)
                {
-                       SigBit bit_a = sigmap(cell->getPort("\\A")).to_single_sigbit();
-                       SigBit bit_b = sigmap(cell->getPort("\\B")).to_single_sigbit();
+                       SigBit bit_a = sigmap(cell->getPort("\\A")).as_bit();
+                       SigBit bit_b = sigmap(cell->getPort("\\B")).as_bit();
 
                        log("  Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort("\\Y"))));
 

diff --git a/passes/equiv/equiv_simple.cc b/passes/equiv/equiv_simple.cc
index 1f52a63210219a5223b3b8488541bfce6f7f94d1..fa22dc62164f38d61e9872fc9aa25ca9b428abbc 100644 (file)
--- a/passes/equiv/equiv_simple.cc
+++ b/passes/equiv/equiv_simple.cc
@@ -89,8 +89,8 @@ struct EquivSimpleWorker
 
        bool run_cell()
        {
-               SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).to_single_sigbit();
-               SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).to_single_sigbit();
+               SigBit bit_a = sigmap(equiv_cell->getPort("\\A")).as_bit();
+               SigBit bit_b = sigmap(equiv_cell->getPort("\\B")).as_bit();
                int ez_context = ez->frozen_literal();
 
                if (satgen.model_undef)
@@ -314,7 +314,7 @@ struct EquivSimplePass : public Pass {
 
                        for (auto cell : module->selected_cells())
                                if (cell->type == "$equiv" && cell->getPort("\\A") != cell->getPort("\\B")) {
-                                       auto bit = sigmap(cell->getPort("\\Y").to_single_sigbit());
+                                       auto bit = sigmap(cell->getPort("\\Y").as_bit());
                                        auto bit_group = bit;
                                        if (!nogroup && bit_group.wire)
                                                bit_group.offset = 0;

diff --git a/passes/fsm/fsm_opt.cc b/passes/fsm/fsm_opt.cc
index 7322368cdb31ca4b27e3b88d954c1876f39b9f43..a7cc95ffa4500d49ff2ae20c8fe667c90cde4900 100644 (file)
--- a/passes/fsm/fsm_opt.cc
+++ b/passes/fsm/fsm_opt.cc
@@ -78,7 +78,7 @@ struct FsmOpt
 
        bool signal_is_unused(RTLIL::SigSpec sig)
        {
-               RTLIL::SigBit bit = sig.to_single_sigbit();
+               RTLIL::SigBit bit = sig.as_bit();
 
                if (bit.wire == NULL || bit.wire->attributes.count("\\unused_bits") == 0)
                        return false;

diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index ca784890b9d21898959e070c048e9df7ded8ffcb..ebdf2ed5d706b5fe75dbf75c7b373d8b046e12c6 100644 (file)
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -116,7 +116,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
                info.cell = it.second;
 
                if (info.cell->type == "$dff") {
-                       info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
+                       info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
                        info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
                        std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
                        std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort("\\Q")).to_sigbit_vector();
@@ -128,8 +128,8 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
                }
 
                if (info.cell->type == "$adff") {
-                       info.bit_clk = sigmap(info.cell->getPort("\\CLK")).to_single_sigbit();
-                       info.bit_arst = sigmap(info.cell->getPort("\\ARST")).to_single_sigbit();
+                       info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
+                       info.bit_arst = sigmap(info.cell->getPort("\\ARST")).as_bit();
                        info.clk_polarity = info.cell->parameters.at("\\CLK_POLARITY").as_bool();
                        info.arst_polarity = info.cell->parameters.at("\\ARST_POLARITY").as_bool();
                        std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort("\\D")).to_sigbit_vector();
@@ -144,21 +144,21 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
                }
 
                if (info.cell->type == "$_DFF_N_" || info.cell->type == "$_DFF_P_") {
-                       info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
+                       info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
                        info.clk_polarity = info.cell->type == "$_DFF_P_";
-                       info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
-                       bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
+                       info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
+                       bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
                        continue;
                }
 
                if (info.cell->type.size() == 10 && info.cell->type.substr(0, 6) == "$_DFF_") {
-                       info.bit_clk = sigmap(info.cell->getPort("\\C")).to_single_sigbit();
-                       info.bit_arst = sigmap(info.cell->getPort("\\R")).to_single_sigbit();
+                       info.bit_clk = sigmap(info.cell->getPort("\\C")).as_bit();
+                       info.bit_arst = sigmap(info.cell->getPort("\\R")).as_bit();
                        info.clk_polarity = info.cell->type[6] == 'P';
                        info.arst_polarity = info.cell->type[7] == 'P';
                        info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
-                       info.bit_d = sigmap(info.cell->getPort("\\D")).to_single_sigbit();
-                       bit_info[sigmap(info.cell->getPort("\\Q")).to_single_sigbit()] = info;
+                       info.bit_d = sigmap(info.cell->getPort("\\D")).as_bit();
+                       bit_info[sigmap(info.cell->getPort("\\Q")).as_bit()] = info;
                        continue;
                }
        }