(no commit message)

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index f84257b0e49e9619ecdb09df2e71c0e252d6260a..914595e8dbd993828ce1f387abe815ba53fd1621 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -481,7 +481,14 @@ Thus, logically, we may set the following rule:
 
 Examples of the former type:
 
-* crand, cror, crnor. These all are 5-bit (BA, BB, BC).
+* crand, cror, crnor. These all are 5-bit (BA, BB, BT). The bit
+  to be tested against `inv` is the one selected by `BT`
+* mcrf. This has only 3-bit (BF, BFA). In order to select the
+  bit to be tested, the alternative FFirst encoding must be used.
+
+This limits sv.mcrf in that it may not use the `VLi` (VL inclusive)
+Mode. This is unfortunste but unavoidable due to encoding pressure
+on SVP64.
 
 # pred-result mode