litedram: Add support for Microwatt-initialized controller

This adds support for initializing the memory controller from microwatt
rather than using a built-in RiscV processor. This might require some
fixes to LiteX and LiteDRAM (they haven't been merged as of this commit
yet).

This is enabled in the shipped generated files and can be changed via
modifying the generator script to pass False to "mw_init"

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/litedram/gen-src/arty.yml b/litedram/gen-src/arty.yml
index e82316a6d32270961589b27e20d80b9158d5a5ed..a84f9645558c55f1098358003d2f2706b38e3d62 100644 (file)
--- a/litedram/gen-src/arty.yml
+++ b/litedram/gen-src/arty.yml
@@ -39,4 +39,5 @@
     # CSR Port -----------------------------------------------------------------
     "csr_expose": "False", # expose access to CSR (I/O) ports
     "csr_align" : 32,      # CSR alignment
+    "csr_base"  : 0xc0100000 # For cpu=None only
 }

diff --git a/litedram/gen-src/generate.py b/litedram/gen-src/generate.py
index 37ee42791c7edbd286130075fda9bdc3d3e90fa8..8c6b70a3b94768b2a142f2dcf14844b60f3dbdc6 100755 (executable)
--- a/litedram/gen-src/generate.py
+++ b/litedram/gen-src/generate.py
@@ -35,7 +35,7 @@ def build_init_code(build_dir):
 
     # More path fudging
     sw_dir = os.path.join(build_dir, "software");
-    sw_inc_dir = os.path.join(build_dir, "include")
+    sw_inc_dir = os.path.join(sw_dir, "include")
     gen_inc_dir = os.path.join(sw_inc_dir, "generated")
     src_dir = os.path.join(gen_src_dir, "sdram_init")
     lxbios_src_dir = os.path.join(soc_directory, "software", "bios")
@@ -59,7 +59,7 @@ def build_init_code(build_dir):
 
     add_var("BUILD_DIR", sw_dir)
     add_var("SRC_DIR", src_dir)
-    add_var("GENINC_DIR", gen_inc_dir)
+    add_var("GENINC_DIR", sw_inc_dir)
     add_var("LXSRC_DIR", lxbios_src_dir)
     add_var("LXINC_DIR", lxbios_inc_dir)
     write_to_file(os.path.join(gen_inc_dir, "variables.mak"), "".join(env_vars))
@@ -72,7 +72,7 @@ def build_init_code(build_dir):
 
     return os.path.join(sw_dir, "obj", "sdram_init.hex")
 
-def generate_one(t):
+def generate_one(t, mw_init):
 
     print("Generating target:", t)
 
@@ -101,6 +101,12 @@ def generate_one(t):
         if k == "sdram_phy":
             core_config[k] = getattr(litedram_phys, core_config[k])
 
+    # Override values for mw_init
+    if mw_init:
+        core_config["cpu"] = None
+        core_config["csr_expose"] = True
+        core_config["csr_align"] = 64
+
     # Generate core
     if core_config["sdram_phy"] in [litedram_phys.ECP5DDRPHY]:
         platform = LatticePlatform("LFE5UM5G-45F-8BG381C", io=[], toolchain="trellis")
@@ -120,8 +126,7 @@ def generate_one(t):
 
     # Generate init-cpu.txt if any and generate init code if none
     cpu = core_config["cpu"]
-    if cpu is None:
-        print("Microwatt based inits not supported yet !")
+    if mw_init:
         src_wrap_file = os.path.join(gen_src_dir, "wrapper-mw-init.vhdl")
         src_init_file = build_init_code(build_dir)
     else:
@@ -141,8 +146,10 @@ def generate_one(t):
 def main():
 
     targets = ['arty','nexys-video']
+
+    # XXX Set mw_init to False to use a local VexRiscV for memory inits
     for t in targets:
-        generate_one(t)
+        generate_one(t, mw_init = True)
 
     # XXX TODO: Remove build dir unless told not to via cmdline option
     

diff --git a/litedram/gen-src/sdram_init/Makefile b/litedram/gen-src/sdram_init/Makefile
index d330a85dd848a6a3362baaf165ffe727f19eeb61..28395a36002350c5ac5c1fd00ea8c0d5e7393747 100644 (file)
--- a/litedram/gen-src/sdram_init/Makefile
+++ b/litedram/gen-src/sdram_init/Makefile
@@ -22,7 +22,7 @@ OBJCOPY = $(CROSS_COMPILE)objcopy
 #### Flags
 
 CPPFLAGS = -nostdinc
-CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../include
+CPPFLAGS += -I$(SRC_DIR)/libc/include -I$(LXSRC_DIR) -I$(LXINC_DIR) -I$(GENINC_DIR) -I$(SRC_DIR)/include -I$(SRC_DIR)/../../../include
 CPPFLAGS += -isystem $(shell $(CC) -print-file-name=include)
 CFLAGS = -Os -g -Wall -std=c99 -m64 -mabi=elfv2 -msoft-float -mno-string -mno-multiple -mno-vsx -mno-altivec -mlittle-endian -fno-stack-protector -mstrict-align -ffreestanding -fdata-sections -ffunction-sections -fno-delete-null-pointer-checks 
 ASFLAGS = $(CPPFLAGS) $(CFLAGS)
@@ -30,7 +30,7 @@ LDFLAGS = -static -nostdlib -Ttext-segment=0xffff0000 -T $(SRC_DIR)/$(PROGRAM).l
 
 #### Pretty print
 
-ifeq ($(VERBOSE),1)
+ifeq ($(V),1)
 define Q
   $(2)
 endef

diff --git a/litedram/gen-src/sdram_init/include/system.h b/litedram/gen-src/sdram_init/include/system.h
index b5df315f62313378884af257205eb755980d3ae6..879f4cab54dd0e673852c2995682074c02d8eb73 100644 (file)
--- a/litedram/gen-src/sdram_init/include/system.h
+++ b/litedram/gen-src/sdram_init/include/system.h
@@ -1,3 +1,17 @@
 static inline void flush_cpu_dcache(void) { }
 static inline void flush_l2_cache(void) { }
 
+#define CONFIG_CPU_NOP "nop"
+#define CONFIG_CLOCK_FREQUENCY 100000000
+
+static inline void timer0_en_write(int e) { }
+static inline void timer0_reload_write(int r) { }
+static inline void timer0_load_write(int l) { }
+static inline void timer0_update_value_write(int v) { }
+static inline uint64_t timer0_value_read(void)
+{
+       uint64_t val;
+
+       __asm__ volatile ("mfdec %0" : "=r" (val));
+       return val;
+}

diff --git a/litedram/gen-src/sdram_init/libc/include/limits.h b/litedram/gen-src/sdram_init/libc/include/limits.h
new file mode 100644 (file)
index 0000000..4726835
--- /dev/null
+++ b/litedram/gen-src/sdram_init/libc/include/limits.h
@@ -0,0 +1,32 @@
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef _LIMITS_H
+#define _LIMITS_H
+
+#define        UCHAR_MAX       255
+#define        SCHAR_MAX       127
+#define        SCHAR_MIN       (-128)
+
+#define        USHRT_MAX       65535
+#define        SHRT_MAX        32767
+#define        SHRT_MIN        (-32768)
+
+#define        UINT_MAX        (4294967295U)
+#define        INT_MAX         2147483647
+#define        INT_MIN         (-2147483648)
+
+#define        ULONG_MAX       ((unsigned long)-1L)
+#define        LONG_MAX        (ULONG_MAX/2)
+#define        LONG_MIN        ((-LONG_MAX)-1)
+
+#endif

diff --git a/litedram/gen-src/sdram_init/main.c b/litedram/gen-src/sdram_init/main.c
index 57baccd7e09be99edbb0c16c6df9038805f63720..e36b1dae3bcfa2d0626310adc1ebbb1def6d81b0 100644 (file)
--- a/litedram/gen-src/sdram_init/main.c
+++ b/litedram/gen-src/sdram_init/main.c
@@ -121,7 +121,7 @@ void main(void)
         * not happy otherwise. The PLL might need to settle ?
         */
        potato_uart_init();
-       for (i = 0; i < 10000; i++)
+       for (i = 0; i < 100000; i++)
                potato_uart_reg_read(POTATO_CONSOLE_STATUS);
        printf("\n\nWelcome to Microwatt !\n\n");
 

diff --git a/litedram/gen-src/wrapper-mw-init.vhdl b/litedram/gen-src/wrapper-mw-init.vhdl
index 70ff006340f4193b13d295b5ab8215720d242448..475e088a8893dca8e30f45d79bc89cdfcffba9a4 100644 (file)
--- a/litedram/gen-src/wrapper-mw-init.vhdl
+++ b/litedram/gen-src/wrapper-mw-init.vhdl
@@ -45,8 +45,8 @@ entity litedram_wrapper is
        ddram_cs_n    : out std_ulogic;
        ddram_dm      : out std_ulogic_vector(1 downto 0);
        ddram_dq      : inout std_ulogic_vector(15 downto 0);
-       ddram_dqs_p   : out std_ulogic_vector(1 downto 0);
-       ddram_dqs_n   : out std_ulogic_vector(1 downto 0);
+       ddram_dqs_p   : inout std_ulogic_vector(1 downto 0);
+       ddram_dqs_n   : inout std_ulogic_vector(1 downto 0);
        ddram_clk_p   : out std_ulogic;
        ddram_clk_n   : out std_ulogic;
        ddram_cke     : out std_ulogic;
@@ -69,8 +69,8 @@ architecture behaviour of litedram_wrapper is
        ddram_cs_n             : out std_ulogic;
        ddram_dm               : out std_ulogic_vector(1 downto 0);
        ddram_dq               : inout std_ulogic_vector(15 downto 0);
-       ddram_dqs_p            : out std_ulogic_vector(1 downto 0);
-       ddram_dqs_n            : out std_ulogic_vector(1 downto 0);
+       ddram_dqs_p            : inout std_ulogic_vector(1 downto 0);
+       ddram_dqs_n            : inout std_ulogic_vector(1 downto 0);
        ddram_clk_p            : out std_ulogic;
        ddram_clk_n            : out std_ulogic;
        ddram_cke              : out std_ulogic;
@@ -84,17 +84,17 @@ architecture behaviour of litedram_wrapper is
        csr_port0_we           : in std_ulogic;
        csr_port0_dat_w        : in std_ulogic_vector(7 downto 0);
        csr_port0_dat_r        : out std_ulogic_vector(7 downto 0);
-       user_port0_cmd_valid   : in std_ulogic;
-       user_port0_cmd_ready   : out std_ulogic;
-       user_port0_cmd_we      : in std_ulogic;
-       user_port0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
-       user_port0_wdata_valid : in std_ulogic;
-       user_port0_wdata_ready : out std_ulogic;
-       user_port0_wdata_we    : in std_ulogic_vector(15 downto 0);
-       user_port0_wdata_data  : in std_ulogic_vector(127 downto 0);
-       user_port0_rdata_valid : out std_ulogic;
-       user_port0_rdata_ready : in std_ulogic;
-       user_port0_rdata_data  : out std_ulogic_vector(127 downto 0)
+       user_port_native_0_cmd_valid   : in std_ulogic;
+       user_port_native_0_cmd_ready   : out std_ulogic;
+       user_port_native_0_cmd_we      : in std_ulogic;
+       user_port_native_0_cmd_addr    : in std_ulogic_vector(DRAM_ABITS-1 downto 0);
+       user_port_native_0_wdata_valid : in std_ulogic;
+       user_port_native_0_wdata_ready : out std_ulogic;
+       user_port_native_0_wdata_we    : in std_ulogic_vector(15 downto 0);
+       user_port_native_0_wdata_data  : in std_ulogic_vector(127 downto 0);
+       user_port_native_0_rdata_valid : out std_ulogic;
+       user_port_native_0_rdata_ready : in std_ulogic;
+       user_port_native_0_rdata_data  : out std_ulogic_vector(127 downto 0)
        );
     end component;
     
@@ -130,7 +130,7 @@ architecture behaviour of litedram_wrapper is
 
     constant INIT_RAM_SIZE : integer := 16384;
     constant INIT_RAM_ABITS :integer := 14;
-    constant INIT_RAM_FILE : string := "sdram_init.hex";
+    constant INIT_RAM_FILE : string := "litedram_core.init";
 
     type ram_t is array(0 to (INIT_RAM_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
 
@@ -176,7 +176,7 @@ begin
                end if;
                wb_init_out.ack <= not wb_init_out.ack;
            end if;
-       end if; 
+       end if;
     end process;
 
     wb_init_in.adr <= wb_in.adr;
@@ -205,7 +205,7 @@ begin
     -- DRAM CSR interface signals. We only support access to the bottom byte
     csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
     csr_write_valid <= wb_in.we and wb_in.sel(0);
-    csr_port0_adr <= wb_in.adr(15 downto 3) & '0' when wb_is_csr = '1' else (others => '0');
+    csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0');
     csr_port0_dat_w <= wb_in.dat(7 downto 0);
     csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';
 
@@ -287,17 +287,17 @@ begin
            csr_port0_we => csr_port0_we,
            csr_port0_dat_w => csr_port0_dat_w,
            csr_port0_dat_r => csr_port0_dat_r,
-           user_port0_cmd_valid => user_port0_cmd_valid,
-           user_port0_cmd_ready => user_port0_cmd_ready,
-           user_port0_cmd_we => user_port0_cmd_we,
-           user_port0_cmd_addr => user_port0_cmd_addr,
-           user_port0_wdata_valid => user_port0_wdata_valid,
-           user_port0_wdata_ready => user_port0_wdata_ready,
-           user_port0_wdata_we => user_port0_wdata_we,
-           user_port0_wdata_data => user_port0_wdata_data,
-           user_port0_rdata_valid => user_port0_rdata_valid,
-           user_port0_rdata_ready => user_port0_rdata_ready,
-           user_port0_rdata_data => user_port0_rdata_data
+           user_port_native_0_cmd_valid => user_port0_cmd_valid,
+           user_port_native_0_cmd_ready => user_port0_cmd_ready,
+           user_port_native_0_cmd_we => user_port0_cmd_we,
+           user_port_native_0_cmd_addr => user_port0_cmd_addr,
+           user_port_native_0_wdata_valid => user_port0_wdata_valid,
+           user_port_native_0_wdata_ready => user_port0_wdata_ready,
+           user_port_native_0_wdata_we => user_port0_wdata_we,
+           user_port_native_0_wdata_data => user_port0_wdata_data,
+           user_port_native_0_rdata_valid => user_port0_rdata_valid,
+           user_port_native_0_rdata_ready => user_port0_rdata_ready,
+           user_port_native_0_rdata_data => user_port0_rdata_data
            );
 
 end architecture behaviour;

diff --git a/litedram/generated/arty/init-cpu.txt b/litedram/generated/arty/init-cpu.txt
deleted file mode 100644 (file)
index b0b6e79..0000000
--- a/litedram/generated/arty/init-cpu.txt
+++ /dev/null
@@ -1 +0,0 @@
-vexriscv
\ No newline at end of file

diff --git a/litedram/generated/arty/litedram-wrapper.vhdl b/litedram/generated/arty/litedram-wrapper.vhdl
index 066486651bceb52fa0b46290b33ffda337220103..475e088a8893dca8e30f45d79bc89cdfcffba9a4 100644 (file)
--- a/litedram/generated/arty/litedram-wrapper.vhdl
+++ b/litedram/generated/arty/litedram-wrapper.vhdl
@@ -60,8 +60,6 @@ architecture behaviour of litedram_wrapper is
     component litedram_core port (
        clk                    : in std_ulogic;
        rst                    : in std_ulogic;
-       serial_tx              : out std_ulogic;
-       serial_rx              : in std_ulogic;
        pll_locked             : out std_ulogic;
        ddram_a                : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
        ddram_ba               : out std_ulogic_vector(2 downto 0);
@@ -82,6 +80,10 @@ architecture behaviour of litedram_wrapper is
        init_error             : out std_ulogic;
        user_clk               : out std_ulogic;
        user_rst               : out std_ulogic;
+       csr_port0_adr          : in std_ulogic_vector(13 downto 0);
+       csr_port0_we           : in std_ulogic;
+       csr_port0_dat_w        : in std_ulogic_vector(7 downto 0);
+       csr_port0_dat_r        : out std_ulogic_vector(7 downto 0);
        user_port_native_0_cmd_valid   : in std_ulogic;
        user_port_native_0_cmd_ready   : out std_ulogic;
        user_port_native_0_cmd_we      : in std_ulogic;
@@ -112,17 +114,84 @@ architecture behaviour of litedram_wrapper is
 
     signal dram_user_reset              : std_ulogic;
 
-    type state_t is (CMD, MWRITE, MREAD);
+    signal csr_port0_adr                : std_ulogic_vector(13 downto 0);
+    signal csr_port0_we                 : std_ulogic;
+    signal csr_port0_dat_w              : std_ulogic_vector(7 downto 0);
+    signal csr_port0_dat_r              : std_ulogic_vector(7 downto 0);
+    signal csr_port_read_comb           : std_ulogic_vector(63 downto 0);
+    signal csr_valid                   : std_ulogic;
+    signal csr_write_valid             : std_ulogic;
+
+    signal wb_init_in                   : wishbone_master_out;
+    signal wb_init_out                  : wishbone_slave_out;
+
+    type state_t is (CMD, MWRITE, MREAD, CSR);
     signal state : state_t;
 
+    constant INIT_RAM_SIZE : integer := 16384;
+    constant INIT_RAM_ABITS :integer := 14;
+    constant INIT_RAM_FILE : string := "litedram_core.init";
+
+    type ram_t is array(0 to (INIT_RAM_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
+
+    impure function init_load_ram(name : string) return ram_t is
+       file ram_file : text open read_mode is name;
+       variable temp_word : std_logic_vector(63 downto 0);
+       variable temp_ram : ram_t := (others => (others => '0'));
+       variable ram_line : line;
+    begin
+       for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+           exit when endfile(ram_file);
+           readline(ram_file, ram_line);
+           hread(ram_line, temp_word);
+           temp_ram(i) := temp_word;
+       end loop;
+       return temp_ram;
+    end function;
+
+    signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
+
+    attribute ram_style : string;
+    attribute ram_style of init_ram: signal is "block";
+
 begin
 
-    -- Address bit 3 selects the top or bottom half of the data
+    -- BRAM Memory slave
+    init_ram_0: process(system_clk)
+       variable adr : integer;
+    begin
+       if rising_edge(system_clk) then
+           wb_init_out.ack <= '0';
+           if (wb_init_in.cyc and wb_init_in.stb) = '1' then
+               adr := to_integer((unsigned(wb_init_in.adr(INIT_RAM_ABITS-1 downto 3))));
+               if wb_init_in.we = '0' then
+                   wb_init_out.dat <= init_ram(adr);
+               else
+                   for i in 0 to 7 loop
+                       if wb_init_in.sel(i) = '1' then
+                           init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+                               wb_init_in.dat(((i + 1) * 8) - 1 downto i * 8);
+                       end if;
+                   end loop;
+               end if;
+               wb_init_out.ack <= not wb_init_out.ack;
+           end if;
+       end if;
+    end process;
+
+    wb_init_in.adr <= wb_in.adr;
+    wb_init_in.dat <= wb_in.dat;
+    wb_init_in.sel <= wb_in.sel;
+    wb_init_in.we <= wb_in.we;
+    wb_init_in.stb <= wb_in.stb;
+    wb_init_in.cyc <= wb_in.cyc and wb_is_init;
+
+   -- Address bit 3 selects the top or bottom half of the data
     -- bus (64-bit wishbone vs. 128-bit DRAM interface)
     --
     ad3 <= wb_in.adr(3);
 
-    -- DRAM interface signals
+    -- DRAM data interface signals
     user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
                            when state = CMD else '0';
     user_port0_cmd_we <= wb_in.we when state = CMD else '0';
@@ -133,18 +202,32 @@ begin
     user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
                           "00000000" & wb_in.sel;
 
-    -- Wishbone out signals. CSR and init memory do nothing, just ack
-    wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else
+    -- DRAM CSR interface signals. We only support access to the bottom byte
+    csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
+    csr_write_valid <= wb_in.we and wb_in.sel(0);
+    csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0');
+    csr_port0_dat_w <= wb_in.dat(7 downto 0);
+    csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';
+
+    -- Wishbone out signals
+    wb_out.ack <= '1' when state = CSR else
+                 wb_init_out.ack when wb_is_init = '1' else
                  user_port0_wdata_ready when state = MWRITE else
                  user_port0_rdata_valid when state = MREAD else '0';
-    wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else
+
+    csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r;
+    wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else
+                 wb_init_out.dat when wb_is_init = '1' else
                  user_port0_rdata_data(127 downto 64) when ad3 = '1' else
                  user_port0_rdata_data(63 downto 0);
+    -- We don't do pipelining yet.
     wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
 
-    -- Reset, lift it when init done, no alt core reset
-    system_reset <= dram_user_reset or not init_done;
-    core_alt_reset <= '0';
+    -- Reset ignored, the reset controller use the pll lock signal,
+    -- and alternate core reset address set when DRAM is not initialized.
+    --
+    system_reset <= '0';
+    core_alt_reset <= not init_done;
 
     -- State machine
     sm: process(system_clk)
@@ -156,7 +239,9 @@ begin
            else
                case state is
                when CMD =>
-                   if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
+                   if csr_valid = '1' then
+                       state <= CSR;
+                   elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
                        state <= MWRITE when wb_in.we = '1' else MREAD;
                    end if;
                when MWRITE =>
@@ -167,6 +252,8 @@ begin
                    if user_port0_rdata_valid = '1' then
                        state <= CMD;
                    end if;
+               when CSR =>
+                   state <= CMD;
                end case;
            end if;
        end if;
@@ -176,8 +263,6 @@ begin
        port map(
            clk => clk_in,
            rst => rst,
-           serial_tx => serial_tx,
-           serial_rx => serial_rx,
            pll_locked => pll_locked,
            ddram_a => ddram_a,
            ddram_ba => ddram_ba,
@@ -198,6 +283,10 @@ begin
            init_error => init_error,
            user_clk => system_clk,
            user_rst => dram_user_reset,
+           csr_port0_adr => csr_port0_adr,
+           csr_port0_we => csr_port0_we,
+           csr_port0_dat_w => csr_port0_dat_w,
+           csr_port0_dat_r => csr_port0_dat_r,
            user_port_native_0_cmd_valid => user_port0_cmd_valid,
            user_port_native_0_cmd_ready => user_port0_cmd_ready,
            user_port_native_0_cmd_we => user_port0_cmd_we,

diff --git a/litedram/generated/arty/litedram_core.init b/litedram/generated/arty/litedram_core.init
index 60f87dee92591c9fb8a92d7c7329cd7468c6f94d..1031ca272d3d54884f8a60d300d277e1aa8b714f 100644 (file)
--- a/litedram/generated/arty/litedram_core.init
+++ b/litedram/generated/arty/litedram_core.init
@@ -1,5817 +1,1511 @@
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diff --git a/litedram/generated/arty/litedram_core.v b/litedram/generated/arty/litedram_core.v
index 9a0843a95eaaae286fc0c2fd3b3ddcb6eb6d4a00..727e21a8fb121d21725c10be9504a69ef3b81e50 100644 (file)
--- a/litedram/generated/arty/litedram_core.v
+++ b/litedram/generated/arty/litedram_core.v
@@ -1,9 +1,7 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (dc9cfe6) & LiteX (79ee135f) on 2020-05-08 01:29:17
+// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:03
 //--------------------------------------------------------------------------------
 module litedram_core(
-       output reg serial_tx,
-       input wire serial_rx,
        input wire clk,
        input wire rst,
        output wire pll_locked,
@@ -24,6 +22,10 @@ module litedram_core(
        output wire ddram_reset_n,
        output wire init_done,
        output wire init_error,
+       input wire [13:0] csr_port0_adr,
+       input wire csr_port0_we,
+       input wire [7:0] csr_port0_dat_w,
+       output wire [7:0] csr_port0_dat_r,
        output wire user_clk,
        output wire user_rst,
        input wire user_port_native_0_cmd_valid,
@@ -39,2520 +41,2000 @@ module litedram_core(
        output wire [127:0] user_port_native_0_rdata_data
 );
 
-reg soc_litedramcore_soccontroller_reset_storage = 1'd0;
-reg soc_litedramcore_soccontroller_reset_re = 1'd0;
-reg [31:0] soc_litedramcore_soccontroller_scratch_storage = 32'd305419896;
-reg soc_litedramcore_soccontroller_scratch_re = 1'd0;
-wire [31:0] soc_litedramcore_soccontroller_bus_errors_status;
-wire soc_litedramcore_soccontroller_bus_errors_we;
-wire soc_litedramcore_soccontroller_reset;
-wire soc_litedramcore_soccontroller_bus_error;
-reg [31:0] soc_litedramcore_soccontroller_bus_errors = 32'd0;
-wire soc_litedramcore_cpu_reset;
-reg [31:0] soc_litedramcore_cpu_interrupt = 32'd0;
-wire [29:0] soc_litedramcore_cpu_ibus_adr;
-wire [31:0] soc_litedramcore_cpu_ibus_dat_w;
-wire [31:0] soc_litedramcore_cpu_ibus_dat_r;
-wire [3:0] soc_litedramcore_cpu_ibus_sel;
-wire soc_litedramcore_cpu_ibus_cyc;
-wire soc_litedramcore_cpu_ibus_stb;
-wire soc_litedramcore_cpu_ibus_ack;
-wire soc_litedramcore_cpu_ibus_we;
-wire [2:0] soc_litedramcore_cpu_ibus_cti;
-wire [1:0] soc_litedramcore_cpu_ibus_bte;
-wire soc_litedramcore_cpu_ibus_err;
-wire [29:0] soc_litedramcore_cpu_dbus_adr;
-wire [31:0] soc_litedramcore_cpu_dbus_dat_w;
-wire [31:0] soc_litedramcore_cpu_dbus_dat_r;
-wire [3:0] soc_litedramcore_cpu_dbus_sel;
-wire soc_litedramcore_cpu_dbus_cyc;
-wire soc_litedramcore_cpu_dbus_stb;
-wire soc_litedramcore_cpu_dbus_ack;
-wire soc_litedramcore_cpu_dbus_we;
-wire [2:0] soc_litedramcore_cpu_dbus_cti;
-wire [1:0] soc_litedramcore_cpu_dbus_bte;
-wire soc_litedramcore_cpu_dbus_err;
-reg [31:0] soc_litedramcore_vexriscv = 32'd0;
-wire [29:0] soc_litedramcore_litedramcore_ram_bus_adr;
-wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_w;
-wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_r;
-wire [3:0] soc_litedramcore_litedramcore_ram_bus_sel;
-wire soc_litedramcore_litedramcore_ram_bus_cyc;
-wire soc_litedramcore_litedramcore_ram_bus_stb;
-reg soc_litedramcore_litedramcore_ram_bus_ack = 1'd0;
-wire soc_litedramcore_litedramcore_ram_bus_we;
-wire [2:0] soc_litedramcore_litedramcore_ram_bus_cti;
-wire [1:0] soc_litedramcore_litedramcore_ram_bus_bte;
-reg soc_litedramcore_litedramcore_ram_bus_err = 1'd0;
-wire [12:0] soc_litedramcore_litedramcore_adr;
-wire [31:0] soc_litedramcore_litedramcore_dat_r;
-wire [29:0] soc_litedramcore_ram_bus_ram_bus_adr;
-wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_w;
-wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_r;
-wire [3:0] soc_litedramcore_ram_bus_ram_bus_sel;
-wire soc_litedramcore_ram_bus_ram_bus_cyc;
-wire soc_litedramcore_ram_bus_ram_bus_stb;
-reg soc_litedramcore_ram_bus_ram_bus_ack = 1'd0;
-wire soc_litedramcore_ram_bus_ram_bus_we;
-wire [2:0] soc_litedramcore_ram_bus_ram_bus_cti;
-wire [1:0] soc_litedramcore_ram_bus_ram_bus_bte;
-reg soc_litedramcore_ram_bus_ram_bus_err = 1'd0;
-wire [9:0] soc_litedramcore_ram_adr;
-wire [31:0] soc_litedramcore_ram_dat_r;
-reg [3:0] soc_litedramcore_ram_we = 4'd0;
-wire [31:0] soc_litedramcore_ram_dat_w;
-reg [31:0] soc_litedramcore_storage = 32'd4947802;
-reg soc_litedramcore_re = 1'd0;
-wire soc_litedramcore_sink_valid;
-reg soc_litedramcore_sink_ready = 1'd0;
-wire soc_litedramcore_sink_first;
-wire soc_litedramcore_sink_last;
-wire [7:0] soc_litedramcore_sink_payload_data;
-reg soc_litedramcore_uart_clk_txen = 1'd0;
-reg [31:0] soc_litedramcore_phase_accumulator_tx = 32'd0;
-reg [7:0] soc_litedramcore_tx_reg = 8'd0;
-reg [3:0] soc_litedramcore_tx_bitcount = 4'd0;
-reg soc_litedramcore_tx_busy = 1'd0;
-reg soc_litedramcore_source_valid = 1'd0;
-wire soc_litedramcore_source_ready;
-reg soc_litedramcore_source_first = 1'd0;
-reg soc_litedramcore_source_last = 1'd0;
-reg [7:0] soc_litedramcore_source_payload_data = 8'd0;
-reg soc_litedramcore_uart_clk_rxen = 1'd0;
-reg [31:0] soc_litedramcore_phase_accumulator_rx = 32'd0;
-wire soc_litedramcore_rx;
-reg soc_litedramcore_rx_r = 1'd0;
-reg [7:0] soc_litedramcore_rx_reg = 8'd0;
-reg [3:0] soc_litedramcore_rx_bitcount = 4'd0;
-reg soc_litedramcore_rx_busy = 1'd0;
-wire soc_litedramcore_uart_rxtx_re;
-wire [7:0] soc_litedramcore_uart_rxtx_r;
-wire soc_litedramcore_uart_rxtx_we;
-wire [7:0] soc_litedramcore_uart_rxtx_w;
-wire soc_litedramcore_uart_txfull_status;
-wire soc_litedramcore_uart_txfull_we;
-wire soc_litedramcore_uart_rxempty_status;
-wire soc_litedramcore_uart_rxempty_we;
-wire soc_litedramcore_uart_irq;
-wire soc_litedramcore_uart_tx_status;
-reg soc_litedramcore_uart_tx_pending = 1'd0;
-wire soc_litedramcore_uart_tx_trigger;
-reg soc_litedramcore_uart_tx_clear = 1'd0;
-reg soc_litedramcore_uart_tx_old_trigger = 1'd0;
-wire soc_litedramcore_uart_rx_status;
-reg soc_litedramcore_uart_rx_pending = 1'd0;
-wire soc_litedramcore_uart_rx_trigger;
-reg soc_litedramcore_uart_rx_clear = 1'd0;
-reg soc_litedramcore_uart_rx_old_trigger = 1'd0;
-wire soc_litedramcore_uart_eventmanager_status_re;
-wire [1:0] soc_litedramcore_uart_eventmanager_status_r;
-wire soc_litedramcore_uart_eventmanager_status_we;
-reg [1:0] soc_litedramcore_uart_eventmanager_status_w = 2'd0;
-wire soc_litedramcore_uart_eventmanager_pending_re;
-wire [1:0] soc_litedramcore_uart_eventmanager_pending_r;
-wire soc_litedramcore_uart_eventmanager_pending_we;
-reg [1:0] soc_litedramcore_uart_eventmanager_pending_w = 2'd0;
-reg [1:0] soc_litedramcore_uart_eventmanager_storage = 2'd0;
-reg soc_litedramcore_uart_eventmanager_re = 1'd0;
-wire soc_litedramcore_uart_uart_sink_valid;
-wire soc_litedramcore_uart_uart_sink_ready;
-wire soc_litedramcore_uart_uart_sink_first;
-wire soc_litedramcore_uart_uart_sink_last;
-wire [7:0] soc_litedramcore_uart_uart_sink_payload_data;
-wire soc_litedramcore_uart_uart_source_valid;
-wire soc_litedramcore_uart_uart_source_ready;
-wire soc_litedramcore_uart_uart_source_first;
-wire soc_litedramcore_uart_uart_source_last;
-wire [7:0] soc_litedramcore_uart_uart_source_payload_data;
-wire soc_litedramcore_uart_tx_fifo_sink_valid;
-wire soc_litedramcore_uart_tx_fifo_sink_ready;
-reg soc_litedramcore_uart_tx_fifo_sink_first = 1'd0;
-reg soc_litedramcore_uart_tx_fifo_sink_last = 1'd0;
-wire [7:0] soc_litedramcore_uart_tx_fifo_sink_payload_data;
-wire soc_litedramcore_uart_tx_fifo_source_valid;
-wire soc_litedramcore_uart_tx_fifo_source_ready;
-wire soc_litedramcore_uart_tx_fifo_source_first;
-wire soc_litedramcore_uart_tx_fifo_source_last;
-wire [7:0] soc_litedramcore_uart_tx_fifo_source_payload_data;
-wire soc_litedramcore_uart_tx_fifo_re;
-reg soc_litedramcore_uart_tx_fifo_readable = 1'd0;
-wire soc_litedramcore_uart_tx_fifo_syncfifo_we;
-wire soc_litedramcore_uart_tx_fifo_syncfifo_writable;
-wire soc_litedramcore_uart_tx_fifo_syncfifo_re;
-wire soc_litedramcore_uart_tx_fifo_syncfifo_readable;
-wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_din;
-wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_dout;
-reg [4:0] soc_litedramcore_uart_tx_fifo_level0 = 5'd0;
-reg soc_litedramcore_uart_tx_fifo_replace = 1'd0;
-reg [3:0] soc_litedramcore_uart_tx_fifo_produce = 4'd0;
-reg [3:0] soc_litedramcore_uart_tx_fifo_consume = 4'd0;
-reg [3:0] soc_litedramcore_uart_tx_fifo_wrport_adr = 4'd0;
-wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_r;
-wire soc_litedramcore_uart_tx_fifo_wrport_we;
-wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_w;
-wire soc_litedramcore_uart_tx_fifo_do_read;
-wire [3:0] soc_litedramcore_uart_tx_fifo_rdport_adr;
-wire [9:0] soc_litedramcore_uart_tx_fifo_rdport_dat_r;
-wire soc_litedramcore_uart_tx_fifo_rdport_re;
-wire [4:0] soc_litedramcore_uart_tx_fifo_level1;
-wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_in_payload_data;
-wire soc_litedramcore_uart_tx_fifo_fifo_in_first;
-wire soc_litedramcore_uart_tx_fifo_fifo_in_last;
-wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_out_payload_data;
-wire soc_litedramcore_uart_tx_fifo_fifo_out_first;
-wire soc_litedramcore_uart_tx_fifo_fifo_out_last;
-wire soc_litedramcore_uart_rx_fifo_sink_valid;
-wire soc_litedramcore_uart_rx_fifo_sink_ready;
-wire soc_litedramcore_uart_rx_fifo_sink_first;
-wire soc_litedramcore_uart_rx_fifo_sink_last;
-wire [7:0] soc_litedramcore_uart_rx_fifo_sink_payload_data;
-wire soc_litedramcore_uart_rx_fifo_source_valid;
-wire soc_litedramcore_uart_rx_fifo_source_ready;
-wire soc_litedramcore_uart_rx_fifo_source_first;
-wire soc_litedramcore_uart_rx_fifo_source_last;
-wire [7:0] soc_litedramcore_uart_rx_fifo_source_payload_data;
-wire soc_litedramcore_uart_rx_fifo_re;
-reg soc_litedramcore_uart_rx_fifo_readable = 1'd0;
-wire soc_litedramcore_uart_rx_fifo_syncfifo_we;
-wire soc_litedramcore_uart_rx_fifo_syncfifo_writable;
-wire soc_litedramcore_uart_rx_fifo_syncfifo_re;
-wire soc_litedramcore_uart_rx_fifo_syncfifo_readable;
-wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_din;
-wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_dout;
-reg [4:0] soc_litedramcore_uart_rx_fifo_level0 = 5'd0;
-reg soc_litedramcore_uart_rx_fifo_replace = 1'd0;
-reg [3:0] soc_litedramcore_uart_rx_fifo_produce = 4'd0;
-reg [3:0] soc_litedramcore_uart_rx_fifo_consume = 4'd0;
-reg [3:0] soc_litedramcore_uart_rx_fifo_wrport_adr = 4'd0;
-wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_r;
-wire soc_litedramcore_uart_rx_fifo_wrport_we;
-wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_w;
-wire soc_litedramcore_uart_rx_fifo_do_read;
-wire [3:0] soc_litedramcore_uart_rx_fifo_rdport_adr;
-wire [9:0] soc_litedramcore_uart_rx_fifo_rdport_dat_r;
-wire soc_litedramcore_uart_rx_fifo_rdport_re;
-wire [4:0] soc_litedramcore_uart_rx_fifo_level1;
-wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_in_payload_data;
-wire soc_litedramcore_uart_rx_fifo_fifo_in_first;
-wire soc_litedramcore_uart_rx_fifo_fifo_in_last;
-wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_out_payload_data;
-wire soc_litedramcore_uart_rx_fifo_fifo_out_first;
-wire soc_litedramcore_uart_rx_fifo_fifo_out_last;
-reg soc_litedramcore_uart_reset = 1'd0;
-reg [31:0] soc_litedramcore_timer_load_storage = 32'd0;
-reg soc_litedramcore_timer_load_re = 1'd0;
-reg [31:0] soc_litedramcore_timer_reload_storage = 32'd0;
-reg soc_litedramcore_timer_reload_re = 1'd0;
-reg soc_litedramcore_timer_en_storage = 1'd0;
-reg soc_litedramcore_timer_en_re = 1'd0;
-reg soc_litedramcore_timer_update_value_storage = 1'd0;
-reg soc_litedramcore_timer_update_value_re = 1'd0;
-reg [31:0] soc_litedramcore_timer_value_status = 32'd0;
-wire soc_litedramcore_timer_value_we;
-wire soc_litedramcore_timer_irq;
-wire soc_litedramcore_timer_zero_status;
-reg soc_litedramcore_timer_zero_pending = 1'd0;
-wire soc_litedramcore_timer_zero_trigger;
-reg soc_litedramcore_timer_zero_clear = 1'd0;
-reg soc_litedramcore_timer_zero_old_trigger = 1'd0;
-wire soc_litedramcore_timer_eventmanager_status_re;
-wire soc_litedramcore_timer_eventmanager_status_r;
-wire soc_litedramcore_timer_eventmanager_status_we;
-wire soc_litedramcore_timer_eventmanager_status_w;
-wire soc_litedramcore_timer_eventmanager_pending_re;
-wire soc_litedramcore_timer_eventmanager_pending_r;
-wire soc_litedramcore_timer_eventmanager_pending_we;
-wire soc_litedramcore_timer_eventmanager_pending_w;
-reg soc_litedramcore_timer_eventmanager_storage = 1'd0;
-reg soc_litedramcore_timer_eventmanager_re = 1'd0;
-reg [31:0] soc_litedramcore_timer_value = 32'd0;
-reg [13:0] soc_litedramcore_interface_adr = 14'd0;
-reg soc_litedramcore_interface_we = 1'd0;
-wire [7:0] soc_litedramcore_interface_dat_w;
-wire [7:0] soc_litedramcore_interface_dat_r;
-wire [29:0] soc_litedramcore_bus_wishbone_adr;
-wire [31:0] soc_litedramcore_bus_wishbone_dat_w;
-wire [31:0] soc_litedramcore_bus_wishbone_dat_r;
-wire [3:0] soc_litedramcore_bus_wishbone_sel;
-wire soc_litedramcore_bus_wishbone_cyc;
-wire soc_litedramcore_bus_wishbone_stb;
-reg soc_litedramcore_bus_wishbone_ack = 1'd0;
-wire soc_litedramcore_bus_wishbone_we;
-wire [2:0] soc_litedramcore_bus_wishbone_cti;
-wire [1:0] soc_litedramcore_bus_wishbone_bte;
-reg soc_litedramcore_bus_wishbone_err = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
 wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
-wire soc_sys_pll_reset;
-wire soc_sys_pll_locked;
-wire soc_s7pll0_clkin;
-wire soc_s7pll0_clkout0;
-wire soc_s7pll0_clkout_buf0;
-wire soc_s7pll0_clkout1;
-wire soc_s7pll0_clkout_buf1;
-wire soc_s7pll0_clkout2;
-wire soc_s7pll0_clkout_buf2;
-wire soc_iodelay_pll_reset;
-wire soc_iodelay_pll_locked;
-wire soc_s7pll1_clkin;
-wire soc_s7pll1_clkout;
-wire soc_s7pll1_clkout_buf;
-reg [3:0] soc_reset_counter = 4'd15;
-reg soc_ic_reset = 1'd1;
-reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg soc_a7ddrphy_wlevel_en_storage = 1'd0;
-reg soc_a7ddrphy_wlevel_en_re = 1'd0;
-wire soc_a7ddrphy_wlevel_strobe_re;
-wire soc_a7ddrphy_wlevel_strobe_r;
-wire soc_a7ddrphy_wlevel_strobe_we;
-reg soc_a7ddrphy_wlevel_strobe_w = 1'd0;
-wire soc_a7ddrphy_cdly_rst_re;
-wire soc_a7ddrphy_cdly_rst_r;
-wire soc_a7ddrphy_cdly_rst_we;
-reg soc_a7ddrphy_cdly_rst_w = 1'd0;
-wire soc_a7ddrphy_cdly_inc_re;
-wire soc_a7ddrphy_cdly_inc_r;
-wire soc_a7ddrphy_cdly_inc_we;
-reg soc_a7ddrphy_cdly_inc_w = 1'd0;
-reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0;
-reg soc_a7ddrphy_dly_sel_re = 1'd0;
-wire soc_a7ddrphy_rdly_dq_rst_re;
-wire soc_a7ddrphy_rdly_dq_rst_r;
-wire soc_a7ddrphy_rdly_dq_rst_we;
-reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0;
-wire soc_a7ddrphy_rdly_dq_inc_re;
-wire soc_a7ddrphy_rdly_dq_inc_r;
-wire soc_a7ddrphy_rdly_dq_inc_we;
-reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0;
-wire soc_a7ddrphy_rdly_dq_bitslip_rst_re;
-wire soc_a7ddrphy_rdly_dq_bitslip_rst_r;
-wire soc_a7ddrphy_rdly_dq_bitslip_rst_we;
-reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-wire soc_a7ddrphy_rdly_dq_bitslip_re;
-wire soc_a7ddrphy_rdly_dq_bitslip_r;
-wire soc_a7ddrphy_rdly_dq_bitslip_we;
-reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-wire [13:0] soc_a7ddrphy_dfi_p0_address;
-wire [2:0] soc_a7ddrphy_dfi_p0_bank;
-wire soc_a7ddrphy_dfi_p0_cas_n;
-wire soc_a7ddrphy_dfi_p0_cs_n;
-wire soc_a7ddrphy_dfi_p0_ras_n;
-wire soc_a7ddrphy_dfi_p0_we_n;
-wire soc_a7ddrphy_dfi_p0_cke;
-wire soc_a7ddrphy_dfi_p0_odt;
-wire soc_a7ddrphy_dfi_p0_reset_n;
-wire soc_a7ddrphy_dfi_p0_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p0_wrdata;
-wire soc_a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask;
-wire soc_a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0;
-wire [13:0] soc_a7ddrphy_dfi_p1_address;
-wire [2:0] soc_a7ddrphy_dfi_p1_bank;
-wire soc_a7ddrphy_dfi_p1_cas_n;
-wire soc_a7ddrphy_dfi_p1_cs_n;
-wire soc_a7ddrphy_dfi_p1_ras_n;
-wire soc_a7ddrphy_dfi_p1_we_n;
-wire soc_a7ddrphy_dfi_p1_cke;
-wire soc_a7ddrphy_dfi_p1_odt;
-wire soc_a7ddrphy_dfi_p1_reset_n;
-wire soc_a7ddrphy_dfi_p1_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p1_wrdata;
-wire soc_a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask;
-wire soc_a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0;
-wire [13:0] soc_a7ddrphy_dfi_p2_address;
-wire [2:0] soc_a7ddrphy_dfi_p2_bank;
-wire soc_a7ddrphy_dfi_p2_cas_n;
-wire soc_a7ddrphy_dfi_p2_cs_n;
-wire soc_a7ddrphy_dfi_p2_ras_n;
-wire soc_a7ddrphy_dfi_p2_we_n;
-wire soc_a7ddrphy_dfi_p2_cke;
-wire soc_a7ddrphy_dfi_p2_odt;
-wire soc_a7ddrphy_dfi_p2_reset_n;
-wire soc_a7ddrphy_dfi_p2_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p2_wrdata;
-wire soc_a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask;
-wire soc_a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0;
-wire [13:0] soc_a7ddrphy_dfi_p3_address;
-wire [2:0] soc_a7ddrphy_dfi_p3_bank;
-wire soc_a7ddrphy_dfi_p3_cas_n;
-wire soc_a7ddrphy_dfi_p3_cs_n;
-wire soc_a7ddrphy_dfi_p3_ras_n;
-wire soc_a7ddrphy_dfi_p3_we_n;
-wire soc_a7ddrphy_dfi_p3_cke;
-wire soc_a7ddrphy_dfi_p3_odt;
-wire soc_a7ddrphy_dfi_p3_reset_n;
-wire soc_a7ddrphy_dfi_p3_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p3_wrdata;
-wire soc_a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask;
-wire soc_a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0;
-wire soc_a7ddrphy_sd_clk_se_nodelay;
-reg soc_a7ddrphy_dqs_oe = 1'd0;
-reg soc_a7ddrphy_dqs_oe_delayed = 1'd0;
-wire soc_a7ddrphy_dqspattern0;
-wire soc_a7ddrphy_dqspattern1;
-reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0;
-wire [1:0] soc_a7ddrphy_dqs_i;
-wire [1:0] soc_a7ddrphy_dqs_i_delayed;
-wire soc_a7ddrphy_dqs_o_no_delay0;
-wire soc_a7ddrphy_dqs_t0;
-wire soc_a7ddrphy0;
-wire soc_a7ddrphy_dqs_o_no_delay1;
-wire soc_a7ddrphy_dqs_t1;
-wire soc_a7ddrphy1;
-wire soc_a7ddrphy_dq_oe;
-reg soc_a7ddrphy_dq_oe_delayed = 1'd0;
-wire soc_a7ddrphy_dq_o_nodelay0;
-wire soc_a7ddrphy_dq_i_nodelay0;
-wire soc_a7ddrphy_dq_i_delayed0;
-wire soc_a7ddrphy_dq_t0;
-wire [7:0] soc_a7ddrphy_dq_i_data0;
-wire [7:0] soc_a7ddrphy_bitslip0_i;
-reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip0_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip0_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay1;
-wire soc_a7ddrphy_dq_i_nodelay1;
-wire soc_a7ddrphy_dq_i_delayed1;
-wire soc_a7ddrphy_dq_t1;
-wire [7:0] soc_a7ddrphy_dq_i_data1;
-wire [7:0] soc_a7ddrphy_bitslip1_i;
-reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip1_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip1_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay2;
-wire soc_a7ddrphy_dq_i_nodelay2;
-wire soc_a7ddrphy_dq_i_delayed2;
-wire soc_a7ddrphy_dq_t2;
-wire [7:0] soc_a7ddrphy_dq_i_data2;
-wire [7:0] soc_a7ddrphy_bitslip2_i;
-reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip2_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip2_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay3;
-wire soc_a7ddrphy_dq_i_nodelay3;
-wire soc_a7ddrphy_dq_i_delayed3;
-wire soc_a7ddrphy_dq_t3;
-wire [7:0] soc_a7ddrphy_dq_i_data3;
-wire [7:0] soc_a7ddrphy_bitslip3_i;
-reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip3_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip3_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay4;
-wire soc_a7ddrphy_dq_i_nodelay4;
-wire soc_a7ddrphy_dq_i_delayed4;
-wire soc_a7ddrphy_dq_t4;
-wire [7:0] soc_a7ddrphy_dq_i_data4;
-wire [7:0] soc_a7ddrphy_bitslip4_i;
-reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip4_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip4_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay5;
-wire soc_a7ddrphy_dq_i_nodelay5;
-wire soc_a7ddrphy_dq_i_delayed5;
-wire soc_a7ddrphy_dq_t5;
-wire [7:0] soc_a7ddrphy_dq_i_data5;
-wire [7:0] soc_a7ddrphy_bitslip5_i;
-reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip5_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip5_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay6;
-wire soc_a7ddrphy_dq_i_nodelay6;
-wire soc_a7ddrphy_dq_i_delayed6;
-wire soc_a7ddrphy_dq_t6;
-wire [7:0] soc_a7ddrphy_dq_i_data6;
-wire [7:0] soc_a7ddrphy_bitslip6_i;
-reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip6_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip6_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay7;
-wire soc_a7ddrphy_dq_i_nodelay7;
-wire soc_a7ddrphy_dq_i_delayed7;
-wire soc_a7ddrphy_dq_t7;
-wire [7:0] soc_a7ddrphy_dq_i_data7;
-wire [7:0] soc_a7ddrphy_bitslip7_i;
-reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip7_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip7_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay8;
-wire soc_a7ddrphy_dq_i_nodelay8;
-wire soc_a7ddrphy_dq_i_delayed8;
-wire soc_a7ddrphy_dq_t8;
-wire [7:0] soc_a7ddrphy_dq_i_data8;
-wire [7:0] soc_a7ddrphy_bitslip8_i;
-reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip8_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip8_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay9;
-wire soc_a7ddrphy_dq_i_nodelay9;
-wire soc_a7ddrphy_dq_i_delayed9;
-wire soc_a7ddrphy_dq_t9;
-wire [7:0] soc_a7ddrphy_dq_i_data9;
-wire [7:0] soc_a7ddrphy_bitslip9_i;
-reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip9_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip9_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay10;
-wire soc_a7ddrphy_dq_i_nodelay10;
-wire soc_a7ddrphy_dq_i_delayed10;
-wire soc_a7ddrphy_dq_t10;
-wire [7:0] soc_a7ddrphy_dq_i_data10;
-wire [7:0] soc_a7ddrphy_bitslip10_i;
-reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip10_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip10_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay11;
-wire soc_a7ddrphy_dq_i_nodelay11;
-wire soc_a7ddrphy_dq_i_delayed11;
-wire soc_a7ddrphy_dq_t11;
-wire [7:0] soc_a7ddrphy_dq_i_data11;
-wire [7:0] soc_a7ddrphy_bitslip11_i;
-reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip11_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip11_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay12;
-wire soc_a7ddrphy_dq_i_nodelay12;
-wire soc_a7ddrphy_dq_i_delayed12;
-wire soc_a7ddrphy_dq_t12;
-wire [7:0] soc_a7ddrphy_dq_i_data12;
-wire [7:0] soc_a7ddrphy_bitslip12_i;
-reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip12_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip12_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay13;
-wire soc_a7ddrphy_dq_i_nodelay13;
-wire soc_a7ddrphy_dq_i_delayed13;
-wire soc_a7ddrphy_dq_t13;
-wire [7:0] soc_a7ddrphy_dq_i_data13;
-wire [7:0] soc_a7ddrphy_bitslip13_i;
-reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip13_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip13_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay14;
-wire soc_a7ddrphy_dq_i_nodelay14;
-wire soc_a7ddrphy_dq_i_delayed14;
-wire soc_a7ddrphy_dq_t14;
-wire [7:0] soc_a7ddrphy_dq_i_data14;
-wire [7:0] soc_a7ddrphy_bitslip14_i;
-reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip14_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip14_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay15;
-wire soc_a7ddrphy_dq_i_nodelay15;
-wire soc_a7ddrphy_dq_i_delayed15;
-wire soc_a7ddrphy_dq_t15;
-wire [7:0] soc_a7ddrphy_dq_i_data15;
-wire [7:0] soc_a7ddrphy_bitslip15_i;
-reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip15_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip15_r = 16'd0;
-wire [7:0] soc_a7ddrphy_rddata_en;
-reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0;
-wire [3:0] soc_a7ddrphy_wrdata_en;
-reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0;
-wire [13:0] soc_sdram_inti_p0_address;
-wire [2:0] soc_sdram_inti_p0_bank;
-reg soc_sdram_inti_p0_cas_n = 1'd1;
-reg soc_sdram_inti_p0_cs_n = 1'd1;
-reg soc_sdram_inti_p0_ras_n = 1'd1;
-reg soc_sdram_inti_p0_we_n = 1'd1;
-wire soc_sdram_inti_p0_cke;
-wire soc_sdram_inti_p0_odt;
-wire soc_sdram_inti_p0_reset_n;
-reg soc_sdram_inti_p0_act_n = 1'd1;
-wire [31:0] soc_sdram_inti_p0_wrdata;
-wire soc_sdram_inti_p0_wrdata_en;
-wire [3:0] soc_sdram_inti_p0_wrdata_mask;
-wire soc_sdram_inti_p0_rddata_en;
-reg [31:0] soc_sdram_inti_p0_rddata = 32'd0;
-reg soc_sdram_inti_p0_rddata_valid = 1'd0;
-wire [13:0] soc_sdram_inti_p1_address;
-wire [2:0] soc_sdram_inti_p1_bank;
-reg soc_sdram_inti_p1_cas_n = 1'd1;
-reg soc_sdram_inti_p1_cs_n = 1'd1;
-reg soc_sdram_inti_p1_ras_n = 1'd1;
-reg soc_sdram_inti_p1_we_n = 1'd1;
-wire soc_sdram_inti_p1_cke;
-wire soc_sdram_inti_p1_odt;
-wire soc_sdram_inti_p1_reset_n;
-reg soc_sdram_inti_p1_act_n = 1'd1;
-wire [31:0] soc_sdram_inti_p1_wrdata;
-wire soc_sdram_inti_p1_wrdata_en;
-wire [3:0] soc_sdram_inti_p1_wrdata_mask;
-wire soc_sdram_inti_p1_rddata_en;
-reg [31:0] soc_sdram_inti_p1_rddata = 32'd0;
-reg soc_sdram_inti_p1_rddata_valid = 1'd0;
-wire [13:0] soc_sdram_inti_p2_address;
-wire [2:0] soc_sdram_inti_p2_bank;
-reg soc_sdram_inti_p2_cas_n = 1'd1;
-reg soc_sdram_inti_p2_cs_n = 1'd1;
-reg soc_sdram_inti_p2_ras_n = 1'd1;
-reg soc_sdram_inti_p2_we_n = 1'd1;
-wire soc_sdram_inti_p2_cke;
-wire soc_sdram_inti_p2_odt;
-wire soc_sdram_inti_p2_reset_n;
-reg soc_sdram_inti_p2_act_n = 1'd1;
-wire [31:0] soc_sdram_inti_p2_wrdata;
-wire soc_sdram_inti_p2_wrdata_en;
-wire [3:0] soc_sdram_inti_p2_wrdata_mask;
-wire soc_sdram_inti_p2_rddata_en;
-reg [31:0] soc_sdram_inti_p2_rddata = 32'd0;
-reg soc_sdram_inti_p2_rddata_valid = 1'd0;
-wire [13:0] soc_sdram_inti_p3_address;
-wire [2:0] soc_sdram_inti_p3_bank;
-reg soc_sdram_inti_p3_cas_n = 1'd1;
-reg soc_sdram_inti_p3_cs_n = 1'd1;
-reg soc_sdram_inti_p3_ras_n = 1'd1;
-reg soc_sdram_inti_p3_we_n = 1'd1;
-wire soc_sdram_inti_p3_cke;
-wire soc_sdram_inti_p3_odt;
-wire soc_sdram_inti_p3_reset_n;
-reg soc_sdram_inti_p3_act_n = 1'd1;
-wire [31:0] soc_sdram_inti_p3_wrdata;
-wire soc_sdram_inti_p3_wrdata_en;
-wire [3:0] soc_sdram_inti_p3_wrdata_mask;
-wire soc_sdram_inti_p3_rddata_en;
-reg [31:0] soc_sdram_inti_p3_rddata = 32'd0;
-reg soc_sdram_inti_p3_rddata_valid = 1'd0;
-wire [13:0] soc_sdram_slave_p0_address;
-wire [2:0] soc_sdram_slave_p0_bank;
-wire soc_sdram_slave_p0_cas_n;
-wire soc_sdram_slave_p0_cs_n;
-wire soc_sdram_slave_p0_ras_n;
-wire soc_sdram_slave_p0_we_n;
-wire soc_sdram_slave_p0_cke;
-wire soc_sdram_slave_p0_odt;
-wire soc_sdram_slave_p0_reset_n;
-wire soc_sdram_slave_p0_act_n;
-wire [31:0] soc_sdram_slave_p0_wrdata;
-wire soc_sdram_slave_p0_wrdata_en;
-wire [3:0] soc_sdram_slave_p0_wrdata_mask;
-wire soc_sdram_slave_p0_rddata_en;
-reg [31:0] soc_sdram_slave_p0_rddata = 32'd0;
-reg soc_sdram_slave_p0_rddata_valid = 1'd0;
-wire [13:0] soc_sdram_slave_p1_address;
-wire [2:0] soc_sdram_slave_p1_bank;
-wire soc_sdram_slave_p1_cas_n;
-wire soc_sdram_slave_p1_cs_n;
-wire soc_sdram_slave_p1_ras_n;
-wire soc_sdram_slave_p1_we_n;
-wire soc_sdram_slave_p1_cke;
-wire soc_sdram_slave_p1_odt;
-wire soc_sdram_slave_p1_reset_n;
-wire soc_sdram_slave_p1_act_n;
-wire [31:0] soc_sdram_slave_p1_wrdata;
-wire soc_sdram_slave_p1_wrdata_en;
-wire [3:0] soc_sdram_slave_p1_wrdata_mask;
-wire soc_sdram_slave_p1_rddata_en;
-reg [31:0] soc_sdram_slave_p1_rddata = 32'd0;
-reg soc_sdram_slave_p1_rddata_valid = 1'd0;
-wire [13:0] soc_sdram_slave_p2_address;
-wire [2:0] soc_sdram_slave_p2_bank;
-wire soc_sdram_slave_p2_cas_n;
-wire soc_sdram_slave_p2_cs_n;
-wire soc_sdram_slave_p2_ras_n;
-wire soc_sdram_slave_p2_we_n;
-wire soc_sdram_slave_p2_cke;
-wire soc_sdram_slave_p2_odt;
-wire soc_sdram_slave_p2_reset_n;
-wire soc_sdram_slave_p2_act_n;
-wire [31:0] soc_sdram_slave_p2_wrdata;
-wire soc_sdram_slave_p2_wrdata_en;
-wire [3:0] soc_sdram_slave_p2_wrdata_mask;
-wire soc_sdram_slave_p2_rddata_en;
-reg [31:0] soc_sdram_slave_p2_rddata = 32'd0;
-reg soc_sdram_slave_p2_rddata_valid = 1'd0;
-wire [13:0] soc_sdram_slave_p3_address;
-wire [2:0] soc_sdram_slave_p3_bank;
-wire soc_sdram_slave_p3_cas_n;
-wire soc_sdram_slave_p3_cs_n;
-wire soc_sdram_slave_p3_ras_n;
-wire soc_sdram_slave_p3_we_n;
-wire soc_sdram_slave_p3_cke;
-wire soc_sdram_slave_p3_odt;
-wire soc_sdram_slave_p3_reset_n;
-wire soc_sdram_slave_p3_act_n;
-wire [31:0] soc_sdram_slave_p3_wrdata;
-wire soc_sdram_slave_p3_wrdata_en;
-wire [3:0] soc_sdram_slave_p3_wrdata_mask;
-wire soc_sdram_slave_p3_rddata_en;
-reg [31:0] soc_sdram_slave_p3_rddata = 32'd0;
-reg soc_sdram_slave_p3_rddata_valid = 1'd0;
-reg [13:0] soc_sdram_master_p0_address = 14'd0;
-reg [2:0] soc_sdram_master_p0_bank = 3'd0;
-reg soc_sdram_master_p0_cas_n = 1'd1;
-reg soc_sdram_master_p0_cs_n = 1'd1;
-reg soc_sdram_master_p0_ras_n = 1'd1;
-reg soc_sdram_master_p0_we_n = 1'd1;
-reg soc_sdram_master_p0_cke = 1'd0;
-reg soc_sdram_master_p0_odt = 1'd0;
-reg soc_sdram_master_p0_reset_n = 1'd0;
-reg soc_sdram_master_p0_act_n = 1'd1;
-reg [31:0] soc_sdram_master_p0_wrdata = 32'd0;
-reg soc_sdram_master_p0_wrdata_en = 1'd0;
-reg [3:0] soc_sdram_master_p0_wrdata_mask = 4'd0;
-reg soc_sdram_master_p0_rddata_en = 1'd0;
-wire [31:0] soc_sdram_master_p0_rddata;
-wire soc_sdram_master_p0_rddata_valid;
-reg [13:0] soc_sdram_master_p1_address = 14'd0;
-reg [2:0] soc_sdram_master_p1_bank = 3'd0;
-reg soc_sdram_master_p1_cas_n = 1'd1;
-reg soc_sdram_master_p1_cs_n = 1'd1;
-reg soc_sdram_master_p1_ras_n = 1'd1;
-reg soc_sdram_master_p1_we_n = 1'd1;
-reg soc_sdram_master_p1_cke = 1'd0;
-reg soc_sdram_master_p1_odt = 1'd0;
-reg soc_sdram_master_p1_reset_n = 1'd0;
-reg soc_sdram_master_p1_act_n = 1'd1;
-reg [31:0] soc_sdram_master_p1_wrdata = 32'd0;
-reg soc_sdram_master_p1_wrdata_en = 1'd0;
-reg [3:0] soc_sdram_master_p1_wrdata_mask = 4'd0;
-reg soc_sdram_master_p1_rddata_en = 1'd0;
-wire [31:0] soc_sdram_master_p1_rddata;
-wire soc_sdram_master_p1_rddata_valid;
-reg [13:0] soc_sdram_master_p2_address = 14'd0;
-reg [2:0] soc_sdram_master_p2_bank = 3'd0;
-reg soc_sdram_master_p2_cas_n = 1'd1;
-reg soc_sdram_master_p2_cs_n = 1'd1;
-reg soc_sdram_master_p2_ras_n = 1'd1;
-reg soc_sdram_master_p2_we_n = 1'd1;
-reg soc_sdram_master_p2_cke = 1'd0;
-reg soc_sdram_master_p2_odt = 1'd0;
-reg soc_sdram_master_p2_reset_n = 1'd0;
-reg soc_sdram_master_p2_act_n = 1'd1;
-reg [31:0] soc_sdram_master_p2_wrdata = 32'd0;
-reg soc_sdram_master_p2_wrdata_en = 1'd0;
-reg [3:0] soc_sdram_master_p2_wrdata_mask = 4'd0;
-reg soc_sdram_master_p2_rddata_en = 1'd0;
-wire [31:0] soc_sdram_master_p2_rddata;
-wire soc_sdram_master_p2_rddata_valid;
-reg [13:0] soc_sdram_master_p3_address = 14'd0;
-reg [2:0] soc_sdram_master_p3_bank = 3'd0;
-reg soc_sdram_master_p3_cas_n = 1'd1;
-reg soc_sdram_master_p3_cs_n = 1'd1;
-reg soc_sdram_master_p3_ras_n = 1'd1;
-reg soc_sdram_master_p3_we_n = 1'd1;
-reg soc_sdram_master_p3_cke = 1'd0;
-reg soc_sdram_master_p3_odt = 1'd0;
-reg soc_sdram_master_p3_reset_n = 1'd0;
-reg soc_sdram_master_p3_act_n = 1'd1;
-reg [31:0] soc_sdram_master_p3_wrdata = 32'd0;
-reg soc_sdram_master_p3_wrdata_en = 1'd0;
-reg [3:0] soc_sdram_master_p3_wrdata_mask = 4'd0;
-reg soc_sdram_master_p3_rddata_en = 1'd0;
-wire [31:0] soc_sdram_master_p3_rddata;
-wire soc_sdram_master_p3_rddata_valid;
-reg [3:0] soc_sdram_storage = 4'd0;
-reg soc_sdram_re = 1'd0;
-reg [5:0] soc_sdram_phaseinjector0_command_storage = 6'd0;
-reg soc_sdram_phaseinjector0_command_re = 1'd0;
-wire soc_sdram_phaseinjector0_command_issue_re;
-wire soc_sdram_phaseinjector0_command_issue_r;
-wire soc_sdram_phaseinjector0_command_issue_we;
-reg soc_sdram_phaseinjector0_command_issue_w = 1'd0;
-reg [13:0] soc_sdram_phaseinjector0_address_storage = 14'd0;
-reg soc_sdram_phaseinjector0_address_re = 1'd0;
-reg [2:0] soc_sdram_phaseinjector0_baddress_storage = 3'd0;
-reg soc_sdram_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector0_wrdata_storage = 32'd0;
-reg soc_sdram_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector0_status = 32'd0;
-wire soc_sdram_phaseinjector0_we;
-reg [5:0] soc_sdram_phaseinjector1_command_storage = 6'd0;
-reg soc_sdram_phaseinjector1_command_re = 1'd0;
-wire soc_sdram_phaseinjector1_command_issue_re;
-wire soc_sdram_phaseinjector1_command_issue_r;
-wire soc_sdram_phaseinjector1_command_issue_we;
-reg soc_sdram_phaseinjector1_command_issue_w = 1'd0;
-reg [13:0] soc_sdram_phaseinjector1_address_storage = 14'd0;
-reg soc_sdram_phaseinjector1_address_re = 1'd0;
-reg [2:0] soc_sdram_phaseinjector1_baddress_storage = 3'd0;
-reg soc_sdram_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector1_wrdata_storage = 32'd0;
-reg soc_sdram_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector1_status = 32'd0;
-wire soc_sdram_phaseinjector1_we;
-reg [5:0] soc_sdram_phaseinjector2_command_storage = 6'd0;
-reg soc_sdram_phaseinjector2_command_re = 1'd0;
-wire soc_sdram_phaseinjector2_command_issue_re;
-wire soc_sdram_phaseinjector2_command_issue_r;
-wire soc_sdram_phaseinjector2_command_issue_we;
-reg soc_sdram_phaseinjector2_command_issue_w = 1'd0;
-reg [13:0] soc_sdram_phaseinjector2_address_storage = 14'd0;
-reg soc_sdram_phaseinjector2_address_re = 1'd0;
-reg [2:0] soc_sdram_phaseinjector2_baddress_storage = 3'd0;
-reg soc_sdram_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector2_wrdata_storage = 32'd0;
-reg soc_sdram_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector2_status = 32'd0;
-wire soc_sdram_phaseinjector2_we;
-reg [5:0] soc_sdram_phaseinjector3_command_storage = 6'd0;
-reg soc_sdram_phaseinjector3_command_re = 1'd0;
-wire soc_sdram_phaseinjector3_command_issue_re;
-wire soc_sdram_phaseinjector3_command_issue_r;
-wire soc_sdram_phaseinjector3_command_issue_we;
-reg soc_sdram_phaseinjector3_command_issue_w = 1'd0;
-reg [13:0] soc_sdram_phaseinjector3_address_storage = 14'd0;
-reg soc_sdram_phaseinjector3_address_re = 1'd0;
-reg [2:0] soc_sdram_phaseinjector3_baddress_storage = 3'd0;
-reg soc_sdram_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector3_wrdata_storage = 32'd0;
-reg soc_sdram_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector3_status = 32'd0;
-wire soc_sdram_phaseinjector3_we;
-wire soc_sdram_interface_bank0_valid;
-wire soc_sdram_interface_bank0_ready;
-wire soc_sdram_interface_bank0_we;
-wire [20:0] soc_sdram_interface_bank0_addr;
-wire soc_sdram_interface_bank0_lock;
-wire soc_sdram_interface_bank0_wdata_ready;
-wire soc_sdram_interface_bank0_rdata_valid;
-wire soc_sdram_interface_bank1_valid;
-wire soc_sdram_interface_bank1_ready;
-wire soc_sdram_interface_bank1_we;
-wire [20:0] soc_sdram_interface_bank1_addr;
-wire soc_sdram_interface_bank1_lock;
-wire soc_sdram_interface_bank1_wdata_ready;
-wire soc_sdram_interface_bank1_rdata_valid;
-wire soc_sdram_interface_bank2_valid;
-wire soc_sdram_interface_bank2_ready;
-wire soc_sdram_interface_bank2_we;
-wire [20:0] soc_sdram_interface_bank2_addr;
-wire soc_sdram_interface_bank2_lock;
-wire soc_sdram_interface_bank2_wdata_ready;
-wire soc_sdram_interface_bank2_rdata_valid;
-wire soc_sdram_interface_bank3_valid;
-wire soc_sdram_interface_bank3_ready;
-wire soc_sdram_interface_bank3_we;
-wire [20:0] soc_sdram_interface_bank3_addr;
-wire soc_sdram_interface_bank3_lock;
-wire soc_sdram_interface_bank3_wdata_ready;
-wire soc_sdram_interface_bank3_rdata_valid;
-wire soc_sdram_interface_bank4_valid;
-wire soc_sdram_interface_bank4_ready;
-wire soc_sdram_interface_bank4_we;
-wire [20:0] soc_sdram_interface_bank4_addr;
-wire soc_sdram_interface_bank4_lock;
-wire soc_sdram_interface_bank4_wdata_ready;
-wire soc_sdram_interface_bank4_rdata_valid;
-wire soc_sdram_interface_bank5_valid;
-wire soc_sdram_interface_bank5_ready;
-wire soc_sdram_interface_bank5_we;
-wire [20:0] soc_sdram_interface_bank5_addr;
-wire soc_sdram_interface_bank5_lock;
-wire soc_sdram_interface_bank5_wdata_ready;
-wire soc_sdram_interface_bank5_rdata_valid;
-wire soc_sdram_interface_bank6_valid;
-wire soc_sdram_interface_bank6_ready;
-wire soc_sdram_interface_bank6_we;
-wire [20:0] soc_sdram_interface_bank6_addr;
-wire soc_sdram_interface_bank6_lock;
-wire soc_sdram_interface_bank6_wdata_ready;
-wire soc_sdram_interface_bank6_rdata_valid;
-wire soc_sdram_interface_bank7_valid;
-wire soc_sdram_interface_bank7_ready;
-wire soc_sdram_interface_bank7_we;
-wire [20:0] soc_sdram_interface_bank7_addr;
-wire soc_sdram_interface_bank7_lock;
-wire soc_sdram_interface_bank7_wdata_ready;
-wire soc_sdram_interface_bank7_rdata_valid;
-reg [127:0] soc_sdram_interface_wdata = 128'd0;
-reg [15:0] soc_sdram_interface_wdata_we = 16'd0;
-wire [127:0] soc_sdram_interface_rdata;
-reg [13:0] soc_sdram_dfi_p0_address = 14'd0;
-reg [2:0] soc_sdram_dfi_p0_bank = 3'd0;
-reg soc_sdram_dfi_p0_cas_n = 1'd1;
-reg soc_sdram_dfi_p0_cs_n = 1'd1;
-reg soc_sdram_dfi_p0_ras_n = 1'd1;
-reg soc_sdram_dfi_p0_we_n = 1'd1;
-wire soc_sdram_dfi_p0_cke;
-wire soc_sdram_dfi_p0_odt;
-wire soc_sdram_dfi_p0_reset_n;
-reg soc_sdram_dfi_p0_act_n = 1'd1;
-wire [31:0] soc_sdram_dfi_p0_wrdata;
-reg soc_sdram_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] soc_sdram_dfi_p0_wrdata_mask;
-reg soc_sdram_dfi_p0_rddata_en = 1'd0;
-wire [31:0] soc_sdram_dfi_p0_rddata;
-wire soc_sdram_dfi_p0_rddata_valid;
-reg [13:0] soc_sdram_dfi_p1_address = 14'd0;
-reg [2:0] soc_sdram_dfi_p1_bank = 3'd0;
-reg soc_sdram_dfi_p1_cas_n = 1'd1;
-reg soc_sdram_dfi_p1_cs_n = 1'd1;
-reg soc_sdram_dfi_p1_ras_n = 1'd1;
-reg soc_sdram_dfi_p1_we_n = 1'd1;
-wire soc_sdram_dfi_p1_cke;
-wire soc_sdram_dfi_p1_odt;
-wire soc_sdram_dfi_p1_reset_n;
-reg soc_sdram_dfi_p1_act_n = 1'd1;
-wire [31:0] soc_sdram_dfi_p1_wrdata;
-reg soc_sdram_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] soc_sdram_dfi_p1_wrdata_mask;
-reg soc_sdram_dfi_p1_rddata_en = 1'd0;
-wire [31:0] soc_sdram_dfi_p1_rddata;
-wire soc_sdram_dfi_p1_rddata_valid;
-reg [13:0] soc_sdram_dfi_p2_address = 14'd0;
-reg [2:0] soc_sdram_dfi_p2_bank = 3'd0;
-reg soc_sdram_dfi_p2_cas_n = 1'd1;
-reg soc_sdram_dfi_p2_cs_n = 1'd1;
-reg soc_sdram_dfi_p2_ras_n = 1'd1;
-reg soc_sdram_dfi_p2_we_n = 1'd1;
-wire soc_sdram_dfi_p2_cke;
-wire soc_sdram_dfi_p2_odt;
-wire soc_sdram_dfi_p2_reset_n;
-reg soc_sdram_dfi_p2_act_n = 1'd1;
-wire [31:0] soc_sdram_dfi_p2_wrdata;
-reg soc_sdram_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] soc_sdram_dfi_p2_wrdata_mask;
-reg soc_sdram_dfi_p2_rddata_en = 1'd0;
-wire [31:0] soc_sdram_dfi_p2_rddata;
-wire soc_sdram_dfi_p2_rddata_valid;
-reg [13:0] soc_sdram_dfi_p3_address = 14'd0;
-reg [2:0] soc_sdram_dfi_p3_bank = 3'd0;
-reg soc_sdram_dfi_p3_cas_n = 1'd1;
-reg soc_sdram_dfi_p3_cs_n = 1'd1;
-reg soc_sdram_dfi_p3_ras_n = 1'd1;
-reg soc_sdram_dfi_p3_we_n = 1'd1;
-wire soc_sdram_dfi_p3_cke;
-wire soc_sdram_dfi_p3_odt;
-wire soc_sdram_dfi_p3_reset_n;
-reg soc_sdram_dfi_p3_act_n = 1'd1;
-wire [31:0] soc_sdram_dfi_p3_wrdata;
-reg soc_sdram_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] soc_sdram_dfi_p3_wrdata_mask;
-reg soc_sdram_dfi_p3_rddata_en = 1'd0;
-wire [31:0] soc_sdram_dfi_p3_rddata;
-wire soc_sdram_dfi_p3_rddata_valid;
-reg soc_sdram_cmd_valid = 1'd0;
-reg soc_sdram_cmd_ready = 1'd0;
-reg soc_sdram_cmd_last = 1'd0;
-reg [13:0] soc_sdram_cmd_payload_a = 14'd0;
-reg [2:0] soc_sdram_cmd_payload_ba = 3'd0;
-reg soc_sdram_cmd_payload_cas = 1'd0;
-reg soc_sdram_cmd_payload_ras = 1'd0;
-reg soc_sdram_cmd_payload_we = 1'd0;
-reg soc_sdram_cmd_payload_is_read = 1'd0;
-reg soc_sdram_cmd_payload_is_write = 1'd0;
-wire soc_sdram_wants_refresh;
-wire soc_sdram_wants_zqcs;
-wire soc_sdram_timer_wait;
-wire soc_sdram_timer_done0;
-wire [9:0] soc_sdram_timer_count0;
-wire soc_sdram_timer_done1;
-reg [9:0] soc_sdram_timer_count1 = 10'd781;
-wire soc_sdram_postponer_req_i;
-reg soc_sdram_postponer_req_o = 1'd0;
-reg soc_sdram_postponer_count = 1'd0;
-reg soc_sdram_sequencer_start0 = 1'd0;
-wire soc_sdram_sequencer_done0;
-wire soc_sdram_sequencer_start1;
-reg soc_sdram_sequencer_done1 = 1'd0;
-reg [5:0] soc_sdram_sequencer_counter = 6'd0;
-reg soc_sdram_sequencer_count = 1'd0;
-wire soc_sdram_zqcs_timer_wait;
-wire soc_sdram_zqcs_timer_done0;
-wire [26:0] soc_sdram_zqcs_timer_count0;
-wire soc_sdram_zqcs_timer_done1;
-reg [26:0] soc_sdram_zqcs_timer_count1 = 27'd99999999;
-reg soc_sdram_zqcs_executer_start = 1'd0;
-reg soc_sdram_zqcs_executer_done = 1'd0;
-reg [4:0] soc_sdram_zqcs_executer_counter = 5'd0;
-wire soc_sdram_bankmachine0_req_valid;
-wire soc_sdram_bankmachine0_req_ready;
-wire soc_sdram_bankmachine0_req_we;
-wire [20:0] soc_sdram_bankmachine0_req_addr;
-wire soc_sdram_bankmachine0_req_lock;
-reg soc_sdram_bankmachine0_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine0_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine0_refresh_req;
-reg soc_sdram_bankmachine0_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine0_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine0_cmd_ready = 1'd0;
-reg [13:0] soc_sdram_bankmachine0_cmd_payload_a = 14'd0;
-wire [2:0] soc_sdram_bankmachine0_cmd_payload_ba;
-reg soc_sdram_bankmachine0_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine0_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine0_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine0_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine0_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine0_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine0_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine0_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine0_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine0_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine0_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_sdram_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_sdram_bankmachine0_row = 14'd0;
-reg soc_sdram_bankmachine0_row_opened = 1'd0;
-wire soc_sdram_bankmachine0_row_hit;
-reg soc_sdram_bankmachine0_row_open = 1'd0;
-reg soc_sdram_bankmachine0_row_close = 1'd0;
-reg soc_sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine0_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine0_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine0_trccon_count = 3'd0;
-wire soc_sdram_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine0_trascon_count = 3'd0;
-wire soc_sdram_bankmachine1_req_valid;
-wire soc_sdram_bankmachine1_req_ready;
-wire soc_sdram_bankmachine1_req_we;
-wire [20:0] soc_sdram_bankmachine1_req_addr;
-wire soc_sdram_bankmachine1_req_lock;
-reg soc_sdram_bankmachine1_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine1_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine1_refresh_req;
-reg soc_sdram_bankmachine1_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine1_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine1_cmd_ready = 1'd0;
-reg [13:0] soc_sdram_bankmachine1_cmd_payload_a = 14'd0;
-wire [2:0] soc_sdram_bankmachine1_cmd_payload_ba;
-reg soc_sdram_bankmachine1_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine1_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine1_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine1_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine1_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine1_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine1_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine1_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine1_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine1_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine1_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_sdram_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_sdram_bankmachine1_row = 14'd0;
-reg soc_sdram_bankmachine1_row_opened = 1'd0;
-wire soc_sdram_bankmachine1_row_hit;
-reg soc_sdram_bankmachine1_row_open = 1'd0;
-reg soc_sdram_bankmachine1_row_close = 1'd0;
-reg soc_sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine1_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine1_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine1_trccon_count = 3'd0;
-wire soc_sdram_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine1_trascon_count = 3'd0;
-wire soc_sdram_bankmachine2_req_valid;
-wire soc_sdram_bankmachine2_req_ready;
-wire soc_sdram_bankmachine2_req_we;
-wire [20:0] soc_sdram_bankmachine2_req_addr;
-wire soc_sdram_bankmachine2_req_lock;
-reg soc_sdram_bankmachine2_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine2_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine2_refresh_req;
-reg soc_sdram_bankmachine2_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine2_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine2_cmd_ready = 1'd0;
-reg [13:0] soc_sdram_bankmachine2_cmd_payload_a = 14'd0;
-wire [2:0] soc_sdram_bankmachine2_cmd_payload_ba;
-reg soc_sdram_bankmachine2_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine2_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine2_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine2_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine2_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine2_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine2_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine2_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine2_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine2_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine2_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_sdram_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_sdram_bankmachine2_row = 14'd0;
-reg soc_sdram_bankmachine2_row_opened = 1'd0;
-wire soc_sdram_bankmachine2_row_hit;
-reg soc_sdram_bankmachine2_row_open = 1'd0;
-reg soc_sdram_bankmachine2_row_close = 1'd0;
-reg soc_sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine2_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine2_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine2_trccon_count = 3'd0;
-wire soc_sdram_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine2_trascon_count = 3'd0;
-wire soc_sdram_bankmachine3_req_valid;
-wire soc_sdram_bankmachine3_req_ready;
-wire soc_sdram_bankmachine3_req_we;
-wire [20:0] soc_sdram_bankmachine3_req_addr;
-wire soc_sdram_bankmachine3_req_lock;
-reg soc_sdram_bankmachine3_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine3_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine3_refresh_req;
-reg soc_sdram_bankmachine3_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine3_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine3_cmd_ready = 1'd0;
-reg [13:0] soc_sdram_bankmachine3_cmd_payload_a = 14'd0;
-wire [2:0] soc_sdram_bankmachine3_cmd_payload_ba;
-reg soc_sdram_bankmachine3_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine3_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine3_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine3_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine3_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine3_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine3_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine3_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine3_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine3_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine3_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_sdram_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_sdram_bankmachine3_row = 14'd0;
-reg soc_sdram_bankmachine3_row_opened = 1'd0;
-wire soc_sdram_bankmachine3_row_hit;
-reg soc_sdram_bankmachine3_row_open = 1'd0;
-reg soc_sdram_bankmachine3_row_close = 1'd0;
-reg soc_sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine3_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine3_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine3_trccon_count = 3'd0;
-wire soc_sdram_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine3_trascon_count = 3'd0;
-wire soc_sdram_bankmachine4_req_valid;
-wire soc_sdram_bankmachine4_req_ready;
-wire soc_sdram_bankmachine4_req_we;
-wire [20:0] soc_sdram_bankmachine4_req_addr;
-wire soc_sdram_bankmachine4_req_lock;
-reg soc_sdram_bankmachine4_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine4_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine4_refresh_req;
-reg soc_sdram_bankmachine4_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine4_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine4_cmd_ready = 1'd0;
-reg [13:0] soc_sdram_bankmachine4_cmd_payload_a = 14'd0;
-wire [2:0] soc_sdram_bankmachine4_cmd_payload_ba;
-reg soc_sdram_bankmachine4_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine4_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine4_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine4_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine4_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine4_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine4_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine4_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine4_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine4_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine4_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_sdram_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_sdram_bankmachine4_row = 14'd0;
-reg soc_sdram_bankmachine4_row_opened = 1'd0;
-wire soc_sdram_bankmachine4_row_hit;
-reg soc_sdram_bankmachine4_row_open = 1'd0;
-reg soc_sdram_bankmachine4_row_close = 1'd0;
-reg soc_sdram_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine4_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine4_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine4_trccon_count = 3'd0;
-wire soc_sdram_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine4_trascon_count = 3'd0;
-wire soc_sdram_bankmachine5_req_valid;
-wire soc_sdram_bankmachine5_req_ready;
-wire soc_sdram_bankmachine5_req_we;
-wire [20:0] soc_sdram_bankmachine5_req_addr;
-wire soc_sdram_bankmachine5_req_lock;
-reg soc_sdram_bankmachine5_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine5_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine5_refresh_req;
-reg soc_sdram_bankmachine5_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine5_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine5_cmd_ready = 1'd0;
-reg [13:0] soc_sdram_bankmachine5_cmd_payload_a = 14'd0;
-wire [2:0] soc_sdram_bankmachine5_cmd_payload_ba;
-reg soc_sdram_bankmachine5_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine5_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine5_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine5_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine5_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine5_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine5_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine5_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine5_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine5_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine5_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_sdram_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_sdram_bankmachine5_row = 14'd0;
-reg soc_sdram_bankmachine5_row_opened = 1'd0;
-wire soc_sdram_bankmachine5_row_hit;
-reg soc_sdram_bankmachine5_row_open = 1'd0;
-reg soc_sdram_bankmachine5_row_close = 1'd0;
-reg soc_sdram_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine5_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine5_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine5_trccon_count = 3'd0;
-wire soc_sdram_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine5_trascon_count = 3'd0;
-wire soc_sdram_bankmachine6_req_valid;
-wire soc_sdram_bankmachine6_req_ready;
-wire soc_sdram_bankmachine6_req_we;
-wire [20:0] soc_sdram_bankmachine6_req_addr;
-wire soc_sdram_bankmachine6_req_lock;
-reg soc_sdram_bankmachine6_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine6_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine6_refresh_req;
-reg soc_sdram_bankmachine6_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine6_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine6_cmd_ready = 1'd0;
-reg [13:0] soc_sdram_bankmachine6_cmd_payload_a = 14'd0;
-wire [2:0] soc_sdram_bankmachine6_cmd_payload_ba;
-reg soc_sdram_bankmachine6_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine6_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine6_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine6_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine6_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine6_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine6_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine6_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine6_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine6_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine6_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_sdram_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_sdram_bankmachine6_row = 14'd0;
-reg soc_sdram_bankmachine6_row_opened = 1'd0;
-wire soc_sdram_bankmachine6_row_hit;
-reg soc_sdram_bankmachine6_row_open = 1'd0;
-reg soc_sdram_bankmachine6_row_close = 1'd0;
-reg soc_sdram_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine6_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine6_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine6_trccon_count = 3'd0;
-wire soc_sdram_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine6_trascon_count = 3'd0;
-wire soc_sdram_bankmachine7_req_valid;
-wire soc_sdram_bankmachine7_req_ready;
-wire soc_sdram_bankmachine7_req_we;
-wire [20:0] soc_sdram_bankmachine7_req_addr;
-wire soc_sdram_bankmachine7_req_lock;
-reg soc_sdram_bankmachine7_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine7_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine7_refresh_req;
-reg soc_sdram_bankmachine7_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine7_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine7_cmd_ready = 1'd0;
-reg [13:0] soc_sdram_bankmachine7_cmd_payload_a = 14'd0;
-wire [2:0] soc_sdram_bankmachine7_cmd_payload_ba;
-reg soc_sdram_bankmachine7_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine7_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine7_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine7_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine7_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine7_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine7_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine7_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine7_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine7_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
-wire [20:0] soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine7_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_sdram_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_sdram_bankmachine7_row = 14'd0;
-reg soc_sdram_bankmachine7_row_opened = 1'd0;
-wire soc_sdram_bankmachine7_row_hit;
-reg soc_sdram_bankmachine7_row_open = 1'd0;
-reg soc_sdram_bankmachine7_row_close = 1'd0;
-reg soc_sdram_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine7_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine7_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine7_trccon_count = 3'd0;
-wire soc_sdram_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine7_trascon_count = 3'd0;
-wire soc_sdram_ras_allowed;
-wire soc_sdram_cas_allowed;
-reg soc_sdram_choose_cmd_want_reads = 1'd0;
-reg soc_sdram_choose_cmd_want_writes = 1'd0;
-reg soc_sdram_choose_cmd_want_cmds = 1'd0;
-reg soc_sdram_choose_cmd_want_activates = 1'd0;
-wire soc_sdram_choose_cmd_cmd_valid;
-reg soc_sdram_choose_cmd_cmd_ready = 1'd0;
-wire [13:0] soc_sdram_choose_cmd_cmd_payload_a;
-wire [2:0] soc_sdram_choose_cmd_cmd_payload_ba;
-reg soc_sdram_choose_cmd_cmd_payload_cas = 1'd0;
-reg soc_sdram_choose_cmd_cmd_payload_ras = 1'd0;
-reg soc_sdram_choose_cmd_cmd_payload_we = 1'd0;
-wire soc_sdram_choose_cmd_cmd_payload_is_cmd;
-wire soc_sdram_choose_cmd_cmd_payload_is_read;
-wire soc_sdram_choose_cmd_cmd_payload_is_write;
-reg [7:0] soc_sdram_choose_cmd_valids = 8'd0;
-wire [7:0] soc_sdram_choose_cmd_request;
-reg [2:0] soc_sdram_choose_cmd_grant = 3'd0;
-wire soc_sdram_choose_cmd_ce;
-reg soc_sdram_choose_req_want_reads = 1'd0;
-reg soc_sdram_choose_req_want_writes = 1'd0;
-reg soc_sdram_choose_req_want_cmds = 1'd0;
-reg soc_sdram_choose_req_want_activates = 1'd0;
-wire soc_sdram_choose_req_cmd_valid;
-reg soc_sdram_choose_req_cmd_ready = 1'd0;
-wire [13:0] soc_sdram_choose_req_cmd_payload_a;
-wire [2:0] soc_sdram_choose_req_cmd_payload_ba;
-reg soc_sdram_choose_req_cmd_payload_cas = 1'd0;
-reg soc_sdram_choose_req_cmd_payload_ras = 1'd0;
-reg soc_sdram_choose_req_cmd_payload_we = 1'd0;
-wire soc_sdram_choose_req_cmd_payload_is_cmd;
-wire soc_sdram_choose_req_cmd_payload_is_read;
-wire soc_sdram_choose_req_cmd_payload_is_write;
-reg [7:0] soc_sdram_choose_req_valids = 8'd0;
-wire [7:0] soc_sdram_choose_req_request;
-reg [2:0] soc_sdram_choose_req_grant = 3'd0;
-wire soc_sdram_choose_req_ce;
-reg [13:0] soc_sdram_nop_a = 14'd0;
-reg [2:0] soc_sdram_nop_ba = 3'd0;
-reg [1:0] soc_sdram_steerer_sel0 = 2'd0;
-reg [1:0] soc_sdram_steerer_sel1 = 2'd0;
-reg [1:0] soc_sdram_steerer_sel2 = 2'd0;
-reg [1:0] soc_sdram_steerer_sel3 = 2'd0;
-reg soc_sdram_steerer0 = 1'd1;
-reg soc_sdram_steerer1 = 1'd1;
-reg soc_sdram_steerer2 = 1'd1;
-reg soc_sdram_steerer3 = 1'd1;
-reg soc_sdram_steerer4 = 1'd1;
-reg soc_sdram_steerer5 = 1'd1;
-reg soc_sdram_steerer6 = 1'd1;
-reg soc_sdram_steerer7 = 1'd1;
-wire soc_sdram_trrdcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_trrdcon_ready = 1'd1;
-reg soc_sdram_trrdcon_count = 1'd0;
-wire soc_sdram_tfawcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_tfawcon_ready = 1'd1;
-wire [2:0] soc_sdram_tfawcon_count;
-reg [4:0] soc_sdram_tfawcon_window = 5'd0;
-wire soc_sdram_tccdcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_tccdcon_ready = 1'd1;
-reg soc_sdram_tccdcon_count = 1'd0;
-wire soc_sdram_twtrcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_twtrcon_ready = 1'd1;
-reg [2:0] soc_sdram_twtrcon_count = 3'd0;
-wire soc_sdram_read_available;
-wire soc_sdram_write_available;
-reg soc_sdram_en0 = 1'd0;
-wire soc_sdram_max_time0;
-reg [4:0] soc_sdram_time0 = 5'd0;
-reg soc_sdram_en1 = 1'd0;
-wire soc_sdram_max_time1;
-reg [3:0] soc_sdram_time1 = 4'd0;
-wire soc_sdram_go_to_refresh;
-reg soc_port_cmd_valid = 1'd0;
-wire soc_port_cmd_ready;
-reg soc_port_cmd_payload_we = 1'd0;
-reg [23:0] soc_port_cmd_payload_addr = 24'd0;
-wire soc_port_wdata_valid;
-wire soc_port_wdata_ready;
-wire soc_port_wdata_first;
-wire soc_port_wdata_last;
-wire [127:0] soc_port_wdata_payload_data;
-wire [15:0] soc_port_wdata_payload_we;
-wire soc_port_rdata_valid;
-wire soc_port_rdata_ready;
-reg soc_port_rdata_first = 1'd0;
-reg soc_port_rdata_last = 1'd0;
-wire [127:0] soc_port_rdata_payload_data;
-wire [29:0] soc_wb_sdram_adr;
-wire [31:0] soc_wb_sdram_dat_w;
-reg [31:0] soc_wb_sdram_dat_r = 32'd0;
-wire [3:0] soc_wb_sdram_sel;
-wire soc_wb_sdram_cyc;
-wire soc_wb_sdram_stb;
-reg soc_wb_sdram_ack = 1'd0;
-wire soc_wb_sdram_we;
-wire [2:0] soc_wb_sdram_cti;
-wire [1:0] soc_wb_sdram_bte;
-reg soc_wb_sdram_err = 1'd0;
-wire [29:0] soc_litedram_wb_adr;
-reg [127:0] soc_litedram_wb_dat_w = 128'd0;
-wire [127:0] soc_litedram_wb_dat_r;
-reg [15:0] soc_litedram_wb_sel = 16'd0;
-reg soc_litedram_wb_cyc = 1'd0;
-reg soc_litedram_wb_stb = 1'd0;
-reg soc_litedram_wb_ack = 1'd0;
-reg soc_litedram_wb_we = 1'd0;
-wire [2:0] soc_litedram_wb_cti;
-reg soc_write = 1'd0;
-reg soc_evict = 1'd0;
-reg soc_refill = 1'd0;
-reg soc_read = 1'd0;
-wire [29:0] soc_address_d;
-reg [29:0] soc_address_q = 30'd0;
-reg soc_address_ce = 1'd0;
-reg soc_address_reset = 1'd0;
-reg [1:0] soc_counter = 2'd0;
-reg soc_counter_ce = 1'd0;
-reg soc_counter_reset = 1'd0;
-wire [1:0] soc_counter_offset;
-wire soc_counter_done;
-wire [127:0] soc_cached_data;
-wire [15:0] soc_cached_sel;
-wire soc_end_of_burst;
-wire soc_need_refill_d;
-reg soc_need_refill_q = 1'd1;
-reg soc_need_refill_ce = 1'd0;
-wire soc_need_refill_reset;
-reg [31:0] soc_cached_datas_flipflop0_d = 32'd0;
-reg [31:0] soc_cached_datas_flipflop0_q = 32'd0;
-reg soc_cached_datas_ce0 = 1'd0;
-reg soc_cached_datas_reset0 = 1'd0;
-reg [31:0] soc_cached_datas_flipflop1_d = 32'd0;
-reg [31:0] soc_cached_datas_flipflop1_q = 32'd0;
-reg soc_cached_datas_ce1 = 1'd0;
-reg soc_cached_datas_reset1 = 1'd0;
-reg [31:0] soc_cached_datas_flipflop2_d = 32'd0;
-reg [31:0] soc_cached_datas_flipflop2_q = 32'd0;
-reg soc_cached_datas_ce2 = 1'd0;
-reg soc_cached_datas_reset2 = 1'd0;
-reg [31:0] soc_cached_datas_flipflop3_d = 32'd0;
-reg [31:0] soc_cached_datas_flipflop3_q = 32'd0;
-reg soc_cached_datas_ce3 = 1'd0;
-reg soc_cached_datas_reset3 = 1'd0;
-wire [3:0] soc_cached_sels_flipflop0_d;
-reg [3:0] soc_cached_sels_flipflop0_q = 4'd0;
-reg soc_cached_sels_ce0 = 1'd0;
-wire soc_cached_sels_reset0;
-wire [3:0] soc_cached_sels_flipflop1_d;
-reg [3:0] soc_cached_sels_flipflop1_q = 4'd0;
-reg soc_cached_sels_ce1 = 1'd0;
-wire soc_cached_sels_reset1;
-wire [3:0] soc_cached_sels_flipflop2_d;
-reg [3:0] soc_cached_sels_flipflop2_q = 4'd0;
-reg soc_cached_sels_ce2 = 1'd0;
-wire soc_cached_sels_reset2;
-wire [3:0] soc_cached_sels_flipflop3_d;
-reg [3:0] soc_cached_sels_flipflop3_q = 4'd0;
-reg soc_cached_sels_ce3 = 1'd0;
-wire soc_cached_sels_reset3;
-reg soc_write_sel0 = 1'd0;
-reg soc_write_sel1 = 1'd0;
-reg soc_write_sel2 = 1'd0;
-reg soc_write_sel3 = 1'd0;
-wire soc_wdata_converter_sink_valid;
-wire soc_wdata_converter_sink_ready;
-reg soc_wdata_converter_sink_first = 1'd0;
-reg soc_wdata_converter_sink_last = 1'd0;
-wire [127:0] soc_wdata_converter_sink_payload_data;
-wire [15:0] soc_wdata_converter_sink_payload_we;
-wire soc_wdata_converter_source_valid;
-wire soc_wdata_converter_source_ready;
-wire soc_wdata_converter_source_first;
-wire soc_wdata_converter_source_last;
-wire [127:0] soc_wdata_converter_source_payload_data;
-wire [15:0] soc_wdata_converter_source_payload_we;
-wire soc_wdata_converter_converter_sink_valid;
-wire soc_wdata_converter_converter_sink_ready;
-wire soc_wdata_converter_converter_sink_first;
-wire soc_wdata_converter_converter_sink_last;
-wire [143:0] soc_wdata_converter_converter_sink_payload_data;
-wire soc_wdata_converter_converter_source_valid;
-wire soc_wdata_converter_converter_source_ready;
-wire soc_wdata_converter_converter_source_first;
-wire soc_wdata_converter_converter_source_last;
-wire [143:0] soc_wdata_converter_converter_source_payload_data;
-wire soc_wdata_converter_converter_source_payload_valid_token_count;
-wire soc_wdata_converter_source_source_valid;
-wire soc_wdata_converter_source_source_ready;
-wire soc_wdata_converter_source_source_first;
-wire soc_wdata_converter_source_source_last;
-wire [143:0] soc_wdata_converter_source_source_payload_data;
-wire soc_rdata_converter_sink_valid;
-wire soc_rdata_converter_sink_ready;
-wire soc_rdata_converter_sink_first;
-wire soc_rdata_converter_sink_last;
-wire [127:0] soc_rdata_converter_sink_payload_data;
-wire soc_rdata_converter_source_valid;
-wire soc_rdata_converter_source_ready;
-wire soc_rdata_converter_source_first;
-wire soc_rdata_converter_source_last;
-wire [127:0] soc_rdata_converter_source_payload_data;
-wire soc_rdata_converter_converter_sink_valid;
-wire soc_rdata_converter_converter_sink_ready;
-wire soc_rdata_converter_converter_sink_first;
-wire soc_rdata_converter_converter_sink_last;
-wire [127:0] soc_rdata_converter_converter_sink_payload_data;
-wire soc_rdata_converter_converter_source_valid;
-wire soc_rdata_converter_converter_source_ready;
-wire soc_rdata_converter_converter_source_first;
-wire soc_rdata_converter_converter_source_last;
-wire [127:0] soc_rdata_converter_converter_source_payload_data;
-wire soc_rdata_converter_converter_source_payload_valid_token_count;
-wire soc_rdata_converter_source_source_valid;
-wire soc_rdata_converter_source_source_ready;
-wire soc_rdata_converter_source_source_first;
-wire soc_rdata_converter_source_source_last;
-wire [127:0] soc_rdata_converter_source_source_payload_data;
-reg soc_count = 1'd0;
-reg soc_init_done_storage = 1'd0;
-reg soc_init_done_re = 1'd0;
-reg soc_init_error_storage = 1'd0;
-reg soc_init_error_re = 1'd0;
-wire soc_cmd_valid;
-wire soc_cmd_ready;
-wire soc_cmd_payload_we;
-wire [23:0] soc_cmd_payload_addr;
-wire soc_wdata_valid;
-wire soc_wdata_ready;
-wire [127:0] soc_wdata_payload_data;
-wire [15:0] soc_wdata_payload_we;
-wire soc_rdata_valid;
-wire soc_rdata_ready;
-wire [127:0] soc_rdata_payload_data;
-reg vns_wb2csr_state = 1'd0;
-reg vns_wb2csr_next_state = 1'd0;
-wire vns_pll_fb0;
-wire vns_pll_fb1;
-reg [1:0] vns_refresher_state = 2'd0;
-reg [1:0] vns_refresher_next_state = 2'd0;
-reg [3:0] vns_bankmachine0_state = 4'd0;
-reg [3:0] vns_bankmachine0_next_state = 4'd0;
-reg [3:0] vns_bankmachine1_state = 4'd0;
-reg [3:0] vns_bankmachine1_next_state = 4'd0;
-reg [3:0] vns_bankmachine2_state = 4'd0;
-reg [3:0] vns_bankmachine2_next_state = 4'd0;
-reg [3:0] vns_bankmachine3_state = 4'd0;
-reg [3:0] vns_bankmachine3_next_state = 4'd0;
-reg [3:0] vns_bankmachine4_state = 4'd0;
-reg [3:0] vns_bankmachine4_next_state = 4'd0;
-reg [3:0] vns_bankmachine5_state = 4'd0;
-reg [3:0] vns_bankmachine5_next_state = 4'd0;
-reg [3:0] vns_bankmachine6_state = 4'd0;
-reg [3:0] vns_bankmachine6_next_state = 4'd0;
-reg [3:0] vns_bankmachine7_state = 4'd0;
-reg [3:0] vns_bankmachine7_next_state = 4'd0;
-reg [3:0] vns_multiplexer_state = 4'd0;
-reg [3:0] vns_multiplexer_next_state = 4'd0;
-wire [1:0] vns_roundrobin0_request;
-reg vns_roundrobin0_grant = 1'd0;
-wire vns_roundrobin0_ce;
-wire [1:0] vns_roundrobin1_request;
-reg vns_roundrobin1_grant = 1'd0;
-wire vns_roundrobin1_ce;
-wire [1:0] vns_roundrobin2_request;
-reg vns_roundrobin2_grant = 1'd0;
-wire vns_roundrobin2_ce;
-wire [1:0] vns_roundrobin3_request;
-reg vns_roundrobin3_grant = 1'd0;
-wire vns_roundrobin3_ce;
-wire [1:0] vns_roundrobin4_request;
-reg vns_roundrobin4_grant = 1'd0;
-wire vns_roundrobin4_ce;
-wire [1:0] vns_roundrobin5_request;
-reg vns_roundrobin5_grant = 1'd0;
-wire vns_roundrobin5_ce;
-wire [1:0] vns_roundrobin6_request;
-reg vns_roundrobin6_grant = 1'd0;
-wire vns_roundrobin6_ce;
-wire [1:0] vns_roundrobin7_request;
-reg vns_roundrobin7_grant = 1'd0;
-wire vns_roundrobin7_ce;
-reg vns_locked0 = 1'd0;
-reg vns_locked1 = 1'd0;
-reg vns_locked2 = 1'd0;
-reg vns_locked3 = 1'd0;
-reg vns_locked4 = 1'd0;
-reg vns_locked5 = 1'd0;
-reg vns_locked6 = 1'd0;
-reg vns_locked7 = 1'd0;
-reg vns_locked8 = 1'd0;
-reg vns_locked9 = 1'd0;
-reg vns_locked10 = 1'd0;
-reg vns_locked11 = 1'd0;
-reg vns_locked12 = 1'd0;
-reg vns_locked13 = 1'd0;
-reg vns_locked14 = 1'd0;
-reg vns_locked15 = 1'd0;
-reg vns_new_master_wdata_ready0 = 1'd0;
-reg vns_new_master_wdata_ready1 = 1'd0;
-reg vns_new_master_wdata_ready2 = 1'd0;
-reg vns_new_master_wdata_ready3 = 1'd0;
-reg vns_new_master_wdata_ready4 = 1'd0;
-reg vns_new_master_wdata_ready5 = 1'd0;
-reg vns_new_master_rdata_valid0 = 1'd0;
-reg vns_new_master_rdata_valid1 = 1'd0;
-reg vns_new_master_rdata_valid2 = 1'd0;
-reg vns_new_master_rdata_valid3 = 1'd0;
-reg vns_new_master_rdata_valid4 = 1'd0;
-reg vns_new_master_rdata_valid5 = 1'd0;
-reg vns_new_master_rdata_valid6 = 1'd0;
-reg vns_new_master_rdata_valid7 = 1'd0;
-reg vns_new_master_rdata_valid8 = 1'd0;
-reg vns_new_master_rdata_valid9 = 1'd0;
-reg vns_new_master_rdata_valid10 = 1'd0;
-reg vns_new_master_rdata_valid11 = 1'd0;
-reg vns_new_master_rdata_valid12 = 1'd0;
-reg vns_new_master_rdata_valid13 = 1'd0;
-reg vns_new_master_rdata_valid14 = 1'd0;
-reg vns_new_master_rdata_valid15 = 1'd0;
-reg vns_new_master_rdata_valid16 = 1'd0;
-reg vns_new_master_rdata_valid17 = 1'd0;
-reg [2:0] vns_converter_state = 3'd0;
-reg [2:0] vns_converter_next_state = 3'd0;
-reg [1:0] vns_litedramwishbone2native_state = 2'd0;
-reg [1:0] vns_litedramwishbone2native_next_state = 2'd0;
-reg soc_count_next_value = 1'd0;
-reg soc_count_next_value_ce = 1'd0;
-wire [29:0] vns_shared_adr;
-wire [31:0] vns_shared_dat_w;
-reg [31:0] vns_shared_dat_r = 32'd0;
-wire [3:0] vns_shared_sel;
-wire vns_shared_cyc;
-wire vns_shared_stb;
-reg vns_shared_ack = 1'd0;
-wire vns_shared_we;
-wire [2:0] vns_shared_cti;
-wire [1:0] vns_shared_bte;
-wire vns_shared_err;
-wire [1:0] vns_request;
-reg vns_grant = 1'd0;
-reg [3:0] vns_slave_sel = 4'd0;
-reg [3:0] vns_slave_sel_r = 4'd0;
-reg vns_error = 1'd0;
-wire vns_wait;
-wire vns_done;
-reg [19:0] vns_count = 20'd1000000;
-wire [13:0] vns_interface0_bank_bus_adr;
-wire vns_interface0_bank_bus_we;
-wire [7:0] vns_interface0_bank_bus_dat_w;
-reg [7:0] vns_interface0_bank_bus_dat_r = 8'd0;
-wire vns_csrbank0_reset0_re;
-wire vns_csrbank0_reset0_r;
-wire vns_csrbank0_reset0_we;
-wire vns_csrbank0_reset0_w;
-wire vns_csrbank0_scratch3_re;
-wire [7:0] vns_csrbank0_scratch3_r;
-wire vns_csrbank0_scratch3_we;
-wire [7:0] vns_csrbank0_scratch3_w;
-wire vns_csrbank0_scratch2_re;
-wire [7:0] vns_csrbank0_scratch2_r;
-wire vns_csrbank0_scratch2_we;
-wire [7:0] vns_csrbank0_scratch2_w;
-wire vns_csrbank0_scratch1_re;
-wire [7:0] vns_csrbank0_scratch1_r;
-wire vns_csrbank0_scratch1_we;
-wire [7:0] vns_csrbank0_scratch1_w;
-wire vns_csrbank0_scratch0_re;
-wire [7:0] vns_csrbank0_scratch0_r;
-wire vns_csrbank0_scratch0_we;
-wire [7:0] vns_csrbank0_scratch0_w;
-wire vns_csrbank0_bus_errors3_re;
-wire [7:0] vns_csrbank0_bus_errors3_r;
-wire vns_csrbank0_bus_errors3_we;
-wire [7:0] vns_csrbank0_bus_errors3_w;
-wire vns_csrbank0_bus_errors2_re;
-wire [7:0] vns_csrbank0_bus_errors2_r;
-wire vns_csrbank0_bus_errors2_we;
-wire [7:0] vns_csrbank0_bus_errors2_w;
-wire vns_csrbank0_bus_errors1_re;
-wire [7:0] vns_csrbank0_bus_errors1_r;
-wire vns_csrbank0_bus_errors1_we;
-wire [7:0] vns_csrbank0_bus_errors1_w;
-wire vns_csrbank0_bus_errors0_re;
-wire [7:0] vns_csrbank0_bus_errors0_r;
-wire vns_csrbank0_bus_errors0_we;
-wire [7:0] vns_csrbank0_bus_errors0_w;
-wire vns_csrbank0_sel;
-wire [13:0] vns_interface1_bank_bus_adr;
-wire vns_interface1_bank_bus_we;
-wire [7:0] vns_interface1_bank_bus_dat_w;
-reg [7:0] vns_interface1_bank_bus_dat_r = 8'd0;
-wire vns_csrbank1_init_done0_re;
-wire vns_csrbank1_init_done0_r;
-wire vns_csrbank1_init_done0_we;
-wire vns_csrbank1_init_done0_w;
-wire vns_csrbank1_init_error0_re;
-wire vns_csrbank1_init_error0_r;
-wire vns_csrbank1_init_error0_we;
-wire vns_csrbank1_init_error0_w;
-wire vns_csrbank1_sel;
-wire [13:0] vns_interface2_bank_bus_adr;
-wire vns_interface2_bank_bus_we;
-wire [7:0] vns_interface2_bank_bus_dat_w;
-reg [7:0] vns_interface2_bank_bus_dat_r = 8'd0;
-wire vns_csrbank2_half_sys8x_taps0_re;
-wire [4:0] vns_csrbank2_half_sys8x_taps0_r;
-wire vns_csrbank2_half_sys8x_taps0_we;
-wire [4:0] vns_csrbank2_half_sys8x_taps0_w;
-wire vns_csrbank2_wlevel_en0_re;
-wire vns_csrbank2_wlevel_en0_r;
-wire vns_csrbank2_wlevel_en0_we;
-wire vns_csrbank2_wlevel_en0_w;
-wire vns_csrbank2_dly_sel0_re;
-wire [1:0] vns_csrbank2_dly_sel0_r;
-wire vns_csrbank2_dly_sel0_we;
-wire [1:0] vns_csrbank2_dly_sel0_w;
-wire vns_csrbank2_sel;
-wire [13:0] vns_interface3_bank_bus_adr;
-wire vns_interface3_bank_bus_we;
-wire [7:0] vns_interface3_bank_bus_dat_w;
-reg [7:0] vns_interface3_bank_bus_dat_r = 8'd0;
-wire vns_csrbank3_dfii_control0_re;
-wire [3:0] vns_csrbank3_dfii_control0_r;
-wire vns_csrbank3_dfii_control0_we;
-wire [3:0] vns_csrbank3_dfii_control0_w;
-wire vns_csrbank3_dfii_pi0_command0_re;
-wire [5:0] vns_csrbank3_dfii_pi0_command0_r;
-wire vns_csrbank3_dfii_pi0_command0_we;
-wire [5:0] vns_csrbank3_dfii_pi0_command0_w;
-wire vns_csrbank3_dfii_pi0_address1_re;
-wire [5:0] vns_csrbank3_dfii_pi0_address1_r;
-wire vns_csrbank3_dfii_pi0_address1_we;
-wire [5:0] vns_csrbank3_dfii_pi0_address1_w;
-wire vns_csrbank3_dfii_pi0_address0_re;
-wire [7:0] vns_csrbank3_dfii_pi0_address0_r;
-wire vns_csrbank3_dfii_pi0_address0_we;
-wire [7:0] vns_csrbank3_dfii_pi0_address0_w;
-wire vns_csrbank3_dfii_pi0_baddress0_re;
-wire [2:0] vns_csrbank3_dfii_pi0_baddress0_r;
-wire vns_csrbank3_dfii_pi0_baddress0_we;
-wire [2:0] vns_csrbank3_dfii_pi0_baddress0_w;
-wire vns_csrbank3_dfii_pi0_wrdata3_re;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_r;
-wire vns_csrbank3_dfii_pi0_wrdata3_we;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_w;
-wire vns_csrbank3_dfii_pi0_wrdata2_re;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_r;
-wire vns_csrbank3_dfii_pi0_wrdata2_we;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_w;
-wire vns_csrbank3_dfii_pi0_wrdata1_re;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_r;
-wire vns_csrbank3_dfii_pi0_wrdata1_we;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_w;
-wire vns_csrbank3_dfii_pi0_wrdata0_re;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_r;
-wire vns_csrbank3_dfii_pi0_wrdata0_we;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_w;
-wire vns_csrbank3_dfii_pi0_rddata3_re;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata3_r;
-wire vns_csrbank3_dfii_pi0_rddata3_we;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata3_w;
-wire vns_csrbank3_dfii_pi0_rddata2_re;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata2_r;
-wire vns_csrbank3_dfii_pi0_rddata2_we;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata2_w;
-wire vns_csrbank3_dfii_pi0_rddata1_re;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata1_r;
-wire vns_csrbank3_dfii_pi0_rddata1_we;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata1_w;
-wire vns_csrbank3_dfii_pi0_rddata0_re;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata0_r;
-wire vns_csrbank3_dfii_pi0_rddata0_we;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata0_w;
-wire vns_csrbank3_dfii_pi1_command0_re;
-wire [5:0] vns_csrbank3_dfii_pi1_command0_r;
-wire vns_csrbank3_dfii_pi1_command0_we;
-wire [5:0] vns_csrbank3_dfii_pi1_command0_w;
-wire vns_csrbank3_dfii_pi1_address1_re;
-wire [5:0] vns_csrbank3_dfii_pi1_address1_r;
-wire vns_csrbank3_dfii_pi1_address1_we;
-wire [5:0] vns_csrbank3_dfii_pi1_address1_w;
-wire vns_csrbank3_dfii_pi1_address0_re;
-wire [7:0] vns_csrbank3_dfii_pi1_address0_r;
-wire vns_csrbank3_dfii_pi1_address0_we;
-wire [7:0] vns_csrbank3_dfii_pi1_address0_w;
-wire vns_csrbank3_dfii_pi1_baddress0_re;
-wire [2:0] vns_csrbank3_dfii_pi1_baddress0_r;
-wire vns_csrbank3_dfii_pi1_baddress0_we;
-wire [2:0] vns_csrbank3_dfii_pi1_baddress0_w;
-wire vns_csrbank3_dfii_pi1_wrdata3_re;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_r;
-wire vns_csrbank3_dfii_pi1_wrdata3_we;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_w;
-wire vns_csrbank3_dfii_pi1_wrdata2_re;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_r;
-wire vns_csrbank3_dfii_pi1_wrdata2_we;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_w;
-wire vns_csrbank3_dfii_pi1_wrdata1_re;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_r;
-wire vns_csrbank3_dfii_pi1_wrdata1_we;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_w;
-wire vns_csrbank3_dfii_pi1_wrdata0_re;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_r;
-wire vns_csrbank3_dfii_pi1_wrdata0_we;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_w;
-wire vns_csrbank3_dfii_pi1_rddata3_re;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata3_r;
-wire vns_csrbank3_dfii_pi1_rddata3_we;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata3_w;
-wire vns_csrbank3_dfii_pi1_rddata2_re;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata2_r;
-wire vns_csrbank3_dfii_pi1_rddata2_we;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata2_w;
-wire vns_csrbank3_dfii_pi1_rddata1_re;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata1_r;
-wire vns_csrbank3_dfii_pi1_rddata1_we;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata1_w;
-wire vns_csrbank3_dfii_pi1_rddata0_re;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata0_r;
-wire vns_csrbank3_dfii_pi1_rddata0_we;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata0_w;
-wire vns_csrbank3_dfii_pi2_command0_re;
-wire [5:0] vns_csrbank3_dfii_pi2_command0_r;
-wire vns_csrbank3_dfii_pi2_command0_we;
-wire [5:0] vns_csrbank3_dfii_pi2_command0_w;
-wire vns_csrbank3_dfii_pi2_address1_re;
-wire [5:0] vns_csrbank3_dfii_pi2_address1_r;
-wire vns_csrbank3_dfii_pi2_address1_we;
-wire [5:0] vns_csrbank3_dfii_pi2_address1_w;
-wire vns_csrbank3_dfii_pi2_address0_re;
-wire [7:0] vns_csrbank3_dfii_pi2_address0_r;
-wire vns_csrbank3_dfii_pi2_address0_we;
-wire [7:0] vns_csrbank3_dfii_pi2_address0_w;
-wire vns_csrbank3_dfii_pi2_baddress0_re;
-wire [2:0] vns_csrbank3_dfii_pi2_baddress0_r;
-wire vns_csrbank3_dfii_pi2_baddress0_we;
-wire [2:0] vns_csrbank3_dfii_pi2_baddress0_w;
-wire vns_csrbank3_dfii_pi2_wrdata3_re;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_r;
-wire vns_csrbank3_dfii_pi2_wrdata3_we;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_w;
-wire vns_csrbank3_dfii_pi2_wrdata2_re;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_r;
-wire vns_csrbank3_dfii_pi2_wrdata2_we;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_w;
-wire vns_csrbank3_dfii_pi2_wrdata1_re;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_r;
-wire vns_csrbank3_dfii_pi2_wrdata1_we;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_w;
-wire vns_csrbank3_dfii_pi2_wrdata0_re;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_r;
-wire vns_csrbank3_dfii_pi2_wrdata0_we;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_w;
-wire vns_csrbank3_dfii_pi2_rddata3_re;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata3_r;
-wire vns_csrbank3_dfii_pi2_rddata3_we;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata3_w;
-wire vns_csrbank3_dfii_pi2_rddata2_re;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata2_r;
-wire vns_csrbank3_dfii_pi2_rddata2_we;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata2_w;
-wire vns_csrbank3_dfii_pi2_rddata1_re;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata1_r;
-wire vns_csrbank3_dfii_pi2_rddata1_we;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata1_w;
-wire vns_csrbank3_dfii_pi2_rddata0_re;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata0_r;
-wire vns_csrbank3_dfii_pi2_rddata0_we;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata0_w;
-wire vns_csrbank3_dfii_pi3_command0_re;
-wire [5:0] vns_csrbank3_dfii_pi3_command0_r;
-wire vns_csrbank3_dfii_pi3_command0_we;
-wire [5:0] vns_csrbank3_dfii_pi3_command0_w;
-wire vns_csrbank3_dfii_pi3_address1_re;
-wire [5:0] vns_csrbank3_dfii_pi3_address1_r;
-wire vns_csrbank3_dfii_pi3_address1_we;
-wire [5:0] vns_csrbank3_dfii_pi3_address1_w;
-wire vns_csrbank3_dfii_pi3_address0_re;
-wire [7:0] vns_csrbank3_dfii_pi3_address0_r;
-wire vns_csrbank3_dfii_pi3_address0_we;
-wire [7:0] vns_csrbank3_dfii_pi3_address0_w;
-wire vns_csrbank3_dfii_pi3_baddress0_re;
-wire [2:0] vns_csrbank3_dfii_pi3_baddress0_r;
-wire vns_csrbank3_dfii_pi3_baddress0_we;
-wire [2:0] vns_csrbank3_dfii_pi3_baddress0_w;
-wire vns_csrbank3_dfii_pi3_wrdata3_re;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_r;
-wire vns_csrbank3_dfii_pi3_wrdata3_we;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_w;
-wire vns_csrbank3_dfii_pi3_wrdata2_re;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_r;
-wire vns_csrbank3_dfii_pi3_wrdata2_we;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_w;
-wire vns_csrbank3_dfii_pi3_wrdata1_re;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_r;
-wire vns_csrbank3_dfii_pi3_wrdata1_we;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_w;
-wire vns_csrbank3_dfii_pi3_wrdata0_re;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_r;
-wire vns_csrbank3_dfii_pi3_wrdata0_we;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_w;
-wire vns_csrbank3_dfii_pi3_rddata3_re;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata3_r;
-wire vns_csrbank3_dfii_pi3_rddata3_we;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata3_w;
-wire vns_csrbank3_dfii_pi3_rddata2_re;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata2_r;
-wire vns_csrbank3_dfii_pi3_rddata2_we;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata2_w;
-wire vns_csrbank3_dfii_pi3_rddata1_re;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata1_r;
-wire vns_csrbank3_dfii_pi3_rddata1_we;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata1_w;
-wire vns_csrbank3_dfii_pi3_rddata0_re;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata0_r;
-wire vns_csrbank3_dfii_pi3_rddata0_we;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata0_w;
-wire vns_csrbank3_sel;
-wire [13:0] vns_interface4_bank_bus_adr;
-wire vns_interface4_bank_bus_we;
-wire [7:0] vns_interface4_bank_bus_dat_w;
-reg [7:0] vns_interface4_bank_bus_dat_r = 8'd0;
-wire vns_csrbank4_load3_re;
-wire [7:0] vns_csrbank4_load3_r;
-wire vns_csrbank4_load3_we;
-wire [7:0] vns_csrbank4_load3_w;
-wire vns_csrbank4_load2_re;
-wire [7:0] vns_csrbank4_load2_r;
-wire vns_csrbank4_load2_we;
-wire [7:0] vns_csrbank4_load2_w;
-wire vns_csrbank4_load1_re;
-wire [7:0] vns_csrbank4_load1_r;
-wire vns_csrbank4_load1_we;
-wire [7:0] vns_csrbank4_load1_w;
-wire vns_csrbank4_load0_re;
-wire [7:0] vns_csrbank4_load0_r;
-wire vns_csrbank4_load0_we;
-wire [7:0] vns_csrbank4_load0_w;
-wire vns_csrbank4_reload3_re;
-wire [7:0] vns_csrbank4_reload3_r;
-wire vns_csrbank4_reload3_we;
-wire [7:0] vns_csrbank4_reload3_w;
-wire vns_csrbank4_reload2_re;
-wire [7:0] vns_csrbank4_reload2_r;
-wire vns_csrbank4_reload2_we;
-wire [7:0] vns_csrbank4_reload2_w;
-wire vns_csrbank4_reload1_re;
-wire [7:0] vns_csrbank4_reload1_r;
-wire vns_csrbank4_reload1_we;
-wire [7:0] vns_csrbank4_reload1_w;
-wire vns_csrbank4_reload0_re;
-wire [7:0] vns_csrbank4_reload0_r;
-wire vns_csrbank4_reload0_we;
-wire [7:0] vns_csrbank4_reload0_w;
-wire vns_csrbank4_en0_re;
-wire vns_csrbank4_en0_r;
-wire vns_csrbank4_en0_we;
-wire vns_csrbank4_en0_w;
-wire vns_csrbank4_update_value0_re;
-wire vns_csrbank4_update_value0_r;
-wire vns_csrbank4_update_value0_we;
-wire vns_csrbank4_update_value0_w;
-wire vns_csrbank4_value3_re;
-wire [7:0] vns_csrbank4_value3_r;
-wire vns_csrbank4_value3_we;
-wire [7:0] vns_csrbank4_value3_w;
-wire vns_csrbank4_value2_re;
-wire [7:0] vns_csrbank4_value2_r;
-wire vns_csrbank4_value2_we;
-wire [7:0] vns_csrbank4_value2_w;
-wire vns_csrbank4_value1_re;
-wire [7:0] vns_csrbank4_value1_r;
-wire vns_csrbank4_value1_we;
-wire [7:0] vns_csrbank4_value1_w;
-wire vns_csrbank4_value0_re;
-wire [7:0] vns_csrbank4_value0_r;
-wire vns_csrbank4_value0_we;
-wire [7:0] vns_csrbank4_value0_w;
-wire vns_csrbank4_ev_enable0_re;
-wire vns_csrbank4_ev_enable0_r;
-wire vns_csrbank4_ev_enable0_we;
-wire vns_csrbank4_ev_enable0_w;
-wire vns_csrbank4_sel;
-wire [13:0] vns_interface5_bank_bus_adr;
-wire vns_interface5_bank_bus_we;
-wire [7:0] vns_interface5_bank_bus_dat_w;
-reg [7:0] vns_interface5_bank_bus_dat_r = 8'd0;
-wire vns_csrbank5_txfull_re;
-wire vns_csrbank5_txfull_r;
-wire vns_csrbank5_txfull_we;
-wire vns_csrbank5_txfull_w;
-wire vns_csrbank5_rxempty_re;
-wire vns_csrbank5_rxempty_r;
-wire vns_csrbank5_rxempty_we;
-wire vns_csrbank5_rxempty_w;
-wire vns_csrbank5_ev_enable0_re;
-wire [1:0] vns_csrbank5_ev_enable0_r;
-wire vns_csrbank5_ev_enable0_we;
-wire [1:0] vns_csrbank5_ev_enable0_w;
-wire vns_csrbank5_sel;
-wire [13:0] vns_interface6_bank_bus_adr;
-wire vns_interface6_bank_bus_we;
-wire [7:0] vns_interface6_bank_bus_dat_w;
-reg [7:0] vns_interface6_bank_bus_dat_r = 8'd0;
-wire vns_csrbank6_tuning_word3_re;
-wire [7:0] vns_csrbank6_tuning_word3_r;
-wire vns_csrbank6_tuning_word3_we;
-wire [7:0] vns_csrbank6_tuning_word3_w;
-wire vns_csrbank6_tuning_word2_re;
-wire [7:0] vns_csrbank6_tuning_word2_r;
-wire vns_csrbank6_tuning_word2_we;
-wire [7:0] vns_csrbank6_tuning_word2_w;
-wire vns_csrbank6_tuning_word1_re;
-wire [7:0] vns_csrbank6_tuning_word1_r;
-wire vns_csrbank6_tuning_word1_we;
-wire [7:0] vns_csrbank6_tuning_word1_w;
-wire vns_csrbank6_tuning_word0_re;
-wire [7:0] vns_csrbank6_tuning_word0_r;
-wire vns_csrbank6_tuning_word0_we;
-wire [7:0] vns_csrbank6_tuning_word0_w;
-wire vns_csrbank6_sel;
-wire [13:0] vns_adr;
-wire vns_we;
-wire [7:0] vns_dat_w;
-wire [7:0] vns_dat_r;
-reg vns_rhs_array_muxed0 = 1'd0;
-reg [13:0] vns_rhs_array_muxed1 = 14'd0;
-reg [2:0] vns_rhs_array_muxed2 = 3'd0;
-reg vns_rhs_array_muxed3 = 1'd0;
-reg vns_rhs_array_muxed4 = 1'd0;
-reg vns_rhs_array_muxed5 = 1'd0;
-reg vns_t_array_muxed0 = 1'd0;
-reg vns_t_array_muxed1 = 1'd0;
-reg vns_t_array_muxed2 = 1'd0;
-reg vns_rhs_array_muxed6 = 1'd0;
-reg [13:0] vns_rhs_array_muxed7 = 14'd0;
-reg [2:0] vns_rhs_array_muxed8 = 3'd0;
-reg vns_rhs_array_muxed9 = 1'd0;
-reg vns_rhs_array_muxed10 = 1'd0;
-reg vns_rhs_array_muxed11 = 1'd0;
-reg vns_t_array_muxed3 = 1'd0;
-reg vns_t_array_muxed4 = 1'd0;
-reg vns_t_array_muxed5 = 1'd0;
-reg [20:0] vns_rhs_array_muxed12 = 21'd0;
-reg vns_rhs_array_muxed13 = 1'd0;
-reg vns_rhs_array_muxed14 = 1'd0;
-reg [20:0] vns_rhs_array_muxed15 = 21'd0;
-reg vns_rhs_array_muxed16 = 1'd0;
-reg vns_rhs_array_muxed17 = 1'd0;
-reg [20:0] vns_rhs_array_muxed18 = 21'd0;
-reg vns_rhs_array_muxed19 = 1'd0;
-reg vns_rhs_array_muxed20 = 1'd0;
-reg [20:0] vns_rhs_array_muxed21 = 21'd0;
-reg vns_rhs_array_muxed22 = 1'd0;
-reg vns_rhs_array_muxed23 = 1'd0;
-reg [20:0] vns_rhs_array_muxed24 = 21'd0;
-reg vns_rhs_array_muxed25 = 1'd0;
-reg vns_rhs_array_muxed26 = 1'd0;
-reg [20:0] vns_rhs_array_muxed27 = 21'd0;
-reg vns_rhs_array_muxed28 = 1'd0;
-reg vns_rhs_array_muxed29 = 1'd0;
-reg [20:0] vns_rhs_array_muxed30 = 21'd0;
-reg vns_rhs_array_muxed31 = 1'd0;
-reg vns_rhs_array_muxed32 = 1'd0;
-reg [20:0] vns_rhs_array_muxed33 = 21'd0;
-reg vns_rhs_array_muxed34 = 1'd0;
-reg vns_rhs_array_muxed35 = 1'd0;
-reg [29:0] vns_rhs_array_muxed36 = 30'd0;
-reg [31:0] vns_rhs_array_muxed37 = 32'd0;
-reg [3:0] vns_rhs_array_muxed38 = 4'd0;
-reg vns_rhs_array_muxed39 = 1'd0;
-reg vns_rhs_array_muxed40 = 1'd0;
-reg vns_rhs_array_muxed41 = 1'd0;
-reg [2:0] vns_rhs_array_muxed42 = 3'd0;
-reg [1:0] vns_rhs_array_muxed43 = 2'd0;
-reg [2:0] vns_array_muxed0 = 3'd0;
-reg [13:0] vns_array_muxed1 = 14'd0;
-reg vns_array_muxed2 = 1'd0;
-reg vns_array_muxed3 = 1'd0;
-reg vns_array_muxed4 = 1'd0;
-reg vns_array_muxed5 = 1'd0;
-reg vns_array_muxed6 = 1'd0;
-reg [2:0] vns_array_muxed7 = 3'd0;
-reg [13:0] vns_array_muxed8 = 14'd0;
-reg vns_array_muxed9 = 1'd0;
-reg vns_array_muxed10 = 1'd0;
-reg vns_array_muxed11 = 1'd0;
-reg vns_array_muxed12 = 1'd0;
-reg vns_array_muxed13 = 1'd0;
-reg [2:0] vns_array_muxed14 = 3'd0;
-reg [13:0] vns_array_muxed15 = 14'd0;
-reg vns_array_muxed16 = 1'd0;
-reg vns_array_muxed17 = 1'd0;
-reg vns_array_muxed18 = 1'd0;
-reg vns_array_muxed19 = 1'd0;
-reg vns_array_muxed20 = 1'd0;
-reg [2:0] vns_array_muxed21 = 3'd0;
-reg [13:0] vns_array_muxed22 = 14'd0;
-reg vns_array_muxed23 = 1'd0;
-reg vns_array_muxed24 = 1'd0;
-reg vns_array_muxed25 = 1'd0;
-reg vns_array_muxed26 = 1'd0;
-reg vns_array_muxed27 = 1'd0;
-(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_regs0 = 1'd0;
-(* async_reg = "true", dont_touch = "true" *) reg vns_regs1 = 1'd0;
-wire vns_xilinxasyncresetsynchronizerimpl0;
-wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire vns_xilinxasyncresetsynchronizerimpl1;
-wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire vns_xilinxasyncresetsynchronizerimpl1_expr;
-wire vns_xilinxasyncresetsynchronizerimpl2;
-wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire vns_xilinxasyncresetsynchronizerimpl2_expr;
-wire vns_xilinxasyncresetsynchronizerimpl3;
-wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire sys_pll_reset;
+wire sys_pll_locked;
+wire s7pll0_clkin;
+wire s7pll0_clkout0;
+wire s7pll0_clkout_buf0;
+wire s7pll0_clkout1;
+wire s7pll0_clkout_buf1;
+wire s7pll0_clkout2;
+wire s7pll0_clkout_buf2;
+wire iodelay_pll_reset;
+wire iodelay_pll_locked;
+wire s7pll1_clkin;
+wire s7pll1_clkout;
+wire s7pll1_clkout_buf;
+reg [3:0] reset_counter = 4'd15;
+reg ic_reset = 1'd1;
+reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg a7ddrphy_wlevel_en_storage = 1'd0;
+reg a7ddrphy_wlevel_en_re = 1'd0;
+wire a7ddrphy_wlevel_strobe_re;
+wire a7ddrphy_wlevel_strobe_r;
+wire a7ddrphy_wlevel_strobe_we;
+reg a7ddrphy_wlevel_strobe_w = 1'd0;
+wire a7ddrphy_cdly_rst_re;
+wire a7ddrphy_cdly_rst_r;
+wire a7ddrphy_cdly_rst_we;
+reg a7ddrphy_cdly_rst_w = 1'd0;
+wire a7ddrphy_cdly_inc_re;
+wire a7ddrphy_cdly_inc_r;
+wire a7ddrphy_cdly_inc_we;
+reg a7ddrphy_cdly_inc_w = 1'd0;
+reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
+reg a7ddrphy_dly_sel_re = 1'd0;
+wire a7ddrphy_rdly_dq_rst_re;
+wire a7ddrphy_rdly_dq_rst_r;
+wire a7ddrphy_rdly_dq_rst_we;
+reg a7ddrphy_rdly_dq_rst_w = 1'd0;
+wire a7ddrphy_rdly_dq_inc_re;
+wire a7ddrphy_rdly_dq_inc_r;
+wire a7ddrphy_rdly_dq_inc_we;
+reg a7ddrphy_rdly_dq_inc_w = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_rst_re;
+wire a7ddrphy_rdly_dq_bitslip_rst_r;
+wire a7ddrphy_rdly_dq_bitslip_rst_we;
+reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_re;
+wire a7ddrphy_rdly_dq_bitslip_r;
+wire a7ddrphy_rdly_dq_bitslip_we;
+reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+wire [13:0] a7ddrphy_dfi_p0_address;
+wire [2:0] a7ddrphy_dfi_p0_bank;
+wire a7ddrphy_dfi_p0_cas_n;
+wire a7ddrphy_dfi_p0_cs_n;
+wire a7ddrphy_dfi_p0_ras_n;
+wire a7ddrphy_dfi_p0_we_n;
+wire a7ddrphy_dfi_p0_cke;
+wire a7ddrphy_dfi_p0_odt;
+wire a7ddrphy_dfi_p0_reset_n;
+wire a7ddrphy_dfi_p0_act_n;
+wire [31:0] a7ddrphy_dfi_p0_wrdata;
+wire a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
+wire a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
+reg a7ddrphy_dfi_p0_rddata_valid = 1'd0;
+wire [13:0] a7ddrphy_dfi_p1_address;
+wire [2:0] a7ddrphy_dfi_p1_bank;
+wire a7ddrphy_dfi_p1_cas_n;
+wire a7ddrphy_dfi_p1_cs_n;
+wire a7ddrphy_dfi_p1_ras_n;
+wire a7ddrphy_dfi_p1_we_n;
+wire a7ddrphy_dfi_p1_cke;
+wire a7ddrphy_dfi_p1_odt;
+wire a7ddrphy_dfi_p1_reset_n;
+wire a7ddrphy_dfi_p1_act_n;
+wire [31:0] a7ddrphy_dfi_p1_wrdata;
+wire a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
+wire a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
+reg a7ddrphy_dfi_p1_rddata_valid = 1'd0;
+wire [13:0] a7ddrphy_dfi_p2_address;
+wire [2:0] a7ddrphy_dfi_p2_bank;
+wire a7ddrphy_dfi_p2_cas_n;
+wire a7ddrphy_dfi_p2_cs_n;
+wire a7ddrphy_dfi_p2_ras_n;
+wire a7ddrphy_dfi_p2_we_n;
+wire a7ddrphy_dfi_p2_cke;
+wire a7ddrphy_dfi_p2_odt;
+wire a7ddrphy_dfi_p2_reset_n;
+wire a7ddrphy_dfi_p2_act_n;
+wire [31:0] a7ddrphy_dfi_p2_wrdata;
+wire a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
+wire a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
+reg a7ddrphy_dfi_p2_rddata_valid = 1'd0;
+wire [13:0] a7ddrphy_dfi_p3_address;
+wire [2:0] a7ddrphy_dfi_p3_bank;
+wire a7ddrphy_dfi_p3_cas_n;
+wire a7ddrphy_dfi_p3_cs_n;
+wire a7ddrphy_dfi_p3_ras_n;
+wire a7ddrphy_dfi_p3_we_n;
+wire a7ddrphy_dfi_p3_cke;
+wire a7ddrphy_dfi_p3_odt;
+wire a7ddrphy_dfi_p3_reset_n;
+wire a7ddrphy_dfi_p3_act_n;
+wire [31:0] a7ddrphy_dfi_p3_wrdata;
+wire a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
+wire a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
+reg a7ddrphy_dfi_p3_rddata_valid = 1'd0;
+wire a7ddrphy_sd_clk_se_nodelay;
+reg a7ddrphy_dqs_oe = 1'd0;
+reg a7ddrphy_dqs_oe_delayed = 1'd0;
+wire a7ddrphy_dqspattern0;
+wire a7ddrphy_dqspattern1;
+reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
+wire [1:0] a7ddrphy_dqs_i;
+wire [1:0] a7ddrphy_dqs_i_delayed;
+wire a7ddrphy_dqs_o_no_delay0;
+wire a7ddrphy_dqs_t0;
+wire a7ddrphy0;
+wire a7ddrphy_dqs_o_no_delay1;
+wire a7ddrphy_dqs_t1;
+wire a7ddrphy1;
+wire a7ddrphy_dq_oe;
+reg a7ddrphy_dq_oe_delayed = 1'd0;
+wire a7ddrphy_dq_o_nodelay0;
+wire a7ddrphy_dq_i_nodelay0;
+wire a7ddrphy_dq_i_delayed0;
+wire a7ddrphy_dq_t0;
+wire [7:0] a7ddrphy_dq_i_data0;
+wire [7:0] a7ddrphy_bitslip0_i;
+reg [7:0] a7ddrphy_bitslip0_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip0_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay1;
+wire a7ddrphy_dq_i_nodelay1;
+wire a7ddrphy_dq_i_delayed1;
+wire a7ddrphy_dq_t1;
+wire [7:0] a7ddrphy_dq_i_data1;
+wire [7:0] a7ddrphy_bitslip1_i;
+reg [7:0] a7ddrphy_bitslip1_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip1_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay2;
+wire a7ddrphy_dq_i_nodelay2;
+wire a7ddrphy_dq_i_delayed2;
+wire a7ddrphy_dq_t2;
+wire [7:0] a7ddrphy_dq_i_data2;
+wire [7:0] a7ddrphy_bitslip2_i;
+reg [7:0] a7ddrphy_bitslip2_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip2_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip2_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay3;
+wire a7ddrphy_dq_i_nodelay3;
+wire a7ddrphy_dq_i_delayed3;
+wire a7ddrphy_dq_t3;
+wire [7:0] a7ddrphy_dq_i_data3;
+wire [7:0] a7ddrphy_bitslip3_i;
+reg [7:0] a7ddrphy_bitslip3_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip3_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip3_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay4;
+wire a7ddrphy_dq_i_nodelay4;
+wire a7ddrphy_dq_i_delayed4;
+wire a7ddrphy_dq_t4;
+wire [7:0] a7ddrphy_dq_i_data4;
+wire [7:0] a7ddrphy_bitslip4_i;
+reg [7:0] a7ddrphy_bitslip4_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip4_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip4_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay5;
+wire a7ddrphy_dq_i_nodelay5;
+wire a7ddrphy_dq_i_delayed5;
+wire a7ddrphy_dq_t5;
+wire [7:0] a7ddrphy_dq_i_data5;
+wire [7:0] a7ddrphy_bitslip5_i;
+reg [7:0] a7ddrphy_bitslip5_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip5_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip5_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay6;
+wire a7ddrphy_dq_i_nodelay6;
+wire a7ddrphy_dq_i_delayed6;
+wire a7ddrphy_dq_t6;
+wire [7:0] a7ddrphy_dq_i_data6;
+wire [7:0] a7ddrphy_bitslip6_i;
+reg [7:0] a7ddrphy_bitslip6_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip6_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip6_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay7;
+wire a7ddrphy_dq_i_nodelay7;
+wire a7ddrphy_dq_i_delayed7;
+wire a7ddrphy_dq_t7;
+wire [7:0] a7ddrphy_dq_i_data7;
+wire [7:0] a7ddrphy_bitslip7_i;
+reg [7:0] a7ddrphy_bitslip7_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip7_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip7_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay8;
+wire a7ddrphy_dq_i_nodelay8;
+wire a7ddrphy_dq_i_delayed8;
+wire a7ddrphy_dq_t8;
+wire [7:0] a7ddrphy_dq_i_data8;
+wire [7:0] a7ddrphy_bitslip8_i;
+reg [7:0] a7ddrphy_bitslip8_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip8_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip8_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay9;
+wire a7ddrphy_dq_i_nodelay9;
+wire a7ddrphy_dq_i_delayed9;
+wire a7ddrphy_dq_t9;
+wire [7:0] a7ddrphy_dq_i_data9;
+wire [7:0] a7ddrphy_bitslip9_i;
+reg [7:0] a7ddrphy_bitslip9_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip9_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip9_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay10;
+wire a7ddrphy_dq_i_nodelay10;
+wire a7ddrphy_dq_i_delayed10;
+wire a7ddrphy_dq_t10;
+wire [7:0] a7ddrphy_dq_i_data10;
+wire [7:0] a7ddrphy_bitslip10_i;
+reg [7:0] a7ddrphy_bitslip10_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip10_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip10_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay11;
+wire a7ddrphy_dq_i_nodelay11;
+wire a7ddrphy_dq_i_delayed11;
+wire a7ddrphy_dq_t11;
+wire [7:0] a7ddrphy_dq_i_data11;
+wire [7:0] a7ddrphy_bitslip11_i;
+reg [7:0] a7ddrphy_bitslip11_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip11_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip11_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay12;
+wire a7ddrphy_dq_i_nodelay12;
+wire a7ddrphy_dq_i_delayed12;
+wire a7ddrphy_dq_t12;
+wire [7:0] a7ddrphy_dq_i_data12;
+wire [7:0] a7ddrphy_bitslip12_i;
+reg [7:0] a7ddrphy_bitslip12_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip12_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip12_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay13;
+wire a7ddrphy_dq_i_nodelay13;
+wire a7ddrphy_dq_i_delayed13;
+wire a7ddrphy_dq_t13;
+wire [7:0] a7ddrphy_dq_i_data13;
+wire [7:0] a7ddrphy_bitslip13_i;
+reg [7:0] a7ddrphy_bitslip13_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip13_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip13_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay14;
+wire a7ddrphy_dq_i_nodelay14;
+wire a7ddrphy_dq_i_delayed14;
+wire a7ddrphy_dq_t14;
+wire [7:0] a7ddrphy_dq_i_data14;
+wire [7:0] a7ddrphy_bitslip14_i;
+reg [7:0] a7ddrphy_bitslip14_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip14_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip14_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay15;
+wire a7ddrphy_dq_i_nodelay15;
+wire a7ddrphy_dq_i_delayed15;
+wire a7ddrphy_dq_t15;
+wire [7:0] a7ddrphy_dq_i_data15;
+wire [7:0] a7ddrphy_bitslip15_i;
+reg [7:0] a7ddrphy_bitslip15_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip15_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip15_r = 16'd0;
+wire [7:0] a7ddrphy_rddata_en;
+reg [7:0] a7ddrphy_rddata_en_last = 8'd0;
+wire [3:0] a7ddrphy_wrdata_en;
+reg [3:0] a7ddrphy_wrdata_en_last = 4'd0;
+wire [13:0] litedramcore_inti_p0_address;
+wire [2:0] litedramcore_inti_p0_bank;
+reg litedramcore_inti_p0_cas_n = 1'd1;
+reg litedramcore_inti_p0_cs_n = 1'd1;
+reg litedramcore_inti_p0_ras_n = 1'd1;
+reg litedramcore_inti_p0_we_n = 1'd1;
+wire litedramcore_inti_p0_cke;
+wire litedramcore_inti_p0_odt;
+wire litedramcore_inti_p0_reset_n;
+reg litedramcore_inti_p0_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p0_wrdata;
+wire litedramcore_inti_p0_wrdata_en;
+wire [3:0] litedramcore_inti_p0_wrdata_mask;
+wire litedramcore_inti_p0_rddata_en;
+reg [31:0] litedramcore_inti_p0_rddata = 32'd0;
+reg litedramcore_inti_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_inti_p1_address;
+wire [2:0] litedramcore_inti_p1_bank;
+reg litedramcore_inti_p1_cas_n = 1'd1;
+reg litedramcore_inti_p1_cs_n = 1'd1;
+reg litedramcore_inti_p1_ras_n = 1'd1;
+reg litedramcore_inti_p1_we_n = 1'd1;
+wire litedramcore_inti_p1_cke;
+wire litedramcore_inti_p1_odt;
+wire litedramcore_inti_p1_reset_n;
+reg litedramcore_inti_p1_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p1_wrdata;
+wire litedramcore_inti_p1_wrdata_en;
+wire [3:0] litedramcore_inti_p1_wrdata_mask;
+wire litedramcore_inti_p1_rddata_en;
+reg [31:0] litedramcore_inti_p1_rddata = 32'd0;
+reg litedramcore_inti_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_inti_p2_address;
+wire [2:0] litedramcore_inti_p2_bank;
+reg litedramcore_inti_p2_cas_n = 1'd1;
+reg litedramcore_inti_p2_cs_n = 1'd1;
+reg litedramcore_inti_p2_ras_n = 1'd1;
+reg litedramcore_inti_p2_we_n = 1'd1;
+wire litedramcore_inti_p2_cke;
+wire litedramcore_inti_p2_odt;
+wire litedramcore_inti_p2_reset_n;
+reg litedramcore_inti_p2_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p2_wrdata;
+wire litedramcore_inti_p2_wrdata_en;
+wire [3:0] litedramcore_inti_p2_wrdata_mask;
+wire litedramcore_inti_p2_rddata_en;
+reg [31:0] litedramcore_inti_p2_rddata = 32'd0;
+reg litedramcore_inti_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_inti_p3_address;
+wire [2:0] litedramcore_inti_p3_bank;
+reg litedramcore_inti_p3_cas_n = 1'd1;
+reg litedramcore_inti_p3_cs_n = 1'd1;
+reg litedramcore_inti_p3_ras_n = 1'd1;
+reg litedramcore_inti_p3_we_n = 1'd1;
+wire litedramcore_inti_p3_cke;
+wire litedramcore_inti_p3_odt;
+wire litedramcore_inti_p3_reset_n;
+reg litedramcore_inti_p3_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p3_wrdata;
+wire litedramcore_inti_p3_wrdata_en;
+wire [3:0] litedramcore_inti_p3_wrdata_mask;
+wire litedramcore_inti_p3_rddata_en;
+reg [31:0] litedramcore_inti_p3_rddata = 32'd0;
+reg litedramcore_inti_p3_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [13:0] litedramcore_master_p0_address = 14'd0;
+reg [2:0] litedramcore_master_p0_bank = 3'd0;
+reg litedramcore_master_p0_cas_n = 1'd1;
+reg litedramcore_master_p0_cs_n = 1'd1;
+reg litedramcore_master_p0_ras_n = 1'd1;
+reg litedramcore_master_p0_we_n = 1'd1;
+reg litedramcore_master_p0_cke = 1'd0;
+reg litedramcore_master_p0_odt = 1'd0;
+reg litedramcore_master_p0_reset_n = 1'd0;
+reg litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg [13:0] litedramcore_master_p1_address = 14'd0;
+reg [2:0] litedramcore_master_p1_bank = 3'd0;
+reg litedramcore_master_p1_cas_n = 1'd1;
+reg litedramcore_master_p1_cs_n = 1'd1;
+reg litedramcore_master_p1_ras_n = 1'd1;
+reg litedramcore_master_p1_we_n = 1'd1;
+reg litedramcore_master_p1_cke = 1'd0;
+reg litedramcore_master_p1_odt = 1'd0;
+reg litedramcore_master_p1_reset_n = 1'd0;
+reg litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg [13:0] litedramcore_master_p2_address = 14'd0;
+reg [2:0] litedramcore_master_p2_bank = 3'd0;
+reg litedramcore_master_p2_cas_n = 1'd1;
+reg litedramcore_master_p2_cs_n = 1'd1;
+reg litedramcore_master_p2_ras_n = 1'd1;
+reg litedramcore_master_p2_we_n = 1'd1;
+reg litedramcore_master_p2_cke = 1'd0;
+reg litedramcore_master_p2_odt = 1'd0;
+reg litedramcore_master_p2_reset_n = 1'd0;
+reg litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg [13:0] litedramcore_master_p3_address = 14'd0;
+reg [2:0] litedramcore_master_p3_bank = 3'd0;
+reg litedramcore_master_p3_cas_n = 1'd1;
+reg litedramcore_master_p3_cs_n = 1'd1;
+reg litedramcore_master_p3_ras_n = 1'd1;
+reg litedramcore_master_p3_we_n = 1'd1;
+reg litedramcore_master_p3_cke = 1'd0;
+reg litedramcore_master_p3_odt = 1'd0;
+reg litedramcore_master_p3_reset_n = 1'd0;
+reg litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+reg [3:0] litedramcore_storage = 4'd0;
+reg litedramcore_re = 1'd0;
+reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg litedramcore_phaseinjector0_command_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_re;
+wire litedramcore_phaseinjector0_command_issue_r;
+wire litedramcore_phaseinjector0_command_issue_we;
+reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
+reg litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_status = 32'd0;
+wire litedramcore_phaseinjector0_we;
+reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg litedramcore_phaseinjector1_command_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_re;
+wire litedramcore_phaseinjector1_command_issue_r;
+wire litedramcore_phaseinjector1_command_issue_we;
+reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
+reg litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_status = 32'd0;
+wire litedramcore_phaseinjector1_we;
+reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg litedramcore_phaseinjector2_command_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_re;
+wire litedramcore_phaseinjector2_command_issue_r;
+wire litedramcore_phaseinjector2_command_issue_we;
+reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
+reg litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_status = 32'd0;
+wire litedramcore_phaseinjector2_we;
+reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg litedramcore_phaseinjector3_command_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_re;
+wire litedramcore_phaseinjector3_command_issue_r;
+wire litedramcore_phaseinjector3_command_issue_we;
+reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
+reg litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_status = 32'd0;
+wire litedramcore_phaseinjector3_we;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [20:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [20:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [20:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [20:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [20:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [20:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [20:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [20:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg [127:0] litedramcore_interface_wdata = 128'd0;
+reg [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg [13:0] litedramcore_dfi_p0_address = 14'd0;
+reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg litedramcore_dfi_p0_cas_n = 1'd1;
+reg litedramcore_dfi_p0_cs_n = 1'd1;
+reg litedramcore_dfi_p0_ras_n = 1'd1;
+reg litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg [13:0] litedramcore_dfi_p1_address = 14'd0;
+reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg litedramcore_dfi_p1_cas_n = 1'd1;
+reg litedramcore_dfi_p1_cs_n = 1'd1;
+reg litedramcore_dfi_p1_ras_n = 1'd1;
+reg litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg [13:0] litedramcore_dfi_p2_address = 14'd0;
+reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg litedramcore_dfi_p2_cas_n = 1'd1;
+reg litedramcore_dfi_p2_cs_n = 1'd1;
+reg litedramcore_dfi_p2_ras_n = 1'd1;
+reg litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg [13:0] litedramcore_dfi_p3_address = 14'd0;
+reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg litedramcore_dfi_p3_cas_n = 1'd1;
+reg litedramcore_dfi_p3_cs_n = 1'd1;
+reg litedramcore_dfi_p3_ras_n = 1'd1;
+reg litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg litedramcore_cmd_valid = 1'd0;
+reg litedramcore_cmd_ready = 1'd0;
+reg litedramcore_cmd_last = 1'd0;
+reg [13:0] litedramcore_cmd_payload_a = 14'd0;
+reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg litedramcore_cmd_payload_cas = 1'd0;
+reg litedramcore_cmd_payload_ras = 1'd0;
+reg litedramcore_cmd_payload_we = 1'd0;
+reg litedramcore_cmd_payload_is_read = 1'd0;
+reg litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg litedramcore_postponer_req_o = 1'd0;
+reg litedramcore_postponer_count = 1'd0;
+reg litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] litedramcore_sequencer_counter = 6'd0;
+reg litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg litedramcore_zqcs_executer_start = 1'd0;
+reg litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [20:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine0_row = 14'd0;
+reg litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg litedramcore_bankmachine0_row_open = 1'd0;
+reg litedramcore_bankmachine0_row_close = 1'd0;
+reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [20:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine1_row = 14'd0;
+reg litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg litedramcore_bankmachine1_row_open = 1'd0;
+reg litedramcore_bankmachine1_row_close = 1'd0;
+reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [20:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine2_row = 14'd0;
+reg litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg litedramcore_bankmachine2_row_open = 1'd0;
+reg litedramcore_bankmachine2_row_close = 1'd0;
+reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [20:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine3_row = 14'd0;
+reg litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg litedramcore_bankmachine3_row_open = 1'd0;
+reg litedramcore_bankmachine3_row_close = 1'd0;
+reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [20:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine4_row = 14'd0;
+reg litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg litedramcore_bankmachine4_row_open = 1'd0;
+reg litedramcore_bankmachine4_row_close = 1'd0;
+reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [20:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine5_row = 14'd0;
+reg litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg litedramcore_bankmachine5_row_open = 1'd0;
+reg litedramcore_bankmachine5_row_close = 1'd0;
+reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [20:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine6_row = 14'd0;
+reg litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg litedramcore_bankmachine6_row_open = 1'd0;
+reg litedramcore_bankmachine6_row_close = 1'd0;
+reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [20:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine7_row = 14'd0;
+reg litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg litedramcore_bankmachine7_row_open = 1'd0;
+reg litedramcore_bankmachine7_row_close = 1'd0;
+reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+reg litedramcore_choose_cmd_want_reads = 1'd0;
+reg litedramcore_choose_cmd_want_writes = 1'd0;
+reg litedramcore_choose_cmd_want_cmds = 1'd0;
+reg litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg litedramcore_choose_req_want_reads = 1'd0;
+reg litedramcore_choose_req_want_writes = 1'd0;
+reg litedramcore_choose_req_want_cmds = 1'd0;
+reg litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg litedramcore_choose_req_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg [13:0] litedramcore_nop_a = 14'd0;
+reg [2:0] litedramcore_nop_ba = 3'd0;
+reg [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg litedramcore_steerer0 = 1'd1;
+reg litedramcore_steerer1 = 1'd1;
+reg litedramcore_steerer2 = 1'd1;
+reg litedramcore_steerer3 = 1'd1;
+reg litedramcore_steerer4 = 1'd1;
+reg litedramcore_steerer5 = 1'd1;
+reg litedramcore_steerer6 = 1'd1;
+reg litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd1;
+reg litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd1;
+reg litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd1;
+reg [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg [4:0] litedramcore_time0 = 5'd0;
+reg litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg init_done_storage = 1'd0;
+reg init_done_re = 1'd0;
+reg init_error_storage = 1'd0;
+reg init_error_re = 1'd0;
+wire [13:0] csr_port_adr;
+wire csr_port_we;
+wire [7:0] csr_port_dat_w;
+wire [7:0] csr_port_dat_r;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [23:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+wire pll_fb0;
+wire pll_fb1;
+reg [1:0] refresher_state = 2'd0;
+reg [1:0] refresher_next_state = 2'd0;
+reg [3:0] bankmachine0_state = 4'd0;
+reg [3:0] bankmachine0_next_state = 4'd0;
+reg [3:0] bankmachine1_state = 4'd0;
+reg [3:0] bankmachine1_next_state = 4'd0;
+reg [3:0] bankmachine2_state = 4'd0;
+reg [3:0] bankmachine2_next_state = 4'd0;
+reg [3:0] bankmachine3_state = 4'd0;
+reg [3:0] bankmachine3_next_state = 4'd0;
+reg [3:0] bankmachine4_state = 4'd0;
+reg [3:0] bankmachine4_next_state = 4'd0;
+reg [3:0] bankmachine5_state = 4'd0;
+reg [3:0] bankmachine5_next_state = 4'd0;
+reg [3:0] bankmachine6_state = 4'd0;
+reg [3:0] bankmachine6_next_state = 4'd0;
+reg [3:0] bankmachine7_state = 4'd0;
+reg [3:0] bankmachine7_next_state = 4'd0;
+reg [3:0] multiplexer_state = 4'd0;
+reg [3:0] multiplexer_next_state = 4'd0;
+wire roundrobin0_request;
+wire roundrobin0_grant;
+wire roundrobin0_ce;
+wire roundrobin1_request;
+wire roundrobin1_grant;
+wire roundrobin1_ce;
+wire roundrobin2_request;
+wire roundrobin2_grant;
+wire roundrobin2_ce;
+wire roundrobin3_request;
+wire roundrobin3_grant;
+wire roundrobin3_ce;
+wire roundrobin4_request;
+wire roundrobin4_grant;
+wire roundrobin4_ce;
+wire roundrobin5_request;
+wire roundrobin5_grant;
+wire roundrobin5_ce;
+wire roundrobin6_request;
+wire roundrobin6_grant;
+wire roundrobin6_ce;
+wire roundrobin7_request;
+wire roundrobin7_grant;
+wire roundrobin7_ce;
+reg locked0 = 1'd0;
+reg locked1 = 1'd0;
+reg locked2 = 1'd0;
+reg locked3 = 1'd0;
+reg locked4 = 1'd0;
+reg locked5 = 1'd0;
+reg locked6 = 1'd0;
+reg locked7 = 1'd0;
+reg new_master_wdata_ready0 = 1'd0;
+reg new_master_wdata_ready1 = 1'd0;
+reg new_master_wdata_ready2 = 1'd0;
+reg new_master_rdata_valid0 = 1'd0;
+reg new_master_rdata_valid1 = 1'd0;
+reg new_master_rdata_valid2 = 1'd0;
+reg new_master_rdata_valid3 = 1'd0;
+reg new_master_rdata_valid4 = 1'd0;
+reg new_master_rdata_valid5 = 1'd0;
+reg new_master_rdata_valid6 = 1'd0;
+reg new_master_rdata_valid7 = 1'd0;
+reg new_master_rdata_valid8 = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [7:0] interface0_bank_bus_dat_w;
+reg [7:0] interface0_bank_bus_dat_r = 8'd0;
+wire csrbank0_init_done0_re;
+wire csrbank0_init_done0_r;
+wire csrbank0_init_done0_we;
+wire csrbank0_init_done0_w;
+wire csrbank0_init_error0_re;
+wire csrbank0_init_error0_r;
+wire csrbank0_init_error0_we;
+wire csrbank0_init_error0_w;
+reg csrbank0_sel = 1'd0;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [7:0] interface1_bank_bus_dat_w;
+reg [7:0] interface1_bank_bus_dat_r = 8'd0;
+wire csrbank1_half_sys8x_taps0_re;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+wire csrbank1_half_sys8x_taps0_we;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+wire csrbank1_wlevel_en0_re;
+wire csrbank1_wlevel_en0_r;
+wire csrbank1_wlevel_en0_we;
+wire csrbank1_wlevel_en0_w;
+wire csrbank1_dly_sel0_re;
+wire [1:0] csrbank1_dly_sel0_r;
+wire csrbank1_dly_sel0_we;
+wire [1:0] csrbank1_dly_sel0_w;
+reg csrbank1_sel = 1'd0;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [7:0] interface2_bank_bus_dat_w;
+reg [7:0] interface2_bank_bus_dat_r = 8'd0;
+wire csrbank2_dfii_control0_re;
+wire [3:0] csrbank2_dfii_control0_r;
+wire csrbank2_dfii_control0_we;
+wire [3:0] csrbank2_dfii_control0_w;
+wire csrbank2_dfii_pi0_command0_re;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+wire csrbank2_dfii_pi0_command0_we;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+wire csrbank2_dfii_pi0_address1_re;
+wire [5:0] csrbank2_dfii_pi0_address1_r;
+wire csrbank2_dfii_pi0_address1_we;
+wire [5:0] csrbank2_dfii_pi0_address1_w;
+wire csrbank2_dfii_pi0_address0_re;
+wire [7:0] csrbank2_dfii_pi0_address0_r;
+wire csrbank2_dfii_pi0_address0_we;
+wire [7:0] csrbank2_dfii_pi0_address0_w;
+wire csrbank2_dfii_pi0_baddress0_re;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+wire csrbank2_dfii_pi0_baddress0_we;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+wire csrbank2_dfii_pi0_wrdata3_re;
+wire [7:0] csrbank2_dfii_pi0_wrdata3_r;
+wire csrbank2_dfii_pi0_wrdata3_we;
+wire [7:0] csrbank2_dfii_pi0_wrdata3_w;
+wire csrbank2_dfii_pi0_wrdata2_re;
+wire [7:0] csrbank2_dfii_pi0_wrdata2_r;
+wire csrbank2_dfii_pi0_wrdata2_we;
+wire [7:0] csrbank2_dfii_pi0_wrdata2_w;
+wire csrbank2_dfii_pi0_wrdata1_re;
+wire [7:0] csrbank2_dfii_pi0_wrdata1_r;
+wire csrbank2_dfii_pi0_wrdata1_we;
+wire [7:0] csrbank2_dfii_pi0_wrdata1_w;
+wire csrbank2_dfii_pi0_wrdata0_re;
+wire [7:0] csrbank2_dfii_pi0_wrdata0_r;
+wire csrbank2_dfii_pi0_wrdata0_we;
+wire [7:0] csrbank2_dfii_pi0_wrdata0_w;
+wire csrbank2_dfii_pi0_rddata3_re;
+wire [7:0] csrbank2_dfii_pi0_rddata3_r;
+wire csrbank2_dfii_pi0_rddata3_we;
+wire [7:0] csrbank2_dfii_pi0_rddata3_w;
+wire csrbank2_dfii_pi0_rddata2_re;
+wire [7:0] csrbank2_dfii_pi0_rddata2_r;
+wire csrbank2_dfii_pi0_rddata2_we;
+wire [7:0] csrbank2_dfii_pi0_rddata2_w;
+wire csrbank2_dfii_pi0_rddata1_re;
+wire [7:0] csrbank2_dfii_pi0_rddata1_r;
+wire csrbank2_dfii_pi0_rddata1_we;
+wire [7:0] csrbank2_dfii_pi0_rddata1_w;
+wire csrbank2_dfii_pi0_rddata0_re;
+wire [7:0] csrbank2_dfii_pi0_rddata0_r;
+wire csrbank2_dfii_pi0_rddata0_we;
+wire [7:0] csrbank2_dfii_pi0_rddata0_w;
+wire csrbank2_dfii_pi1_command0_re;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+wire csrbank2_dfii_pi1_command0_we;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+wire csrbank2_dfii_pi1_address1_re;
+wire [5:0] csrbank2_dfii_pi1_address1_r;
+wire csrbank2_dfii_pi1_address1_we;
+wire [5:0] csrbank2_dfii_pi1_address1_w;
+wire csrbank2_dfii_pi1_address0_re;
+wire [7:0] csrbank2_dfii_pi1_address0_r;
+wire csrbank2_dfii_pi1_address0_we;
+wire [7:0] csrbank2_dfii_pi1_address0_w;
+wire csrbank2_dfii_pi1_baddress0_re;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+wire csrbank2_dfii_pi1_baddress0_we;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+wire csrbank2_dfii_pi1_wrdata3_re;
+wire [7:0] csrbank2_dfii_pi1_wrdata3_r;
+wire csrbank2_dfii_pi1_wrdata3_we;
+wire [7:0] csrbank2_dfii_pi1_wrdata3_w;
+wire csrbank2_dfii_pi1_wrdata2_re;
+wire [7:0] csrbank2_dfii_pi1_wrdata2_r;
+wire csrbank2_dfii_pi1_wrdata2_we;
+wire [7:0] csrbank2_dfii_pi1_wrdata2_w;
+wire csrbank2_dfii_pi1_wrdata1_re;
+wire [7:0] csrbank2_dfii_pi1_wrdata1_r;
+wire csrbank2_dfii_pi1_wrdata1_we;
+wire [7:0] csrbank2_dfii_pi1_wrdata1_w;
+wire csrbank2_dfii_pi1_wrdata0_re;
+wire [7:0] csrbank2_dfii_pi1_wrdata0_r;
+wire csrbank2_dfii_pi1_wrdata0_we;
+wire [7:0] csrbank2_dfii_pi1_wrdata0_w;
+wire csrbank2_dfii_pi1_rddata3_re;
+wire [7:0] csrbank2_dfii_pi1_rddata3_r;
+wire csrbank2_dfii_pi1_rddata3_we;
+wire [7:0] csrbank2_dfii_pi1_rddata3_w;
+wire csrbank2_dfii_pi1_rddata2_re;
+wire [7:0] csrbank2_dfii_pi1_rddata2_r;
+wire csrbank2_dfii_pi1_rddata2_we;
+wire [7:0] csrbank2_dfii_pi1_rddata2_w;
+wire csrbank2_dfii_pi1_rddata1_re;
+wire [7:0] csrbank2_dfii_pi1_rddata1_r;
+wire csrbank2_dfii_pi1_rddata1_we;
+wire [7:0] csrbank2_dfii_pi1_rddata1_w;
+wire csrbank2_dfii_pi1_rddata0_re;
+wire [7:0] csrbank2_dfii_pi1_rddata0_r;
+wire csrbank2_dfii_pi1_rddata0_we;
+wire [7:0] csrbank2_dfii_pi1_rddata0_w;
+wire csrbank2_dfii_pi2_command0_re;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+wire csrbank2_dfii_pi2_command0_we;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+wire csrbank2_dfii_pi2_address1_re;
+wire [5:0] csrbank2_dfii_pi2_address1_r;
+wire csrbank2_dfii_pi2_address1_we;
+wire [5:0] csrbank2_dfii_pi2_address1_w;
+wire csrbank2_dfii_pi2_address0_re;
+wire [7:0] csrbank2_dfii_pi2_address0_r;
+wire csrbank2_dfii_pi2_address0_we;
+wire [7:0] csrbank2_dfii_pi2_address0_w;
+wire csrbank2_dfii_pi2_baddress0_re;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+wire csrbank2_dfii_pi2_baddress0_we;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+wire csrbank2_dfii_pi2_wrdata3_re;
+wire [7:0] csrbank2_dfii_pi2_wrdata3_r;
+wire csrbank2_dfii_pi2_wrdata3_we;
+wire [7:0] csrbank2_dfii_pi2_wrdata3_w;
+wire csrbank2_dfii_pi2_wrdata2_re;
+wire [7:0] csrbank2_dfii_pi2_wrdata2_r;
+wire csrbank2_dfii_pi2_wrdata2_we;
+wire [7:0] csrbank2_dfii_pi2_wrdata2_w;
+wire csrbank2_dfii_pi2_wrdata1_re;
+wire [7:0] csrbank2_dfii_pi2_wrdata1_r;
+wire csrbank2_dfii_pi2_wrdata1_we;
+wire [7:0] csrbank2_dfii_pi2_wrdata1_w;
+wire csrbank2_dfii_pi2_wrdata0_re;
+wire [7:0] csrbank2_dfii_pi2_wrdata0_r;
+wire csrbank2_dfii_pi2_wrdata0_we;
+wire [7:0] csrbank2_dfii_pi2_wrdata0_w;
+wire csrbank2_dfii_pi2_rddata3_re;
+wire [7:0] csrbank2_dfii_pi2_rddata3_r;
+wire csrbank2_dfii_pi2_rddata3_we;
+wire [7:0] csrbank2_dfii_pi2_rddata3_w;
+wire csrbank2_dfii_pi2_rddata2_re;
+wire [7:0] csrbank2_dfii_pi2_rddata2_r;
+wire csrbank2_dfii_pi2_rddata2_we;
+wire [7:0] csrbank2_dfii_pi2_rddata2_w;
+wire csrbank2_dfii_pi2_rddata1_re;
+wire [7:0] csrbank2_dfii_pi2_rddata1_r;
+wire csrbank2_dfii_pi2_rddata1_we;
+wire [7:0] csrbank2_dfii_pi2_rddata1_w;
+wire csrbank2_dfii_pi2_rddata0_re;
+wire [7:0] csrbank2_dfii_pi2_rddata0_r;
+wire csrbank2_dfii_pi2_rddata0_we;
+wire [7:0] csrbank2_dfii_pi2_rddata0_w;
+wire csrbank2_dfii_pi3_command0_re;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+wire csrbank2_dfii_pi3_command0_we;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+wire csrbank2_dfii_pi3_address1_re;
+wire [5:0] csrbank2_dfii_pi3_address1_r;
+wire csrbank2_dfii_pi3_address1_we;
+wire [5:0] csrbank2_dfii_pi3_address1_w;
+wire csrbank2_dfii_pi3_address0_re;
+wire [7:0] csrbank2_dfii_pi3_address0_r;
+wire csrbank2_dfii_pi3_address0_we;
+wire [7:0] csrbank2_dfii_pi3_address0_w;
+wire csrbank2_dfii_pi3_baddress0_re;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+wire csrbank2_dfii_pi3_baddress0_we;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+wire csrbank2_dfii_pi3_wrdata3_re;
+wire [7:0] csrbank2_dfii_pi3_wrdata3_r;
+wire csrbank2_dfii_pi3_wrdata3_we;
+wire [7:0] csrbank2_dfii_pi3_wrdata3_w;
+wire csrbank2_dfii_pi3_wrdata2_re;
+wire [7:0] csrbank2_dfii_pi3_wrdata2_r;
+wire csrbank2_dfii_pi3_wrdata2_we;
+wire [7:0] csrbank2_dfii_pi3_wrdata2_w;
+wire csrbank2_dfii_pi3_wrdata1_re;
+wire [7:0] csrbank2_dfii_pi3_wrdata1_r;
+wire csrbank2_dfii_pi3_wrdata1_we;
+wire [7:0] csrbank2_dfii_pi3_wrdata1_w;
+wire csrbank2_dfii_pi3_wrdata0_re;
+wire [7:0] csrbank2_dfii_pi3_wrdata0_r;
+wire csrbank2_dfii_pi3_wrdata0_we;
+wire [7:0] csrbank2_dfii_pi3_wrdata0_w;
+wire csrbank2_dfii_pi3_rddata3_re;
+wire [7:0] csrbank2_dfii_pi3_rddata3_r;
+wire csrbank2_dfii_pi3_rddata3_we;
+wire [7:0] csrbank2_dfii_pi3_rddata3_w;
+wire csrbank2_dfii_pi3_rddata2_re;
+wire [7:0] csrbank2_dfii_pi3_rddata2_r;
+wire csrbank2_dfii_pi3_rddata2_we;
+wire [7:0] csrbank2_dfii_pi3_rddata2_w;
+wire csrbank2_dfii_pi3_rddata1_re;
+wire [7:0] csrbank2_dfii_pi3_rddata1_r;
+wire csrbank2_dfii_pi3_rddata1_we;
+wire [7:0] csrbank2_dfii_pi3_rddata1_w;
+wire csrbank2_dfii_pi3_rddata0_re;
+wire [7:0] csrbank2_dfii_pi3_rddata0_r;
+wire csrbank2_dfii_pi3_rddata0_we;
+wire [7:0] csrbank2_dfii_pi3_rddata0_w;
+reg csrbank2_sel = 1'd0;
+wire [13:0] adr;
+wire we;
+wire [7:0] dat_w;
+wire [7:0] dat_r;
+reg rhs_array_muxed0 = 1'd0;
+reg [13:0] rhs_array_muxed1 = 14'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [13:0] rhs_array_muxed7 = 14'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [20:0] rhs_array_muxed12 = 21'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [20:0] rhs_array_muxed15 = 21'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [20:0] rhs_array_muxed18 = 21'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [20:0] rhs_array_muxed21 = 21'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [20:0] rhs_array_muxed24 = 21'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [20:0] rhs_array_muxed27 = 21'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [20:0] rhs_array_muxed30 = 21'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [20:0] rhs_array_muxed33 = 21'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [13:0] array_muxed1 = 14'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [13:0] array_muxed8 = 14'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+reg [2:0] array_muxed14 = 3'd0;
+reg [13:0] array_muxed15 = 14'd0;
+reg array_muxed16 = 1'd0;
+reg array_muxed17 = 1'd0;
+reg array_muxed18 = 1'd0;
+reg array_muxed19 = 1'd0;
+reg array_muxed20 = 1'd0;
+reg [2:0] array_muxed21 = 3'd0;
+reg [13:0] array_muxed22 = 14'd0;
+reg array_muxed23 = 1'd0;
+reg array_muxed24 = 1'd0;
+reg array_muxed25 = 1'd0;
+reg array_muxed26 = 1'd0;
+reg array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1_expr;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
 
 // synthesis translate_off
 reg dummy_s;
 initial dummy_s <= 1'd0;
 // synthesis translate_on
-assign soc_litedramcore_cpu_reset = soc_litedramcore_soccontroller_reset;
-assign init_done = soc_init_done_storage;
-assign init_error = soc_init_error_storage;
+assign init_done = init_done_storage;
+assign init_error = init_error_storage;
+assign csr_port_adr = csr_port0_adr;
+assign csr_port_we = csr_port0_we;
+assign csr_port_dat_w = csr_port0_dat_w;
+assign csr_port0_dat_r = csr_port_dat_r;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign soc_cmd_valid = user_port_native_0_cmd_valid;
-assign user_port_native_0_cmd_ready = soc_cmd_ready;
-assign soc_cmd_payload_we = user_port_native_0_cmd_we;
-assign soc_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign soc_wdata_valid = user_port_native_0_wdata_valid;
-assign user_port_native_0_wdata_ready = soc_wdata_ready;
-assign soc_wdata_payload_we = user_port_native_0_wdata_we;
-assign soc_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = soc_rdata_valid;
-assign soc_rdata_ready = user_port_native_0_rdata_ready;
-assign user_port_native_0_rdata_data = soc_rdata_payload_data;
-assign soc_litedramcore_soccontroller_bus_error = vns_error;
+assign user_port_cmd_valid = user_port_native_0_cmd_valid;
+assign user_port_native_0_cmd_ready = user_port_cmd_ready;
+assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign user_port_wdata_valid = user_port_native_0_wdata_valid;
+assign user_port_native_0_wdata_ready = user_port_wdata_ready;
+assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = user_port_rdata_valid;
+assign user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign sys_pll_reset = rst;
+assign pll_locked = sys_pll_locked;
+assign iodelay_pll_reset = rst;
+assign s7pll0_clkin = clk;
+assign sys_clk = s7pll0_clkout_buf0;
+assign sys4x_clk = s7pll0_clkout_buf1;
+assign sys4x_dqs_clk = s7pll0_clkout_buf2;
+assign s7pll1_clkin = clk;
+assign iodelay_clk = s7pll1_clkout_buf;
+assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0;
 
 // synthesis translate_off
 reg dummy_d;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_cpu_interrupt <= 32'd0;
-       soc_litedramcore_cpu_interrupt[1] <= soc_litedramcore_timer_irq;
-       soc_litedramcore_cpu_interrupt[0] <= soc_litedramcore_uart_irq;
+       a7ddrphy_dfi_p0_rddata <= 32'd0;
+       a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip0_o[0];
+       a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip0_o[1];
+       a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip1_o[0];
+       a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip1_o[1];
+       a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip2_o[0];
+       a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip2_o[1];
+       a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip3_o[0];
+       a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip3_o[1];
+       a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip4_o[0];
+       a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip4_o[1];
+       a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip5_o[0];
+       a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip5_o[1];
+       a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip6_o[0];
+       a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip6_o[1];
+       a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip7_o[0];
+       a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip7_o[1];
+       a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip8_o[0];
+       a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip8_o[1];
+       a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip9_o[0];
+       a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip9_o[1];
+       a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip10_o[0];
+       a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip10_o[1];
+       a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip11_o[0];
+       a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip11_o[1];
+       a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip12_o[0];
+       a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip12_o[1];
+       a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip13_o[0];
+       a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip13_o[1];
+       a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip14_o[0];
+       a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip14_o[1];
+       a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0];
+       a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1];
 // synthesis translate_off
        dummy_d = dummy_s;
 // synthesis translate_on
 end
-assign soc_litedramcore_soccontroller_reset = soc_litedramcore_soccontroller_reset_re;
-assign soc_litedramcore_soccontroller_bus_errors_status = soc_litedramcore_soccontroller_bus_errors;
-assign soc_litedramcore_litedramcore_adr = soc_litedramcore_litedramcore_ram_bus_adr[12:0];
-assign soc_litedramcore_litedramcore_ram_bus_dat_r = soc_litedramcore_litedramcore_dat_r;
 
 // synthesis translate_off
 reg dummy_d_1;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_ram_we <= 4'd0;
-       soc_litedramcore_ram_we[0] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[0]);
-       soc_litedramcore_ram_we[1] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[1]);
-       soc_litedramcore_ram_we[2] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[2]);
-       soc_litedramcore_ram_we[3] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[3]);
+       a7ddrphy_dfi_p1_rddata <= 32'd0;
+       a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip0_o[2];
+       a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip0_o[3];
+       a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip1_o[2];
+       a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip1_o[3];
+       a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip2_o[2];
+       a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip2_o[3];
+       a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip3_o[2];
+       a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip3_o[3];
+       a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip4_o[2];
+       a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip4_o[3];
+       a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip5_o[2];
+       a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip5_o[3];
+       a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip6_o[2];
+       a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip6_o[3];
+       a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip7_o[2];
+       a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip7_o[3];
+       a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip8_o[2];
+       a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip8_o[3];
+       a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip9_o[2];
+       a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip9_o[3];
+       a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip10_o[2];
+       a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip10_o[3];
+       a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip11_o[2];
+       a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip11_o[3];
+       a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip12_o[2];
+       a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip12_o[3];
+       a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip13_o[2];
+       a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip13_o[3];
+       a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip14_o[2];
+       a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip14_o[3];
+       a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2];
+       a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3];
 // synthesis translate_off
        dummy_d_1 = dummy_s;
 // synthesis translate_on
 end
-assign soc_litedramcore_ram_adr = soc_litedramcore_ram_bus_ram_bus_adr[9:0];
-assign soc_litedramcore_ram_bus_ram_bus_dat_r = soc_litedramcore_ram_dat_r;
-assign soc_litedramcore_ram_dat_w = soc_litedramcore_ram_bus_ram_bus_dat_w;
-assign soc_litedramcore_uart_uart_sink_valid = soc_litedramcore_source_valid;
-assign soc_litedramcore_source_ready = soc_litedramcore_uart_uart_sink_ready;
-assign soc_litedramcore_uart_uart_sink_first = soc_litedramcore_source_first;
-assign soc_litedramcore_uart_uart_sink_last = soc_litedramcore_source_last;
-assign soc_litedramcore_uart_uart_sink_payload_data = soc_litedramcore_source_payload_data;
-assign soc_litedramcore_sink_valid = soc_litedramcore_uart_uart_source_valid;
-assign soc_litedramcore_uart_uart_source_ready = soc_litedramcore_sink_ready;
-assign soc_litedramcore_sink_first = soc_litedramcore_uart_uart_source_first;
-assign soc_litedramcore_sink_last = soc_litedramcore_uart_uart_source_last;
-assign soc_litedramcore_sink_payload_data = soc_litedramcore_uart_uart_source_payload_data;
-assign soc_litedramcore_uart_tx_fifo_sink_valid = soc_litedramcore_uart_rxtx_re;
-assign soc_litedramcore_uart_tx_fifo_sink_payload_data = soc_litedramcore_uart_rxtx_r;
-assign soc_litedramcore_uart_txfull_status = (~soc_litedramcore_uart_tx_fifo_sink_ready);
-assign soc_litedramcore_uart_uart_source_valid = soc_litedramcore_uart_tx_fifo_source_valid;
-assign soc_litedramcore_uart_tx_fifo_source_ready = soc_litedramcore_uart_uart_source_ready;
-assign soc_litedramcore_uart_uart_source_first = soc_litedramcore_uart_tx_fifo_source_first;
-assign soc_litedramcore_uart_uart_source_last = soc_litedramcore_uart_tx_fifo_source_last;
-assign soc_litedramcore_uart_uart_source_payload_data = soc_litedramcore_uart_tx_fifo_source_payload_data;
-assign soc_litedramcore_uart_tx_trigger = (~soc_litedramcore_uart_tx_fifo_sink_ready);
-assign soc_litedramcore_uart_rx_fifo_sink_valid = soc_litedramcore_uart_uart_sink_valid;
-assign soc_litedramcore_uart_uart_sink_ready = soc_litedramcore_uart_rx_fifo_sink_ready;
-assign soc_litedramcore_uart_rx_fifo_sink_first = soc_litedramcore_uart_uart_sink_first;
-assign soc_litedramcore_uart_rx_fifo_sink_last = soc_litedramcore_uart_uart_sink_last;
-assign soc_litedramcore_uart_rx_fifo_sink_payload_data = soc_litedramcore_uart_uart_sink_payload_data;
-assign soc_litedramcore_uart_rxempty_status = (~soc_litedramcore_uart_rx_fifo_source_valid);
-assign soc_litedramcore_uart_rxtx_w = soc_litedramcore_uart_rx_fifo_source_payload_data;
-assign soc_litedramcore_uart_rx_fifo_source_ready = (soc_litedramcore_uart_rx_clear | (1'd0 & soc_litedramcore_uart_rxtx_we));
-assign soc_litedramcore_uart_rx_trigger = (~soc_litedramcore_uart_rx_fifo_source_valid);
 
 // synthesis translate_off
 reg dummy_d_2;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_uart_eventmanager_status_w <= 2'd0;
-       soc_litedramcore_uart_eventmanager_status_w[0] <= soc_litedramcore_uart_tx_status;
-       soc_litedramcore_uart_eventmanager_status_w[1] <= soc_litedramcore_uart_rx_status;
+       a7ddrphy_dfi_p2_rddata <= 32'd0;
+       a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip0_o[4];
+       a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip0_o[5];
+       a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip1_o[4];
+       a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip1_o[5];
+       a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip2_o[4];
+       a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip2_o[5];
+       a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip3_o[4];
+       a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip3_o[5];
+       a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip4_o[4];
+       a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip4_o[5];
+       a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip5_o[4];
+       a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip5_o[5];
+       a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip6_o[4];
+       a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip6_o[5];
+       a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip7_o[4];
+       a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip7_o[5];
+       a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip8_o[4];
+       a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip8_o[5];
+       a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip9_o[4];
+       a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip9_o[5];
+       a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip10_o[4];
+       a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip10_o[5];
+       a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip11_o[4];
+       a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip11_o[5];
+       a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip12_o[4];
+       a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip12_o[5];
+       a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip13_o[4];
+       a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip13_o[5];
+       a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip14_o[4];
+       a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip14_o[5];
+       a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4];
+       a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5];
 // synthesis translate_off
        dummy_d_2 = dummy_s;
 // synthesis translate_on
@@ -2562,1302 +2044,1144 @@ end
 reg dummy_d_3;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_uart_tx_clear <= 1'd0;
-       if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[0])) begin
-               soc_litedramcore_uart_tx_clear <= 1'd1;
-       end
+       a7ddrphy_dfi_p3_rddata <= 32'd0;
+       a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip0_o[6];
+       a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip0_o[7];
+       a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip1_o[6];
+       a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip1_o[7];
+       a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip2_o[6];
+       a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip2_o[7];
+       a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip3_o[6];
+       a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip3_o[7];
+       a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip4_o[6];
+       a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip4_o[7];
+       a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip5_o[6];
+       a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip5_o[7];
+       a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip6_o[6];
+       a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip6_o[7];
+       a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip7_o[6];
+       a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip7_o[7];
+       a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip8_o[6];
+       a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip8_o[7];
+       a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip9_o[6];
+       a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip9_o[7];
+       a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip10_o[6];
+       a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip10_o[7];
+       a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip11_o[6];
+       a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip11_o[7];
+       a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip12_o[6];
+       a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip12_o[7];
+       a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip13_o[6];
+       a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip13_o[7];
+       a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip14_o[6];
+       a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip14_o[7];
+       a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6];
+       a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7];
 // synthesis translate_off
        dummy_d_3 = dummy_s;
 // synthesis translate_on
 end
+assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1;
+assign a7ddrphy_bitslip2_i = a7ddrphy_dq_i_data2;
+assign a7ddrphy_bitslip3_i = a7ddrphy_dq_i_data3;
+assign a7ddrphy_bitslip4_i = a7ddrphy_dq_i_data4;
+assign a7ddrphy_bitslip5_i = a7ddrphy_dq_i_data5;
+assign a7ddrphy_bitslip6_i = a7ddrphy_dq_i_data6;
+assign a7ddrphy_bitslip7_i = a7ddrphy_dq_i_data7;
+assign a7ddrphy_bitslip8_i = a7ddrphy_dq_i_data8;
+assign a7ddrphy_bitslip9_i = a7ddrphy_dq_i_data9;
+assign a7ddrphy_bitslip10_i = a7ddrphy_dq_i_data10;
+assign a7ddrphy_bitslip11_i = a7ddrphy_dq_i_data11;
+assign a7ddrphy_bitslip12_i = a7ddrphy_dq_i_data12;
+assign a7ddrphy_bitslip13_i = a7ddrphy_dq_i_data13;
+assign a7ddrphy_bitslip14_i = a7ddrphy_dq_i_data14;
+assign a7ddrphy_bitslip15_i = a7ddrphy_dq_i_data15;
+assign a7ddrphy_rddata_en = {a7ddrphy_rddata_en_last, a7ddrphy_dfi_p2_rddata_en};
+assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en};
+assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2];
 
 // synthesis translate_off
 reg dummy_d_4;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_uart_eventmanager_pending_w <= 2'd0;
-       soc_litedramcore_uart_eventmanager_pending_w[0] <= soc_litedramcore_uart_tx_pending;
-       soc_litedramcore_uart_eventmanager_pending_w[1] <= soc_litedramcore_uart_rx_pending;
-// synthesis translate_off
-       dummy_d_4 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_5;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_uart_rx_clear <= 1'd0;
-       if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[1])) begin
-               soc_litedramcore_uart_rx_clear <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_5 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_uart_irq = ((soc_litedramcore_uart_eventmanager_pending_w[0] & soc_litedramcore_uart_eventmanager_storage[0]) | (soc_litedramcore_uart_eventmanager_pending_w[1] & soc_litedramcore_uart_eventmanager_storage[1]));
-assign soc_litedramcore_uart_tx_status = soc_litedramcore_uart_tx_trigger;
-assign soc_litedramcore_uart_rx_status = soc_litedramcore_uart_rx_trigger;
-assign soc_litedramcore_uart_tx_fifo_syncfifo_din = {soc_litedramcore_uart_tx_fifo_fifo_in_last, soc_litedramcore_uart_tx_fifo_fifo_in_first, soc_litedramcore_uart_tx_fifo_fifo_in_payload_data};
-assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
-assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
-assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
-assign soc_litedramcore_uart_tx_fifo_sink_ready = soc_litedramcore_uart_tx_fifo_syncfifo_writable;
-assign soc_litedramcore_uart_tx_fifo_syncfifo_we = soc_litedramcore_uart_tx_fifo_sink_valid;
-assign soc_litedramcore_uart_tx_fifo_fifo_in_first = soc_litedramcore_uart_tx_fifo_sink_first;
-assign soc_litedramcore_uart_tx_fifo_fifo_in_last = soc_litedramcore_uart_tx_fifo_sink_last;
-assign soc_litedramcore_uart_tx_fifo_fifo_in_payload_data = soc_litedramcore_uart_tx_fifo_sink_payload_data;
-assign soc_litedramcore_uart_tx_fifo_source_valid = soc_litedramcore_uart_tx_fifo_readable;
-assign soc_litedramcore_uart_tx_fifo_source_first = soc_litedramcore_uart_tx_fifo_fifo_out_first;
-assign soc_litedramcore_uart_tx_fifo_source_last = soc_litedramcore_uart_tx_fifo_fifo_out_last;
-assign soc_litedramcore_uart_tx_fifo_source_payload_data = soc_litedramcore_uart_tx_fifo_fifo_out_payload_data;
-assign soc_litedramcore_uart_tx_fifo_re = soc_litedramcore_uart_tx_fifo_source_ready;
-assign soc_litedramcore_uart_tx_fifo_syncfifo_re = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_tx_fifo_readable) | soc_litedramcore_uart_tx_fifo_re));
-assign soc_litedramcore_uart_tx_fifo_level1 = (soc_litedramcore_uart_tx_fifo_level0 + soc_litedramcore_uart_tx_fifo_readable);
-
-// synthesis translate_off
-reg dummy_d_6;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_uart_tx_fifo_wrport_adr <= 4'd0;
-       if (soc_litedramcore_uart_tx_fifo_replace) begin
-               soc_litedramcore_uart_tx_fifo_wrport_adr <= (soc_litedramcore_uart_tx_fifo_produce - 1'd1);
-       end else begin
-               soc_litedramcore_uart_tx_fifo_wrport_adr <= soc_litedramcore_uart_tx_fifo_produce;
-       end
-// synthesis translate_off
-       dummy_d_6 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_uart_tx_fifo_wrport_dat_w = soc_litedramcore_uart_tx_fifo_syncfifo_din;
-assign soc_litedramcore_uart_tx_fifo_wrport_we = (soc_litedramcore_uart_tx_fifo_syncfifo_we & (soc_litedramcore_uart_tx_fifo_syncfifo_writable | soc_litedramcore_uart_tx_fifo_replace));
-assign soc_litedramcore_uart_tx_fifo_do_read = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & soc_litedramcore_uart_tx_fifo_syncfifo_re);
-assign soc_litedramcore_uart_tx_fifo_rdport_adr = soc_litedramcore_uart_tx_fifo_consume;
-assign soc_litedramcore_uart_tx_fifo_syncfifo_dout = soc_litedramcore_uart_tx_fifo_rdport_dat_r;
-assign soc_litedramcore_uart_tx_fifo_rdport_re = soc_litedramcore_uart_tx_fifo_do_read;
-assign soc_litedramcore_uart_tx_fifo_syncfifo_writable = (soc_litedramcore_uart_tx_fifo_level0 != 5'd16);
-assign soc_litedramcore_uart_tx_fifo_syncfifo_readable = (soc_litedramcore_uart_tx_fifo_level0 != 1'd0);
-assign soc_litedramcore_uart_rx_fifo_syncfifo_din = {soc_litedramcore_uart_rx_fifo_fifo_in_last, soc_litedramcore_uart_rx_fifo_fifo_in_first, soc_litedramcore_uart_rx_fifo_fifo_in_payload_data};
-assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
-assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
-assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
-assign soc_litedramcore_uart_rx_fifo_sink_ready = soc_litedramcore_uart_rx_fifo_syncfifo_writable;
-assign soc_litedramcore_uart_rx_fifo_syncfifo_we = soc_litedramcore_uart_rx_fifo_sink_valid;
-assign soc_litedramcore_uart_rx_fifo_fifo_in_first = soc_litedramcore_uart_rx_fifo_sink_first;
-assign soc_litedramcore_uart_rx_fifo_fifo_in_last = soc_litedramcore_uart_rx_fifo_sink_last;
-assign soc_litedramcore_uart_rx_fifo_fifo_in_payload_data = soc_litedramcore_uart_rx_fifo_sink_payload_data;
-assign soc_litedramcore_uart_rx_fifo_source_valid = soc_litedramcore_uart_rx_fifo_readable;
-assign soc_litedramcore_uart_rx_fifo_source_first = soc_litedramcore_uart_rx_fifo_fifo_out_first;
-assign soc_litedramcore_uart_rx_fifo_source_last = soc_litedramcore_uart_rx_fifo_fifo_out_last;
-assign soc_litedramcore_uart_rx_fifo_source_payload_data = soc_litedramcore_uart_rx_fifo_fifo_out_payload_data;
-assign soc_litedramcore_uart_rx_fifo_re = soc_litedramcore_uart_rx_fifo_source_ready;
-assign soc_litedramcore_uart_rx_fifo_syncfifo_re = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_rx_fifo_readable) | soc_litedramcore_uart_rx_fifo_re));
-assign soc_litedramcore_uart_rx_fifo_level1 = (soc_litedramcore_uart_rx_fifo_level0 + soc_litedramcore_uart_rx_fifo_readable);
-
-// synthesis translate_off
-reg dummy_d_7;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_uart_rx_fifo_wrport_adr <= 4'd0;
-       if (soc_litedramcore_uart_rx_fifo_replace) begin
-               soc_litedramcore_uart_rx_fifo_wrport_adr <= (soc_litedramcore_uart_rx_fifo_produce - 1'd1);
-       end else begin
-               soc_litedramcore_uart_rx_fifo_wrport_adr <= soc_litedramcore_uart_rx_fifo_produce;
-       end
-// synthesis translate_off
-       dummy_d_7 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_uart_rx_fifo_wrport_dat_w = soc_litedramcore_uart_rx_fifo_syncfifo_din;
-assign soc_litedramcore_uart_rx_fifo_wrport_we = (soc_litedramcore_uart_rx_fifo_syncfifo_we & (soc_litedramcore_uart_rx_fifo_syncfifo_writable | soc_litedramcore_uart_rx_fifo_replace));
-assign soc_litedramcore_uart_rx_fifo_do_read = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & soc_litedramcore_uart_rx_fifo_syncfifo_re);
-assign soc_litedramcore_uart_rx_fifo_rdport_adr = soc_litedramcore_uart_rx_fifo_consume;
-assign soc_litedramcore_uart_rx_fifo_syncfifo_dout = soc_litedramcore_uart_rx_fifo_rdport_dat_r;
-assign soc_litedramcore_uart_rx_fifo_rdport_re = soc_litedramcore_uart_rx_fifo_do_read;
-assign soc_litedramcore_uart_rx_fifo_syncfifo_writable = (soc_litedramcore_uart_rx_fifo_level0 != 5'd16);
-assign soc_litedramcore_uart_rx_fifo_syncfifo_readable = (soc_litedramcore_uart_rx_fifo_level0 != 1'd0);
-assign soc_litedramcore_timer_zero_trigger = (soc_litedramcore_timer_value != 1'd0);
-assign soc_litedramcore_timer_eventmanager_status_w = soc_litedramcore_timer_zero_status;
-
-// synthesis translate_off
-reg dummy_d_8;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_timer_zero_clear <= 1'd0;
-       if ((soc_litedramcore_timer_eventmanager_pending_re & soc_litedramcore_timer_eventmanager_pending_r)) begin
-               soc_litedramcore_timer_zero_clear <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_8 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_timer_eventmanager_pending_w = soc_litedramcore_timer_zero_pending;
-assign soc_litedramcore_timer_irq = (soc_litedramcore_timer_eventmanager_pending_w & soc_litedramcore_timer_eventmanager_storage);
-assign soc_litedramcore_timer_zero_status = soc_litedramcore_timer_zero_trigger;
-assign soc_litedramcore_interface_dat_w = soc_litedramcore_bus_wishbone_dat_w;
-assign soc_litedramcore_bus_wishbone_dat_r = soc_litedramcore_interface_dat_r;
-
-// synthesis translate_off
-reg dummy_d_9;
-// synthesis translate_on
-always @(*) begin
-       vns_wb2csr_next_state <= 1'd0;
-       vns_wb2csr_next_state <= vns_wb2csr_state;
-       case (vns_wb2csr_state)
-               1'd1: begin
-                       vns_wb2csr_next_state <= 1'd0;
-               end
-               default: begin
-                       if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
-                               vns_wb2csr_next_state <= 1'd1;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_9 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_10;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_interface_we <= 1'd0;
-       case (vns_wb2csr_state)
-               1'd1: begin
-               end
-               default: begin
-                       if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
-                               soc_litedramcore_interface_we <= soc_litedramcore_bus_wishbone_we;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_10 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_11;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_bus_wishbone_ack <= 1'd0;
-       case (vns_wb2csr_state)
-               1'd1: begin
-                       soc_litedramcore_bus_wishbone_ack <= 1'd1;
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_11 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_12;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_interface_adr <= 14'd0;
-       case (vns_wb2csr_state)
-               1'd1: begin
-               end
-               default: begin
-                       if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
-                               soc_litedramcore_interface_adr <= soc_litedramcore_bus_wishbone_adr;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_12 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sys_pll_reset = rst;
-assign pll_locked = soc_sys_pll_locked;
-assign soc_iodelay_pll_reset = rst;
-assign soc_s7pll0_clkin = clk;
-assign sys_clk = soc_s7pll0_clkout_buf0;
-assign sys4x_clk = soc_s7pll0_clkout_buf1;
-assign sys4x_dqs_clk = soc_s7pll0_clkout_buf2;
-assign soc_s7pll1_clkin = clk;
-assign iodelay_clk = soc_s7pll1_clkout_buf;
-assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0;
-
-// synthesis translate_off
-reg dummy_d_13;
-// synthesis translate_on
-always @(*) begin
-       soc_a7ddrphy_dfi_p0_rddata <= 32'd0;
-       soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1];
-// synthesis translate_off
-       dummy_d_13 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_14;
-// synthesis translate_on
-always @(*) begin
-       soc_a7ddrphy_dfi_p1_rddata <= 32'd0;
-       soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3];
-// synthesis translate_off
-       dummy_d_14 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_15;
-// synthesis translate_on
-always @(*) begin
-       soc_a7ddrphy_dfi_p2_rddata <= 32'd0;
-       soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5];
-// synthesis translate_off
-       dummy_d_15 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_16;
-// synthesis translate_on
-always @(*) begin
-       soc_a7ddrphy_dfi_p3_rddata <= 32'd0;
-       soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7];
-// synthesis translate_off
-       dummy_d_16 = dummy_s;
-// synthesis translate_on
-end
-assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1;
-assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2;
-assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3;
-assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4;
-assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5;
-assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6;
-assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7;
-assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8;
-assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9;
-assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10;
-assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11;
-assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12;
-assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13;
-assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14;
-assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15;
-assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en};
-assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en};
-assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2];
-
-// synthesis translate_off
-reg dummy_d_17;
-// synthesis translate_on
-always @(*) begin
-       soc_a7ddrphy_dqs_oe <= 1'd0;
-       if (soc_a7ddrphy_wlevel_en_storage) begin
-               soc_a7ddrphy_dqs_oe <= 1'd1;
+       a7ddrphy_dqs_oe <= 1'd0;
+       if (a7ddrphy_wlevel_en_storage) begin
+               a7ddrphy_dqs_oe <= 1'd1;
        end else begin
-               soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe;
+               a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
        end
 // synthesis translate_off
-       dummy_d_17 = dummy_s;
+       dummy_d_4 = dummy_s;
 // synthesis translate_on
 end
-assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2]));
-assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2]));
+assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2]));
+assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2]));
 
 // synthesis translate_off
-reg dummy_d_18;
+reg dummy_d_5;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_dqspattern_o0 <= 8'd0;
-       soc_a7ddrphy_dqspattern_o0 <= 7'd85;
-       if (soc_a7ddrphy_dqspattern0) begin
-               soc_a7ddrphy_dqspattern_o0 <= 5'd21;
+       a7ddrphy_dqspattern_o0 <= 8'd0;
+       a7ddrphy_dqspattern_o0 <= 7'd85;
+       if (a7ddrphy_dqspattern0) begin
+               a7ddrphy_dqspattern_o0 <= 5'd21;
        end
-       if (soc_a7ddrphy_dqspattern1) begin
-               soc_a7ddrphy_dqspattern_o0 <= 7'd84;
+       if (a7ddrphy_dqspattern1) begin
+               a7ddrphy_dqspattern_o0 <= 7'd84;
        end
-       if (soc_a7ddrphy_wlevel_en_storage) begin
-               soc_a7ddrphy_dqspattern_o0 <= 1'd0;
-               if (soc_a7ddrphy_wlevel_strobe_re) begin
-                       soc_a7ddrphy_dqspattern_o0 <= 1'd1;
+       if (a7ddrphy_wlevel_en_storage) begin
+               a7ddrphy_dqspattern_o0 <= 1'd0;
+               if (a7ddrphy_wlevel_strobe_re) begin
+                       a7ddrphy_dqspattern_o0 <= 1'd1;
                end
        end
 // synthesis translate_off
-       dummy_d_18 = dummy_s;
+       dummy_d_5 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_19;
+reg dummy_d_6;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip0_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip0_value)
+       a7ddrphy_bitslip0_o <= 8'd0;
+       case (a7ddrphy_bitslip0_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_19 = dummy_s;
+       dummy_d_6 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_20;
+reg dummy_d_7;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip1_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip1_value)
+       a7ddrphy_bitslip1_o <= 8'd0;
+       case (a7ddrphy_bitslip1_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_20 = dummy_s;
+       dummy_d_7 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_21;
+reg dummy_d_8;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip2_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip2_value)
+       a7ddrphy_bitslip2_o <= 8'd0;
+       case (a7ddrphy_bitslip2_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_21 = dummy_s;
+       dummy_d_8 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_22;
+reg dummy_d_9;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip3_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip3_value)
+       a7ddrphy_bitslip3_o <= 8'd0;
+       case (a7ddrphy_bitslip3_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_22 = dummy_s;
+       dummy_d_9 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_23;
+reg dummy_d_10;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip4_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip4_value)
+       a7ddrphy_bitslip4_o <= 8'd0;
+       case (a7ddrphy_bitslip4_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_23 = dummy_s;
+       dummy_d_10 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_24;
+reg dummy_d_11;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip5_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip5_value)
+       a7ddrphy_bitslip5_o <= 8'd0;
+       case (a7ddrphy_bitslip5_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_24 = dummy_s;
+       dummy_d_11 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_25;
+reg dummy_d_12;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip6_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip6_value)
+       a7ddrphy_bitslip6_o <= 8'd0;
+       case (a7ddrphy_bitslip6_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_25 = dummy_s;
+       dummy_d_12 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_26;
+reg dummy_d_13;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip7_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip7_value)
+       a7ddrphy_bitslip7_o <= 8'd0;
+       case (a7ddrphy_bitslip7_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_26 = dummy_s;
+       dummy_d_13 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_27;
+reg dummy_d_14;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip8_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip8_value)
+       a7ddrphy_bitslip8_o <= 8'd0;
+       case (a7ddrphy_bitslip8_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_27 = dummy_s;
+       dummy_d_14 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_28;
+reg dummy_d_15;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip9_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip9_value)
+       a7ddrphy_bitslip9_o <= 8'd0;
+       case (a7ddrphy_bitslip9_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_28 = dummy_s;
+       dummy_d_15 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_29;
+reg dummy_d_16;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip10_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip10_value)
+       a7ddrphy_bitslip10_o <= 8'd0;
+       case (a7ddrphy_bitslip10_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_29 = dummy_s;
+       dummy_d_16 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_30;
+reg dummy_d_17;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip11_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip11_value)
+       a7ddrphy_bitslip11_o <= 8'd0;
+       case (a7ddrphy_bitslip11_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_30 = dummy_s;
+       dummy_d_17 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_31;
+reg dummy_d_18;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip12_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip12_value)
+       a7ddrphy_bitslip12_o <= 8'd0;
+       case (a7ddrphy_bitslip12_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_31 = dummy_s;
+       dummy_d_18 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_32;
+reg dummy_d_19;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip13_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip13_value)
+       a7ddrphy_bitslip13_o <= 8'd0;
+       case (a7ddrphy_bitslip13_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_32 = dummy_s;
+       dummy_d_19 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_33;
+reg dummy_d_20;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip14_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip14_value)
+       a7ddrphy_bitslip14_o <= 8'd0;
+       case (a7ddrphy_bitslip14_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_33 = dummy_s;
+       dummy_d_20 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_34;
+reg dummy_d_21;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip15_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip15_value)
+       a7ddrphy_bitslip15_o <= 8'd0;
+       case (a7ddrphy_bitslip15_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_34 = dummy_s;
+       dummy_d_21 = dummy_s;
 // synthesis translate_on
 end
-assign soc_a7ddrphy_dfi_p0_address = soc_sdram_master_p0_address;
-assign soc_a7ddrphy_dfi_p0_bank = soc_sdram_master_p0_bank;
-assign soc_a7ddrphy_dfi_p0_cas_n = soc_sdram_master_p0_cas_n;
-assign soc_a7ddrphy_dfi_p0_cs_n = soc_sdram_master_p0_cs_n;
-assign soc_a7ddrphy_dfi_p0_ras_n = soc_sdram_master_p0_ras_n;
-assign soc_a7ddrphy_dfi_p0_we_n = soc_sdram_master_p0_we_n;
-assign soc_a7ddrphy_dfi_p0_cke = soc_sdram_master_p0_cke;
-assign soc_a7ddrphy_dfi_p0_odt = soc_sdram_master_p0_odt;
-assign soc_a7ddrphy_dfi_p0_reset_n = soc_sdram_master_p0_reset_n;
-assign soc_a7ddrphy_dfi_p0_act_n = soc_sdram_master_p0_act_n;
-assign soc_a7ddrphy_dfi_p0_wrdata = soc_sdram_master_p0_wrdata;
-assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_sdram_master_p0_wrdata_en;
-assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_sdram_master_p0_wrdata_mask;
-assign soc_a7ddrphy_dfi_p0_rddata_en = soc_sdram_master_p0_rddata_en;
-assign soc_sdram_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata;
-assign soc_sdram_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid;
-assign soc_a7ddrphy_dfi_p1_address = soc_sdram_master_p1_address;
-assign soc_a7ddrphy_dfi_p1_bank = soc_sdram_master_p1_bank;
-assign soc_a7ddrphy_dfi_p1_cas_n = soc_sdram_master_p1_cas_n;
-assign soc_a7ddrphy_dfi_p1_cs_n = soc_sdram_master_p1_cs_n;
-assign soc_a7ddrphy_dfi_p1_ras_n = soc_sdram_master_p1_ras_n;
-assign soc_a7ddrphy_dfi_p1_we_n = soc_sdram_master_p1_we_n;
-assign soc_a7ddrphy_dfi_p1_cke = soc_sdram_master_p1_cke;
-assign soc_a7ddrphy_dfi_p1_odt = soc_sdram_master_p1_odt;
-assign soc_a7ddrphy_dfi_p1_reset_n = soc_sdram_master_p1_reset_n;
-assign soc_a7ddrphy_dfi_p1_act_n = soc_sdram_master_p1_act_n;
-assign soc_a7ddrphy_dfi_p1_wrdata = soc_sdram_master_p1_wrdata;
-assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_sdram_master_p1_wrdata_en;
-assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_sdram_master_p1_wrdata_mask;
-assign soc_a7ddrphy_dfi_p1_rddata_en = soc_sdram_master_p1_rddata_en;
-assign soc_sdram_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata;
-assign soc_sdram_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid;
-assign soc_a7ddrphy_dfi_p2_address = soc_sdram_master_p2_address;
-assign soc_a7ddrphy_dfi_p2_bank = soc_sdram_master_p2_bank;
-assign soc_a7ddrphy_dfi_p2_cas_n = soc_sdram_master_p2_cas_n;
-assign soc_a7ddrphy_dfi_p2_cs_n = soc_sdram_master_p2_cs_n;
-assign soc_a7ddrphy_dfi_p2_ras_n = soc_sdram_master_p2_ras_n;
-assign soc_a7ddrphy_dfi_p2_we_n = soc_sdram_master_p2_we_n;
-assign soc_a7ddrphy_dfi_p2_cke = soc_sdram_master_p2_cke;
-assign soc_a7ddrphy_dfi_p2_odt = soc_sdram_master_p2_odt;
-assign soc_a7ddrphy_dfi_p2_reset_n = soc_sdram_master_p2_reset_n;
-assign soc_a7ddrphy_dfi_p2_act_n = soc_sdram_master_p2_act_n;
-assign soc_a7ddrphy_dfi_p2_wrdata = soc_sdram_master_p2_wrdata;
-assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_sdram_master_p2_wrdata_en;
-assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_sdram_master_p2_wrdata_mask;
-assign soc_a7ddrphy_dfi_p2_rddata_en = soc_sdram_master_p2_rddata_en;
-assign soc_sdram_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata;
-assign soc_sdram_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid;
-assign soc_a7ddrphy_dfi_p3_address = soc_sdram_master_p3_address;
-assign soc_a7ddrphy_dfi_p3_bank = soc_sdram_master_p3_bank;
-assign soc_a7ddrphy_dfi_p3_cas_n = soc_sdram_master_p3_cas_n;
-assign soc_a7ddrphy_dfi_p3_cs_n = soc_sdram_master_p3_cs_n;
-assign soc_a7ddrphy_dfi_p3_ras_n = soc_sdram_master_p3_ras_n;
-assign soc_a7ddrphy_dfi_p3_we_n = soc_sdram_master_p3_we_n;
-assign soc_a7ddrphy_dfi_p3_cke = soc_sdram_master_p3_cke;
-assign soc_a7ddrphy_dfi_p3_odt = soc_sdram_master_p3_odt;
-assign soc_a7ddrphy_dfi_p3_reset_n = soc_sdram_master_p3_reset_n;
-assign soc_a7ddrphy_dfi_p3_act_n = soc_sdram_master_p3_act_n;
-assign soc_a7ddrphy_dfi_p3_wrdata = soc_sdram_master_p3_wrdata;
-assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_sdram_master_p3_wrdata_en;
-assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_sdram_master_p3_wrdata_mask;
-assign soc_a7ddrphy_dfi_p3_rddata_en = soc_sdram_master_p3_rddata_en;
-assign soc_sdram_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata;
-assign soc_sdram_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid;
-assign soc_sdram_slave_p0_address = soc_sdram_dfi_p0_address;
-assign soc_sdram_slave_p0_bank = soc_sdram_dfi_p0_bank;
-assign soc_sdram_slave_p0_cas_n = soc_sdram_dfi_p0_cas_n;
-assign soc_sdram_slave_p0_cs_n = soc_sdram_dfi_p0_cs_n;
-assign soc_sdram_slave_p0_ras_n = soc_sdram_dfi_p0_ras_n;
-assign soc_sdram_slave_p0_we_n = soc_sdram_dfi_p0_we_n;
-assign soc_sdram_slave_p0_cke = soc_sdram_dfi_p0_cke;
-assign soc_sdram_slave_p0_odt = soc_sdram_dfi_p0_odt;
-assign soc_sdram_slave_p0_reset_n = soc_sdram_dfi_p0_reset_n;
-assign soc_sdram_slave_p0_act_n = soc_sdram_dfi_p0_act_n;
-assign soc_sdram_slave_p0_wrdata = soc_sdram_dfi_p0_wrdata;
-assign soc_sdram_slave_p0_wrdata_en = soc_sdram_dfi_p0_wrdata_en;
-assign soc_sdram_slave_p0_wrdata_mask = soc_sdram_dfi_p0_wrdata_mask;
-assign soc_sdram_slave_p0_rddata_en = soc_sdram_dfi_p0_rddata_en;
-assign soc_sdram_dfi_p0_rddata = soc_sdram_slave_p0_rddata;
-assign soc_sdram_dfi_p0_rddata_valid = soc_sdram_slave_p0_rddata_valid;
-assign soc_sdram_slave_p1_address = soc_sdram_dfi_p1_address;
-assign soc_sdram_slave_p1_bank = soc_sdram_dfi_p1_bank;
-assign soc_sdram_slave_p1_cas_n = soc_sdram_dfi_p1_cas_n;
-assign soc_sdram_slave_p1_cs_n = soc_sdram_dfi_p1_cs_n;
-assign soc_sdram_slave_p1_ras_n = soc_sdram_dfi_p1_ras_n;
-assign soc_sdram_slave_p1_we_n = soc_sdram_dfi_p1_we_n;
-assign soc_sdram_slave_p1_cke = soc_sdram_dfi_p1_cke;
-assign soc_sdram_slave_p1_odt = soc_sdram_dfi_p1_odt;
-assign soc_sdram_slave_p1_reset_n = soc_sdram_dfi_p1_reset_n;
-assign soc_sdram_slave_p1_act_n = soc_sdram_dfi_p1_act_n;
-assign soc_sdram_slave_p1_wrdata = soc_sdram_dfi_p1_wrdata;
-assign soc_sdram_slave_p1_wrdata_en = soc_sdram_dfi_p1_wrdata_en;
-assign soc_sdram_slave_p1_wrdata_mask = soc_sdram_dfi_p1_wrdata_mask;
-assign soc_sdram_slave_p1_rddata_en = soc_sdram_dfi_p1_rddata_en;
-assign soc_sdram_dfi_p1_rddata = soc_sdram_slave_p1_rddata;
-assign soc_sdram_dfi_p1_rddata_valid = soc_sdram_slave_p1_rddata_valid;
-assign soc_sdram_slave_p2_address = soc_sdram_dfi_p2_address;
-assign soc_sdram_slave_p2_bank = soc_sdram_dfi_p2_bank;
-assign soc_sdram_slave_p2_cas_n = soc_sdram_dfi_p2_cas_n;
-assign soc_sdram_slave_p2_cs_n = soc_sdram_dfi_p2_cs_n;
-assign soc_sdram_slave_p2_ras_n = soc_sdram_dfi_p2_ras_n;
-assign soc_sdram_slave_p2_we_n = soc_sdram_dfi_p2_we_n;
-assign soc_sdram_slave_p2_cke = soc_sdram_dfi_p2_cke;
-assign soc_sdram_slave_p2_odt = soc_sdram_dfi_p2_odt;
-assign soc_sdram_slave_p2_reset_n = soc_sdram_dfi_p2_reset_n;
-assign soc_sdram_slave_p2_act_n = soc_sdram_dfi_p2_act_n;
-assign soc_sdram_slave_p2_wrdata = soc_sdram_dfi_p2_wrdata;
-assign soc_sdram_slave_p2_wrdata_en = soc_sdram_dfi_p2_wrdata_en;
-assign soc_sdram_slave_p2_wrdata_mask = soc_sdram_dfi_p2_wrdata_mask;
-assign soc_sdram_slave_p2_rddata_en = soc_sdram_dfi_p2_rddata_en;
-assign soc_sdram_dfi_p2_rddata = soc_sdram_slave_p2_rddata;
-assign soc_sdram_dfi_p2_rddata_valid = soc_sdram_slave_p2_rddata_valid;
-assign soc_sdram_slave_p3_address = soc_sdram_dfi_p3_address;
-assign soc_sdram_slave_p3_bank = soc_sdram_dfi_p3_bank;
-assign soc_sdram_slave_p3_cas_n = soc_sdram_dfi_p3_cas_n;
-assign soc_sdram_slave_p3_cs_n = soc_sdram_dfi_p3_cs_n;
-assign soc_sdram_slave_p3_ras_n = soc_sdram_dfi_p3_ras_n;
-assign soc_sdram_slave_p3_we_n = soc_sdram_dfi_p3_we_n;
-assign soc_sdram_slave_p3_cke = soc_sdram_dfi_p3_cke;
-assign soc_sdram_slave_p3_odt = soc_sdram_dfi_p3_odt;
-assign soc_sdram_slave_p3_reset_n = soc_sdram_dfi_p3_reset_n;
-assign soc_sdram_slave_p3_act_n = soc_sdram_dfi_p3_act_n;
-assign soc_sdram_slave_p3_wrdata = soc_sdram_dfi_p3_wrdata;
-assign soc_sdram_slave_p3_wrdata_en = soc_sdram_dfi_p3_wrdata_en;
-assign soc_sdram_slave_p3_wrdata_mask = soc_sdram_dfi_p3_wrdata_mask;
-assign soc_sdram_slave_p3_rddata_en = soc_sdram_dfi_p3_rddata_en;
-assign soc_sdram_dfi_p3_rddata = soc_sdram_slave_p3_rddata;
-assign soc_sdram_dfi_p3_rddata_valid = soc_sdram_slave_p3_rddata_valid;
+assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
+assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
+assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
+assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
+assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
+assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
+assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
+assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
+assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
+assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
+assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
+assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
+assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
+assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
+assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
+assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
+assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
+assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
+assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
+assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
+assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
+assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
+assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
+assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
+assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
+assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
+assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
+assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
+assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
+assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
+assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
+assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
+assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
+assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
+assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
+assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
+assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
+assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
+assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
+assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
+assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
+assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
+assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
+assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
+assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
+assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
+assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
+assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
+assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
+assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
+assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
+assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
+assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
+assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
+assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
+assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
+assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
+assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
+assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
+assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
+assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
+assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
+assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
+assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
+assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
+assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
+assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
+assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
+assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
+assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
+assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
+assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
+assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
+assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
+assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
+assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
+assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
+assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
+assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
+assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
+assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
+assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
+assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
+assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
+assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
+assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
+assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
+assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
+assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
+assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
+assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
+assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
+assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
+assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
+assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
+assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
+assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
+assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
+assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
+assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
+assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
+assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
+assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
+assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
+assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
+assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
+assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
+assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
+assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
+assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
+assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
+assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
+assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
+assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
+assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
+assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
+assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
+assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
+assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
+assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
+assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
+assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
+assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
+assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
+assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
+assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
+assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
+assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
 
 // synthesis translate_off
-reg dummy_d_35;
+reg dummy_d_22;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_bank <= 3'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_bank <= soc_sdram_slave_p0_bank;
+       litedramcore_master_p3_cke <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
        end else begin
-               soc_sdram_master_p0_bank <= soc_sdram_inti_p0_bank;
+               litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
        end
 // synthesis translate_off
-       dummy_d_35 = dummy_s;
+       dummy_d_22 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_36;
+reg dummy_d_23;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_cas_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_cas_n <= soc_sdram_slave_p0_cas_n;
+       litedramcore_master_p3_odt <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
        end else begin
-               soc_sdram_master_p0_cas_n <= soc_sdram_inti_p0_cas_n;
+               litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
        end
 // synthesis translate_off
-       dummy_d_36 = dummy_s;
+       dummy_d_23 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_37;
+reg dummy_d_24;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_cs_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_cs_n <= soc_sdram_slave_p0_cs_n;
+       litedramcore_master_p3_reset_n <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
        end else begin
-               soc_sdram_master_p0_cs_n <= soc_sdram_inti_p0_cs_n;
+               litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
        end
 // synthesis translate_off
-       dummy_d_37 = dummy_s;
+       dummy_d_24 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_38;
+reg dummy_d_25;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_ras_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_ras_n <= soc_sdram_slave_p0_ras_n;
+       litedramcore_master_p3_act_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
        end else begin
-               soc_sdram_master_p0_ras_n <= soc_sdram_inti_p0_ras_n;
+               litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
        end
 // synthesis translate_off
-       dummy_d_38 = dummy_s;
+       dummy_d_25 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_39;
+reg dummy_d_26;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p0_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p0_rddata <= soc_sdram_master_p0_rddata;
+       litedramcore_master_p3_wrdata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
        end else begin
+               litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
        end
 // synthesis translate_off
-       dummy_d_39 = dummy_s;
+       dummy_d_26 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_40;
+reg dummy_d_27;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_we_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_we_n <= soc_sdram_slave_p0_we_n;
+       litedramcore_inti_p0_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p0_we_n <= soc_sdram_inti_p0_we_n;
+               litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
        end
 // synthesis translate_off
-       dummy_d_40 = dummy_s;
+       dummy_d_27 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_41;
+reg dummy_d_28;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p0_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid;
+       litedramcore_master_p3_wrdata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
        end else begin
+               litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
        end
 // synthesis translate_off
-       dummy_d_41 = dummy_s;
+       dummy_d_28 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_42;
+reg dummy_d_29;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_cke <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_cke <= soc_sdram_slave_p0_cke;
+       litedramcore_inti_p0_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p0_cke <= soc_sdram_inti_p0_cke;
+               litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
        end
 // synthesis translate_off
-       dummy_d_42 = dummy_s;
+       dummy_d_29 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_43;
+reg dummy_d_30;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_odt <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_odt <= soc_sdram_slave_p0_odt;
+       litedramcore_master_p3_wrdata_mask <= 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
        end else begin
-               soc_sdram_master_p0_odt <= soc_sdram_inti_p0_odt;
+               litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
        end
 // synthesis translate_off
-       dummy_d_43 = dummy_s;
+       dummy_d_30 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_44;
+reg dummy_d_31;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_reset_n <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_reset_n <= soc_sdram_slave_p0_reset_n;
+       litedramcore_master_p3_rddata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
        end else begin
-               soc_sdram_master_p0_reset_n <= soc_sdram_inti_p0_reset_n;
+               litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
        end
 // synthesis translate_off
-       dummy_d_44 = dummy_s;
+       dummy_d_31 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_32;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_address <= 14'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+       end else begin
+               litedramcore_master_p0_address <= litedramcore_inti_p0_address;
+       end
+// synthesis translate_off
+       dummy_d_32 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_33;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_bank <= 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+       end else begin
+               litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
+       end
+// synthesis translate_off
+       dummy_d_33 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_34;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_cas_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+       end else begin
+               litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
+       end
+// synthesis translate_off
+       dummy_d_34 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_35;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_cs_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+       end else begin
+               litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
+       end
+// synthesis translate_off
+       dummy_d_35 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_36;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_slave_p0_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+       end else begin
+       end
+// synthesis translate_off
+       dummy_d_36 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_37;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_ras_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+       end else begin
+               litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
+       end
+// synthesis translate_off
+       dummy_d_37 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_38;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_slave_p0_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+       end else begin
+       end
+// synthesis translate_off
+       dummy_d_38 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_39;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_we_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+       end else begin
+               litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
+       end
+// synthesis translate_off
+       dummy_d_39 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_40;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_cke <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+       end else begin
+               litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
+       end
+// synthesis translate_off
+       dummy_d_40 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_41;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_odt <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+       end else begin
+               litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
+       end
+// synthesis translate_off
+       dummy_d_41 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_42;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_reset_n <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+       end else begin
+               litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
+       end
+// synthesis translate_off
+       dummy_d_42 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_43;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_act_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+       end else begin
+               litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
+       end
+// synthesis translate_off
+       dummy_d_43 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_44;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p0_wrdata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+       end else begin
+               litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
+       end
+// synthesis translate_off
+       dummy_d_44 = dummy_s;
 // synthesis translate_on
 end
 
@@ -3865,11 +3189,10 @@ end
 reg dummy_d_45;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_act_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_act_n <= soc_sdram_slave_p0_act_n;
+       litedramcore_inti_p1_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p0_act_n <= soc_sdram_inti_p0_act_n;
+               litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
        end
 // synthesis translate_off
        dummy_d_45 = dummy_s;
@@ -3880,11 +3203,11 @@ end
 reg dummy_d_46;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_wrdata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_wrdata <= soc_sdram_slave_p0_wrdata;
+       litedramcore_master_p0_wrdata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
        end else begin
-               soc_sdram_master_p0_wrdata <= soc_sdram_inti_p0_wrdata;
+               litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
        end
 // synthesis translate_off
        dummy_d_46 = dummy_s;
@@ -3895,10 +3218,10 @@ end
 reg dummy_d_47;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_inti_p1_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_inti_p1_rddata <= soc_sdram_master_p1_rddata;
+               litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
        end
 // synthesis translate_off
        dummy_d_47 = dummy_s;
@@ -3909,11 +3232,11 @@ end
 reg dummy_d_48;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_wrdata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_wrdata_en <= soc_sdram_slave_p0_wrdata_en;
+       litedramcore_master_p0_wrdata_mask <= 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
        end else begin
-               soc_sdram_master_p0_wrdata_en <= soc_sdram_inti_p0_wrdata_en;
+               litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_48 = dummy_s;
@@ -3924,10 +3247,11 @@ end
 reg dummy_d_49;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_master_p0_rddata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
        end else begin
-               soc_sdram_inti_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid;
+               litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
        end
 // synthesis translate_off
        dummy_d_49 = dummy_s;
@@ -3938,11 +3262,11 @@ end
 reg dummy_d_50;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_wrdata_mask <= 4'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_wrdata_mask <= soc_sdram_slave_p0_wrdata_mask;
+       litedramcore_master_p1_address <= 14'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_address <= litedramcore_slave_p1_address;
        end else begin
-               soc_sdram_master_p0_wrdata_mask <= soc_sdram_inti_p0_wrdata_mask;
+               litedramcore_master_p1_address <= litedramcore_inti_p1_address;
        end
 // synthesis translate_off
        dummy_d_50 = dummy_s;
@@ -3953,11 +3277,11 @@ end
 reg dummy_d_51;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_rddata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_rddata_en <= soc_sdram_slave_p0_rddata_en;
+       litedramcore_master_p1_bank <= 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
        end else begin
-               soc_sdram_master_p0_rddata_en <= soc_sdram_inti_p0_rddata_en;
+               litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
        end
 // synthesis translate_off
        dummy_d_51 = dummy_s;
@@ -3968,11 +3292,11 @@ end
 reg dummy_d_52;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_address <= 14'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_address <= soc_sdram_slave_p1_address;
+       litedramcore_master_p1_cas_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
        end else begin
-               soc_sdram_master_p1_address <= soc_sdram_inti_p1_address;
+               litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
        end
 // synthesis translate_off
        dummy_d_52 = dummy_s;
@@ -3983,11 +3307,11 @@ end
 reg dummy_d_53;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_bank <= 3'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_bank <= soc_sdram_slave_p1_bank;
+       litedramcore_master_p1_cs_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
        end else begin
-               soc_sdram_master_p1_bank <= soc_sdram_inti_p1_bank;
+               litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
        end
 // synthesis translate_off
        dummy_d_53 = dummy_s;
@@ -3998,11 +3322,11 @@ end
 reg dummy_d_54;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_cas_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_cas_n <= soc_sdram_slave_p1_cas_n;
+       litedramcore_master_p1_ras_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
        end else begin
-               soc_sdram_master_p1_cas_n <= soc_sdram_inti_p1_cas_n;
+               litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
        end
 // synthesis translate_off
        dummy_d_54 = dummy_s;
@@ -4013,11 +3337,10 @@ end
 reg dummy_d_55;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_cs_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_cs_n <= soc_sdram_slave_p1_cs_n;
+       litedramcore_slave_p1_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
        end else begin
-               soc_sdram_master_p1_cs_n <= soc_sdram_inti_p1_cs_n;
        end
 // synthesis translate_off
        dummy_d_55 = dummy_s;
@@ -4028,11 +3351,11 @@ end
 reg dummy_d_56;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_ras_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_ras_n <= soc_sdram_slave_p1_ras_n;
+       litedramcore_master_p1_we_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
        end else begin
-               soc_sdram_master_p1_ras_n <= soc_sdram_inti_p1_ras_n;
+               litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
        end
 // synthesis translate_off
        dummy_d_56 = dummy_s;
@@ -4043,9 +3366,9 @@ end
 reg dummy_d_57;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p1_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p1_rddata <= soc_sdram_master_p1_rddata;
+       litedramcore_slave_p1_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
        end else begin
        end
 // synthesis translate_off
@@ -4057,11 +3380,11 @@ end
 reg dummy_d_58;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_we_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_we_n <= soc_sdram_slave_p1_we_n;
+       litedramcore_master_p1_cke <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
        end else begin
-               soc_sdram_master_p1_we_n <= soc_sdram_inti_p1_we_n;
+               litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
        end
 // synthesis translate_off
        dummy_d_58 = dummy_s;
@@ -4072,10 +3395,11 @@ end
 reg dummy_d_59;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p1_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid;
+       litedramcore_master_p1_odt <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
        end else begin
+               litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
        end
 // synthesis translate_off
        dummy_d_59 = dummy_s;
@@ -4086,11 +3410,11 @@ end
 reg dummy_d_60;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_cke <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_cke <= soc_sdram_slave_p1_cke;
+       litedramcore_master_p1_reset_n <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
        end else begin
-               soc_sdram_master_p1_cke <= soc_sdram_inti_p1_cke;
+               litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
        end
 // synthesis translate_off
        dummy_d_60 = dummy_s;
@@ -4101,11 +3425,11 @@ end
 reg dummy_d_61;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_odt <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_odt <= soc_sdram_slave_p1_odt;
+       litedramcore_master_p1_act_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
        end else begin
-               soc_sdram_master_p1_odt <= soc_sdram_inti_p1_odt;
+               litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
        end
 // synthesis translate_off
        dummy_d_61 = dummy_s;
@@ -4116,11 +3440,11 @@ end
 reg dummy_d_62;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_reset_n <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_reset_n <= soc_sdram_slave_p1_reset_n;
+       litedramcore_master_p1_wrdata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
        end else begin
-               soc_sdram_master_p1_reset_n <= soc_sdram_inti_p1_reset_n;
+               litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
        end
 // synthesis translate_off
        dummy_d_62 = dummy_s;
@@ -4131,11 +3455,10 @@ end
 reg dummy_d_63;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_act_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_act_n <= soc_sdram_slave_p1_act_n;
+       litedramcore_inti_p2_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p1_act_n <= soc_sdram_inti_p1_act_n;
+               litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
        end
 // synthesis translate_off
        dummy_d_63 = dummy_s;
@@ -4146,11 +3469,11 @@ end
 reg dummy_d_64;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_wrdata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_wrdata <= soc_sdram_slave_p1_wrdata;
+       litedramcore_master_p1_wrdata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
        end else begin
-               soc_sdram_master_p1_wrdata <= soc_sdram_inti_p1_wrdata;
+               litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
        end
 // synthesis translate_off
        dummy_d_64 = dummy_s;
@@ -4161,10 +3484,10 @@ end
 reg dummy_d_65;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_inti_p2_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_inti_p2_rddata <= soc_sdram_master_p2_rddata;
+               litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
        end
 // synthesis translate_off
        dummy_d_65 = dummy_s;
@@ -4175,11 +3498,11 @@ end
 reg dummy_d_66;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_wrdata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_wrdata_en <= soc_sdram_slave_p1_wrdata_en;
+       litedramcore_master_p1_wrdata_mask <= 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
        end else begin
-               soc_sdram_master_p1_wrdata_en <= soc_sdram_inti_p1_wrdata_en;
+               litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_66 = dummy_s;
@@ -4190,10 +3513,11 @@ end
 reg dummy_d_67;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_master_p1_rddata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
        end else begin
-               soc_sdram_inti_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid;
+               litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
        end
 // synthesis translate_off
        dummy_d_67 = dummy_s;
@@ -4204,11 +3528,10 @@ end
 reg dummy_d_68;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_wrdata_mask <= 4'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_wrdata_mask <= soc_sdram_slave_p1_wrdata_mask;
+       litedramcore_slave_p3_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
        end else begin
-               soc_sdram_master_p1_wrdata_mask <= soc_sdram_inti_p1_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_68 = dummy_s;
@@ -4219,11 +3542,11 @@ end
 reg dummy_d_69;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_rddata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_rddata_en <= soc_sdram_slave_p1_rddata_en;
+       litedramcore_master_p2_address <= 14'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_address <= litedramcore_slave_p2_address;
        end else begin
-               soc_sdram_master_p1_rddata_en <= soc_sdram_inti_p1_rddata_en;
+               litedramcore_master_p2_address <= litedramcore_inti_p2_address;
        end
 // synthesis translate_off
        dummy_d_69 = dummy_s;
@@ -4234,11 +3557,11 @@ end
 reg dummy_d_70;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_address <= 14'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_address <= soc_sdram_slave_p2_address;
+       litedramcore_master_p2_bank <= 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
        end else begin
-               soc_sdram_master_p2_address <= soc_sdram_inti_p2_address;
+               litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
        end
 // synthesis translate_off
        dummy_d_70 = dummy_s;
@@ -4249,11 +3572,11 @@ end
 reg dummy_d_71;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_bank <= 3'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_bank <= soc_sdram_slave_p2_bank;
+       litedramcore_master_p2_cas_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
        end else begin
-               soc_sdram_master_p2_bank <= soc_sdram_inti_p2_bank;
+               litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
        end
 // synthesis translate_off
        dummy_d_71 = dummy_s;
@@ -4264,11 +3587,11 @@ end
 reg dummy_d_72;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_cas_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_cas_n <= soc_sdram_slave_p2_cas_n;
+       litedramcore_master_p2_cs_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
        end else begin
-               soc_sdram_master_p2_cas_n <= soc_sdram_inti_p2_cas_n;
+               litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
        end
 // synthesis translate_off
        dummy_d_72 = dummy_s;
@@ -4279,11 +3602,10 @@ end
 reg dummy_d_73;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_cs_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_cs_n <= soc_sdram_slave_p2_cs_n;
+       litedramcore_slave_p3_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
        end else begin
-               soc_sdram_master_p2_cs_n <= soc_sdram_inti_p2_cs_n;
        end
 // synthesis translate_off
        dummy_d_73 = dummy_s;
@@ -4294,11 +3616,11 @@ end
 reg dummy_d_74;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_ras_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_ras_n <= soc_sdram_slave_p2_ras_n;
+       litedramcore_master_p2_ras_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
        end else begin
-               soc_sdram_master_p2_ras_n <= soc_sdram_inti_p2_ras_n;
+               litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
        end
 // synthesis translate_off
        dummy_d_74 = dummy_s;
@@ -4309,9 +3631,9 @@ end
 reg dummy_d_75;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p2_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p2_rddata <= soc_sdram_master_p2_rddata;
+       litedramcore_slave_p2_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
        end else begin
        end
 // synthesis translate_off
@@ -4323,11 +3645,11 @@ end
 reg dummy_d_76;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_we_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_we_n <= soc_sdram_slave_p2_we_n;
+       litedramcore_master_p2_we_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
        end else begin
-               soc_sdram_master_p2_we_n <= soc_sdram_inti_p2_we_n;
+               litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
        end
 // synthesis translate_off
        dummy_d_76 = dummy_s;
@@ -4338,9 +3660,9 @@ end
 reg dummy_d_77;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p2_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid;
+       litedramcore_slave_p2_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
        end else begin
        end
 // synthesis translate_off
@@ -4352,11 +3674,11 @@ end
 reg dummy_d_78;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_cke <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_cke <= soc_sdram_slave_p2_cke;
+       litedramcore_master_p2_cke <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
        end else begin
-               soc_sdram_master_p2_cke <= soc_sdram_inti_p2_cke;
+               litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
        end
 // synthesis translate_off
        dummy_d_78 = dummy_s;
@@ -4367,11 +3689,11 @@ end
 reg dummy_d_79;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_odt <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_odt <= soc_sdram_slave_p2_odt;
+       litedramcore_master_p2_odt <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
        end else begin
-               soc_sdram_master_p2_odt <= soc_sdram_inti_p2_odt;
+               litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
        end
 // synthesis translate_off
        dummy_d_79 = dummy_s;
@@ -4382,11 +3704,11 @@ end
 reg dummy_d_80;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_reset_n <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_reset_n <= soc_sdram_slave_p2_reset_n;
+       litedramcore_master_p2_reset_n <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
        end else begin
-               soc_sdram_master_p2_reset_n <= soc_sdram_inti_p2_reset_n;
+               litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
        end
 // synthesis translate_off
        dummy_d_80 = dummy_s;
@@ -4397,11 +3719,11 @@ end
 reg dummy_d_81;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_act_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_act_n <= soc_sdram_slave_p2_act_n;
+       litedramcore_master_p2_act_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
        end else begin
-               soc_sdram_master_p2_act_n <= soc_sdram_inti_p2_act_n;
+               litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
        end
 // synthesis translate_off
        dummy_d_81 = dummy_s;
@@ -4412,11 +3734,11 @@ end
 reg dummy_d_82;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_wrdata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_wrdata <= soc_sdram_slave_p2_wrdata;
+       litedramcore_master_p2_wrdata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
        end else begin
-               soc_sdram_master_p2_wrdata <= soc_sdram_inti_p2_wrdata;
+               litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
        end
 // synthesis translate_off
        dummy_d_82 = dummy_s;
@@ -4427,10 +3749,10 @@ end
 reg dummy_d_83;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p3_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_inti_p3_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_inti_p3_rddata <= soc_sdram_master_p3_rddata;
+               litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
        end
 // synthesis translate_off
        dummy_d_83 = dummy_s;
@@ -4441,11 +3763,11 @@ end
 reg dummy_d_84;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_wrdata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_wrdata_en <= soc_sdram_slave_p2_wrdata_en;
+       litedramcore_master_p2_wrdata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
        end else begin
-               soc_sdram_master_p2_wrdata_en <= soc_sdram_inti_p2_wrdata_en;
+               litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
        end
 // synthesis translate_off
        dummy_d_84 = dummy_s;
@@ -4456,10 +3778,10 @@ end
 reg dummy_d_85;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p3_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_inti_p3_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_inti_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid;
+               litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
        end
 // synthesis translate_off
        dummy_d_85 = dummy_s;
@@ -4470,11 +3792,11 @@ end
 reg dummy_d_86;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_wrdata_mask <= 4'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_wrdata_mask <= soc_sdram_slave_p2_wrdata_mask;
+       litedramcore_master_p2_wrdata_mask <= 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
        end else begin
-               soc_sdram_master_p2_wrdata_mask <= soc_sdram_inti_p2_wrdata_mask;
+               litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_86 = dummy_s;
@@ -4485,11 +3807,11 @@ end
 reg dummy_d_87;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_rddata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_rddata_en <= soc_sdram_slave_p2_rddata_en;
+       litedramcore_master_p2_rddata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
        end else begin
-               soc_sdram_master_p2_rddata_en <= soc_sdram_inti_p2_rddata_en;
+               litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
        end
 // synthesis translate_off
        dummy_d_87 = dummy_s;
@@ -4500,11 +3822,11 @@ end
 reg dummy_d_88;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_address <= 14'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_address <= soc_sdram_slave_p3_address;
+       litedramcore_master_p3_address <= 14'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_address <= litedramcore_slave_p3_address;
        end else begin
-               soc_sdram_master_p3_address <= soc_sdram_inti_p3_address;
+               litedramcore_master_p3_address <= litedramcore_inti_p3_address;
        end
 // synthesis translate_off
        dummy_d_88 = dummy_s;
@@ -4515,11 +3837,11 @@ end
 reg dummy_d_89;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_bank <= 3'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_bank <= soc_sdram_slave_p3_bank;
+       litedramcore_master_p3_bank <= 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
        end else begin
-               soc_sdram_master_p3_bank <= soc_sdram_inti_p3_bank;
+               litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
        end
 // synthesis translate_off
        dummy_d_89 = dummy_s;
@@ -4530,11 +3852,11 @@ end
 reg dummy_d_90;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_cas_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_cas_n <= soc_sdram_slave_p3_cas_n;
+       litedramcore_master_p3_cas_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
        end else begin
-               soc_sdram_master_p3_cas_n <= soc_sdram_inti_p3_cas_n;
+               litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
        end
 // synthesis translate_off
        dummy_d_90 = dummy_s;
@@ -4545,11 +3867,11 @@ end
 reg dummy_d_91;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_cs_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_cs_n <= soc_sdram_slave_p3_cs_n;
+       litedramcore_master_p3_cs_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
        end else begin
-               soc_sdram_master_p3_cs_n <= soc_sdram_inti_p3_cs_n;
+               litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
        end
 // synthesis translate_off
        dummy_d_91 = dummy_s;
@@ -4560,11 +3882,11 @@ end
 reg dummy_d_92;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_ras_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_ras_n <= soc_sdram_slave_p3_ras_n;
+       litedramcore_master_p3_ras_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
        end else begin
-               soc_sdram_master_p3_ras_n <= soc_sdram_inti_p3_ras_n;
+               litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
        end
 // synthesis translate_off
        dummy_d_92 = dummy_s;
@@ -4575,25 +3897,38 @@ end
 reg dummy_d_93;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p3_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p3_rddata <= soc_sdram_master_p3_rddata;
+       litedramcore_master_p3_we_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
        end else begin
+               litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
        end
 // synthesis translate_off
        dummy_d_93 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_inti_p0_cke = litedramcore_storage[1];
+assign litedramcore_inti_p1_cke = litedramcore_storage[1];
+assign litedramcore_inti_p2_cke = litedramcore_storage[1];
+assign litedramcore_inti_p3_cke = litedramcore_storage[1];
+assign litedramcore_inti_p0_odt = litedramcore_storage[2];
+assign litedramcore_inti_p1_odt = litedramcore_storage[2];
+assign litedramcore_inti_p2_odt = litedramcore_storage[2];
+assign litedramcore_inti_p3_odt = litedramcore_storage[2];
+assign litedramcore_inti_p0_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p1_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p2_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];
 
 // synthesis translate_off
 reg dummy_d_94;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_we_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_we_n <= soc_sdram_slave_p3_we_n;
+       litedramcore_inti_p0_cas_n <= 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
        end else begin
-               soc_sdram_master_p3_we_n <= soc_sdram_inti_p3_we_n;
+               litedramcore_inti_p0_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_94 = dummy_s;
@@ -4604,10 +3939,11 @@ end
 reg dummy_d_95;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p3_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid;
+       litedramcore_inti_p0_cs_n <= 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
        end else begin
+               litedramcore_inti_p0_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_95 = dummy_s;
@@ -4618,11 +3954,11 @@ end
 reg dummy_d_96;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_cke <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_cke <= soc_sdram_slave_p3_cke;
+       litedramcore_inti_p0_ras_n <= 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
        end else begin
-               soc_sdram_master_p3_cke <= soc_sdram_inti_p3_cke;
+               litedramcore_inti_p0_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_96 = dummy_s;
@@ -4633,26 +3969,32 @@ end
 reg dummy_d_97;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_odt <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_odt <= soc_sdram_slave_p3_odt;
+       litedramcore_inti_p0_we_n <= 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
        end else begin
-               soc_sdram_master_p3_odt <= soc_sdram_inti_p3_odt;
+               litedramcore_inti_p0_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_97 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
+assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
+assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_inti_p0_wrdata_mask = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_98;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_reset_n <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_reset_n <= soc_sdram_slave_p3_reset_n;
+       litedramcore_inti_p1_cas_n <= 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
        end else begin
-               soc_sdram_master_p3_reset_n <= soc_sdram_inti_p3_reset_n;
+               litedramcore_inti_p1_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_98 = dummy_s;
@@ -4663,11 +4005,11 @@ end
 reg dummy_d_99;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_act_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_act_n <= soc_sdram_slave_p3_act_n;
+       litedramcore_inti_p1_cs_n <= 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
        end else begin
-               soc_sdram_master_p3_act_n <= soc_sdram_inti_p3_act_n;
+               litedramcore_inti_p1_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_99 = dummy_s;
@@ -4678,11 +4020,11 @@ end
 reg dummy_d_100;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_wrdata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_wrdata <= soc_sdram_slave_p3_wrdata;
+       litedramcore_inti_p1_ras_n <= 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
        end else begin
-               soc_sdram_master_p3_wrdata <= soc_sdram_inti_p3_wrdata;
+               litedramcore_inti_p1_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_100 = dummy_s;
@@ -4693,25 +4035,32 @@ end
 reg dummy_d_101;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_inti_p1_we_n <= 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
        end else begin
-               soc_sdram_inti_p0_rddata <= soc_sdram_master_p0_rddata;
+               litedramcore_inti_p1_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_101 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
+assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
+assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_inti_p1_wrdata_mask = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_102;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_wrdata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_wrdata_en <= soc_sdram_slave_p3_wrdata_en;
+       litedramcore_inti_p2_cas_n <= 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]);
        end else begin
-               soc_sdram_master_p3_wrdata_en <= soc_sdram_inti_p3_wrdata_en;
+               litedramcore_inti_p2_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_102 = dummy_s;
@@ -4722,10 +4071,11 @@ end
 reg dummy_d_103;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_inti_p2_cs_n <= 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
        end else begin
-               soc_sdram_inti_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid;
+               litedramcore_inti_p2_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_103 = dummy_s;
@@ -4736,11 +4086,11 @@ end
 reg dummy_d_104;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_wrdata_mask <= 4'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_wrdata_mask <= soc_sdram_slave_p3_wrdata_mask;
+       litedramcore_inti_p2_ras_n <= 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]);
        end else begin
-               soc_sdram_master_p3_wrdata_mask <= soc_sdram_inti_p3_wrdata_mask;
+               litedramcore_inti_p2_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_104 = dummy_s;
@@ -4751,53 +4101,47 @@ end
 reg dummy_d_105;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_rddata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_rddata_en <= soc_sdram_slave_p3_rddata_en;
+       litedramcore_inti_p2_we_n <= 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]);
        end else begin
-               soc_sdram_master_p3_rddata_en <= soc_sdram_inti_p3_rddata_en;
+               litedramcore_inti_p2_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_105 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
+assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
+assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
+assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
+assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
+assign litedramcore_inti_p2_wrdata_mask = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_106;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_address <= 14'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_address <= soc_sdram_slave_p0_address;
+       litedramcore_inti_p3_cas_n <= 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]);
        end else begin
-               soc_sdram_master_p0_address <= soc_sdram_inti_p0_address;
+               litedramcore_inti_p3_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_106 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_inti_p0_cke = soc_sdram_storage[1];
-assign soc_sdram_inti_p1_cke = soc_sdram_storage[1];
-assign soc_sdram_inti_p2_cke = soc_sdram_storage[1];
-assign soc_sdram_inti_p3_cke = soc_sdram_storage[1];
-assign soc_sdram_inti_p0_odt = soc_sdram_storage[2];
-assign soc_sdram_inti_p1_odt = soc_sdram_storage[2];
-assign soc_sdram_inti_p2_odt = soc_sdram_storage[2];
-assign soc_sdram_inti_p3_odt = soc_sdram_storage[2];
-assign soc_sdram_inti_p0_reset_n = soc_sdram_storage[3];
-assign soc_sdram_inti_p1_reset_n = soc_sdram_storage[3];
-assign soc_sdram_inti_p2_reset_n = soc_sdram_storage[3];
-assign soc_sdram_inti_p3_reset_n = soc_sdram_storage[3];
 
 // synthesis translate_off
 reg dummy_d_107;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_we_n <= 1'd1;
-       if (soc_sdram_phaseinjector0_command_issue_re) begin
-               soc_sdram_inti_p0_we_n <= (~soc_sdram_phaseinjector0_command_storage[1]);
+       litedramcore_inti_p3_cs_n <= 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
        end else begin
-               soc_sdram_inti_p0_we_n <= 1'd1;
+               litedramcore_inti_p3_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_107 = dummy_s;
@@ -4808,11 +4152,11 @@ end
 reg dummy_d_108;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_cas_n <= 1'd1;
-       if (soc_sdram_phaseinjector0_command_issue_re) begin
-               soc_sdram_inti_p0_cas_n <= (~soc_sdram_phaseinjector0_command_storage[2]);
+       litedramcore_inti_p3_ras_n <= 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]);
        end else begin
-               soc_sdram_inti_p0_cas_n <= 1'd1;
+               litedramcore_inti_p3_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_108 = dummy_s;
@@ -4823,48 +4167,158 @@ end
 reg dummy_d_109;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_cs_n <= 1'd1;
-       if (soc_sdram_phaseinjector0_command_issue_re) begin
-               soc_sdram_inti_p0_cs_n <= {1{(~soc_sdram_phaseinjector0_command_storage[0])}};
+       litedramcore_inti_p3_we_n <= 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]);
        end else begin
-               soc_sdram_inti_p0_cs_n <= {1{1'd1}};
+               litedramcore_inti_p3_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_109 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
+assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage;
+assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]);
+assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]);
+assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
+assign litedramcore_inti_p3_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
+assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
+assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
+assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
+assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
+assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
+assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
+assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
+assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
+assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
+assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
+assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
+assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
+assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
+assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
+assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
+assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
+assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
+assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
+assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
+assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
+assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
+assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
+assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
+assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
+assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
+assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
+assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
+assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
+assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
+assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
+assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
+assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
+assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
+assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
+assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
+assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
+assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
+assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
+assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
+assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
+assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
+assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
+assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
+assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
+assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
+assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
+assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
+assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
+assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
+assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
+assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
+assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
+assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
+assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
+assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
+assign litedramcore_timer_wait = (~litedramcore_timer_done0);
+assign litedramcore_postponer_req_i = litedramcore_timer_done0;
+assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
+assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
+assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
+assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
+assign litedramcore_timer_done0 = litedramcore_timer_done1;
+assign litedramcore_timer_count0 = litedramcore_timer_count1;
+assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
+assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
+assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
+assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
+assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
 
 // synthesis translate_off
 reg dummy_d_110;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_ras_n <= 1'd1;
-       if (soc_sdram_phaseinjector0_command_issue_re) begin
-               soc_sdram_inti_p0_ras_n <= (~soc_sdram_phaseinjector0_command_storage[3]);
-       end else begin
-               soc_sdram_inti_p0_ras_n <= 1'd1;
-       end
+       refresher_next_state <= 2'd0;
+       refresher_next_state <= refresher_state;
+       case (refresher_state)
+               1'd1: begin
+                       if (litedramcore_cmd_ready) begin
+                               refresher_next_state <= 2'd2;
+                       end
+               end
+               2'd2: begin
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                                       refresher_next_state <= 2'd3;
+                               end else begin
+                                       refresher_next_state <= 1'd0;
+                               end
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_zqcs_executer_done) begin
+                               refresher_next_state <= 1'd0;
+                       end
+               end
+               default: begin
+                       if (1'd1) begin
+                               if (litedramcore_wants_refresh) begin
+                                       refresher_next_state <= 1'd1;
+                               end
+                       end
+               end
+       endcase
 // synthesis translate_off
        dummy_d_110 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_inti_p0_address = soc_sdram_phaseinjector0_address_storage;
-assign soc_sdram_inti_p0_bank = soc_sdram_phaseinjector0_baddress_storage;
-assign soc_sdram_inti_p0_wrdata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[4]);
-assign soc_sdram_inti_p0_rddata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[5]);
-assign soc_sdram_inti_p0_wrdata = soc_sdram_phaseinjector0_wrdata_storage;
-assign soc_sdram_inti_p0_wrdata_mask = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_111;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_we_n <= 1'd1;
-       if (soc_sdram_phaseinjector1_command_issue_re) begin
-               soc_sdram_inti_p1_we_n <= (~soc_sdram_phaseinjector1_command_storage[1]);
-       end else begin
-               soc_sdram_inti_p1_we_n <= 1'd1;
-       end
+       litedramcore_cmd_valid <= 1'd0;
+       case (refresher_state)
+               1'd1: begin
+                       litedramcore_cmd_valid <= 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_cmd_valid <= 1'd1;
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                               end else begin
+                                       litedramcore_cmd_valid <= 1'd0;
+                               end
+                       end
+               end
+               2'd3: begin
+                       litedramcore_cmd_valid <= 1'd1;
+                       if (litedramcore_zqcs_executer_done) begin
+                               litedramcore_cmd_valid <= 1'd0;
+                       end
+               end
+               default: begin
+               end
+       endcase
 // synthesis translate_off
        dummy_d_111 = dummy_s;
 // synthesis translate_on
@@ -4874,12 +4328,23 @@ end
 reg dummy_d_112;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_cas_n <= 1'd1;
-       if (soc_sdram_phaseinjector1_command_issue_re) begin
-               soc_sdram_inti_p1_cas_n <= (~soc_sdram_phaseinjector1_command_storage[2]);
-       end else begin
-               soc_sdram_inti_p1_cas_n <= 1'd1;
-       end
+       litedramcore_zqcs_executer_start <= 1'd0;
+       case (refresher_state)
+               1'd1: begin
+               end
+               2'd2: begin
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                                       litedramcore_zqcs_executer_start <= 1'd1;
+                               end else begin
+                               end
+                       end
+               end
+               2'd3: begin
+               end
+               default: begin
+               end
+       endcase
 // synthesis translate_off
        dummy_d_112 = dummy_s;
 // synthesis translate_on
@@ -4889,12 +4354,26 @@ end
 reg dummy_d_113;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_cs_n <= 1'd1;
-       if (soc_sdram_phaseinjector1_command_issue_re) begin
-               soc_sdram_inti_p1_cs_n <= {1{(~soc_sdram_phaseinjector1_command_storage[0])}};
-       end else begin
-               soc_sdram_inti_p1_cs_n <= {1{1'd1}};
-       end
+       litedramcore_cmd_last <= 1'd0;
+       case (refresher_state)
+               1'd1: begin
+               end
+               2'd2: begin
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                               end else begin
+                                       litedramcore_cmd_last <= 1'd1;
+                               end
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_zqcs_executer_done) begin
+                               litedramcore_cmd_last <= 1'd1;
+                       end
+               end
+               default: begin
+               end
+       endcase
 // synthesis translate_off
        dummy_d_113 = dummy_s;
 // synthesis translate_on
@@ -4904,542 +4383,431 @@ end
 reg dummy_d_114;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_ras_n <= 1'd1;
-       if (soc_sdram_phaseinjector1_command_issue_re) begin
-               soc_sdram_inti_p1_ras_n <= (~soc_sdram_phaseinjector1_command_storage[3]);
-       end else begin
-               soc_sdram_inti_p1_ras_n <= 1'd1;
-       end
+       litedramcore_sequencer_start0 <= 1'd0;
+       case (refresher_state)
+               1'd1: begin
+                       if (litedramcore_cmd_ready) begin
+                               litedramcore_sequencer_start0 <= 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               default: begin
+               end
+       endcase
 // synthesis translate_off
        dummy_d_114 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_inti_p1_address = soc_sdram_phaseinjector1_address_storage;
-assign soc_sdram_inti_p1_bank = soc_sdram_phaseinjector1_baddress_storage;
-assign soc_sdram_inti_p1_wrdata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[4]);
-assign soc_sdram_inti_p1_rddata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[5]);
-assign soc_sdram_inti_p1_wrdata = soc_sdram_phaseinjector1_wrdata_storage;
-assign soc_sdram_inti_p1_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_115;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_we_n <= 1'd1;
-       if (soc_sdram_phaseinjector2_command_issue_re) begin
-               soc_sdram_inti_p2_we_n <= (~soc_sdram_phaseinjector2_command_storage[1]);
+       litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
+       if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+               litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
        end else begin
-               soc_sdram_inti_p2_we_n <= 1'd1;
+               litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
        end
 // synthesis translate_off
        dummy_d_115 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
+assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
 
 // synthesis translate_off
 reg dummy_d_116;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_cas_n <= 1'd1;
-       if (soc_sdram_phaseinjector2_command_issue_re) begin
-               soc_sdram_inti_p2_cas_n <= (~soc_sdram_phaseinjector2_command_storage[2]);
-       end else begin
-               soc_sdram_inti_p2_cas_n <= 1'd1;
+       litedramcore_bankmachine0_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+               end
        end
 // synthesis translate_off
        dummy_d_116 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
 
 // synthesis translate_off
 reg dummy_d_117;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_cs_n <= 1'd1;
-       if (soc_sdram_phaseinjector2_command_issue_re) begin
-               soc_sdram_inti_p2_cs_n <= {1{(~soc_sdram_phaseinjector2_command_storage[0])}};
+       litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
        end else begin
-               soc_sdram_inti_p2_cs_n <= {1{1'd1}};
+               litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
        end
 // synthesis translate_off
        dummy_d_117 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
 
 // synthesis translate_off
 reg dummy_d_118;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_ras_n <= 1'd1;
-       if (soc_sdram_phaseinjector2_command_issue_re) begin
-               soc_sdram_inti_p2_ras_n <= (~soc_sdram_phaseinjector2_command_storage[3]);
-       end else begin
-               soc_sdram_inti_p2_ras_n <= 1'd1;
-       end
+       bankmachine0_next_state <= 4'd0;
+       bankmachine0_next_state <= bankmachine0_state;
+       case (bankmachine0_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               if (litedramcore_bankmachine0_cmd_ready) begin
+                                       bankmachine0_next_state <= 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               bankmachine0_next_state <= 3'd5;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               if (litedramcore_bankmachine0_cmd_ready) begin
+                                       bankmachine0_next_state <= 3'd7;
+                               end
+                       end
+               end
+               3'd4: begin
+                       if ((~litedramcore_bankmachine0_refresh_req)) begin
+                               bankmachine0_next_state <= 1'd0;
+                       end
+               end
+               3'd5: begin
+                       bankmachine0_next_state <= 3'd6;
+               end
+               3'd6: begin
+                       bankmachine0_next_state <= 2'd3;
+               end
+               3'd7: begin
+                       bankmachine0_next_state <= 4'd8;
+               end
+               4'd8: begin
+                       bankmachine0_next_state <= 1'd0;
+               end
+               default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                               bankmachine0_next_state <= 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+                                                               bankmachine0_next_state <= 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine0_next_state <= 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine0_next_state <= 2'd3;
+                                       end
+                               end
+                       end
+               end
+       endcase
 // synthesis translate_off
        dummy_d_118 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_inti_p2_address = soc_sdram_phaseinjector2_address_storage;
-assign soc_sdram_inti_p2_bank = soc_sdram_phaseinjector2_baddress_storage;
-assign soc_sdram_inti_p2_wrdata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[4]);
-assign soc_sdram_inti_p2_rddata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[5]);
-assign soc_sdram_inti_p2_wrdata = soc_sdram_phaseinjector2_wrdata_storage;
-assign soc_sdram_inti_p2_wrdata_mask = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_119;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p3_we_n <= 1'd1;
-       if (soc_sdram_phaseinjector3_command_issue_re) begin
-               soc_sdram_inti_p3_we_n <= (~soc_sdram_phaseinjector3_command_storage[1]);
-       end else begin
-               soc_sdram_inti_p3_we_n <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_119 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_120;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_inti_p3_cas_n <= 1'd1;
-       if (soc_sdram_phaseinjector3_command_issue_re) begin
-               soc_sdram_inti_p3_cas_n <= (~soc_sdram_phaseinjector3_command_storage[2]);
-       end else begin
-               soc_sdram_inti_p3_cas_n <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_120 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_121;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_inti_p3_cs_n <= 1'd1;
-       if (soc_sdram_phaseinjector3_command_issue_re) begin
-               soc_sdram_inti_p3_cs_n <= {1{(~soc_sdram_phaseinjector3_command_storage[0])}};
-       end else begin
-               soc_sdram_inti_p3_cs_n <= {1{1'd1}};
-       end
-// synthesis translate_off
-       dummy_d_121 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_122;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_inti_p3_ras_n <= 1'd1;
-       if (soc_sdram_phaseinjector3_command_issue_re) begin
-               soc_sdram_inti_p3_ras_n <= (~soc_sdram_phaseinjector3_command_storage[3]);
-       end else begin
-               soc_sdram_inti_p3_ras_n <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_122 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_inti_p3_address = soc_sdram_phaseinjector3_address_storage;
-assign soc_sdram_inti_p3_bank = soc_sdram_phaseinjector3_baddress_storage;
-assign soc_sdram_inti_p3_wrdata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[4]);
-assign soc_sdram_inti_p3_rddata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[5]);
-assign soc_sdram_inti_p3_wrdata = soc_sdram_phaseinjector3_wrdata_storage;
-assign soc_sdram_inti_p3_wrdata_mask = 1'd0;
-assign soc_sdram_bankmachine0_req_valid = soc_sdram_interface_bank0_valid;
-assign soc_sdram_interface_bank0_ready = soc_sdram_bankmachine0_req_ready;
-assign soc_sdram_bankmachine0_req_we = soc_sdram_interface_bank0_we;
-assign soc_sdram_bankmachine0_req_addr = soc_sdram_interface_bank0_addr;
-assign soc_sdram_interface_bank0_lock = soc_sdram_bankmachine0_req_lock;
-assign soc_sdram_interface_bank0_wdata_ready = soc_sdram_bankmachine0_req_wdata_ready;
-assign soc_sdram_interface_bank0_rdata_valid = soc_sdram_bankmachine0_req_rdata_valid;
-assign soc_sdram_bankmachine1_req_valid = soc_sdram_interface_bank1_valid;
-assign soc_sdram_interface_bank1_ready = soc_sdram_bankmachine1_req_ready;
-assign soc_sdram_bankmachine1_req_we = soc_sdram_interface_bank1_we;
-assign soc_sdram_bankmachine1_req_addr = soc_sdram_interface_bank1_addr;
-assign soc_sdram_interface_bank1_lock = soc_sdram_bankmachine1_req_lock;
-assign soc_sdram_interface_bank1_wdata_ready = soc_sdram_bankmachine1_req_wdata_ready;
-assign soc_sdram_interface_bank1_rdata_valid = soc_sdram_bankmachine1_req_rdata_valid;
-assign soc_sdram_bankmachine2_req_valid = soc_sdram_interface_bank2_valid;
-assign soc_sdram_interface_bank2_ready = soc_sdram_bankmachine2_req_ready;
-assign soc_sdram_bankmachine2_req_we = soc_sdram_interface_bank2_we;
-assign soc_sdram_bankmachine2_req_addr = soc_sdram_interface_bank2_addr;
-assign soc_sdram_interface_bank2_lock = soc_sdram_bankmachine2_req_lock;
-assign soc_sdram_interface_bank2_wdata_ready = soc_sdram_bankmachine2_req_wdata_ready;
-assign soc_sdram_interface_bank2_rdata_valid = soc_sdram_bankmachine2_req_rdata_valid;
-assign soc_sdram_bankmachine3_req_valid = soc_sdram_interface_bank3_valid;
-assign soc_sdram_interface_bank3_ready = soc_sdram_bankmachine3_req_ready;
-assign soc_sdram_bankmachine3_req_we = soc_sdram_interface_bank3_we;
-assign soc_sdram_bankmachine3_req_addr = soc_sdram_interface_bank3_addr;
-assign soc_sdram_interface_bank3_lock = soc_sdram_bankmachine3_req_lock;
-assign soc_sdram_interface_bank3_wdata_ready = soc_sdram_bankmachine3_req_wdata_ready;
-assign soc_sdram_interface_bank3_rdata_valid = soc_sdram_bankmachine3_req_rdata_valid;
-assign soc_sdram_bankmachine4_req_valid = soc_sdram_interface_bank4_valid;
-assign soc_sdram_interface_bank4_ready = soc_sdram_bankmachine4_req_ready;
-assign soc_sdram_bankmachine4_req_we = soc_sdram_interface_bank4_we;
-assign soc_sdram_bankmachine4_req_addr = soc_sdram_interface_bank4_addr;
-assign soc_sdram_interface_bank4_lock = soc_sdram_bankmachine4_req_lock;
-assign soc_sdram_interface_bank4_wdata_ready = soc_sdram_bankmachine4_req_wdata_ready;
-assign soc_sdram_interface_bank4_rdata_valid = soc_sdram_bankmachine4_req_rdata_valid;
-assign soc_sdram_bankmachine5_req_valid = soc_sdram_interface_bank5_valid;
-assign soc_sdram_interface_bank5_ready = soc_sdram_bankmachine5_req_ready;
-assign soc_sdram_bankmachine5_req_we = soc_sdram_interface_bank5_we;
-assign soc_sdram_bankmachine5_req_addr = soc_sdram_interface_bank5_addr;
-assign soc_sdram_interface_bank5_lock = soc_sdram_bankmachine5_req_lock;
-assign soc_sdram_interface_bank5_wdata_ready = soc_sdram_bankmachine5_req_wdata_ready;
-assign soc_sdram_interface_bank5_rdata_valid = soc_sdram_bankmachine5_req_rdata_valid;
-assign soc_sdram_bankmachine6_req_valid = soc_sdram_interface_bank6_valid;
-assign soc_sdram_interface_bank6_ready = soc_sdram_bankmachine6_req_ready;
-assign soc_sdram_bankmachine6_req_we = soc_sdram_interface_bank6_we;
-assign soc_sdram_bankmachine6_req_addr = soc_sdram_interface_bank6_addr;
-assign soc_sdram_interface_bank6_lock = soc_sdram_bankmachine6_req_lock;
-assign soc_sdram_interface_bank6_wdata_ready = soc_sdram_bankmachine6_req_wdata_ready;
-assign soc_sdram_interface_bank6_rdata_valid = soc_sdram_bankmachine6_req_rdata_valid;
-assign soc_sdram_bankmachine7_req_valid = soc_sdram_interface_bank7_valid;
-assign soc_sdram_interface_bank7_ready = soc_sdram_bankmachine7_req_ready;
-assign soc_sdram_bankmachine7_req_we = soc_sdram_interface_bank7_we;
-assign soc_sdram_bankmachine7_req_addr = soc_sdram_interface_bank7_addr;
-assign soc_sdram_interface_bank7_lock = soc_sdram_bankmachine7_req_lock;
-assign soc_sdram_interface_bank7_wdata_ready = soc_sdram_bankmachine7_req_wdata_ready;
-assign soc_sdram_interface_bank7_rdata_valid = soc_sdram_bankmachine7_req_rdata_valid;
-assign soc_sdram_timer_wait = (~soc_sdram_timer_done0);
-assign soc_sdram_postponer_req_i = soc_sdram_timer_done0;
-assign soc_sdram_wants_refresh = soc_sdram_postponer_req_o;
-assign soc_sdram_wants_zqcs = soc_sdram_zqcs_timer_done0;
-assign soc_sdram_zqcs_timer_wait = (~soc_sdram_zqcs_executer_done);
-assign soc_sdram_timer_done1 = (soc_sdram_timer_count1 == 1'd0);
-assign soc_sdram_timer_done0 = soc_sdram_timer_done1;
-assign soc_sdram_timer_count0 = soc_sdram_timer_count1;
-assign soc_sdram_sequencer_start1 = (soc_sdram_sequencer_start0 | (soc_sdram_sequencer_count != 1'd0));
-assign soc_sdram_sequencer_done0 = (soc_sdram_sequencer_done1 & (soc_sdram_sequencer_count == 1'd0));
-assign soc_sdram_zqcs_timer_done1 = (soc_sdram_zqcs_timer_count1 == 1'd0);
-assign soc_sdram_zqcs_timer_done0 = soc_sdram_zqcs_timer_done1;
-assign soc_sdram_zqcs_timer_count0 = soc_sdram_zqcs_timer_count1;
-
-// synthesis translate_off
-reg dummy_d_123;
-// synthesis translate_on
-always @(*) begin
-       vns_refresher_next_state <= 2'd0;
-       vns_refresher_next_state <= vns_refresher_state;
-       case (vns_refresher_state)
+       litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if (soc_sdram_cmd_ready) begin
-                               vns_refresher_next_state <= 2'd2;
-                       end
                end
                2'd2: begin
-                       if (soc_sdram_sequencer_done0) begin
-                               if (soc_sdram_wants_zqcs) begin
-                                       vns_refresher_next_state <= 2'd3;
-                               end else begin
-                                       vns_refresher_next_state <= 1'd0;
-                               end
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_zqcs_executer_done) begin
-                               vns_refresher_next_state <= 1'd0;
-                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
                end
                default: begin
-                       if (1'd1) begin
-                               if (soc_sdram_wants_refresh) begin
-                                       vns_refresher_next_state <= 1'd1;
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_123 = dummy_s;
+       dummy_d_119 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_124;
+reg dummy_d_120;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_sequencer_start0 <= 1'd0;
-       case (vns_refresher_state)
+       litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if (soc_sdram_cmd_ready) begin
-                               soc_sdram_sequencer_start0 <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
                end
+               3'd4: begin
+                       if (litedramcore_bankmachine0_twtpcon_ready) begin
+                               litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+                       end
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
                default: begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_124 = dummy_s;
+       dummy_d_120 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_125;
+reg dummy_d_121;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_cmd_valid <= 1'd0;
-       case (vns_refresher_state)
+       litedramcore_bankmachine0_cmd_valid <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       soc_sdram_cmd_valid <= 1'd1;
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                       end
                end
                2'd2: begin
-                       soc_sdram_cmd_valid <= 1'd1;
-                       if (soc_sdram_sequencer_done0) begin
-                               if (soc_sdram_wants_zqcs) begin
-                               end else begin
-                                       soc_sdram_cmd_valid <= 1'd0;
-                               end
-                       end
                end
                2'd3: begin
-                       soc_sdram_cmd_valid <= 1'd1;
-                       if (soc_sdram_zqcs_executer_done) begin
-                               soc_sdram_cmd_valid <= 1'd0;
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_cmd_valid <= 1'd1;
                        end
                end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
                default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_125 = dummy_s;
+       dummy_d_121 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_126;
+reg dummy_d_122;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_zqcs_executer_start <= 1'd0;
-       case (vns_refresher_state)
+       litedramcore_bankmachine0_row_open <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
-                       if (soc_sdram_sequencer_done0) begin
-                               if (soc_sdram_wants_zqcs) begin
-                                       soc_sdram_zqcs_executer_start <= 1'd1;
-                               end else begin
-                               end
-                       end
                end
                2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_row_open <= 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
                end
                default: begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_126 = dummy_s;
+       dummy_d_122 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_127;
+reg dummy_d_123;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_cmd_last <= 1'd0;
-       case (vns_refresher_state)
+       litedramcore_bankmachine0_row_close <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
+                       litedramcore_bankmachine0_row_close <= 1'd1;
                end
                2'd2: begin
-                       if (soc_sdram_sequencer_done0) begin
-                               if (soc_sdram_wants_zqcs) begin
-                               end else begin
-                                       soc_sdram_cmd_last <= 1'd1;
-                               end
-                       end
+                       litedramcore_bankmachine0_row_close <= 1'd1;
                end
                2'd3: begin
-                       if (soc_sdram_zqcs_executer_done) begin
-                               soc_sdram_cmd_last <= 1'd1;
-                       end
+               end
+               3'd4: begin
+                       litedramcore_bankmachine0_row_close <= 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
                end
                default: begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_127 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine0_req_valid;
-assign soc_sdram_bankmachine0_req_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine0_req_we;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine0_req_addr;
-assign soc_sdram_bankmachine0_cmd_buffer_sink_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine0_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine0_cmd_buffer_sink_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine0_cmd_buffer_sink_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine0_cmd_buffer_source_ready = (soc_sdram_bankmachine0_req_wdata_ready | soc_sdram_bankmachine0_req_rdata_valid);
-assign soc_sdram_bankmachine0_req_lock = (soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine0_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine0_row_hit = (soc_sdram_bankmachine0_row == soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
-assign soc_sdram_bankmachine0_cmd_payload_ba = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_128;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_a <= 14'd0;
-       if (soc_sdram_bankmachine0_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine0_cmd_payload_a <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
-       end else begin
-               soc_sdram_bankmachine0_cmd_payload_a <= ((soc_sdram_bankmachine0_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-       end
-// synthesis translate_off
-       dummy_d_128 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine0_twtpcon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_cmd_payload_is_write);
-assign soc_sdram_bankmachine0_trccon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open);
-assign soc_sdram_bankmachine0_trascon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open);
-
-// synthesis translate_off
-reg dummy_d_129;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine0_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine0_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
-                       soc_sdram_bankmachine0_auto_precharge <= (soc_sdram_bankmachine0_row_close == 1'd0);
-               end
-       end
-// synthesis translate_off
-       dummy_d_129 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_130;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
-       end else begin
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine0_cmd_buffer_lookahead_produce;
-       end
-// synthesis translate_off
-       dummy_d_130 = dummy_s;
+       dummy_d_123 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_sdram_bankmachine0_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine0_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine0_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_131;
+reg dummy_d_124;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine0_next_state <= 4'd0;
-       vns_bankmachine0_next_state <= vns_bankmachine0_state;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               if (soc_sdram_bankmachine0_cmd_ready) begin
-                                       vns_bankmachine0_next_state <= 3'd5;
-                               end
-                       end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               vns_bankmachine0_next_state <= 3'd5;
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               if (soc_sdram_bankmachine0_cmd_ready) begin
-                                       vns_bankmachine0_next_state <= 3'd7;
-                               end
-                       end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine0_refresh_req)) begin
-                               vns_bankmachine0_next_state <= 1'd0;
-                       end
                end
                3'd5: begin
-                       vns_bankmachine0_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine0_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine0_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine0_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
-                               vns_bankmachine0_next_state <= 3'd4;
+                       if (litedramcore_bankmachine0_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if ((soc_sdram_bankmachine0_cmd_ready & soc_sdram_bankmachine0_auto_precharge)) begin
-                                                               vns_bankmachine0_next_state <= 2'd2;
-                                                       end
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
                                                end else begin
-                                                       vns_bankmachine0_next_state <= 1'd1;
                                                end
                                        end else begin
-                                               vns_bankmachine0_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_131 = dummy_s;
+       dummy_d_124 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_132;
+reg dummy_d_125;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               soc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -5452,42 +4820,27 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_132 = dummy_s;
+       dummy_d_125 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_133;
+reg dummy_d_126;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -5500,33 +4853,44 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_133 = dummy_s;
+       dummy_d_126 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_134;
+reg dummy_d_127;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -5540,23 +4904,30 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_134 = dummy_s;
+       dummy_d_127 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_135;
+reg dummy_d_128;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                3'd4: begin
+                       litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -5567,34 +4938,19 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_135 = dummy_s;
+       dummy_d_128 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_136;
+reg dummy_d_129;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
@@ -5612,14 +4968,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
                                                        end else begin
+                                                               litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
                                                        end
                                                end else begin
                                                end
@@ -5630,16 +4986,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_136 = dummy_s;
+       dummy_d_129 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_137;
+reg dummy_d_130;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
@@ -5657,13 +5013,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine0_req_wdata_ready <= soc_sdram_bankmachine0_cmd_ready;
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -5675,16 +5031,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_137 = dummy_s;
+       dummy_d_130 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_138;
+reg dummy_d_131;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
@@ -5702,14 +5058,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
                                                        end else begin
-                                                               soc_sdram_bankmachine0_req_rdata_valid <= soc_sdram_bankmachine0_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -5720,60 +5076,176 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_138 = dummy_s;
+       dummy_d_131 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
 
 // synthesis translate_off
-reg dummy_d_139;
+reg dummy_d_132;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_refresh_gnt <= 1'd0;
-       case (vns_bankmachine0_state)
-               1'd1: begin
-               end
-               2'd2: begin
+       litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
+       if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+               litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+// synthesis translate_off
+       dummy_d_132 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
+assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+
+// synthesis translate_off
+reg dummy_d_133;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine1_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+               end
+       end
+// synthesis translate_off
+       dummy_d_133 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_134;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+       end
+// synthesis translate_off
+       dummy_d_134 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_135;
+// synthesis translate_on
+always @(*) begin
+       bankmachine1_next_state <= 4'd0;
+       bankmachine1_next_state <= bankmachine1_state;
+       case (bankmachine1_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               if (litedramcore_bankmachine1_cmd_ready) begin
+                                       bankmachine1_next_state <= 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               bankmachine1_next_state <= 3'd5;
+                       end
                end
                2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               if (litedramcore_bankmachine1_cmd_ready) begin
+                                       bankmachine1_next_state <= 3'd7;
+                               end
+                       end
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine0_twtpcon_ready) begin
-                               soc_sdram_bankmachine0_refresh_gnt <= 1'd1;
+                       if ((~litedramcore_bankmachine1_refresh_req)) begin
+                               bankmachine1_next_state <= 1'd0;
                        end
                end
                3'd5: begin
+                       bankmachine1_next_state <= 3'd6;
                end
                3'd6: begin
+                       bankmachine1_next_state <= 2'd3;
                end
                3'd7: begin
+                       bankmachine1_next_state <= 4'd8;
                end
                4'd8: begin
+                       bankmachine1_next_state <= 1'd0;
                end
                default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                               bankmachine1_next_state <= 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+                                                               bankmachine1_next_state <= 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine1_next_state <= 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine1_next_state <= 2'd3;
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_139 = dummy_s;
+       dummy_d_135 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_140;
+reg dummy_d_136;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_valid <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               soc_sdram_bankmachine0_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               soc_sdram_bankmachine0_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -5786,12 +5258,15 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       soc_sdram_bankmachine0_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -5801,23 +5276,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_140 = dummy_s;
+       dummy_d_136 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_141;
+reg dummy_d_137;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_row_open <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               soc_sdram_bankmachine0_row_open <= 1'd1;
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
                        end
                end
                3'd4: begin
@@ -5834,26 +5309,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_141 = dummy_s;
+       dummy_d_137 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_142;
+reg dummy_d_138;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_row_close <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       soc_sdram_bankmachine0_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_sdram_bankmachine0_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine0_row_close <= 1'd1;
+                       if (litedramcore_bankmachine1_twtpcon_ready) begin
+                               litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -5867,21 +5342,27 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_142 = dummy_s;
+       dummy_d_138 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_143;
+reg dummy_d_139;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine1_cmd_valid <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -5894,12 +5375,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       soc_sdram_bankmachine0_cmd_payload_cas <= 1'd1;
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       litedramcore_bankmachine1_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -5909,26 +5390,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_143 = dummy_s;
+       dummy_d_139 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_144;
+reg dummy_d_140;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine1_row_open <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_row_open <= 1'd1;
                        end
                end
                3'd4: begin
@@ -5945,174 +5423,130 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_144 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine1_req_valid;
-assign soc_sdram_bankmachine1_req_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine1_req_we;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine1_req_addr;
-assign soc_sdram_bankmachine1_cmd_buffer_sink_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine1_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine1_cmd_buffer_sink_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine1_cmd_buffer_sink_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine1_cmd_buffer_source_ready = (soc_sdram_bankmachine1_req_wdata_ready | soc_sdram_bankmachine1_req_rdata_valid);
-assign soc_sdram_bankmachine1_req_lock = (soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine1_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine1_row_hit = (soc_sdram_bankmachine1_row == soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
-assign soc_sdram_bankmachine1_cmd_payload_ba = 1'd1;
-
-// synthesis translate_off
-reg dummy_d_145;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_a <= 14'd0;
-       if (soc_sdram_bankmachine1_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine1_cmd_payload_a <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
-       end else begin
-               soc_sdram_bankmachine1_cmd_payload_a <= ((soc_sdram_bankmachine1_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-       end
-// synthesis translate_off
-       dummy_d_145 = dummy_s;
+       dummy_d_140 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine1_twtpcon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_cmd_payload_is_write);
-assign soc_sdram_bankmachine1_trccon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open);
-assign soc_sdram_bankmachine1_trascon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open);
 
 // synthesis translate_off
-reg dummy_d_146;
+reg dummy_d_141;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine1_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
-                       soc_sdram_bankmachine1_auto_precharge <= (soc_sdram_bankmachine1_row_close == 1'd0);
+       litedramcore_bankmachine1_row_close <= 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+                       litedramcore_bankmachine1_row_close <= 1'd1;
                end
-       end
+               2'd2: begin
+                       litedramcore_bankmachine1_row_close <= 1'd1;
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+                       litedramcore_bankmachine1_row_close <= 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
 // synthesis translate_off
-       dummy_d_146 = dummy_s;
+       dummy_d_141 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
 
 // synthesis translate_off
-reg dummy_d_147;
+reg dummy_d_142;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
-       end else begin
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine1_cmd_buffer_lookahead_produce;
-       end
+       litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+       case (bankmachine1_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
 // synthesis translate_off
-       dummy_d_147 = dummy_s;
+       dummy_d_142 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_sdram_bankmachine1_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine1_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine1_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_148;
+reg dummy_d_143;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine1_next_state <= 4'd0;
-       vns_bankmachine1_next_state <= vns_bankmachine1_state;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               if (soc_sdram_bankmachine1_cmd_ready) begin
-                                       vns_bankmachine1_next_state <= 3'd5;
-                               end
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               vns_bankmachine1_next_state <= 3'd5;
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               if (soc_sdram_bankmachine1_cmd_ready) begin
-                                       vns_bankmachine1_next_state <= 3'd7;
-                               end
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine1_refresh_req)) begin
-                               vns_bankmachine1_next_state <= 1'd0;
-                       end
                end
                3'd5: begin
-                       vns_bankmachine1_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine1_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine1_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine1_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
-                               vns_bankmachine1_next_state <= 3'd4;
-                       end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if ((soc_sdram_bankmachine1_cmd_ready & soc_sdram_bankmachine1_auto_precharge)) begin
-                                                               vns_bankmachine1_next_state <= 2'd2;
-                                                       end
-                                               end else begin
-                                                       vns_bankmachine1_next_state <= 1'd1;
-                                               end
-                                       end else begin
-                                               vns_bankmachine1_next_state <= 2'd3;
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_148 = dummy_s;
+       dummy_d_143 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_149;
+reg dummy_d_144;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               soc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
                        end
                end
                2'd2: begin
@@ -6130,13 +5564,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -6148,26 +5582,30 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_149 = dummy_s;
+       dummy_d_144 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_150;
+reg dummy_d_145;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -6181,30 +5619,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_150 = dummy_s;
+       dummy_d_145 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_151;
+reg dummy_d_146;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -6215,19 +5646,34 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_151 = dummy_s;
+       dummy_d_146 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_152;
+reg dummy_d_147;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
                end
                2'd2: begin
@@ -6245,14 +5691,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
                                                        end else begin
-                                                               soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
                                                        end
                                                end else begin
                                                end
@@ -6263,16 +5709,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_152 = dummy_s;
+       dummy_d_147 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_153;
+reg dummy_d_148;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
                end
                2'd2: begin
@@ -6290,13 +5736,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
                                                        end else begin
                                                        end
                                                end else begin
@@ -6308,61 +5754,171 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_153 = dummy_s;
+       dummy_d_148 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
 
 // synthesis translate_off
-reg dummy_d_154;
+reg dummy_d_149;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+       if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+               litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+// synthesis translate_off
+       dummy_d_149 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
+assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+
+// synthesis translate_off
+reg dummy_d_150;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine2_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+               end
+       end
+// synthesis translate_off
+       dummy_d_150 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_151;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
+       end
+// synthesis translate_off
+       dummy_d_151 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_152;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine1_state)
+       bankmachine2_next_state <= 4'd0;
+       bankmachine2_next_state <= bankmachine2_state;
+       case (bankmachine2_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               if (litedramcore_bankmachine2_cmd_ready) begin
+                                       bankmachine2_next_state <= 3'd5;
+                               end
+                       end
                end
                2'd2: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               bankmachine2_next_state <= 3'd5;
+                       end
                end
                2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               if (litedramcore_bankmachine2_cmd_ready) begin
+                                       bankmachine2_next_state <= 3'd7;
+                               end
+                       end
                end
                3'd4: begin
+                       if ((~litedramcore_bankmachine2_refresh_req)) begin
+                               bankmachine2_next_state <= 1'd0;
+                       end
                end
                3'd5: begin
+                       bankmachine2_next_state <= 3'd6;
                end
                3'd6: begin
+                       bankmachine2_next_state <= 2'd3;
                end
                3'd7: begin
+                       bankmachine2_next_state <= 4'd8;
                end
                4'd8: begin
+                       bankmachine2_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                               bankmachine2_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine1_req_wdata_ready <= soc_sdram_bankmachine1_cmd_ready;
-                                                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+                                                               bankmachine2_next_state <= 2'd2;
                                                        end
                                                end else begin
+                                                       bankmachine2_next_state <= 1'd1;
                                                end
                                        end else begin
+                                               bankmachine2_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_154 = dummy_s;
+       dummy_d_152 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_155;
+reg dummy_d_153;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
@@ -6380,14 +5936,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
                                                        end else begin
-                                                               soc_sdram_bankmachine1_req_rdata_valid <= soc_sdram_bankmachine1_cmd_ready;
+                                                               litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -6398,16 +5954,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_155 = dummy_s;
+       dummy_d_153 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_156;
+reg dummy_d_154;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_refresh_gnt <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
@@ -6415,8 +5971,8 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine1_twtpcon_ready) begin
-                               soc_sdram_bankmachine1_refresh_gnt <= 1'd1;
+                       if (litedramcore_bankmachine2_twtpcon_ready) begin
+                               litedramcore_bankmachine2_refresh_gnt <= 1'd1;
                        end
                end
                3'd5: begin
@@ -6431,26 +5987,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_156 = dummy_s;
+       dummy_d_154 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_157;
+reg dummy_d_155;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_valid <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine2_cmd_valid <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_cmd_valid <= 1'd1;
                        end
                end
                3'd4: begin
@@ -6464,12 +6020,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       litedramcore_bankmachine2_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -6479,23 +6035,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_157 = dummy_s;
+       dummy_d_155 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_158;
+reg dummy_d_156;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_row_open <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               soc_sdram_bankmachine1_row_open <= 1'd1;
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
                        end
                end
                3'd4: begin
@@ -6512,26 +6068,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_158 = dummy_s;
+       dummy_d_156 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_159;
+reg dummy_d_157;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_row_close <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine2_row_open <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       soc_sdram_bankmachine1_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_sdram_bankmachine1_row_close <= 1'd1;
                end
                2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_row_open <= 1'd1;
+                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine1_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -6545,23 +6101,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_159 = dummy_s;
+       dummy_d_157 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_160;
+reg dummy_d_158;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine2_row_close <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
+                       litedramcore_bankmachine2_row_close <= 1'd1;
                end
                2'd2: begin
+                       litedramcore_bankmachine2_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       litedramcore_bankmachine2_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -6572,42 +6131,24 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       soc_sdram_bankmachine1_cmd_payload_cas <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_160 = dummy_s;
+       dummy_d_158 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_161;
+reg dummy_d_159;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -6620,177 +6161,70 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_161 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine2_req_valid;
-assign soc_sdram_bankmachine2_req_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine2_req_we;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine2_req_addr;
-assign soc_sdram_bankmachine2_cmd_buffer_sink_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine2_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine2_cmd_buffer_sink_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine2_cmd_buffer_sink_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine2_cmd_buffer_source_ready = (soc_sdram_bankmachine2_req_wdata_ready | soc_sdram_bankmachine2_req_rdata_valid);
-assign soc_sdram_bankmachine2_req_lock = (soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine2_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine2_row_hit = (soc_sdram_bankmachine2_row == soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
-assign soc_sdram_bankmachine2_cmd_payload_ba = 2'd2;
-
-// synthesis translate_off
-reg dummy_d_162;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_a <= 14'd0;
-       if (soc_sdram_bankmachine2_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine2_cmd_payload_a <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
-       end else begin
-               soc_sdram_bankmachine2_cmd_payload_a <= ((soc_sdram_bankmachine2_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-       end
-// synthesis translate_off
-       dummy_d_162 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine2_twtpcon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_cmd_payload_is_write);
-assign soc_sdram_bankmachine2_trccon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open);
-assign soc_sdram_bankmachine2_trascon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open);
-
-// synthesis translate_off
-reg dummy_d_163;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine2_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine2_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
-                       soc_sdram_bankmachine2_auto_precharge <= (soc_sdram_bankmachine2_row_close == 1'd0);
-               end
-       end
-// synthesis translate_off
-       dummy_d_163 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_164;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
-       end else begin
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine2_cmd_buffer_lookahead_produce;
-       end
-// synthesis translate_off
-       dummy_d_164 = dummy_s;
+       dummy_d_159 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_sdram_bankmachine2_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine2_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine2_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_165;
+reg dummy_d_160;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine2_next_state <= 4'd0;
-       vns_bankmachine2_next_state <= vns_bankmachine2_state;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               if (soc_sdram_bankmachine2_cmd_ready) begin
-                                       vns_bankmachine2_next_state <= 3'd5;
-                               end
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               vns_bankmachine2_next_state <= 3'd5;
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               if (soc_sdram_bankmachine2_cmd_ready) begin
-                                       vns_bankmachine2_next_state <= 3'd7;
-                               end
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine2_refresh_req)) begin
-                               vns_bankmachine2_next_state <= 1'd0;
-                       end
                end
                3'd5: begin
-                       vns_bankmachine2_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine2_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine2_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine2_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
-                               vns_bankmachine2_next_state <= 3'd4;
-                       end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if ((soc_sdram_bankmachine2_cmd_ready & soc_sdram_bankmachine2_auto_precharge)) begin
-                                                               vns_bankmachine2_next_state <= 2'd2;
-                                                       end
-                                               end else begin
-                                                       vns_bankmachine2_next_state <= 1'd1;
-                                               end
-                                       end else begin
-                                               vns_bankmachine2_next_state <= 2'd3;
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_165 = dummy_s;
+       dummy_d_160 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_166;
+reg dummy_d_161;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               soc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
                        end
                end
                2'd2: begin
@@ -6808,13 +6242,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -6826,26 +6260,30 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_166 = dummy_s;
+       dummy_d_161 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_167;
+reg dummy_d_162;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -6859,30 +6297,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_167 = dummy_s;
+       dummy_d_162 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_168;
+reg dummy_d_163;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -6893,19 +6324,34 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_168 = dummy_s;
+       dummy_d_163 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_169;
+reg dummy_d_164;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
@@ -6923,14 +6369,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
                                                        end else begin
-                                                               soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
                                                        end
                                                end else begin
                                                end
@@ -6941,16 +6387,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_169 = dummy_s;
+       dummy_d_164 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_170;
+reg dummy_d_165;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
@@ -6968,13 +6414,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
                                                        end else begin
                                                        end
                                                end else begin
@@ -6986,61 +6432,171 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_170 = dummy_s;
+       dummy_d_165 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
 
 // synthesis translate_off
-reg dummy_d_171;
+reg dummy_d_166;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
+       if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+               litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+// synthesis translate_off
+       dummy_d_166 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
+assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+
+// synthesis translate_off
+reg dummy_d_167;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine3_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+               end
+       end
+// synthesis translate_off
+       dummy_d_167 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_168;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
+       end
+// synthesis translate_off
+       dummy_d_168 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_169;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine2_state)
+       bankmachine3_next_state <= 4'd0;
+       bankmachine3_next_state <= bankmachine3_state;
+       case (bankmachine3_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               if (litedramcore_bankmachine3_cmd_ready) begin
+                                       bankmachine3_next_state <= 3'd5;
+                               end
+                       end
                end
                2'd2: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               bankmachine3_next_state <= 3'd5;
+                       end
                end
                2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               if (litedramcore_bankmachine3_cmd_ready) begin
+                                       bankmachine3_next_state <= 3'd7;
+                               end
+                       end
                end
                3'd4: begin
+                       if ((~litedramcore_bankmachine3_refresh_req)) begin
+                               bankmachine3_next_state <= 1'd0;
+                       end
                end
                3'd5: begin
+                       bankmachine3_next_state <= 3'd6;
                end
                3'd6: begin
+                       bankmachine3_next_state <= 2'd3;
                end
                3'd7: begin
+                       bankmachine3_next_state <= 4'd8;
                end
                4'd8: begin
+                       bankmachine3_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                               bankmachine3_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine2_req_wdata_ready <= soc_sdram_bankmachine2_cmd_ready;
-                                                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+                                                               bankmachine3_next_state <= 2'd2;
                                                        end
                                                end else begin
+                                                       bankmachine3_next_state <= 1'd1;
                                                end
                                        end else begin
+                                               bankmachine3_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_171 = dummy_s;
+       dummy_d_169 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_172;
+reg dummy_d_170;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
@@ -7058,14 +6614,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
                                                        end else begin
-                                                               soc_sdram_bankmachine2_req_rdata_valid <= soc_sdram_bankmachine2_cmd_ready;
+                                                               litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -7076,16 +6632,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_172 = dummy_s;
+       dummy_d_170 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_173;
+reg dummy_d_171;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_refresh_gnt <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
@@ -7093,8 +6649,8 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine2_twtpcon_ready) begin
-                               soc_sdram_bankmachine2_refresh_gnt <= 1'd1;
+                       if (litedramcore_bankmachine3_twtpcon_ready) begin
+                               litedramcore_bankmachine3_refresh_gnt <= 1'd1;
                        end
                end
                3'd5: begin
@@ -7109,26 +6665,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_173 = dummy_s;
+       dummy_d_171 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_174;
+reg dummy_d_172;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_valid <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine3_cmd_valid <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               soc_sdram_bankmachine2_cmd_valid <= 1'd1;
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               soc_sdram_bankmachine2_cmd_valid <= 1'd1;
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_cmd_valid <= 1'd1;
                        end
                end
                3'd4: begin
@@ -7142,12 +6698,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       soc_sdram_bankmachine2_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       litedramcore_bankmachine3_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -7157,23 +6713,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_174 = dummy_s;
+       dummy_d_172 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_175;
+reg dummy_d_173;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_row_open <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine3_row_open <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               soc_sdram_bankmachine2_row_open <= 1'd1;
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_row_open <= 1'd1;
                        end
                end
                3'd4: begin
@@ -7190,26 +6746,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_175 = dummy_s;
+       dummy_d_173 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_176;
+reg dummy_d_174;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_row_close <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine3_row_close <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       soc_sdram_bankmachine2_row_close <= 1'd1;
+                       litedramcore_bankmachine3_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_sdram_bankmachine2_row_close <= 1'd1;
+                       litedramcore_bankmachine3_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine2_row_close <= 1'd1;
+                       litedramcore_bankmachine3_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -7223,16 +6779,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_176 = dummy_s;
+       dummy_d_174 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_177;
+reg dummy_d_175;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
@@ -7250,12 +6806,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       soc_sdram_bankmachine2_cmd_payload_cas <= 1'd1;
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -7265,26 +6821,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_177 = dummy_s;
+       dummy_d_175 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_178;
+reg dummy_d_176;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
                        end
                end
                3'd4: begin
@@ -7301,174 +6854,55 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_178 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine3_req_valid;
-assign soc_sdram_bankmachine3_req_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine3_req_we;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine3_req_addr;
-assign soc_sdram_bankmachine3_cmd_buffer_sink_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine3_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine3_cmd_buffer_sink_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine3_cmd_buffer_sink_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine3_cmd_buffer_source_ready = (soc_sdram_bankmachine3_req_wdata_ready | soc_sdram_bankmachine3_req_rdata_valid);
-assign soc_sdram_bankmachine3_req_lock = (soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine3_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine3_row_hit = (soc_sdram_bankmachine3_row == soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
-assign soc_sdram_bankmachine3_cmd_payload_ba = 2'd3;
-
-// synthesis translate_off
-reg dummy_d_179;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_a <= 14'd0;
-       if (soc_sdram_bankmachine3_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine3_cmd_payload_a <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
-       end else begin
-               soc_sdram_bankmachine3_cmd_payload_a <= ((soc_sdram_bankmachine3_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-       end
-// synthesis translate_off
-       dummy_d_179 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine3_twtpcon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_cmd_payload_is_write);
-assign soc_sdram_bankmachine3_trccon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open);
-assign soc_sdram_bankmachine3_trascon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open);
-
-// synthesis translate_off
-reg dummy_d_180;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine3_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine3_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
-                       soc_sdram_bankmachine3_auto_precharge <= (soc_sdram_bankmachine3_row_close == 1'd0);
-               end
-       end
-// synthesis translate_off
-       dummy_d_180 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_181;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
-       end else begin
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine3_cmd_buffer_lookahead_produce;
-       end
-// synthesis translate_off
-       dummy_d_181 = dummy_s;
+       dummy_d_176 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_sdram_bankmachine3_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine3_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine3_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_182;
+reg dummy_d_177;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine3_next_state <= 4'd0;
-       vns_bankmachine3_next_state <= vns_bankmachine3_state;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               if (soc_sdram_bankmachine3_cmd_ready) begin
-                                       vns_bankmachine3_next_state <= 3'd5;
-                               end
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               vns_bankmachine3_next_state <= 3'd5;
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               if (soc_sdram_bankmachine3_cmd_ready) begin
-                                       vns_bankmachine3_next_state <= 3'd7;
-                               end
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine3_refresh_req)) begin
-                               vns_bankmachine3_next_state <= 1'd0;
-                       end
                end
                3'd5: begin
-                       vns_bankmachine3_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine3_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine3_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine3_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
-                               vns_bankmachine3_next_state <= 3'd4;
-                       end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if ((soc_sdram_bankmachine3_cmd_ready & soc_sdram_bankmachine3_auto_precharge)) begin
-                                                               vns_bankmachine3_next_state <= 2'd2;
-                                                       end
-                                               end else begin
-                                                       vns_bankmachine3_next_state <= 1'd1;
-                                               end
-                                       end else begin
-                                               vns_bankmachine3_next_state <= 2'd3;
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_182 = dummy_s;
+       dummy_d_177 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_183;
+reg dummy_d_178;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               soc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
                        end
                end
                2'd2: begin
@@ -7486,13 +6920,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -7504,26 +6938,30 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_183 = dummy_s;
+       dummy_d_178 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_184;
+reg dummy_d_179;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -7537,30 +6975,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_184 = dummy_s;
+       dummy_d_179 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_185;
+reg dummy_d_180;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -7571,19 +7002,34 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_185 = dummy_s;
+       dummy_d_180 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_186;
+reg dummy_d_181;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
@@ -7601,14 +7047,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
                                                        end else begin
-                                                               soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
                                                        end
                                                end else begin
                                                end
@@ -7619,16 +7065,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_186 = dummy_s;
+       dummy_d_181 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_187;
+reg dummy_d_182;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
@@ -7646,13 +7092,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
                                                        end else begin
                                                        end
                                                end else begin
@@ -7664,61 +7110,171 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_187 = dummy_s;
+       dummy_d_182 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
 
 // synthesis translate_off
-reg dummy_d_188;
+reg dummy_d_183;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
+       if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+               litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+// synthesis translate_off
+       dummy_d_183 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
+assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+
+// synthesis translate_off
+reg dummy_d_184;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine4_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+               end
+       end
+// synthesis translate_off
+       dummy_d_184 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_185;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
+       end
+// synthesis translate_off
+       dummy_d_185 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_186;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine3_state)
+       bankmachine4_next_state <= 4'd0;
+       bankmachine4_next_state <= bankmachine4_state;
+       case (bankmachine4_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               if (litedramcore_bankmachine4_cmd_ready) begin
+                                       bankmachine4_next_state <= 3'd5;
+                               end
+                       end
                end
                2'd2: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               bankmachine4_next_state <= 3'd5;
+                       end
                end
                2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               if (litedramcore_bankmachine4_cmd_ready) begin
+                                       bankmachine4_next_state <= 3'd7;
+                               end
+                       end
                end
                3'd4: begin
+                       if ((~litedramcore_bankmachine4_refresh_req)) begin
+                               bankmachine4_next_state <= 1'd0;
+                       end
                end
                3'd5: begin
+                       bankmachine4_next_state <= 3'd6;
                end
                3'd6: begin
+                       bankmachine4_next_state <= 2'd3;
                end
                3'd7: begin
+                       bankmachine4_next_state <= 4'd8;
                end
                4'd8: begin
+                       bankmachine4_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                               bankmachine4_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine3_req_wdata_ready <= soc_sdram_bankmachine3_cmd_ready;
-                                                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+                                                               bankmachine4_next_state <= 2'd2;
                                                        end
                                                end else begin
+                                                       bankmachine4_next_state <= 1'd1;
                                                end
                                        end else begin
+                                               bankmachine4_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_188 = dummy_s;
+       dummy_d_186 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_189;
+reg dummy_d_187;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
@@ -7736,14 +7292,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
                                                        end else begin
-                                                               soc_sdram_bankmachine3_req_rdata_valid <= soc_sdram_bankmachine3_cmd_ready;
+                                                               litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -7754,16 +7310,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_189 = dummy_s;
+       dummy_d_187 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_190;
+reg dummy_d_188;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_refresh_gnt <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
@@ -7771,8 +7327,8 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine3_twtpcon_ready) begin
-                               soc_sdram_bankmachine3_refresh_gnt <= 1'd1;
+                       if (litedramcore_bankmachine4_twtpcon_ready) begin
+                               litedramcore_bankmachine4_refresh_gnt <= 1'd1;
                        end
                end
                3'd5: begin
@@ -7787,26 +7343,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_190 = dummy_s;
+       dummy_d_188 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_191;
+reg dummy_d_189;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_valid <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine4_cmd_valid <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               soc_sdram_bankmachine3_cmd_valid <= 1'd1;
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               soc_sdram_bankmachine3_cmd_valid <= 1'd1;
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_cmd_valid <= 1'd1;
                        end
                end
                3'd4: begin
@@ -7820,12 +7376,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       soc_sdram_bankmachine3_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       litedramcore_bankmachine4_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -7835,23 +7391,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_191 = dummy_s;
+       dummy_d_189 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_192;
+reg dummy_d_190;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_row_open <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine4_row_open <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               soc_sdram_bankmachine3_row_open <= 1'd1;
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_row_open <= 1'd1;
                        end
                end
                3'd4: begin
@@ -7868,26 +7424,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_192 = dummy_s;
+       dummy_d_190 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_193;
+reg dummy_d_191;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_row_close <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine4_row_close <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       soc_sdram_bankmachine3_row_close <= 1'd1;
+                       litedramcore_bankmachine4_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_sdram_bankmachine3_row_close <= 1'd1;
+                       litedramcore_bankmachine4_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine3_row_close <= 1'd1;
+                       litedramcore_bankmachine4_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -7901,16 +7457,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_193 = dummy_s;
+       dummy_d_191 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_194;
+reg dummy_d_192;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
@@ -7928,12 +7484,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       soc_sdram_bankmachine3_cmd_payload_cas <= 1'd1;
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -7943,26 +7499,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_194 = dummy_s;
+       dummy_d_192 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_195;
+reg dummy_d_193;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
@@ -7979,181 +7535,78 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_195 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine4_req_valid;
-assign soc_sdram_bankmachine4_req_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine4_req_we;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine4_req_addr;
-assign soc_sdram_bankmachine4_cmd_buffer_sink_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine4_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine4_cmd_buffer_sink_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine4_cmd_buffer_sink_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine4_cmd_buffer_source_ready = (soc_sdram_bankmachine4_req_wdata_ready | soc_sdram_bankmachine4_req_rdata_valid);
-assign soc_sdram_bankmachine4_req_lock = (soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine4_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine4_row_hit = (soc_sdram_bankmachine4_row == soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
-assign soc_sdram_bankmachine4_cmd_payload_ba = 3'd4;
-
-// synthesis translate_off
-reg dummy_d_196;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_a <= 14'd0;
-       if (soc_sdram_bankmachine4_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine4_cmd_payload_a <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
-       end else begin
-               soc_sdram_bankmachine4_cmd_payload_a <= ((soc_sdram_bankmachine4_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-       end
-// synthesis translate_off
-       dummy_d_196 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine4_twtpcon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_cmd_payload_is_write);
-assign soc_sdram_bankmachine4_trccon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open);
-assign soc_sdram_bankmachine4_trascon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open);
-
-// synthesis translate_off
-reg dummy_d_197;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine4_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine4_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
-                       soc_sdram_bankmachine4_auto_precharge <= (soc_sdram_bankmachine4_row_close == 1'd0);
-               end
-       end
-// synthesis translate_off
-       dummy_d_197 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_198;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
-       end else begin
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine4_cmd_buffer_lookahead_produce;
-       end
-// synthesis translate_off
-       dummy_d_198 = dummy_s;
+       dummy_d_193 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_sdram_bankmachine4_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine4_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine4_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_199;
+reg dummy_d_194;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine4_next_state <= 4'd0;
-       vns_bankmachine4_next_state <= vns_bankmachine4_state;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               if (soc_sdram_bankmachine4_cmd_ready) begin
-                                       vns_bankmachine4_next_state <= 3'd5;
-                               end
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               vns_bankmachine4_next_state <= 3'd5;
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               if (soc_sdram_bankmachine4_cmd_ready) begin
-                                       vns_bankmachine4_next_state <= 3'd7;
-                               end
-                       end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine4_refresh_req)) begin
-                               vns_bankmachine4_next_state <= 1'd0;
-                       end
                end
                3'd5: begin
-                       vns_bankmachine4_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine4_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine4_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine4_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
-                               vns_bankmachine4_next_state <= 3'd4;
+                       if (litedramcore_bankmachine4_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if ((soc_sdram_bankmachine4_cmd_ready & soc_sdram_bankmachine4_auto_precharge)) begin
-                                                               vns_bankmachine4_next_state <= 2'd2;
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                                                       end else begin
                                                        end
                                                end else begin
-                                                       vns_bankmachine4_next_state <= 1'd1;
                                                end
                                        end else begin
-                                               vns_bankmachine4_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_199 = dummy_s;
+       dummy_d_194 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_200;
+reg dummy_d_195;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               soc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                3'd4: begin
+                       litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -8164,42 +7617,24 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_200 = dummy_s;
+       dummy_d_195 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_201;
+reg dummy_d_196;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -8212,33 +7647,44 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_201 = dummy_s;
+       dummy_d_196 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_202;
+reg dummy_d_197;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -8252,16 +7698,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_202 = dummy_s;
+       dummy_d_197 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_203;
+reg dummy_d_198;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
@@ -8279,14 +7725,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
                                                        end else begin
-                                                               soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd1;
                                                        end
                                                end else begin
                                                end
@@ -8297,16 +7743,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_203 = dummy_s;
+       dummy_d_198 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_204;
+reg dummy_d_199;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
@@ -8324,13 +7770,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd1;
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
                                                        end else begin
                                                        end
                                                end else begin
@@ -8342,61 +7788,171 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_204 = dummy_s;
+       dummy_d_199 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
 
 // synthesis translate_off
-reg dummy_d_205;
+reg dummy_d_200;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
+       if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+               litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+// synthesis translate_off
+       dummy_d_200 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
+assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+
+// synthesis translate_off
+reg dummy_d_201;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine5_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+               end
+       end
+// synthesis translate_off
+       dummy_d_201 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_202;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
+       end
+// synthesis translate_off
+       dummy_d_202 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_203;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine4_state)
+       bankmachine5_next_state <= 4'd0;
+       bankmachine5_next_state <= bankmachine5_state;
+       case (bankmachine5_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               if (litedramcore_bankmachine5_cmd_ready) begin
+                                       bankmachine5_next_state <= 3'd5;
+                               end
+                       end
                end
                2'd2: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               bankmachine5_next_state <= 3'd5;
+                       end
                end
                2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               if (litedramcore_bankmachine5_cmd_ready) begin
+                                       bankmachine5_next_state <= 3'd7;
+                               end
+                       end
                end
                3'd4: begin
+                       if ((~litedramcore_bankmachine5_refresh_req)) begin
+                               bankmachine5_next_state <= 1'd0;
+                       end
                end
                3'd5: begin
+                       bankmachine5_next_state <= 3'd6;
                end
                3'd6: begin
+                       bankmachine5_next_state <= 2'd3;
                end
                3'd7: begin
+                       bankmachine5_next_state <= 4'd8;
                end
                4'd8: begin
+                       bankmachine5_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                               bankmachine5_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine4_req_wdata_ready <= soc_sdram_bankmachine4_cmd_ready;
-                                                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+                                                               bankmachine5_next_state <= 2'd2;
                                                        end
                                                end else begin
+                                                       bankmachine5_next_state <= 1'd1;
                                                end
                                        end else begin
+                                               bankmachine5_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_205 = dummy_s;
+       dummy_d_203 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_206;
+reg dummy_d_204;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
                end
                2'd2: begin
@@ -8414,14 +7970,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
                                                        end else begin
-                                                               soc_sdram_bankmachine4_req_rdata_valid <= soc_sdram_bankmachine4_cmd_ready;
+                                                               litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -8432,16 +7988,49 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_206 = dummy_s;
+       dummy_d_204 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_207;
+reg dummy_d_205;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+// synthesis translate_off
+       dummy_d_205 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_206;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_refresh_gnt <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
                end
                2'd2: begin
@@ -8449,8 +8038,8 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine4_twtpcon_ready) begin
-                               soc_sdram_bankmachine4_refresh_gnt <= 1'd1;
+                       if (litedramcore_bankmachine5_twtpcon_ready) begin
+                               litedramcore_bankmachine5_refresh_gnt <= 1'd1;
                        end
                end
                3'd5: begin
@@ -8465,26 +8054,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_207 = dummy_s;
+       dummy_d_206 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_208;
+reg dummy_d_207;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_valid <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine5_cmd_valid <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               soc_sdram_bankmachine4_cmd_valid <= 1'd1;
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               soc_sdram_bankmachine4_cmd_valid <= 1'd1;
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_cmd_valid <= 1'd1;
                        end
                end
                3'd4: begin
@@ -8498,12 +8087,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       soc_sdram_bankmachine4_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       litedramcore_bankmachine5_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -8513,23 +8102,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_208 = dummy_s;
+       dummy_d_207 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_209;
+reg dummy_d_208;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_row_open <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine5_row_open <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               soc_sdram_bankmachine4_row_open <= 1'd1;
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_row_open <= 1'd1;
                        end
                end
                3'd4: begin
@@ -8546,26 +8135,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_209 = dummy_s;
+       dummy_d_208 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_210;
+reg dummy_d_209;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_row_close <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine5_row_close <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       soc_sdram_bankmachine4_row_close <= 1'd1;
+                       litedramcore_bankmachine5_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_sdram_bankmachine4_row_close <= 1'd1;
+                       litedramcore_bankmachine5_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine4_row_close <= 1'd1;
+                       litedramcore_bankmachine5_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -8579,16 +8168,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_210 = dummy_s;
+       dummy_d_209 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_211;
+reg dummy_d_210;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
                end
                2'd2: begin
@@ -8606,12 +8195,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       soc_sdram_bankmachine4_cmd_payload_cas <= 1'd1;
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -8621,26 +8210,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_211 = dummy_s;
+       dummy_d_210 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_212;
+reg dummy_d_211;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
@@ -8657,176 +8246,103 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_212 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine5_req_valid;
-assign soc_sdram_bankmachine5_req_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine5_req_we;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine5_req_addr;
-assign soc_sdram_bankmachine5_cmd_buffer_sink_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine5_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine5_cmd_buffer_sink_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine5_cmd_buffer_sink_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine5_cmd_buffer_source_ready = (soc_sdram_bankmachine5_req_wdata_ready | soc_sdram_bankmachine5_req_rdata_valid);
-assign soc_sdram_bankmachine5_req_lock = (soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine5_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine5_row_hit = (soc_sdram_bankmachine5_row == soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
-assign soc_sdram_bankmachine5_cmd_payload_ba = 3'd5;
-
-// synthesis translate_off
-reg dummy_d_213;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_a <= 14'd0;
-       if (soc_sdram_bankmachine5_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine5_cmd_payload_a <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
-       end else begin
-               soc_sdram_bankmachine5_cmd_payload_a <= ((soc_sdram_bankmachine5_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-       end
-// synthesis translate_off
-       dummy_d_213 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine5_twtpcon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_cmd_payload_is_write);
-assign soc_sdram_bankmachine5_trccon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open);
-assign soc_sdram_bankmachine5_trascon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open);
-
-// synthesis translate_off
-reg dummy_d_214;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine5_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine5_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
-                       soc_sdram_bankmachine5_auto_precharge <= (soc_sdram_bankmachine5_row_close == 1'd0);
-               end
-       end
-// synthesis translate_off
-       dummy_d_214 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_215;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
-       end else begin
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine5_cmd_buffer_lookahead_produce;
-       end
-// synthesis translate_off
-       dummy_d_215 = dummy_s;
+       dummy_d_211 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_sdram_bankmachine5_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine5_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine5_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_216;
+reg dummy_d_212;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine5_next_state <= 4'd0;
-       vns_bankmachine5_next_state <= vns_bankmachine5_state;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               if (soc_sdram_bankmachine5_cmd_ready) begin
-                                       vns_bankmachine5_next_state <= 3'd5;
-                               end
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               vns_bankmachine5_next_state <= 3'd5;
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               if (soc_sdram_bankmachine5_cmd_ready) begin
-                                       vns_bankmachine5_next_state <= 3'd7;
-                               end
-                       end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine5_refresh_req)) begin
-                               vns_bankmachine5_next_state <= 1'd0;
-                       end
                end
                3'd5: begin
-                       vns_bankmachine5_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine5_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine5_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine5_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
-                               vns_bankmachine5_next_state <= 3'd4;
+                       if (litedramcore_bankmachine5_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if ((soc_sdram_bankmachine5_cmd_ready & soc_sdram_bankmachine5_auto_precharge)) begin
-                                                               vns_bankmachine5_next_state <= 2'd2;
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                                                       end else begin
                                                        end
                                                end else begin
-                                                       vns_bankmachine5_next_state <= 1'd1;
                                                end
                                        end else begin
-                                               vns_bankmachine5_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_216 = dummy_s;
+       dummy_d_212 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_217;
+reg dummy_d_213;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               soc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
                        end
                end
+               3'd4: begin
+                       litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
+       endcase
+// synthesis translate_off
+       dummy_d_213 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_214;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+       case (bankmachine5_state)
+               1'd1: begin
+               end
                2'd2: begin
                end
                2'd3: begin
@@ -8842,14 +8358,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
                                                        end else begin
+                                                               litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
                                                        end
                                                end else begin
                                                end
@@ -8860,24 +8376,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_217 = dummy_s;
+       dummy_d_214 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_218;
+reg dummy_d_215;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -8890,33 +8403,41 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_218 = dummy_s;
+       dummy_d_215 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_219;
+reg dummy_d_216;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -8927,48 +8448,173 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
+// synthesis translate_off
+       dummy_d_216 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
+
+// synthesis translate_off
+reg dummy_d_217;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
+       if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+               litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+// synthesis translate_off
+       dummy_d_217 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
+assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+
+// synthesis translate_off
+reg dummy_d_218;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine6_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+               end
+       end
+// synthesis translate_off
+       dummy_d_218 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_219;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
+       end
 // synthesis translate_off
        dummy_d_219 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
 
 // synthesis translate_off
 reg dummy_d_220;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine5_state)
+       bankmachine6_next_state <= 4'd0;
+       bankmachine6_next_state <= bankmachine6_state;
+       case (bankmachine6_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               if (litedramcore_bankmachine6_cmd_ready) begin
+                                       bankmachine6_next_state <= 3'd5;
+                               end
+                       end
                end
                2'd2: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               bankmachine6_next_state <= 3'd5;
+                       end
                end
                2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               if (litedramcore_bankmachine6_cmd_ready) begin
+                                       bankmachine6_next_state <= 3'd7;
+                               end
+                       end
                end
                3'd4: begin
+                       if ((~litedramcore_bankmachine6_refresh_req)) begin
+                               bankmachine6_next_state <= 1'd0;
+                       end
                end
                3'd5: begin
+                       bankmachine6_next_state <= 3'd6;
                end
                3'd6: begin
+                       bankmachine6_next_state <= 2'd3;
                end
                3'd7: begin
+                       bankmachine6_next_state <= 4'd8;
                end
                4'd8: begin
+                       bankmachine6_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                               bankmachine6_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd1;
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+                                                               bankmachine6_next_state <= 2'd2;
                                                        end
                                                end else begin
+                                                       bankmachine6_next_state <= 1'd1;
                                                end
                                        end else begin
+                                               bankmachine6_next_state <= 2'd3;
                                        end
                                end
                        end
@@ -8983,8 +8629,8 @@ end
 reg dummy_d_221;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
@@ -9002,14 +8648,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd1;
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
                                                        end else begin
+                                                               litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -9028,8 +8674,8 @@ end
 reg dummy_d_222;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
@@ -9037,6 +8683,9 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
+                       if (litedramcore_bankmachine6_twtpcon_ready) begin
+                               litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -9047,21 +8696,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine5_req_wdata_ready <= soc_sdram_bankmachine5_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -9073,13 +8707,19 @@ end
 reg dummy_d_223;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine6_cmd_valid <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -9092,15 +8732,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine5_req_rdata_valid <= soc_sdram_bankmachine5_cmd_ready;
-                                                       end
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       litedramcore_bankmachine6_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -9118,18 +8755,18 @@ end
 reg dummy_d_224;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_refresh_gnt <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine5_twtpcon_ready) begin
-                               soc_sdram_bankmachine5_refresh_gnt <= 1'd1;
-                       end
                end
                3'd5: begin
                end
@@ -9151,18 +8788,15 @@ end
 reg dummy_d_225;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_valid <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine6_row_open <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               soc_sdram_bankmachine5_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               soc_sdram_bankmachine5_cmd_valid <= 1'd1;
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_row_open <= 1'd1;
                        end
                end
                3'd4: begin
@@ -9176,18 +8810,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       soc_sdram_bankmachine5_cmd_valid <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -9199,18 +8821,18 @@ end
 reg dummy_d_226;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_row_open <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine6_row_close <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
+                       litedramcore_bankmachine6_row_close <= 1'd1;
                end
                2'd2: begin
+                       litedramcore_bankmachine6_row_close <= 1'd1;
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               soc_sdram_bankmachine5_row_open <= 1'd1;
-                       end
                end
                3'd4: begin
+                       litedramcore_bankmachine6_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -9232,18 +8854,15 @@ end
 reg dummy_d_227;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_row_close <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
-                       soc_sdram_bankmachine5_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_sdram_bankmachine5_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine5_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -9254,6 +8873,18 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -9265,13 +8896,19 @@ end
 reg dummy_d_228;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -9284,18 +8921,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       soc_sdram_bankmachine5_cmd_payload_cas <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -9307,19 +8932,16 @@ end
 reg dummy_d_229;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -9332,178 +8954,72 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
        dummy_d_229 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine6_req_valid;
-assign soc_sdram_bankmachine6_req_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine6_req_we;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine6_req_addr;
-assign soc_sdram_bankmachine6_cmd_buffer_sink_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine6_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine6_cmd_buffer_sink_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine6_cmd_buffer_sink_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine6_cmd_buffer_source_ready = (soc_sdram_bankmachine6_req_wdata_ready | soc_sdram_bankmachine6_req_rdata_valid);
-assign soc_sdram_bankmachine6_req_lock = (soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine6_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine6_row_hit = (soc_sdram_bankmachine6_row == soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
-assign soc_sdram_bankmachine6_cmd_payload_ba = 3'd6;
 
 // synthesis translate_off
 reg dummy_d_230;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_a <= 14'd0;
-       if (soc_sdram_bankmachine6_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine6_cmd_payload_a <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
-       end else begin
-               soc_sdram_bankmachine6_cmd_payload_a <= ((soc_sdram_bankmachine6_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-       end
-// synthesis translate_off
-       dummy_d_230 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine6_twtpcon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_cmd_payload_is_write);
-assign soc_sdram_bankmachine6_trccon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open);
-assign soc_sdram_bankmachine6_trascon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open);
-
-// synthesis translate_off
-reg dummy_d_231;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine6_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine6_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
-                       soc_sdram_bankmachine6_auto_precharge <= (soc_sdram_bankmachine6_row_close == 1'd0);
-               end
-       end
-// synthesis translate_off
-       dummy_d_231 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_232;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
-       end else begin
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine6_cmd_buffer_lookahead_produce;
-       end
-// synthesis translate_off
-       dummy_d_232 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_sdram_bankmachine6_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine6_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine6_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready);
-
-// synthesis translate_off
-reg dummy_d_233;
-// synthesis translate_on
-always @(*) begin
-       vns_bankmachine6_next_state <= 4'd0;
-       vns_bankmachine6_next_state <= vns_bankmachine6_state;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               if (soc_sdram_bankmachine6_cmd_ready) begin
-                                       vns_bankmachine6_next_state <= 3'd5;
-                               end
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               vns_bankmachine6_next_state <= 3'd5;
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               if (soc_sdram_bankmachine6_cmd_ready) begin
-                                       vns_bankmachine6_next_state <= 3'd7;
-                               end
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine6_refresh_req)) begin
-                               vns_bankmachine6_next_state <= 1'd0;
-                       end
+                       litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
-                       vns_bankmachine6_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine6_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine6_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine6_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
-                               vns_bankmachine6_next_state <= 3'd4;
-                       end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if ((soc_sdram_bankmachine6_cmd_ready & soc_sdram_bankmachine6_auto_precharge)) begin
-                                                               vns_bankmachine6_next_state <= 2'd2;
-                                                       end
-                                               end else begin
-                                                       vns_bankmachine6_next_state <= 1'd1;
-                                               end
-                                       end else begin
-                                               vns_bankmachine6_next_state <= 2'd3;
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_233 = dummy_s;
+       dummy_d_230 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_234;
+reg dummy_d_231;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               soc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
-                       end
                end
                2'd2: begin
                end
@@ -9520,14 +9036,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
                                                        end else begin
+                                                               litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
                                                        end
                                                end else begin
                                                end
@@ -9538,24 +9054,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_234 = dummy_s;
+       dummy_d_231 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_235;
+reg dummy_d_232;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -9568,81 +9081,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_235 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_236;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine6_state)
-               1'd1: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-                       end
-               end
-               3'd4: begin
-                       soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_236 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_237;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine6_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
                                                        end else begin
-                                                               soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd1;
                                                        end
                                                end else begin
                                                end
@@ -9653,16 +9099,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_237 = dummy_s;
+       dummy_d_232 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_238;
+reg dummy_d_233;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
@@ -9680,13 +9126,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd1;
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
                                                        end else begin
                                                        end
                                                end else begin
@@ -9698,61 +9144,171 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_238 = dummy_s;
+       dummy_d_233 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
+assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
 
 // synthesis translate_off
-reg dummy_d_239;
+reg dummy_d_234;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
+       if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+               litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+       end else begin
+               litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
+// synthesis translate_off
+       dummy_d_234 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
+assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+
+// synthesis translate_off
+reg dummy_d_235;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine7_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
+                       litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+               end
+       end
+// synthesis translate_off
+       dummy_d_235 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+
+// synthesis translate_off
+reg dummy_d_236;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
+       end
+// synthesis translate_off
+       dummy_d_236 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_237;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine6_state)
+       bankmachine7_next_state <= 4'd0;
+       bankmachine7_next_state <= bankmachine7_state;
+       case (bankmachine7_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               if (litedramcore_bankmachine7_cmd_ready) begin
+                                       bankmachine7_next_state <= 3'd5;
+                               end
+                       end
                end
                2'd2: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               bankmachine7_next_state <= 3'd5;
+                       end
                end
                2'd3: begin
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               if (litedramcore_bankmachine7_cmd_ready) begin
+                                       bankmachine7_next_state <= 3'd7;
+                               end
+                       end
                end
                3'd4: begin
+                       if ((~litedramcore_bankmachine7_refresh_req)) begin
+                               bankmachine7_next_state <= 1'd0;
+                       end
                end
                3'd5: begin
+                       bankmachine7_next_state <= 3'd6;
                end
                3'd6: begin
+                       bankmachine7_next_state <= 2'd3;
                end
                3'd7: begin
+                       bankmachine7_next_state <= 4'd8;
                end
                4'd8: begin
+                       bankmachine7_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                               bankmachine7_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine6_req_wdata_ready <= soc_sdram_bankmachine6_cmd_ready;
-                                                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+                                                               bankmachine7_next_state <= 2'd2;
                                                        end
                                                end else begin
+                                                       bankmachine7_next_state <= 1'd1;
                                                end
                                        end else begin
+                                               bankmachine7_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_239 = dummy_s;
+       dummy_d_237 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_240;
+reg dummy_d_238;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
@@ -9770,14 +9326,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
                                                        end else begin
-                                                               soc_sdram_bankmachine6_req_rdata_valid <= soc_sdram_bankmachine6_cmd_ready;
+                                                               litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -9788,16 +9344,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_240 = dummy_s;
+       dummy_d_238 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_241;
+reg dummy_d_239;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_refresh_gnt <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
@@ -9805,8 +9361,8 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine6_twtpcon_ready) begin
-                               soc_sdram_bankmachine6_refresh_gnt <= 1'd1;
+                       if (litedramcore_bankmachine7_twtpcon_ready) begin
+                               litedramcore_bankmachine7_refresh_gnt <= 1'd1;
                        end
                end
                3'd5: begin
@@ -9821,26 +9377,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_241 = dummy_s;
+       dummy_d_239 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_242;
+reg dummy_d_240;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_valid <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine7_cmd_valid <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               soc_sdram_bankmachine6_cmd_valid <= 1'd1;
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               soc_sdram_bankmachine6_cmd_valid <= 1'd1;
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_cmd_valid <= 1'd1;
                        end
                end
                3'd4: begin
@@ -9854,12 +9410,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       soc_sdram_bankmachine6_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       litedramcore_bankmachine7_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -9869,23 +9425,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_242 = dummy_s;
+       dummy_d_240 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_243;
+reg dummy_d_241;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_row_open <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine7_row_open <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               soc_sdram_bankmachine6_row_open <= 1'd1;
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_row_open <= 1'd1;
                        end
                end
                3'd4: begin
@@ -9902,26 +9458,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_243 = dummy_s;
+       dummy_d_241 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_244;
+reg dummy_d_242;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_row_close <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine7_row_close <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
-                       soc_sdram_bankmachine6_row_close <= 1'd1;
+                       litedramcore_bankmachine7_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_sdram_bankmachine6_row_close <= 1'd1;
+                       litedramcore_bankmachine7_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine6_row_close <= 1'd1;
+                       litedramcore_bankmachine7_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -9935,16 +9491,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_244 = dummy_s;
+       dummy_d_242 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_245;
+reg dummy_d_243;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
@@ -9962,12 +9518,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       soc_sdram_bankmachine6_cmd_payload_cas <= 1'd1;
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -9977,210 +9533,55 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_245 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_246;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine6_state)
-               1'd1: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
-                       end
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_246 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine7_req_valid;
-assign soc_sdram_bankmachine7_req_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine7_req_we;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine7_req_addr;
-assign soc_sdram_bankmachine7_cmd_buffer_sink_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine7_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine7_cmd_buffer_sink_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine7_cmd_buffer_sink_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine7_cmd_buffer_source_ready = (soc_sdram_bankmachine7_req_wdata_ready | soc_sdram_bankmachine7_req_rdata_valid);
-assign soc_sdram_bankmachine7_req_lock = (soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine7_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine7_row_hit = (soc_sdram_bankmachine7_row == soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
-assign soc_sdram_bankmachine7_cmd_payload_ba = 3'd7;
-
-// synthesis translate_off
-reg dummy_d_247;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_a <= 14'd0;
-       if (soc_sdram_bankmachine7_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine7_cmd_payload_a <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
-       end else begin
-               soc_sdram_bankmachine7_cmd_payload_a <= ((soc_sdram_bankmachine7_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-       end
-// synthesis translate_off
-       dummy_d_247 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine7_twtpcon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_cmd_payload_is_write);
-assign soc_sdram_bankmachine7_trccon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open);
-assign soc_sdram_bankmachine7_trascon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open);
-
-// synthesis translate_off
-reg dummy_d_248;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine7_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine7_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
-                       soc_sdram_bankmachine7_auto_precharge <= (soc_sdram_bankmachine7_row_close == 1'd0);
-               end
-       end
-// synthesis translate_off
-       dummy_d_248 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_249;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
-       end else begin
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine7_cmd_buffer_lookahead_produce;
-       end
-// synthesis translate_off
-       dummy_d_249 = dummy_s;
+       dummy_d_243 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_sdram_bankmachine7_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine7_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine7_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_250;
+reg dummy_d_244;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine7_next_state <= 4'd0;
-       vns_bankmachine7_next_state <= vns_bankmachine7_state;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               if (soc_sdram_bankmachine7_cmd_ready) begin
-                                       vns_bankmachine7_next_state <= 3'd5;
-                               end
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               vns_bankmachine7_next_state <= 3'd5;
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               if (soc_sdram_bankmachine7_cmd_ready) begin
-                                       vns_bankmachine7_next_state <= 3'd7;
-                               end
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine7_refresh_req)) begin
-                               vns_bankmachine7_next_state <= 1'd0;
-                       end
                end
                3'd5: begin
-                       vns_bankmachine7_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine7_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine7_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine7_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
-                               vns_bankmachine7_next_state <= 3'd4;
-                       end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if ((soc_sdram_bankmachine7_cmd_ready & soc_sdram_bankmachine7_auto_precharge)) begin
-                                                               vns_bankmachine7_next_state <= 2'd2;
-                                                       end
-                                               end else begin
-                                                       vns_bankmachine7_next_state <= 1'd1;
-                                               end
-                                       end else begin
-                                               vns_bankmachine7_next_state <= 2'd3;
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_250 = dummy_s;
+       dummy_d_244 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_251;
+reg dummy_d_245;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               soc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                        end
                end
                2'd2: begin
@@ -10198,13 +9599,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -10216,26 +9617,30 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_251 = dummy_s;
+       dummy_d_245 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_252;
+reg dummy_d_246;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1;
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -10249,30 +9654,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_252 = dummy_s;
+       dummy_d_246 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_253;
+reg dummy_d_247;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -10286,16 +9687,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_253 = dummy_s;
+       dummy_d_247 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_254;
+reg dummy_d_248;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
@@ -10313,14 +9714,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
                                                        end else begin
-                                                               soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd1;
+                                                               litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
                                                        end
                                                end else begin
                                                end
@@ -10331,16 +9732,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_254 = dummy_s;
+       dummy_d_248 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_255;
+reg dummy_d_249;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
@@ -10358,13 +9759,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd1;
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -10376,16 +9777,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_255 = dummy_s;
+       dummy_d_249 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_256;
+reg dummy_d_250;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
@@ -10403,13 +9804,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine7_req_wdata_ready <= soc_sdram_bankmachine7_cmd_ready;
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
                                                        end else begin
                                                        end
                                                end else begin
@@ -10421,50 +9822,145 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_256 = dummy_s;
+       dummy_d_250 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
+assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
+assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
+assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
+assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
+assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
+assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
+assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
+assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
 
 // synthesis translate_off
-reg dummy_d_257;
+reg dummy_d_251;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine7_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine7_req_rdata_valid <= soc_sdram_bankmachine7_cmd_ready;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
-               end
-       endcase
+       litedramcore_choose_cmd_valids <= 8'd0;
+       litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+// synthesis translate_off
+       dummy_d_251 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
+assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
+assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
+assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
+
+// synthesis translate_off
+reg dummy_d_252;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+       if (litedramcore_choose_cmd_cmd_valid) begin
+               litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+       end
+// synthesis translate_off
+       dummy_d_252 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_253;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+       if (litedramcore_choose_cmd_cmd_valid) begin
+               litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+       end
+// synthesis translate_off
+       dummy_d_253 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_254;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+       if (litedramcore_choose_cmd_cmd_valid) begin
+               litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+       end
+// synthesis translate_off
+       dummy_d_254 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_255;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine0_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+               litedramcore_bankmachine0_cmd_ready <= 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+               litedramcore_bankmachine0_cmd_ready <= 1'd1;
+       end
+// synthesis translate_off
+       dummy_d_255 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_256;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine1_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+               litedramcore_bankmachine1_cmd_ready <= 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+               litedramcore_bankmachine1_cmd_ready <= 1'd1;
+       end
+// synthesis translate_off
+       dummy_d_256 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_257;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine2_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+               litedramcore_bankmachine2_cmd_ready <= 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+               litedramcore_bankmachine2_cmd_ready <= 1'd1;
+       end
 // synthesis translate_off
        dummy_d_257 = dummy_s;
 // synthesis translate_on
@@ -10474,52 +9970,236 @@ end
 reg dummy_d_258;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_refresh_gnt <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine3_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+               litedramcore_bankmachine3_cmd_ready <= 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+               litedramcore_bankmachine3_cmd_ready <= 1'd1;
+       end
+// synthesis translate_off
+       dummy_d_258 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_259;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine4_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+               litedramcore_bankmachine4_cmd_ready <= 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+               litedramcore_bankmachine4_cmd_ready <= 1'd1;
+       end
+// synthesis translate_off
+       dummy_d_259 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_260;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine5_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+               litedramcore_bankmachine5_cmd_ready <= 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+               litedramcore_bankmachine5_cmd_ready <= 1'd1;
+       end
+// synthesis translate_off
+       dummy_d_260 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_261;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine6_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+               litedramcore_bankmachine6_cmd_ready <= 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+               litedramcore_bankmachine6_cmd_ready <= 1'd1;
+       end
+// synthesis translate_off
+       dummy_d_261 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_262;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_bankmachine7_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+               litedramcore_bankmachine7_cmd_ready <= 1'd1;
+       end
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+               litedramcore_bankmachine7_cmd_ready <= 1'd1;
+       end
+// synthesis translate_off
+       dummy_d_262 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
+
+// synthesis translate_off
+reg dummy_d_263;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_choose_req_valids <= 8'd0;
+       litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+// synthesis translate_off
+       dummy_d_263 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
+assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
+assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
+assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
+assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
+assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
+
+// synthesis translate_off
+reg dummy_d_264;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+       if (litedramcore_choose_req_cmd_valid) begin
+               litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+       end
+// synthesis translate_off
+       dummy_d_264 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_265;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+       if (litedramcore_choose_req_cmd_valid) begin
+               litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+       end
+// synthesis translate_off
+       dummy_d_265 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_266;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_choose_req_cmd_payload_we <= 1'd0;
+       if (litedramcore_choose_req_cmd_valid) begin
+               litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+       end
+// synthesis translate_off
+       dummy_d_266 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
+assign litedramcore_dfi_p0_reset_n = 1'd1;
+assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
+assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
+assign litedramcore_dfi_p1_reset_n = 1'd1;
+assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
+assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
+assign litedramcore_dfi_p2_reset_n = 1'd1;
+assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
+assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
+assign litedramcore_dfi_p3_reset_n = 1'd1;
+assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
+assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
+assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
+
+// synthesis translate_off
+reg dummy_d_267;
+// synthesis translate_on
+always @(*) begin
+       multiplexer_next_state <= 4'd0;
+       multiplexer_next_state <= multiplexer_state;
+       case (multiplexer_state)
                1'd1: begin
+                       if (litedramcore_read_available) begin
+                               if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+                                       multiplexer_next_state <= 2'd3;
+                               end
+                       end
+                       if (litedramcore_go_to_refresh) begin
+                               multiplexer_next_state <= 2'd2;
+                       end
                end
                2'd2: begin
+                       if (litedramcore_cmd_last) begin
+                               multiplexer_next_state <= 1'd0;
+                       end
                end
                2'd3: begin
+                       if (litedramcore_twtrcon_ready) begin
+                               multiplexer_next_state <= 1'd0;
+                       end
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine7_twtpcon_ready) begin
-                               soc_sdram_bankmachine7_refresh_gnt <= 1'd1;
-                       end
+                       multiplexer_next_state <= 3'd5;
                end
                3'd5: begin
+                       multiplexer_next_state <= 3'd6;
                end
                3'd6: begin
+                       multiplexer_next_state <= 3'd7;
                end
                3'd7: begin
+                       multiplexer_next_state <= 4'd8;
                end
                4'd8: begin
+                       multiplexer_next_state <= 4'd9;
+               end
+               4'd9: begin
+                       multiplexer_next_state <= 4'd10;
+               end
+               4'd10: begin
+                       multiplexer_next_state <= 1'd1;
                end
                default: begin
+                       if (litedramcore_write_available) begin
+                               if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+                                       multiplexer_next_state <= 3'd4;
+                               end
+                       end
+                       if (litedramcore_go_to_refresh) begin
+                               multiplexer_next_state <= 2'd2;
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_258 = dummy_s;
+       dummy_d_267 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_259;
+reg dummy_d_268;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_valid <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_en0 <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               soc_sdram_bankmachine7_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               soc_sdram_bankmachine7_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -10531,40 +10211,31 @@ always @(*) begin
                end
                4'd8: begin
                end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       soc_sdram_bankmachine7_cmd_valid <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
+                       litedramcore_en0 <= 1'd1;
                end
        endcase
 // synthesis translate_off
-       dummy_d_259 = dummy_s;
+       dummy_d_268 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_260;
+reg dummy_d_269;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_row_open <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_cmd_ready <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
                end
                2'd2: begin
+                       litedramcore_cmd_ready <= 1'd1;
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               soc_sdram_bankmachine7_row_open <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -10576,30 +10247,35 @@ always @(*) begin
                end
                4'd8: begin
                end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
                default: begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_260 = dummy_s;
+       dummy_d_269 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_261;
+reg dummy_d_270;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_row_close <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_choose_cmd_cmd_ready <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       soc_sdram_bankmachine7_row_close <= 1'd1;
+                       if (1'd0) begin
+                       end else begin
+                               litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                       end
                end
                2'd2: begin
-                       soc_sdram_bankmachine7_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine7_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -10609,20 +10285,28 @@ always @(*) begin
                end
                4'd8: begin
                end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
                default: begin
+                       if (1'd0) begin
+                       end else begin
+                               litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_261 = dummy_s;
+       dummy_d_270 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_262;
+reg dummy_d_271;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_choose_req_want_reads <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
                end
                2'd2: begin
@@ -10639,43 +10323,31 @@ always @(*) begin
                end
                4'd8: begin
                end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       soc_sdram_bankmachine7_cmd_payload_cas <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
+                       litedramcore_choose_req_want_reads <= 1'd1;
                end
        endcase
 // synthesis translate_off
-       dummy_d_262 = dummy_s;
+       dummy_d_271 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_263;
+reg dummy_d_272;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_choose_req_want_writes <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
-                       end
+                       litedramcore_choose_req_want_writes <= 1'd1;
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -10687,423 +10359,31 @@ always @(*) begin
                end
                4'd8: begin
                end
+               4'd9: begin
+               end
+               4'd10: begin
+               end
                default: begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_263 = dummy_s;
+       dummy_d_272 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_trrdcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we)));
-assign soc_sdram_tfawcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we)));
-assign soc_sdram_ras_allowed = (soc_sdram_trrdcon_ready & soc_sdram_tfawcon_ready);
-assign soc_sdram_tccdcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_cmd_payload_is_write | soc_sdram_choose_req_cmd_payload_is_read));
-assign soc_sdram_cas_allowed = soc_sdram_tccdcon_ready;
-assign soc_sdram_twtrcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
-assign soc_sdram_read_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_read) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_read)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_read)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_read)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_read)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_read)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_read)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_read));
-assign soc_sdram_write_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_write) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_write)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_write)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_write)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_write)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_write)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_write)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_write));
-assign soc_sdram_max_time0 = (soc_sdram_time0 == 1'd0);
-assign soc_sdram_max_time1 = (soc_sdram_time1 == 1'd0);
-assign soc_sdram_bankmachine0_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine1_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine2_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine3_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine4_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine5_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine6_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine7_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_go_to_refresh = (((((((soc_sdram_bankmachine0_refresh_gnt & soc_sdram_bankmachine1_refresh_gnt) & soc_sdram_bankmachine2_refresh_gnt) & soc_sdram_bankmachine3_refresh_gnt) & soc_sdram_bankmachine4_refresh_gnt) & soc_sdram_bankmachine5_refresh_gnt) & soc_sdram_bankmachine6_refresh_gnt) & soc_sdram_bankmachine7_refresh_gnt);
-assign soc_sdram_interface_rdata = {soc_sdram_dfi_p3_rddata, soc_sdram_dfi_p2_rddata, soc_sdram_dfi_p1_rddata, soc_sdram_dfi_p0_rddata};
-assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
-assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
-assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
-assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
-assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
-assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
-assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
-assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
 
 // synthesis translate_off
-reg dummy_d_264;
+reg dummy_d_273;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_cmd_valids <= 8'd0;
-       soc_sdram_choose_cmd_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-// synthesis translate_off
-       dummy_d_264 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_choose_cmd_request = soc_sdram_choose_cmd_valids;
-assign soc_sdram_choose_cmd_cmd_valid = vns_rhs_array_muxed0;
-assign soc_sdram_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1;
-assign soc_sdram_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2;
-assign soc_sdram_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3;
-assign soc_sdram_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4;
-assign soc_sdram_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5;
-
-// synthesis translate_off
-reg dummy_d_265;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_cmd_cmd_payload_cas <= 1'd0;
-       if (soc_sdram_choose_cmd_cmd_valid) begin
-               soc_sdram_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0;
-       end
-// synthesis translate_off
-       dummy_d_265 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_266;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_cmd_cmd_payload_ras <= 1'd0;
-       if (soc_sdram_choose_cmd_cmd_valid) begin
-               soc_sdram_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1;
-       end
-// synthesis translate_off
-       dummy_d_266 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_267;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_cmd_cmd_payload_we <= 1'd0;
-       if (soc_sdram_choose_cmd_cmd_valid) begin
-               soc_sdram_choose_cmd_cmd_payload_we <= vns_t_array_muxed2;
-       end
-// synthesis translate_off
-       dummy_d_267 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_268;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine0_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd0))) begin
-               soc_sdram_bankmachine0_cmd_ready <= 1'd1;
-       end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd0))) begin
-               soc_sdram_bankmachine0_cmd_ready <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_268 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_269;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine1_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd1))) begin
-               soc_sdram_bankmachine1_cmd_ready <= 1'd1;
-       end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd1))) begin
-               soc_sdram_bankmachine1_cmd_ready <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_269 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_270;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine2_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd2))) begin
-               soc_sdram_bankmachine2_cmd_ready <= 1'd1;
-       end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd2))) begin
-               soc_sdram_bankmachine2_cmd_ready <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_270 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_271;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine3_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd3))) begin
-               soc_sdram_bankmachine3_cmd_ready <= 1'd1;
-       end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd3))) begin
-               soc_sdram_bankmachine3_cmd_ready <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_271 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_272;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine4_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd4))) begin
-               soc_sdram_bankmachine4_cmd_ready <= 1'd1;
-       end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd4))) begin
-               soc_sdram_bankmachine4_cmd_ready <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_272 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_273;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine5_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd5))) begin
-               soc_sdram_bankmachine5_cmd_ready <= 1'd1;
-       end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd5))) begin
-               soc_sdram_bankmachine5_cmd_ready <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_273 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_274;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine6_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd6))) begin
-               soc_sdram_bankmachine6_cmd_ready <= 1'd1;
-       end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd6))) begin
-               soc_sdram_bankmachine6_cmd_ready <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_274 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_275;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine7_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd7))) begin
-               soc_sdram_bankmachine7_cmd_ready <= 1'd1;
-       end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd7))) begin
-               soc_sdram_bankmachine7_cmd_ready <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_275 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_choose_cmd_ce = (soc_sdram_choose_cmd_cmd_ready | (~soc_sdram_choose_cmd_cmd_valid));
-
-// synthesis translate_off
-reg dummy_d_276;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_req_valids <= 8'd0;
-       soc_sdram_choose_req_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-// synthesis translate_off
-       dummy_d_276 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_choose_req_request = soc_sdram_choose_req_valids;
-assign soc_sdram_choose_req_cmd_valid = vns_rhs_array_muxed6;
-assign soc_sdram_choose_req_cmd_payload_a = vns_rhs_array_muxed7;
-assign soc_sdram_choose_req_cmd_payload_ba = vns_rhs_array_muxed8;
-assign soc_sdram_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9;
-assign soc_sdram_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10;
-assign soc_sdram_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11;
-
-// synthesis translate_off
-reg dummy_d_277;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_req_cmd_payload_cas <= 1'd0;
-       if (soc_sdram_choose_req_cmd_valid) begin
-               soc_sdram_choose_req_cmd_payload_cas <= vns_t_array_muxed3;
-       end
-// synthesis translate_off
-       dummy_d_277 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_278;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_req_cmd_payload_ras <= 1'd0;
-       if (soc_sdram_choose_req_cmd_valid) begin
-               soc_sdram_choose_req_cmd_payload_ras <= vns_t_array_muxed4;
-       end
-// synthesis translate_off
-       dummy_d_278 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_279;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_req_cmd_payload_we <= 1'd0;
-       if (soc_sdram_choose_req_cmd_valid) begin
-               soc_sdram_choose_req_cmd_payload_we <= vns_t_array_muxed5;
-       end
-// synthesis translate_off
-       dummy_d_279 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_choose_req_ce = (soc_sdram_choose_req_cmd_ready | (~soc_sdram_choose_req_cmd_valid));
-assign soc_sdram_dfi_p0_reset_n = 1'd1;
-assign soc_sdram_dfi_p0_cke = {1{soc_sdram_steerer0}};
-assign soc_sdram_dfi_p0_odt = {1{soc_sdram_steerer1}};
-assign soc_sdram_dfi_p1_reset_n = 1'd1;
-assign soc_sdram_dfi_p1_cke = {1{soc_sdram_steerer2}};
-assign soc_sdram_dfi_p1_odt = {1{soc_sdram_steerer3}};
-assign soc_sdram_dfi_p2_reset_n = 1'd1;
-assign soc_sdram_dfi_p2_cke = {1{soc_sdram_steerer4}};
-assign soc_sdram_dfi_p2_odt = {1{soc_sdram_steerer5}};
-assign soc_sdram_dfi_p3_reset_n = 1'd1;
-assign soc_sdram_dfi_p3_cke = {1{soc_sdram_steerer6}};
-assign soc_sdram_dfi_p3_odt = {1{soc_sdram_steerer7}};
-assign soc_sdram_tfawcon_count = ((((soc_sdram_tfawcon_window[0] + soc_sdram_tfawcon_window[1]) + soc_sdram_tfawcon_window[2]) + soc_sdram_tfawcon_window[3]) + soc_sdram_tfawcon_window[4]);
-
-// synthesis translate_off
-reg dummy_d_280;
-// synthesis translate_on
-always @(*) begin
-       vns_multiplexer_next_state <= 4'd0;
-       vns_multiplexer_next_state <= vns_multiplexer_state;
-       case (vns_multiplexer_state)
+       litedramcore_choose_req_cmd_ready <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       if (soc_sdram_read_available) begin
-                               if (((~soc_sdram_write_available) | soc_sdram_max_time1)) begin
-                                       vns_multiplexer_next_state <= 2'd3;
-                               end
-                       end
-                       if (soc_sdram_go_to_refresh) begin
-                               vns_multiplexer_next_state <= 2'd2;
-                       end
-               end
-               2'd2: begin
-                       if (soc_sdram_cmd_last) begin
-                               vns_multiplexer_next_state <= 1'd0;
-                       end
-               end
-               2'd3: begin
-                       if (soc_sdram_twtrcon_ready) begin
-                               vns_multiplexer_next_state <= 1'd0;
-                       end
-               end
-               3'd4: begin
-                       vns_multiplexer_next_state <= 3'd5;
-               end
-               3'd5: begin
-                       vns_multiplexer_next_state <= 3'd6;
-               end
-               3'd6: begin
-                       vns_multiplexer_next_state <= 3'd7;
-               end
-               3'd7: begin
-                       vns_multiplexer_next_state <= 4'd8;
-               end
-               4'd8: begin
-                       vns_multiplexer_next_state <= 4'd9;
-               end
-               4'd9: begin
-                       vns_multiplexer_next_state <= 4'd10;
-               end
-               4'd10: begin
-                       vns_multiplexer_next_state <= 1'd1;
-               end
-               default: begin
-                       if (soc_sdram_write_available) begin
-                               if (((~soc_sdram_read_available) | soc_sdram_max_time0)) begin
-                                       vns_multiplexer_next_state <= 3'd4;
-                               end
-                       end
-                       if (soc_sdram_go_to_refresh) begin
-                               vns_multiplexer_next_state <= 2'd2;
+                       if (1'd0) begin
+                               litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+                       end else begin
+                               litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
                        end
                end
-       endcase
-// synthesis translate_off
-       dummy_d_280 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_281;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_steerer_sel0 <= 2'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       soc_sdram_steerer_sel0 <= 1'd0;
-               end
-               2'd2: begin
-                       soc_sdram_steerer_sel0 <= 2'd3;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       soc_sdram_steerer_sel0 <= 1'd0;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_281 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_282;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_steerer_sel1 <= 2'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       soc_sdram_steerer_sel1 <= 1'd0;
-               end
                2'd2: begin
                end
                2'd3: begin
@@ -11121,4875 +10401,3215 @@ always @(*) begin
                4'd9: begin
                end
                4'd10: begin
-               end
-               default: begin
-                       soc_sdram_steerer_sel1 <= 1'd1;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_282 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_283;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_steerer_sel2 <= 2'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       soc_sdram_steerer_sel2 <= 1'd1;
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       soc_sdram_steerer_sel2 <= 2'd2;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_283 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_284;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_cmd_want_activates <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       if (1'd0) begin
-                       end else begin
-                               soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed;
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       if (1'd0) begin
-                       end else begin
-                               soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_284 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_285;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_steerer_sel3 <= 2'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       soc_sdram_steerer_sel3 <= 2'd2;
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       soc_sdram_steerer_sel3 <= 1'd0;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_285 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_286;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_en0 <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       soc_sdram_en0 <= 1'd1;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_286 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_287;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_cmd_ready <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_sdram_cmd_ready <= 1'd1;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_287 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_288;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_cmd_cmd_ready <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       if (1'd0) begin
-                       end else begin
-                               soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed);
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       if (1'd0) begin
-                       end else begin
-                               soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed);
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_288 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_289;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_req_want_reads <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       soc_sdram_choose_req_want_reads <= 1'd1;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_289 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_290;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_req_want_writes <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       soc_sdram_choose_req_want_writes <= 1'd1;
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_290 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_291;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_en1 <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       soc_sdram_en1 <= 1'd1;
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_291 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_292;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_req_cmd_ready <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       if (1'd0) begin
-                               soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed));
-                       end else begin
-                               soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed;
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       if (1'd0) begin
-                               soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed));
-                       end else begin
-                               soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_292 = dummy_s;
-// synthesis translate_on
-end
-assign vns_roundrobin0_request = {(((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin0_ce = ((~soc_sdram_interface_bank0_valid) & (~soc_sdram_interface_bank0_lock));
-assign soc_sdram_interface_bank0_addr = vns_rhs_array_muxed12;
-assign soc_sdram_interface_bank0_we = vns_rhs_array_muxed13;
-assign soc_sdram_interface_bank0_valid = vns_rhs_array_muxed14;
-assign vns_roundrobin1_request = {(((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin1_ce = ((~soc_sdram_interface_bank1_valid) & (~soc_sdram_interface_bank1_lock));
-assign soc_sdram_interface_bank1_addr = vns_rhs_array_muxed15;
-assign soc_sdram_interface_bank1_we = vns_rhs_array_muxed16;
-assign soc_sdram_interface_bank1_valid = vns_rhs_array_muxed17;
-assign vns_roundrobin2_request = {(((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin2_ce = ((~soc_sdram_interface_bank2_valid) & (~soc_sdram_interface_bank2_lock));
-assign soc_sdram_interface_bank2_addr = vns_rhs_array_muxed18;
-assign soc_sdram_interface_bank2_we = vns_rhs_array_muxed19;
-assign soc_sdram_interface_bank2_valid = vns_rhs_array_muxed20;
-assign vns_roundrobin3_request = {(((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin3_ce = ((~soc_sdram_interface_bank3_valid) & (~soc_sdram_interface_bank3_lock));
-assign soc_sdram_interface_bank3_addr = vns_rhs_array_muxed21;
-assign soc_sdram_interface_bank3_we = vns_rhs_array_muxed22;
-assign soc_sdram_interface_bank3_valid = vns_rhs_array_muxed23;
-assign vns_roundrobin4_request = {(((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin4_ce = ((~soc_sdram_interface_bank4_valid) & (~soc_sdram_interface_bank4_lock));
-assign soc_sdram_interface_bank4_addr = vns_rhs_array_muxed24;
-assign soc_sdram_interface_bank4_we = vns_rhs_array_muxed25;
-assign soc_sdram_interface_bank4_valid = vns_rhs_array_muxed26;
-assign vns_roundrobin5_request = {(((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin5_ce = ((~soc_sdram_interface_bank5_valid) & (~soc_sdram_interface_bank5_lock));
-assign soc_sdram_interface_bank5_addr = vns_rhs_array_muxed27;
-assign soc_sdram_interface_bank5_we = vns_rhs_array_muxed28;
-assign soc_sdram_interface_bank5_valid = vns_rhs_array_muxed29;
-assign vns_roundrobin6_request = {(((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin6_ce = ((~soc_sdram_interface_bank6_valid) & (~soc_sdram_interface_bank6_lock));
-assign soc_sdram_interface_bank6_addr = vns_rhs_array_muxed30;
-assign soc_sdram_interface_bank6_we = vns_rhs_array_muxed31;
-assign soc_sdram_interface_bank6_valid = vns_rhs_array_muxed32;
-assign vns_roundrobin7_request = {(((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin7_ce = ((~soc_sdram_interface_bank7_valid) & (~soc_sdram_interface_bank7_lock));
-assign soc_sdram_interface_bank7_addr = vns_rhs_array_muxed33;
-assign soc_sdram_interface_bank7_we = vns_rhs_array_muxed34;
-assign soc_sdram_interface_bank7_valid = vns_rhs_array_muxed35;
-assign soc_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_sdram_interface_bank7_ready));
-assign soc_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1)))))) & soc_sdram_interface_bank7_ready));
-assign soc_port_wdata_ready = vns_new_master_wdata_ready2;
-assign soc_wdata_ready = vns_new_master_wdata_ready5;
-assign soc_port_rdata_valid = vns_new_master_rdata_valid8;
-assign soc_rdata_valid = vns_new_master_rdata_valid17;
-
-// synthesis translate_off
-reg dummy_d_293;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_interface_wdata <= 128'd0;
-       case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2})
-               1'd1: begin
-                       soc_sdram_interface_wdata <= soc_port_wdata_payload_data;
-               end
-               2'd2: begin
-                       soc_sdram_interface_wdata <= soc_wdata_payload_data;
-               end
-               default: begin
-                       soc_sdram_interface_wdata <= 1'd0;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_293 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_294;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_interface_wdata_we <= 16'd0;
-       case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2})
-               1'd1: begin
-                       soc_sdram_interface_wdata_we <= soc_port_wdata_payload_we;
-               end
-               2'd2: begin
-                       soc_sdram_interface_wdata_we <= soc_wdata_payload_we;
-               end
-               default: begin
-                       soc_sdram_interface_wdata_we <= 1'd0;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_294 = dummy_s;
-// synthesis translate_on
-end
-assign soc_port_rdata_payload_data = soc_sdram_interface_rdata;
-assign soc_rdata_payload_data = soc_sdram_interface_rdata;
-assign soc_address_d = soc_wb_sdram_adr;
-assign soc_counter_offset = soc_address_q;
-assign soc_counter_done = ((soc_counter + soc_counter_offset) == 2'd3);
-assign soc_end_of_burst = ((~soc_wb_sdram_cyc) | (((soc_wb_sdram_stb & soc_wb_sdram_cyc) & soc_wb_sdram_ack) & ((soc_wb_sdram_cti == 3'd7) | soc_counter_done)));
-assign soc_need_refill_reset = soc_end_of_burst;
-assign soc_need_refill_d = 1'd0;
-assign soc_litedram_wb_cti = 3'd7;
-assign soc_litedram_wb_adr = soc_address_q[29:2];
-assign soc_cached_sels_reset0 = soc_counter_reset;
-
-// synthesis translate_off
-reg dummy_d_295;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_flipflop0_d <= 32'd0;
-       if (soc_write) begin
-               soc_cached_datas_flipflop0_d <= soc_wb_sdram_dat_w;
-       end else begin
-               soc_cached_datas_flipflop0_d <= soc_litedram_wb_dat_r[31:0];
-       end
-// synthesis translate_off
-       dummy_d_295 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_flipflop0_d = soc_wb_sdram_sel;
-
-// synthesis translate_off
-reg dummy_d_296;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_ce0 <= 1'd0;
-       if (((soc_write & soc_write_sel0) | soc_refill)) begin
-               soc_cached_datas_ce0 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_296 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_297;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_sels_ce0 <= 1'd0;
-       if (((soc_write & soc_write_sel0) | soc_refill)) begin
-               soc_cached_sels_ce0 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_297 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_reset1 = soc_counter_reset;
-
-// synthesis translate_off
-reg dummy_d_298;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_flipflop1_d <= 32'd0;
-       if (soc_write) begin
-               soc_cached_datas_flipflop1_d <= soc_wb_sdram_dat_w;
-       end else begin
-               soc_cached_datas_flipflop1_d <= soc_litedram_wb_dat_r[63:32];
-       end
-// synthesis translate_off
-       dummy_d_298 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_flipflop1_d = soc_wb_sdram_sel;
-
-// synthesis translate_off
-reg dummy_d_299;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_ce1 <= 1'd0;
-       if (((soc_write & soc_write_sel1) | soc_refill)) begin
-               soc_cached_datas_ce1 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_299 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_300;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_sels_ce1 <= 1'd0;
-       if (((soc_write & soc_write_sel1) | soc_refill)) begin
-               soc_cached_sels_ce1 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_300 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_reset2 = soc_counter_reset;
-
-// synthesis translate_off
-reg dummy_d_301;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_flipflop2_d <= 32'd0;
-       if (soc_write) begin
-               soc_cached_datas_flipflop2_d <= soc_wb_sdram_dat_w;
-       end else begin
-               soc_cached_datas_flipflop2_d <= soc_litedram_wb_dat_r[95:64];
-       end
-// synthesis translate_off
-       dummy_d_301 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_flipflop2_d = soc_wb_sdram_sel;
-
-// synthesis translate_off
-reg dummy_d_302;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_ce2 <= 1'd0;
-       if (((soc_write & soc_write_sel2) | soc_refill)) begin
-               soc_cached_datas_ce2 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_302 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_303;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_sels_ce2 <= 1'd0;
-       if (((soc_write & soc_write_sel2) | soc_refill)) begin
-               soc_cached_sels_ce2 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_303 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_reset3 = soc_counter_reset;
-
-// synthesis translate_off
-reg dummy_d_304;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_flipflop3_d <= 32'd0;
-       if (soc_write) begin
-               soc_cached_datas_flipflop3_d <= soc_wb_sdram_dat_w;
-       end else begin
-               soc_cached_datas_flipflop3_d <= soc_litedram_wb_dat_r[127:96];
-       end
-// synthesis translate_off
-       dummy_d_304 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_flipflop3_d = soc_wb_sdram_sel;
-
-// synthesis translate_off
-reg dummy_d_305;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_ce3 <= 1'd0;
-       if (((soc_write & soc_write_sel3) | soc_refill)) begin
-               soc_cached_datas_ce3 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_305 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_306;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_sels_ce3 <= 1'd0;
-       if (((soc_write & soc_write_sel3) | soc_refill)) begin
-               soc_cached_sels_ce3 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_306 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_307;
-// synthesis translate_on
-always @(*) begin
-       soc_write_sel2 <= 1'd0;
-       case ((soc_counter + soc_counter_offset))
-               1'd0: begin
-               end
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_write_sel2 <= 1'd1;
-               end
-               2'd3: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_307 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_308;
-// synthesis translate_on
-always @(*) begin
-       soc_write_sel3 <= 1'd0;
-       case ((soc_counter + soc_counter_offset))
-               1'd0: begin
-               end
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       soc_write_sel3 <= 1'd1;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_308 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_309;
-// synthesis translate_on
-always @(*) begin
-       soc_write_sel0 <= 1'd0;
-       case ((soc_counter + soc_counter_offset))
-               1'd0: begin
-                       soc_write_sel0 <= 1'd1;
-               end
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_309 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_310;
-// synthesis translate_on
-always @(*) begin
-       soc_write_sel1 <= 1'd0;
-       case ((soc_counter + soc_counter_offset))
-               1'd0: begin
-               end
-               1'd1: begin
-                       soc_write_sel1 <= 1'd1;
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_310 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_311;
-// synthesis translate_on
-always @(*) begin
-       soc_wb_sdram_dat_r <= 32'd0;
-       case (soc_address_q[1:0])
-               1'd0: begin
-                       soc_wb_sdram_dat_r <= soc_cached_datas_flipflop0_q;
-               end
-               1'd1: begin
-                       soc_wb_sdram_dat_r <= soc_cached_datas_flipflop1_q;
-               end
-               2'd2: begin
-                       soc_wb_sdram_dat_r <= soc_cached_datas_flipflop2_q;
-               end
-               2'd3: begin
-                       soc_wb_sdram_dat_r <= soc_cached_datas_flipflop3_q;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_311 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_data = {soc_cached_datas_flipflop3_q, soc_cached_datas_flipflop2_q, soc_cached_datas_flipflop1_q, soc_cached_datas_flipflop0_q};
-assign soc_cached_sel = {soc_cached_sels_flipflop3_q, soc_cached_sels_flipflop2_q, soc_cached_sels_flipflop1_q, soc_cached_sels_flipflop0_q};
-
-// synthesis translate_off
-reg dummy_d_312;
-// synthesis translate_on
-always @(*) begin
-       vns_converter_next_state <= 3'd0;
-       vns_converter_next_state <= vns_converter_state;
-       case (vns_converter_state)
-               1'd1: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               if (soc_counter_done) begin
-                                       vns_converter_next_state <= 2'd2;
-                               end
-                       end else begin
-                               if ((~soc_wb_sdram_cyc)) begin
-                                       vns_converter_next_state <= 2'd2;
-                               end
-                       end
-               end
-               2'd2: begin
-                       if (soc_litedram_wb_ack) begin
-                               vns_converter_next_state <= 1'd0;
-                       end
-               end
-               2'd3: begin
-                       if (soc_litedram_wb_ack) begin
-                               vns_converter_next_state <= 3'd4;
-                       end
-               end
-               3'd4: begin
-                       vns_converter_next_state <= 1'd0;
-               end
-               default: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               if (soc_wb_sdram_we) begin
-                                       vns_converter_next_state <= 1'd1;
-                               end else begin
-                                       if (soc_need_refill_q) begin
-                                               vns_converter_next_state <= 2'd3;
-                                       end else begin
-                                               vns_converter_next_state <= 3'd4;
-                                       end
-                               end
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_312 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_313;
-// synthesis translate_on
-always @(*) begin
-       soc_address_ce <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               soc_address_ce <= 1'd1;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_313 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_314;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_dat_w <= 128'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_litedram_wb_dat_w <= soc_cached_data;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_314 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_315;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_sel <= 16'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_litedram_wb_sel <= soc_cached_sel;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_315 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_316;
-// synthesis translate_on
-always @(*) begin
-       soc_counter_ce <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               soc_counter_ce <= 1'd1;
-                       end else begin
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_316 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_317;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_cyc <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_litedram_wb_cyc <= 1'd1;
-               end
-               2'd3: begin
-                       soc_litedram_wb_cyc <= 1'd1;
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_317 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_318;
-// synthesis translate_on
-always @(*) begin
-       soc_counter_reset <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-                       soc_counter_reset <= 1'd1;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_318 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_319;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_stb <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_litedram_wb_stb <= 1'd1;
-               end
-               2'd3: begin
-                       soc_litedram_wb_stb <= 1'd1;
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_319 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_320;
-// synthesis translate_on
-always @(*) begin
-       soc_need_refill_ce <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       if (soc_litedram_wb_ack) begin
-                               soc_need_refill_ce <= 1'd1;
-                       end
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_320 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_321;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_we <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_litedram_wb_we <= 1'd1;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_321 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_322;
-// synthesis translate_on
-always @(*) begin
-       soc_write <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               soc_write <= 1'd1;
-                       end else begin
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_322 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_323;
-// synthesis translate_on
-always @(*) begin
-       soc_wb_sdram_ack <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               soc_wb_sdram_ack <= 1'd1;
-                       end else begin
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               soc_wb_sdram_ack <= 1'd1;
-                       end
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_323 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_324;
-// synthesis translate_on
-always @(*) begin
-       soc_evict <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_evict <= 1'd1;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_324 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_325;
-// synthesis translate_on
-always @(*) begin
-       soc_refill <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       soc_refill <= 1'd1;
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_325 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_326;
-// synthesis translate_on
-always @(*) begin
-       soc_read <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-                       soc_read <= 1'd1;
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_326 = dummy_s;
-// synthesis translate_on
-end
-assign soc_wdata_converter_sink_valid = ((soc_litedram_wb_cyc & soc_litedram_wb_stb) & soc_litedram_wb_we);
-assign soc_wdata_converter_sink_payload_data = soc_litedram_wb_dat_w;
-assign soc_wdata_converter_sink_payload_we = soc_litedram_wb_sel;
-assign soc_port_wdata_valid = soc_wdata_converter_source_valid;
-assign soc_wdata_converter_source_ready = soc_port_wdata_ready;
-assign soc_port_wdata_first = soc_wdata_converter_source_first;
-assign soc_port_wdata_last = soc_wdata_converter_source_last;
-assign soc_port_wdata_payload_data = soc_wdata_converter_source_payload_data;
-assign soc_port_wdata_payload_we = soc_wdata_converter_source_payload_we;
-assign soc_rdata_converter_sink_valid = soc_port_rdata_valid;
-assign soc_port_rdata_ready = soc_rdata_converter_sink_ready;
-assign soc_rdata_converter_sink_first = soc_port_rdata_first;
-assign soc_rdata_converter_sink_last = soc_port_rdata_last;
-assign soc_rdata_converter_sink_payload_data = soc_port_rdata_payload_data;
-assign soc_rdata_converter_source_ready = 1'd1;
-assign soc_litedram_wb_dat_r = soc_rdata_converter_source_payload_data;
-assign soc_wdata_converter_converter_sink_valid = soc_wdata_converter_sink_valid;
-assign soc_wdata_converter_converter_sink_first = soc_wdata_converter_sink_first;
-assign soc_wdata_converter_converter_sink_last = soc_wdata_converter_sink_last;
-assign soc_wdata_converter_sink_ready = soc_wdata_converter_converter_sink_ready;
-assign soc_wdata_converter_converter_sink_payload_data = {soc_wdata_converter_sink_payload_we, soc_wdata_converter_sink_payload_data};
-assign soc_wdata_converter_source_valid = soc_wdata_converter_source_source_valid;
-assign soc_wdata_converter_source_first = soc_wdata_converter_source_source_first;
-assign soc_wdata_converter_source_last = soc_wdata_converter_source_source_last;
-assign soc_wdata_converter_source_source_ready = soc_wdata_converter_source_ready;
-assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data;
-assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data;
-assign soc_wdata_converter_source_source_valid = soc_wdata_converter_converter_source_valid;
-assign soc_wdata_converter_converter_source_ready = soc_wdata_converter_source_source_ready;
-assign soc_wdata_converter_source_source_first = soc_wdata_converter_converter_source_first;
-assign soc_wdata_converter_source_source_last = soc_wdata_converter_converter_source_last;
-assign soc_wdata_converter_source_source_payload_data = soc_wdata_converter_converter_source_payload_data;
-assign soc_wdata_converter_converter_source_valid = soc_wdata_converter_converter_sink_valid;
-assign soc_wdata_converter_converter_sink_ready = soc_wdata_converter_converter_source_ready;
-assign soc_wdata_converter_converter_source_first = soc_wdata_converter_converter_sink_first;
-assign soc_wdata_converter_converter_source_last = soc_wdata_converter_converter_sink_last;
-assign soc_wdata_converter_converter_source_payload_data = soc_wdata_converter_converter_sink_payload_data;
-assign soc_wdata_converter_converter_source_payload_valid_token_count = 1'd1;
-assign soc_rdata_converter_converter_sink_valid = soc_rdata_converter_sink_valid;
-assign soc_rdata_converter_converter_sink_first = soc_rdata_converter_sink_first;
-assign soc_rdata_converter_converter_sink_last = soc_rdata_converter_sink_last;
-assign soc_rdata_converter_sink_ready = soc_rdata_converter_converter_sink_ready;
-assign soc_rdata_converter_converter_sink_payload_data = {soc_rdata_converter_sink_payload_data};
-assign soc_rdata_converter_source_valid = soc_rdata_converter_source_source_valid;
-assign soc_rdata_converter_source_first = soc_rdata_converter_source_source_first;
-assign soc_rdata_converter_source_last = soc_rdata_converter_source_source_last;
-assign soc_rdata_converter_source_source_ready = soc_rdata_converter_source_ready;
-assign {soc_rdata_converter_source_payload_data} = soc_rdata_converter_source_source_payload_data;
-assign soc_rdata_converter_source_source_valid = soc_rdata_converter_converter_source_valid;
-assign soc_rdata_converter_converter_source_ready = soc_rdata_converter_source_source_ready;
-assign soc_rdata_converter_source_source_first = soc_rdata_converter_converter_source_first;
-assign soc_rdata_converter_source_source_last = soc_rdata_converter_converter_source_last;
-assign soc_rdata_converter_source_source_payload_data = soc_rdata_converter_converter_source_payload_data;
-assign soc_rdata_converter_converter_source_valid = soc_rdata_converter_converter_sink_valid;
-assign soc_rdata_converter_converter_sink_ready = soc_rdata_converter_converter_source_ready;
-assign soc_rdata_converter_converter_source_first = soc_rdata_converter_converter_sink_first;
-assign soc_rdata_converter_converter_source_last = soc_rdata_converter_converter_sink_last;
-assign soc_rdata_converter_converter_source_payload_data = soc_rdata_converter_converter_sink_payload_data;
-assign soc_rdata_converter_converter_source_payload_valid_token_count = 1'd1;
-
-// synthesis translate_off
-reg dummy_d_327;
-// synthesis translate_on
-always @(*) begin
-       vns_litedramwishbone2native_next_state <= 2'd0;
-       vns_litedramwishbone2native_next_state <= vns_litedramwishbone2native_state;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-                       if (soc_wdata_converter_sink_ready) begin
-                               vns_litedramwishbone2native_next_state <= 1'd0;
-                       end
-               end
-               2'd2: begin
-                       if (soc_rdata_converter_source_valid) begin
-                               vns_litedramwishbone2native_next_state <= 1'd0;
-                       end
-               end
-               default: begin
-                       if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
-                               if ((soc_count == 1'd0)) begin
-                                       if (soc_litedram_wb_we) begin
-                                               vns_litedramwishbone2native_next_state <= 1'd1;
-                                       end else begin
-                                               vns_litedramwishbone2native_next_state <= 2'd2;
-                                       end
-                               end
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_327 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_328;
-// synthesis translate_on
-always @(*) begin
-       soc_count_next_value <= 1'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               default: begin
-                       if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
-                               soc_count_next_value <= (soc_count + 1'd1);
-                               if ((soc_count == 1'd0)) begin
-                                       soc_count_next_value <= 1'd0;
-                               end
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_328 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_329;
-// synthesis translate_on
-always @(*) begin
-       soc_count_next_value_ce <= 1'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               default: begin
-                       if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
-                               soc_count_next_value_ce <= 1'd1;
-                               if ((soc_count == 1'd0)) begin
-                                       soc_count_next_value_ce <= 1'd1;
-                               end
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_329 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_330;
-// synthesis translate_on
-always @(*) begin
-       soc_port_cmd_valid <= 1'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               default: begin
-                       soc_port_cmd_valid <= (soc_litedram_wb_cyc & soc_litedram_wb_stb);
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_330 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_331;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_ack <= 1'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-                       if (soc_wdata_converter_sink_ready) begin
-                               soc_litedram_wb_ack <= 1'd1;
-                       end
-               end
-               2'd2: begin
-                       if (soc_rdata_converter_source_valid) begin
-                               soc_litedram_wb_ack <= 1'd1;
-                       end
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_331 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_332;
-// synthesis translate_on
-always @(*) begin
-       soc_port_cmd_payload_we <= 1'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               default: begin
-                       soc_port_cmd_payload_we <= soc_litedram_wb_we;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_332 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_333;
-// synthesis translate_on
-always @(*) begin
-       soc_port_cmd_payload_addr <= 24'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               default: begin
-                       soc_port_cmd_payload_addr <= (((soc_litedram_wb_adr * 1'd1) + soc_count) - 27'd67108864);
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_333 = dummy_s;
-// synthesis translate_on
-end
-assign vns_shared_adr = vns_rhs_array_muxed36;
-assign vns_shared_dat_w = vns_rhs_array_muxed37;
-assign vns_shared_sel = vns_rhs_array_muxed38;
-assign vns_shared_cyc = vns_rhs_array_muxed39;
-assign vns_shared_stb = vns_rhs_array_muxed40;
-assign vns_shared_we = vns_rhs_array_muxed41;
-assign vns_shared_cti = vns_rhs_array_muxed42;
-assign vns_shared_bte = vns_rhs_array_muxed43;
-assign soc_litedramcore_cpu_ibus_dat_r = vns_shared_dat_r;
-assign soc_litedramcore_cpu_dbus_dat_r = vns_shared_dat_r;
-assign soc_litedramcore_cpu_ibus_ack = (vns_shared_ack & (vns_grant == 1'd0));
-assign soc_litedramcore_cpu_dbus_ack = (vns_shared_ack & (vns_grant == 1'd1));
-assign soc_litedramcore_cpu_ibus_err = (vns_shared_err & (vns_grant == 1'd0));
-assign soc_litedramcore_cpu_dbus_err = (vns_shared_err & (vns_grant == 1'd1));
-assign vns_request = {soc_litedramcore_cpu_dbus_cyc, soc_litedramcore_cpu_ibus_cyc};
-
-// synthesis translate_off
-reg dummy_d_334;
-// synthesis translate_on
-always @(*) begin
-       vns_slave_sel <= 4'd0;
-       vns_slave_sel[0] <= (vns_shared_adr[29:13] == 1'd0);
-       vns_slave_sel[1] <= (vns_shared_adr[29:10] == 13'd4096);
-       vns_slave_sel[2] <= (vns_shared_adr[29:14] == 16'd33280);
-       vns_slave_sel[3] <= (vns_shared_adr[29:22] == 7'd64);
-// synthesis translate_off
-       dummy_d_334 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_litedramcore_ram_bus_adr = vns_shared_adr;
-assign soc_litedramcore_litedramcore_ram_bus_dat_w = vns_shared_dat_w;
-assign soc_litedramcore_litedramcore_ram_bus_sel = vns_shared_sel;
-assign soc_litedramcore_litedramcore_ram_bus_stb = vns_shared_stb;
-assign soc_litedramcore_litedramcore_ram_bus_we = vns_shared_we;
-assign soc_litedramcore_litedramcore_ram_bus_cti = vns_shared_cti;
-assign soc_litedramcore_litedramcore_ram_bus_bte = vns_shared_bte;
-assign soc_litedramcore_ram_bus_ram_bus_adr = vns_shared_adr;
-assign soc_litedramcore_ram_bus_ram_bus_dat_w = vns_shared_dat_w;
-assign soc_litedramcore_ram_bus_ram_bus_sel = vns_shared_sel;
-assign soc_litedramcore_ram_bus_ram_bus_stb = vns_shared_stb;
-assign soc_litedramcore_ram_bus_ram_bus_we = vns_shared_we;
-assign soc_litedramcore_ram_bus_ram_bus_cti = vns_shared_cti;
-assign soc_litedramcore_ram_bus_ram_bus_bte = vns_shared_bte;
-assign soc_litedramcore_bus_wishbone_adr = vns_shared_adr;
-assign soc_litedramcore_bus_wishbone_dat_w = vns_shared_dat_w;
-assign soc_litedramcore_bus_wishbone_sel = vns_shared_sel;
-assign soc_litedramcore_bus_wishbone_stb = vns_shared_stb;
-assign soc_litedramcore_bus_wishbone_we = vns_shared_we;
-assign soc_litedramcore_bus_wishbone_cti = vns_shared_cti;
-assign soc_litedramcore_bus_wishbone_bte = vns_shared_bte;
-assign soc_wb_sdram_adr = vns_shared_adr;
-assign soc_wb_sdram_dat_w = vns_shared_dat_w;
-assign soc_wb_sdram_sel = vns_shared_sel;
-assign soc_wb_sdram_stb = vns_shared_stb;
-assign soc_wb_sdram_we = vns_shared_we;
-assign soc_wb_sdram_cti = vns_shared_cti;
-assign soc_wb_sdram_bte = vns_shared_bte;
-assign soc_litedramcore_litedramcore_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[0]);
-assign soc_litedramcore_ram_bus_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[1]);
-assign soc_litedramcore_bus_wishbone_cyc = (vns_shared_cyc & vns_slave_sel[2]);
-assign soc_wb_sdram_cyc = (vns_shared_cyc & vns_slave_sel[3]);
-
-// synthesis translate_off
-reg dummy_d_335;
-// synthesis translate_on
-always @(*) begin
-       vns_shared_ack <= 1'd0;
-       vns_shared_ack <= (((soc_litedramcore_litedramcore_ram_bus_ack | soc_litedramcore_ram_bus_ram_bus_ack) | soc_litedramcore_bus_wishbone_ack) | soc_wb_sdram_ack);
-       if (vns_done) begin
-               vns_shared_ack <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_335 = dummy_s;
-// synthesis translate_on
-end
-assign vns_shared_err = (((soc_litedramcore_litedramcore_ram_bus_err | soc_litedramcore_ram_bus_ram_bus_err) | soc_litedramcore_bus_wishbone_err) | soc_wb_sdram_err);
-
-// synthesis translate_off
-reg dummy_d_336;
-// synthesis translate_on
-always @(*) begin
-       vns_shared_dat_r <= 32'd0;
-       vns_shared_dat_r <= (((({32{vns_slave_sel_r[0]}} & soc_litedramcore_litedramcore_ram_bus_dat_r) | ({32{vns_slave_sel_r[1]}} & soc_litedramcore_ram_bus_ram_bus_dat_r)) | ({32{vns_slave_sel_r[2]}} & soc_litedramcore_bus_wishbone_dat_r)) | ({32{vns_slave_sel_r[3]}} & soc_wb_sdram_dat_r));
-       if (vns_done) begin
-               vns_shared_dat_r <= 32'd4294967295;
-       end
-// synthesis translate_off
-       dummy_d_336 = dummy_s;
-// synthesis translate_on
-end
-assign vns_wait = ((vns_shared_stb & vns_shared_cyc) & (~vns_shared_ack));
-
-// synthesis translate_off
-reg dummy_d_337;
-// synthesis translate_on
-always @(*) begin
-       vns_error <= 1'd0;
-       if (vns_done) begin
-               vns_error <= 1'd1;
-       end
+               end
+               default: begin
+                       if (1'd0) begin
+                               litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+                       end else begin
+                               litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+                       end
+               end
+       endcase
 // synthesis translate_off
-       dummy_d_337 = dummy_s;
+       dummy_d_273 = dummy_s;
 // synthesis translate_on
 end
-assign vns_done = (vns_count == 1'd0);
-assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 1'd0);
-assign vns_csrbank0_reset0_r = vns_interface0_bank_bus_dat_w[0];
-assign vns_csrbank0_reset0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd0));
-assign vns_csrbank0_reset0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd0));
-assign vns_csrbank0_scratch3_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_scratch3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd1));
-assign vns_csrbank0_scratch3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd1));
-assign vns_csrbank0_scratch2_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_scratch2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd2));
-assign vns_csrbank0_scratch2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd2));
-assign vns_csrbank0_scratch1_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_scratch1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd3));
-assign vns_csrbank0_scratch1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd3));
-assign vns_csrbank0_scratch0_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_scratch0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd4));
-assign vns_csrbank0_scratch0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd4));
-assign vns_csrbank0_bus_errors3_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_bus_errors3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd5));
-assign vns_csrbank0_bus_errors3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd5));
-assign vns_csrbank0_bus_errors2_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_bus_errors2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd6));
-assign vns_csrbank0_bus_errors2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd6));
-assign vns_csrbank0_bus_errors1_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_bus_errors1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd7));
-assign vns_csrbank0_bus_errors1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd7));
-assign vns_csrbank0_bus_errors0_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_bus_errors0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 4'd8));
-assign vns_csrbank0_bus_errors0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 4'd8));
-assign vns_csrbank0_reset0_w = soc_litedramcore_soccontroller_reset_storage;
-assign vns_csrbank0_scratch3_w = soc_litedramcore_soccontroller_scratch_storage[31:24];
-assign vns_csrbank0_scratch2_w = soc_litedramcore_soccontroller_scratch_storage[23:16];
-assign vns_csrbank0_scratch1_w = soc_litedramcore_soccontroller_scratch_storage[15:8];
-assign vns_csrbank0_scratch0_w = soc_litedramcore_soccontroller_scratch_storage[7:0];
-assign vns_csrbank0_bus_errors3_w = soc_litedramcore_soccontroller_bus_errors_status[31:24];
-assign vns_csrbank0_bus_errors2_w = soc_litedramcore_soccontroller_bus_errors_status[23:16];
-assign vns_csrbank0_bus_errors1_w = soc_litedramcore_soccontroller_bus_errors_status[15:8];
-assign vns_csrbank0_bus_errors0_w = soc_litedramcore_soccontroller_bus_errors_status[7:0];
-assign soc_litedramcore_soccontroller_bus_errors_we = vns_csrbank0_bus_errors0_we;
-assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 3'd7);
-assign vns_csrbank1_init_done0_r = vns_interface1_bank_bus_dat_w[0];
-assign vns_csrbank1_init_done0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd0));
-assign vns_csrbank1_init_done0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd0));
-assign vns_csrbank1_init_error0_r = vns_interface1_bank_bus_dat_w[0];
-assign vns_csrbank1_init_error0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd1));
-assign vns_csrbank1_init_error0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd1));
-assign vns_csrbank1_init_done0_w = soc_init_done_storage;
-assign vns_csrbank1_init_error0_w = soc_init_error_storage;
-assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 3'd5);
-assign vns_csrbank2_half_sys8x_taps0_r = vns_interface2_bank_bus_dat_w[4:0];
-assign vns_csrbank2_half_sys8x_taps0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd0));
-assign vns_csrbank2_half_sys8x_taps0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd0));
-assign vns_csrbank2_wlevel_en0_r = vns_interface2_bank_bus_dat_w[0];
-assign vns_csrbank2_wlevel_en0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd1));
-assign vns_csrbank2_wlevel_en0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd1));
-assign soc_a7ddrphy_wlevel_strobe_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd2));
-assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd2));
-assign soc_a7ddrphy_cdly_rst_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd3));
-assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd3));
-assign soc_a7ddrphy_cdly_inc_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd4));
-assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd4));
-assign vns_csrbank2_dly_sel0_r = vns_interface2_bank_bus_dat_w[1:0];
-assign vns_csrbank2_dly_sel0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd5));
-assign vns_csrbank2_dly_sel0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd5));
-assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd6));
-assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd6));
-assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd7));
-assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd7));
-assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd8));
-assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd8));
-assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd9));
-assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd9));
-assign vns_csrbank2_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0];
-assign vns_csrbank2_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage;
-assign vns_csrbank2_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0];
-assign vns_csrbank3_sel = (vns_interface3_bank_bus_adr[13:9] == 3'd6);
-assign vns_csrbank3_dfii_control0_r = vns_interface3_bank_bus_dat_w[3:0];
-assign vns_csrbank3_dfii_control0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd0));
-assign vns_csrbank3_dfii_control0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd0));
-assign vns_csrbank3_dfii_pi0_command0_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi0_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd1));
-assign vns_csrbank3_dfii_pi0_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd1));
-assign soc_sdram_phaseinjector0_command_issue_r = vns_interface3_bank_bus_dat_w[0];
-assign soc_sdram_phaseinjector0_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd2));
-assign soc_sdram_phaseinjector0_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd2));
-assign vns_csrbank3_dfii_pi0_address1_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi0_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd3));
-assign vns_csrbank3_dfii_pi0_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd3));
-assign vns_csrbank3_dfii_pi0_address0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd4));
-assign vns_csrbank3_dfii_pi0_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd4));
-assign vns_csrbank3_dfii_pi0_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
-assign vns_csrbank3_dfii_pi0_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd5));
-assign vns_csrbank3_dfii_pi0_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd5));
-assign vns_csrbank3_dfii_pi0_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd6));
-assign vns_csrbank3_dfii_pi0_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd6));
-assign vns_csrbank3_dfii_pi0_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd7));
-assign vns_csrbank3_dfii_pi0_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd7));
-assign vns_csrbank3_dfii_pi0_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd8));
-assign vns_csrbank3_dfii_pi0_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd8));
-assign vns_csrbank3_dfii_pi0_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd9));
-assign vns_csrbank3_dfii_pi0_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd9));
-assign vns_csrbank3_dfii_pi0_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd10));
-assign vns_csrbank3_dfii_pi0_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd10));
-assign vns_csrbank3_dfii_pi0_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd11));
-assign vns_csrbank3_dfii_pi0_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd11));
-assign vns_csrbank3_dfii_pi0_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd12));
-assign vns_csrbank3_dfii_pi0_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd12));
-assign vns_csrbank3_dfii_pi0_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd13));
-assign vns_csrbank3_dfii_pi0_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd13));
-assign vns_csrbank3_dfii_pi1_command0_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi1_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd14));
-assign vns_csrbank3_dfii_pi1_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd14));
-assign soc_sdram_phaseinjector1_command_issue_r = vns_interface3_bank_bus_dat_w[0];
-assign soc_sdram_phaseinjector1_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd15));
-assign soc_sdram_phaseinjector1_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd15));
-assign vns_csrbank3_dfii_pi1_address1_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi1_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd16));
-assign vns_csrbank3_dfii_pi1_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd16));
-assign vns_csrbank3_dfii_pi1_address0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd17));
-assign vns_csrbank3_dfii_pi1_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd17));
-assign vns_csrbank3_dfii_pi1_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
-assign vns_csrbank3_dfii_pi1_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd18));
-assign vns_csrbank3_dfii_pi1_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd18));
-assign vns_csrbank3_dfii_pi1_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd19));
-assign vns_csrbank3_dfii_pi1_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd19));
-assign vns_csrbank3_dfii_pi1_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd20));
-assign vns_csrbank3_dfii_pi1_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd20));
-assign vns_csrbank3_dfii_pi1_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd21));
-assign vns_csrbank3_dfii_pi1_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd21));
-assign vns_csrbank3_dfii_pi1_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd22));
-assign vns_csrbank3_dfii_pi1_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd22));
-assign vns_csrbank3_dfii_pi1_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd23));
-assign vns_csrbank3_dfii_pi1_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd23));
-assign vns_csrbank3_dfii_pi1_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd24));
-assign vns_csrbank3_dfii_pi1_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd24));
-assign vns_csrbank3_dfii_pi1_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd25));
-assign vns_csrbank3_dfii_pi1_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd25));
-assign vns_csrbank3_dfii_pi1_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd26));
-assign vns_csrbank3_dfii_pi1_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd26));
-assign vns_csrbank3_dfii_pi2_command0_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi2_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd27));
-assign vns_csrbank3_dfii_pi2_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd27));
-assign soc_sdram_phaseinjector2_command_issue_r = vns_interface3_bank_bus_dat_w[0];
-assign soc_sdram_phaseinjector2_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd28));
-assign soc_sdram_phaseinjector2_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd28));
-assign vns_csrbank3_dfii_pi2_address1_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi2_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd29));
-assign vns_csrbank3_dfii_pi2_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd29));
-assign vns_csrbank3_dfii_pi2_address0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd30));
-assign vns_csrbank3_dfii_pi2_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd30));
-assign vns_csrbank3_dfii_pi2_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
-assign vns_csrbank3_dfii_pi2_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd31));
-assign vns_csrbank3_dfii_pi2_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd31));
-assign vns_csrbank3_dfii_pi2_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd32));
-assign vns_csrbank3_dfii_pi2_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd32));
-assign vns_csrbank3_dfii_pi2_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd33));
-assign vns_csrbank3_dfii_pi2_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd33));
-assign vns_csrbank3_dfii_pi2_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd34));
-assign vns_csrbank3_dfii_pi2_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd34));
-assign vns_csrbank3_dfii_pi2_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd35));
-assign vns_csrbank3_dfii_pi2_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd35));
-assign vns_csrbank3_dfii_pi2_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd36));
-assign vns_csrbank3_dfii_pi2_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd36));
-assign vns_csrbank3_dfii_pi2_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd37));
-assign vns_csrbank3_dfii_pi2_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd37));
-assign vns_csrbank3_dfii_pi2_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd38));
-assign vns_csrbank3_dfii_pi2_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd38));
-assign vns_csrbank3_dfii_pi2_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd39));
-assign vns_csrbank3_dfii_pi2_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd39));
-assign vns_csrbank3_dfii_pi3_command0_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi3_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd40));
-assign vns_csrbank3_dfii_pi3_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd40));
-assign soc_sdram_phaseinjector3_command_issue_r = vns_interface3_bank_bus_dat_w[0];
-assign soc_sdram_phaseinjector3_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd41));
-assign soc_sdram_phaseinjector3_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd41));
-assign vns_csrbank3_dfii_pi3_address1_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi3_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd42));
-assign vns_csrbank3_dfii_pi3_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd42));
-assign vns_csrbank3_dfii_pi3_address0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd43));
-assign vns_csrbank3_dfii_pi3_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd43));
-assign vns_csrbank3_dfii_pi3_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
-assign vns_csrbank3_dfii_pi3_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd44));
-assign vns_csrbank3_dfii_pi3_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd44));
-assign vns_csrbank3_dfii_pi3_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd45));
-assign vns_csrbank3_dfii_pi3_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd45));
-assign vns_csrbank3_dfii_pi3_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd46));
-assign vns_csrbank3_dfii_pi3_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd46));
-assign vns_csrbank3_dfii_pi3_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd47));
-assign vns_csrbank3_dfii_pi3_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd47));
-assign vns_csrbank3_dfii_pi3_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd48));
-assign vns_csrbank3_dfii_pi3_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd48));
-assign vns_csrbank3_dfii_pi3_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd49));
-assign vns_csrbank3_dfii_pi3_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd49));
-assign vns_csrbank3_dfii_pi3_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd50));
-assign vns_csrbank3_dfii_pi3_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd50));
-assign vns_csrbank3_dfii_pi3_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd51));
-assign vns_csrbank3_dfii_pi3_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd51));
-assign vns_csrbank3_dfii_pi3_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd52));
-assign vns_csrbank3_dfii_pi3_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd52));
-assign vns_csrbank3_dfii_control0_w = soc_sdram_storage[3:0];
-assign vns_csrbank3_dfii_pi0_command0_w = soc_sdram_phaseinjector0_command_storage[5:0];
-assign vns_csrbank3_dfii_pi0_address1_w = soc_sdram_phaseinjector0_address_storage[13:8];
-assign vns_csrbank3_dfii_pi0_address0_w = soc_sdram_phaseinjector0_address_storage[7:0];
-assign vns_csrbank3_dfii_pi0_baddress0_w = soc_sdram_phaseinjector0_baddress_storage[2:0];
-assign vns_csrbank3_dfii_pi0_wrdata3_w = soc_sdram_phaseinjector0_wrdata_storage[31:24];
-assign vns_csrbank3_dfii_pi0_wrdata2_w = soc_sdram_phaseinjector0_wrdata_storage[23:16];
-assign vns_csrbank3_dfii_pi0_wrdata1_w = soc_sdram_phaseinjector0_wrdata_storage[15:8];
-assign vns_csrbank3_dfii_pi0_wrdata0_w = soc_sdram_phaseinjector0_wrdata_storage[7:0];
-assign vns_csrbank3_dfii_pi0_rddata3_w = soc_sdram_phaseinjector0_status[31:24];
-assign vns_csrbank3_dfii_pi0_rddata2_w = soc_sdram_phaseinjector0_status[23:16];
-assign vns_csrbank3_dfii_pi0_rddata1_w = soc_sdram_phaseinjector0_status[15:8];
-assign vns_csrbank3_dfii_pi0_rddata0_w = soc_sdram_phaseinjector0_status[7:0];
-assign soc_sdram_phaseinjector0_we = vns_csrbank3_dfii_pi0_rddata0_we;
-assign vns_csrbank3_dfii_pi1_command0_w = soc_sdram_phaseinjector1_command_storage[5:0];
-assign vns_csrbank3_dfii_pi1_address1_w = soc_sdram_phaseinjector1_address_storage[13:8];
-assign vns_csrbank3_dfii_pi1_address0_w = soc_sdram_phaseinjector1_address_storage[7:0];
-assign vns_csrbank3_dfii_pi1_baddress0_w = soc_sdram_phaseinjector1_baddress_storage[2:0];
-assign vns_csrbank3_dfii_pi1_wrdata3_w = soc_sdram_phaseinjector1_wrdata_storage[31:24];
-assign vns_csrbank3_dfii_pi1_wrdata2_w = soc_sdram_phaseinjector1_wrdata_storage[23:16];
-assign vns_csrbank3_dfii_pi1_wrdata1_w = soc_sdram_phaseinjector1_wrdata_storage[15:8];
-assign vns_csrbank3_dfii_pi1_wrdata0_w = soc_sdram_phaseinjector1_wrdata_storage[7:0];
-assign vns_csrbank3_dfii_pi1_rddata3_w = soc_sdram_phaseinjector1_status[31:24];
-assign vns_csrbank3_dfii_pi1_rddata2_w = soc_sdram_phaseinjector1_status[23:16];
-assign vns_csrbank3_dfii_pi1_rddata1_w = soc_sdram_phaseinjector1_status[15:8];
-assign vns_csrbank3_dfii_pi1_rddata0_w = soc_sdram_phaseinjector1_status[7:0];
-assign soc_sdram_phaseinjector1_we = vns_csrbank3_dfii_pi1_rddata0_we;
-assign vns_csrbank3_dfii_pi2_command0_w = soc_sdram_phaseinjector2_command_storage[5:0];
-assign vns_csrbank3_dfii_pi2_address1_w = soc_sdram_phaseinjector2_address_storage[13:8];
-assign vns_csrbank3_dfii_pi2_address0_w = soc_sdram_phaseinjector2_address_storage[7:0];
-assign vns_csrbank3_dfii_pi2_baddress0_w = soc_sdram_phaseinjector2_baddress_storage[2:0];
-assign vns_csrbank3_dfii_pi2_wrdata3_w = soc_sdram_phaseinjector2_wrdata_storage[31:24];
-assign vns_csrbank3_dfii_pi2_wrdata2_w = soc_sdram_phaseinjector2_wrdata_storage[23:16];
-assign vns_csrbank3_dfii_pi2_wrdata1_w = soc_sdram_phaseinjector2_wrdata_storage[15:8];
-assign vns_csrbank3_dfii_pi2_wrdata0_w = soc_sdram_phaseinjector2_wrdata_storage[7:0];
-assign vns_csrbank3_dfii_pi2_rddata3_w = soc_sdram_phaseinjector2_status[31:24];
-assign vns_csrbank3_dfii_pi2_rddata2_w = soc_sdram_phaseinjector2_status[23:16];
-assign vns_csrbank3_dfii_pi2_rddata1_w = soc_sdram_phaseinjector2_status[15:8];
-assign vns_csrbank3_dfii_pi2_rddata0_w = soc_sdram_phaseinjector2_status[7:0];
-assign soc_sdram_phaseinjector2_we = vns_csrbank3_dfii_pi2_rddata0_we;
-assign vns_csrbank3_dfii_pi3_command0_w = soc_sdram_phaseinjector3_command_storage[5:0];
-assign vns_csrbank3_dfii_pi3_address1_w = soc_sdram_phaseinjector3_address_storage[13:8];
-assign vns_csrbank3_dfii_pi3_address0_w = soc_sdram_phaseinjector3_address_storage[7:0];
-assign vns_csrbank3_dfii_pi3_baddress0_w = soc_sdram_phaseinjector3_baddress_storage[2:0];
-assign vns_csrbank3_dfii_pi3_wrdata3_w = soc_sdram_phaseinjector3_wrdata_storage[31:24];
-assign vns_csrbank3_dfii_pi3_wrdata2_w = soc_sdram_phaseinjector3_wrdata_storage[23:16];
-assign vns_csrbank3_dfii_pi3_wrdata1_w = soc_sdram_phaseinjector3_wrdata_storage[15:8];
-assign vns_csrbank3_dfii_pi3_wrdata0_w = soc_sdram_phaseinjector3_wrdata_storage[7:0];
-assign vns_csrbank3_dfii_pi3_rddata3_w = soc_sdram_phaseinjector3_status[31:24];
-assign vns_csrbank3_dfii_pi3_rddata2_w = soc_sdram_phaseinjector3_status[23:16];
-assign vns_csrbank3_dfii_pi3_rddata1_w = soc_sdram_phaseinjector3_status[15:8];
-assign vns_csrbank3_dfii_pi3_rddata0_w = soc_sdram_phaseinjector3_status[7:0];
-assign soc_sdram_phaseinjector3_we = vns_csrbank3_dfii_pi3_rddata0_we;
-assign vns_csrbank4_sel = (vns_interface4_bank_bus_adr[13:9] == 3'd4);
-assign vns_csrbank4_load3_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_load3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd0));
-assign vns_csrbank4_load3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd0));
-assign vns_csrbank4_load2_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_load2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd1));
-assign vns_csrbank4_load2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd1));
-assign vns_csrbank4_load1_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_load1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd2));
-assign vns_csrbank4_load1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd2));
-assign vns_csrbank4_load0_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_load0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd3));
-assign vns_csrbank4_load0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd3));
-assign vns_csrbank4_reload3_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_reload3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd4));
-assign vns_csrbank4_reload3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd4));
-assign vns_csrbank4_reload2_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_reload2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd5));
-assign vns_csrbank4_reload2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd5));
-assign vns_csrbank4_reload1_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_reload1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd6));
-assign vns_csrbank4_reload1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd6));
-assign vns_csrbank4_reload0_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_reload0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd7));
-assign vns_csrbank4_reload0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd7));
-assign vns_csrbank4_en0_r = vns_interface4_bank_bus_dat_w[0];
-assign vns_csrbank4_en0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd8));
-assign vns_csrbank4_en0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd8));
-assign vns_csrbank4_update_value0_r = vns_interface4_bank_bus_dat_w[0];
-assign vns_csrbank4_update_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd9));
-assign vns_csrbank4_update_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd9));
-assign vns_csrbank4_value3_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_value3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd10));
-assign vns_csrbank4_value3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd10));
-assign vns_csrbank4_value2_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_value2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd11));
-assign vns_csrbank4_value2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd11));
-assign vns_csrbank4_value1_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_value1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd12));
-assign vns_csrbank4_value1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd12));
-assign vns_csrbank4_value0_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd13));
-assign vns_csrbank4_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd13));
-assign soc_litedramcore_timer_eventmanager_status_r = vns_interface4_bank_bus_dat_w[0];
-assign soc_litedramcore_timer_eventmanager_status_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd14));
-assign soc_litedramcore_timer_eventmanager_status_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd14));
-assign soc_litedramcore_timer_eventmanager_pending_r = vns_interface4_bank_bus_dat_w[0];
-assign soc_litedramcore_timer_eventmanager_pending_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd15));
-assign soc_litedramcore_timer_eventmanager_pending_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd15));
-assign vns_csrbank4_ev_enable0_r = vns_interface4_bank_bus_dat_w[0];
-assign vns_csrbank4_ev_enable0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 5'd16));
-assign vns_csrbank4_ev_enable0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 5'd16));
-assign vns_csrbank4_load3_w = soc_litedramcore_timer_load_storage[31:24];
-assign vns_csrbank4_load2_w = soc_litedramcore_timer_load_storage[23:16];
-assign vns_csrbank4_load1_w = soc_litedramcore_timer_load_storage[15:8];
-assign vns_csrbank4_load0_w = soc_litedramcore_timer_load_storage[7:0];
-assign vns_csrbank4_reload3_w = soc_litedramcore_timer_reload_storage[31:24];
-assign vns_csrbank4_reload2_w = soc_litedramcore_timer_reload_storage[23:16];
-assign vns_csrbank4_reload1_w = soc_litedramcore_timer_reload_storage[15:8];
-assign vns_csrbank4_reload0_w = soc_litedramcore_timer_reload_storage[7:0];
-assign vns_csrbank4_en0_w = soc_litedramcore_timer_en_storage;
-assign vns_csrbank4_update_value0_w = soc_litedramcore_timer_update_value_storage;
-assign vns_csrbank4_value3_w = soc_litedramcore_timer_value_status[31:24];
-assign vns_csrbank4_value2_w = soc_litedramcore_timer_value_status[23:16];
-assign vns_csrbank4_value1_w = soc_litedramcore_timer_value_status[15:8];
-assign vns_csrbank4_value0_w = soc_litedramcore_timer_value_status[7:0];
-assign soc_litedramcore_timer_value_we = vns_csrbank4_value0_we;
-assign vns_csrbank4_ev_enable0_w = soc_litedramcore_timer_eventmanager_storage;
-assign vns_csrbank5_sel = (vns_interface5_bank_bus_adr[13:9] == 2'd3);
-assign soc_litedramcore_uart_rxtx_r = vns_interface5_bank_bus_dat_w[7:0];
-assign soc_litedramcore_uart_rxtx_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd0));
-assign soc_litedramcore_uart_rxtx_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd0));
-assign vns_csrbank5_txfull_r = vns_interface5_bank_bus_dat_w[0];
-assign vns_csrbank5_txfull_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd1));
-assign vns_csrbank5_txfull_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd1));
-assign vns_csrbank5_rxempty_r = vns_interface5_bank_bus_dat_w[0];
-assign vns_csrbank5_rxempty_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd2));
-assign vns_csrbank5_rxempty_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd2));
-assign soc_litedramcore_uart_eventmanager_status_r = vns_interface5_bank_bus_dat_w[1:0];
-assign soc_litedramcore_uart_eventmanager_status_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd3));
-assign soc_litedramcore_uart_eventmanager_status_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd3));
-assign soc_litedramcore_uart_eventmanager_pending_r = vns_interface5_bank_bus_dat_w[1:0];
-assign soc_litedramcore_uart_eventmanager_pending_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd4));
-assign soc_litedramcore_uart_eventmanager_pending_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd4));
-assign vns_csrbank5_ev_enable0_r = vns_interface5_bank_bus_dat_w[1:0];
-assign vns_csrbank5_ev_enable0_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd5));
-assign vns_csrbank5_ev_enable0_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd5));
-assign vns_csrbank5_txfull_w = soc_litedramcore_uart_txfull_status;
-assign soc_litedramcore_uart_txfull_we = vns_csrbank5_txfull_we;
-assign vns_csrbank5_rxempty_w = soc_litedramcore_uart_rxempty_status;
-assign soc_litedramcore_uart_rxempty_we = vns_csrbank5_rxempty_we;
-assign vns_csrbank5_ev_enable0_w = soc_litedramcore_uart_eventmanager_storage[1:0];
-assign vns_csrbank6_sel = (vns_interface6_bank_bus_adr[13:9] == 2'd2);
-assign vns_csrbank6_tuning_word3_r = vns_interface6_bank_bus_dat_w[7:0];
-assign vns_csrbank6_tuning_word3_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd0));
-assign vns_csrbank6_tuning_word3_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd0));
-assign vns_csrbank6_tuning_word2_r = vns_interface6_bank_bus_dat_w[7:0];
-assign vns_csrbank6_tuning_word2_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd1));
-assign vns_csrbank6_tuning_word2_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd1));
-assign vns_csrbank6_tuning_word1_r = vns_interface6_bank_bus_dat_w[7:0];
-assign vns_csrbank6_tuning_word1_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd2));
-assign vns_csrbank6_tuning_word1_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd2));
-assign vns_csrbank6_tuning_word0_r = vns_interface6_bank_bus_dat_w[7:0];
-assign vns_csrbank6_tuning_word0_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd3));
-assign vns_csrbank6_tuning_word0_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd3));
-assign vns_csrbank6_tuning_word3_w = soc_litedramcore_storage[31:24];
-assign vns_csrbank6_tuning_word2_w = soc_litedramcore_storage[23:16];
-assign vns_csrbank6_tuning_word1_w = soc_litedramcore_storage[15:8];
-assign vns_csrbank6_tuning_word0_w = soc_litedramcore_storage[7:0];
-assign vns_adr = soc_litedramcore_interface_adr;
-assign vns_we = soc_litedramcore_interface_we;
-assign vns_dat_w = soc_litedramcore_interface_dat_w;
-assign soc_litedramcore_interface_dat_r = vns_dat_r;
-assign vns_interface0_bank_bus_adr = vns_adr;
-assign vns_interface1_bank_bus_adr = vns_adr;
-assign vns_interface2_bank_bus_adr = vns_adr;
-assign vns_interface3_bank_bus_adr = vns_adr;
-assign vns_interface4_bank_bus_adr = vns_adr;
-assign vns_interface5_bank_bus_adr = vns_adr;
-assign vns_interface6_bank_bus_adr = vns_adr;
-assign vns_interface0_bank_bus_we = vns_we;
-assign vns_interface1_bank_bus_we = vns_we;
-assign vns_interface2_bank_bus_we = vns_we;
-assign vns_interface3_bank_bus_we = vns_we;
-assign vns_interface4_bank_bus_we = vns_we;
-assign vns_interface5_bank_bus_we = vns_we;
-assign vns_interface6_bank_bus_we = vns_we;
-assign vns_interface0_bank_bus_dat_w = vns_dat_w;
-assign vns_interface1_bank_bus_dat_w = vns_dat_w;
-assign vns_interface2_bank_bus_dat_w = vns_dat_w;
-assign vns_interface3_bank_bus_dat_w = vns_dat_w;
-assign vns_interface4_bank_bus_dat_w = vns_dat_w;
-assign vns_interface5_bank_bus_dat_w = vns_dat_w;
-assign vns_interface6_bank_bus_dat_w = vns_dat_w;
-assign vns_dat_r = ((((((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r) | vns_interface3_bank_bus_dat_r) | vns_interface4_bank_bus_dat_r) | vns_interface5_bank_bus_dat_r) | vns_interface6_bank_bus_dat_r);
 
 // synthesis translate_off
-reg dummy_d_338;
+reg dummy_d_274;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed0 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[0];
-               end
+       litedramcore_en1 <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[1];
+                       litedramcore_en1 <= 1'd1;
                end
                2'd2: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[2];
                end
                2'd3: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[3];
                end
                3'd4: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[4];
                end
                3'd5: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[5];
                end
                3'd6: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[6];
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_338 = dummy_s;
+       dummy_d_274 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_339;
+reg dummy_d_275;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed1 <= 14'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_a;
-               end
+       litedramcore_steerer_sel3 <= 2'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_a;
+                       litedramcore_steerer_sel3 <= 2'd2;
                end
                2'd2: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_a;
                end
                2'd3: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_a;
                end
                3'd4: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_a;
                end
                3'd5: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_a;
                end
                3'd6: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_a;
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_a;
+                       litedramcore_steerer_sel3 <= 1'd0;
                end
        endcase
 // synthesis translate_off
-       dummy_d_339 = dummy_s;
+       dummy_d_275 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_340;
+reg dummy_d_276;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed2 <= 3'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_ba;
-               end
+       litedramcore_steerer_sel0 <= 2'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_ba;
+                       litedramcore_steerer_sel0 <= 1'd0;
                end
                2'd2: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_ba;
+                       litedramcore_steerer_sel0 <= 2'd3;
                end
                2'd3: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_ba;
                end
                3'd4: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_ba;
                end
                3'd5: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_ba;
                end
                3'd6: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_ba;
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_ba;
+                       litedramcore_steerer_sel0 <= 1'd0;
                end
        endcase
 // synthesis translate_off
-       dummy_d_340 = dummy_s;
+       dummy_d_276 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_341;
+reg dummy_d_277;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed3 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_is_read;
-               end
+       litedramcore_steerer_sel1 <= 2'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_is_read;
+                       litedramcore_steerer_sel1 <= 1'd0;
                end
                2'd2: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_is_read;
                end
                2'd3: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_is_read;
                end
                3'd4: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_is_read;
                end
                3'd5: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_is_read;
                end
                3'd6: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_is_read;
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_is_read;
+                       litedramcore_steerer_sel1 <= 1'd1;
                end
        endcase
 // synthesis translate_off
-       dummy_d_341 = dummy_s;
+       dummy_d_277 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_342;
+reg dummy_d_278;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed4 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_is_write;
-               end
+       litedramcore_steerer_sel2 <= 2'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_is_write;
+                       litedramcore_steerer_sel2 <= 1'd1;
                end
                2'd2: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_is_write;
                end
                2'd3: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_is_write;
                end
                3'd4: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_is_write;
                end
                3'd5: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_is_write;
                end
                3'd6: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_is_write;
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_is_write;
+                       litedramcore_steerer_sel2 <= 2'd2;
                end
        endcase
 // synthesis translate_off
-       dummy_d_342 = dummy_s;
+       dummy_d_278 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_343;
+reg dummy_d_279;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed5 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_is_cmd;
-               end
+       litedramcore_choose_cmd_want_activates <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_is_cmd;
+                       if (1'd0) begin
+                       end else begin
+                               litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+                       end
                end
                2'd2: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_is_cmd;
                end
                2'd3: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_is_cmd;
                end
                3'd4: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_is_cmd;
                end
                3'd5: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_is_cmd;
                end
                3'd6: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_is_cmd;
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_is_cmd;
+                       if (1'd0) begin
+                       end else begin
+                               litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_343 = dummy_s;
+       dummy_d_279 = dummy_s;
 // synthesis translate_on
 end
+assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
+assign litedramcore_interface_bank0_we = rhs_array_muxed13;
+assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
+assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
+assign litedramcore_interface_bank1_we = rhs_array_muxed16;
+assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
+assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
+assign litedramcore_interface_bank2_we = rhs_array_muxed19;
+assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
+assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
+assign litedramcore_interface_bank3_we = rhs_array_muxed22;
+assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
+assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
+assign litedramcore_interface_bank4_we = rhs_array_muxed25;
+assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
+assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
+assign litedramcore_interface_bank5_we = rhs_array_muxed28;
+assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
+assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
+assign litedramcore_interface_bank6_we = rhs_array_muxed31;
+assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
+assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
+assign litedramcore_interface_bank7_we = rhs_array_muxed34;
+assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
+assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = new_master_wdata_ready2;
+assign user_port_rdata_valid = new_master_rdata_valid8;
 
 // synthesis translate_off
-reg dummy_d_344;
+reg dummy_d_280;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed0 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine0_cmd_payload_cas;
-               end
+       litedramcore_interface_wdata_we <= 16'd0;
+       case ({new_master_wdata_ready2})
                1'd1: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine1_cmd_payload_cas;
-               end
-               2'd2: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine2_cmd_payload_cas;
-               end
-               2'd3: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine3_cmd_payload_cas;
-               end
-               3'd4: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine4_cmd_payload_cas;
+                       litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
                end
-               3'd5: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine5_cmd_payload_cas;
+               default: begin
+                       litedramcore_interface_wdata_we <= 1'd0;
                end
-               3'd6: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine6_cmd_payload_cas;
+       endcase
+// synthesis translate_off
+       dummy_d_280 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_281;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_interface_wdata <= 128'd0;
+       case ({new_master_wdata_ready2})
+               1'd1: begin
+                       litedramcore_interface_wdata <= user_port_wdata_payload_data;
                end
                default: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine7_cmd_payload_cas;
+                       litedramcore_interface_wdata <= 1'd0;
                end
        endcase
 // synthesis translate_off
-       dummy_d_344 = dummy_s;
+       dummy_d_281 = dummy_s;
 // synthesis translate_on
 end
+assign user_port_rdata_payload_data = litedramcore_interface_rdata;
+assign roundrobin0_grant = 1'd0;
+assign roundrobin1_grant = 1'd0;
+assign roundrobin2_grant = 1'd0;
+assign roundrobin3_grant = 1'd0;
+assign roundrobin4_grant = 1'd0;
+assign roundrobin5_grant = 1'd0;
+assign roundrobin6_grant = 1'd0;
+assign roundrobin7_grant = 1'd0;
 
 // synthesis translate_off
-reg dummy_d_345;
+reg dummy_d_282;
+// synthesis translate_on
+always @(*) begin
+       csrbank0_sel <= 1'd0;
+       csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2);
+       if (interface0_bank_bus_adr[0]) begin
+               csrbank0_sel <= 1'd0;
+       end
+// synthesis translate_off
+       dummy_d_282 = dummy_s;
+// synthesis translate_on
+end
+assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0));
+assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0));
+assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1));
+assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1));
+assign csrbank0_init_done0_w = init_done_storage;
+assign csrbank0_init_error0_w = init_error_storage;
+
+// synthesis translate_off
+reg dummy_d_283;
+// synthesis translate_on
+always @(*) begin
+       csrbank1_sel <= 1'd0;
+       csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0);
+       if (interface1_bank_bus_adr[0]) begin
+               csrbank1_sel <= 1'd0;
+       end
+// synthesis translate_off
+       dummy_d_283 = dummy_s;
+// synthesis translate_on
+end
+assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
+assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0));
+assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0));
+assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
+assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1));
+assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1));
+assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2));
+assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2));
+assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3));
+assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3));
+assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4));
+assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4));
+assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
+assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5));
+assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5));
+assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6));
+assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6));
+assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7));
+assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7));
+assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9));
+assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9));
+assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
+assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
+assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
+
+// synthesis translate_off
+reg dummy_d_284;
+// synthesis translate_on
+always @(*) begin
+       csrbank2_sel <= 1'd0;
+       csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1);
+       if (interface2_bank_bus_adr[0]) begin
+               csrbank2_sel <= 1'd0;
+       end
+// synthesis translate_off
+       dummy_d_284 = dummy_s;
+// synthesis translate_on
+end
+assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
+assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0));
+assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0));
+assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1));
+assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1));
+assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2));
+assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3));
+assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3));
+assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4));
+assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4));
+assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5));
+assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5));
+assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6));
+assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6));
+assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7));
+assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7));
+assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8));
+assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8));
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9));
+assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9));
+assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10));
+assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10));
+assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11));
+assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11));
+assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12));
+assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12));
+assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13));
+assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13));
+assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14));
+assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14));
+assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15));
+assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15));
+assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16));
+assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16));
+assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17));
+assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17));
+assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18));
+assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18));
+assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19));
+assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19));
+assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20));
+assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20));
+assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21));
+assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21));
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22));
+assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22));
+assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23));
+assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23));
+assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24));
+assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24));
+assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25));
+assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25));
+assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26));
+assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26));
+assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27));
+assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27));
+assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28));
+assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28));
+assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29));
+assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29));
+assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30));
+assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30));
+assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31));
+assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31));
+assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32));
+assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32));
+assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33));
+assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33));
+assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34));
+assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34));
+assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35));
+assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35));
+assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36));
+assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36));
+assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37));
+assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37));
+assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38));
+assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38));
+assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39));
+assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39));
+assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40));
+assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40));
+assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41));
+assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41));
+assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42));
+assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42));
+assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43));
+assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43));
+assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44));
+assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44));
+assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45));
+assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45));
+assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46));
+assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46));
+assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47));
+assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47));
+assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48));
+assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48));
+assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49));
+assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49));
+assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50));
+assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50));
+assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51));
+assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51));
+assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52));
+assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52));
+assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
+assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[13:8];
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0];
+assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24];
+assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16];
+assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8];
+assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0];
+assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24];
+assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16];
+assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8];
+assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0];
+assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we;
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
+assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[13:8];
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0];
+assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24];
+assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16];
+assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8];
+assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0];
+assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24];
+assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16];
+assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8];
+assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0];
+assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we;
+assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
+assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[13:8];
+assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0];
+assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
+assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24];
+assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16];
+assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8];
+assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0];
+assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24];
+assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16];
+assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8];
+assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0];
+assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we;
+assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
+assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[13:8];
+assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0];
+assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
+assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24];
+assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16];
+assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8];
+assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0];
+assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24];
+assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16];
+assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8];
+assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0];
+assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we;
+assign adr = csr_port_adr;
+assign we = csr_port_we;
+assign dat_w = csr_port_dat_w;
+assign csr_port_dat_r = dat_r;
+assign interface0_bank_bus_adr = adr;
+assign interface1_bank_bus_adr = adr;
+assign interface2_bank_bus_adr = adr;
+assign interface0_bank_bus_we = we;
+assign interface1_bank_bus_we = we;
+assign interface2_bank_bus_we = we;
+assign interface0_bank_bus_dat_w = dat_w;
+assign interface1_bank_bus_dat_w = dat_w;
+assign interface2_bank_bus_dat_w = dat_w;
+assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+
+// synthesis translate_off
+reg dummy_d_285;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed1 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
+       rhs_array_muxed0 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
                end
                1'd1: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
                end
                2'd2: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
                end
                2'd3: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
                end
                3'd4: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
                end
                3'd5: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
                end
                3'd6: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
                end
                default: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_345 = dummy_s;
+       dummy_d_285 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_346;
+reg dummy_d_286;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed2 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
+       rhs_array_muxed1 <= 14'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
                end
                1'd1: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
                end
                2'd2: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
                end
                2'd3: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
                end
                3'd4: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
                end
                3'd5: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
                end
                3'd6: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
                end
                default: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_346 = dummy_s;
+       dummy_d_286 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_347;
+reg dummy_d_287;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed6 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed2 <= 3'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[0];
+                       rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
                end
                1'd1: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[1];
+                       rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
                end
                2'd2: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[2];
+                       rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
                end
                2'd3: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[3];
+                       rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
                end
                3'd4: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[4];
+                       rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
                end
                3'd5: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[5];
+                       rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
                end
                3'd6: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[6];
+                       rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
                end
                default: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[7];
+                       rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
                end
        endcase
 // synthesis translate_off
-       dummy_d_347 = dummy_s;
+       dummy_d_287 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_348;
+reg dummy_d_288;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed7 <= 14'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed3 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine0_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
                end
                1'd1: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine1_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
                end
                2'd2: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine2_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
                end
                2'd3: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine3_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
                end
                3'd4: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine4_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
                end
                3'd5: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine5_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
                end
                3'd6: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine6_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
                end
                default: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine7_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
                end
        endcase
 // synthesis translate_off
-       dummy_d_348 = dummy_s;
+       dummy_d_288 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_349;
+reg dummy_d_289;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed8 <= 3'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed4 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine0_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
                end
                1'd1: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine1_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
                end
                2'd2: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine2_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
                end
                2'd3: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine3_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
                end
                3'd4: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine4_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
                end
                3'd5: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine5_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
                end
                3'd6: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine6_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
                end
                default: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine7_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
                end
        endcase
 // synthesis translate_off
-       dummy_d_349 = dummy_s;
+       dummy_d_289 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_350;
+reg dummy_d_290;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed9 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed5 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine0_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
                end
                1'd1: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine1_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
                end
                2'd2: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine2_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
                end
                2'd3: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine3_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
                end
                3'd4: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine4_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
                end
                3'd5: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine5_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
                end
                3'd6: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine6_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
                end
                default: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine7_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
                end
        endcase
 // synthesis translate_off
-       dummy_d_350 = dummy_s;
+       dummy_d_290 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_351;
+reg dummy_d_291;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed10 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       t_array_muxed0 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine0_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
                end
                1'd1: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine1_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
                end
                2'd2: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine2_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
                end
                2'd3: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine3_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
                end
                3'd4: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine4_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
                end
                3'd5: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine5_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
                end
                3'd6: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine6_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
                end
                default: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine7_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
                end
        endcase
 // synthesis translate_off
-       dummy_d_351 = dummy_s;
+       dummy_d_291 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_352;
+reg dummy_d_292;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed11 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       t_array_muxed1 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine0_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
                end
                1'd1: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine1_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
                end
                2'd2: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine2_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
                end
                2'd3: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine3_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
                end
                3'd4: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine4_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
                end
                3'd5: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine5_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
                end
                3'd6: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine6_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
                end
                default: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine7_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
                end
        endcase
 // synthesis translate_off
-       dummy_d_352 = dummy_s;
+       dummy_d_292 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_353;
+reg dummy_d_293;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed3 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       t_array_muxed2 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
                end
                1'd1: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
                end
                2'd2: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
                end
                2'd3: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
                end
                3'd4: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
                end
                3'd5: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
                end
                3'd6: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
                end
                default: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_353 = dummy_s;
+       dummy_d_293 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_354;
+reg dummy_d_294;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed4 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed6 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
                end
                1'd1: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
                end
                2'd2: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
                end
                2'd3: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
                end
                3'd4: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
                end
                3'd5: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
                end
                3'd6: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
                end
                default: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_354 = dummy_s;
+       dummy_d_294 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_355;
+reg dummy_d_295;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed5 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed7 <= 14'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
                end
                1'd1: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
                end
                2'd2: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
                end
                2'd3: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
                end
                3'd4: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
                end
                3'd5: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
                end
                3'd6: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
                end
                default: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_355 = dummy_s;
+       dummy_d_295 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_356;
+reg dummy_d_296;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed12 <= 21'd0;
-       case (vns_roundrobin0_grant)
+       rhs_array_muxed8 <= 3'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed12 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+                       rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
                end
-               default: begin
-                       vns_rhs_array_muxed12 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+               1'd1: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
                end
-       endcase
-// synthesis translate_off
-       dummy_d_356 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_357;
-// synthesis translate_on
-always @(*) begin
-       vns_rhs_array_muxed13 <= 1'd0;
-       case (vns_roundrobin0_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed13 <= soc_port_cmd_payload_we;
+               2'd2: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+               end
+               2'd3: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+               end
+               3'd4: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+               end
+               3'd5: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+               end
+               3'd6: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
                end
                default: begin
-                       vns_rhs_array_muxed13 <= soc_cmd_payload_we;
+                       rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
                end
        endcase
 // synthesis translate_off
-       dummy_d_357 = dummy_s;
+       dummy_d_296 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_358;
+reg dummy_d_297;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed14 <= 1'd0;
-       case (vns_roundrobin0_grant)
+       rhs_array_muxed9 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed14 <= (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+                       rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+               end
+               1'd1: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+               end
+               2'd2: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+               end
+               2'd3: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+               end
+               3'd4: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+               end
+               3'd5: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+               end
+               3'd6: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
                end
                default: begin
-                       vns_rhs_array_muxed14 <= (((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
                end
        endcase
 // synthesis translate_off
-       dummy_d_358 = dummy_s;
+       dummy_d_297 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_359;
+reg dummy_d_298;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed15 <= 21'd0;
-       case (vns_roundrobin1_grant)
+       rhs_array_muxed10 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed15 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+                       rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+               end
+               1'd1: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+               end
+               2'd2: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+               end
+               2'd3: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+               end
+               3'd4: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+               end
+               3'd5: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+               end
+               3'd6: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
                end
                default: begin
-                       vns_rhs_array_muxed15 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
                end
        endcase
 // synthesis translate_off
-       dummy_d_359 = dummy_s;
+       dummy_d_298 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_360;
+reg dummy_d_299;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed16 <= 1'd0;
-       case (vns_roundrobin1_grant)
+       rhs_array_muxed11 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed16 <= soc_port_cmd_payload_we;
+                       rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+               end
+               1'd1: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+               end
+               2'd2: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+               end
+               2'd3: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+               end
+               3'd4: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+               end
+               3'd5: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+               end
+               3'd6: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
                end
                default: begin
-                       vns_rhs_array_muxed16 <= soc_cmd_payload_we;
+                       rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
                end
        endcase
 // synthesis translate_off
-       dummy_d_360 = dummy_s;
+       dummy_d_299 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_361;
+reg dummy_d_300;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed17 <= 1'd0;
-       case (vns_roundrobin1_grant)
+       t_array_muxed3 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed17 <= (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+                       t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+               end
+               1'd1: begin
+                       t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+               end
+               2'd2: begin
+                       t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+               end
+               2'd3: begin
+                       t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+               end
+               3'd4: begin
+                       t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+               end
+               3'd5: begin
+                       t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+               end
+               3'd6: begin
+                       t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
                end
                default: begin
-                       vns_rhs_array_muxed17 <= (((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
                end
        endcase
 // synthesis translate_off
-       dummy_d_361 = dummy_s;
+       dummy_d_300 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_362;
+reg dummy_d_301;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed18 <= 21'd0;
-       case (vns_roundrobin2_grant)
+       t_array_muxed4 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed18 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
+                       t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+               end
+               1'd1: begin
+                       t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+               end
+               2'd2: begin
+                       t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+               end
+               2'd3: begin
+                       t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+               end
+               3'd4: begin
+                       t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+               end
+               3'd5: begin
+                       t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+               end
+               3'd6: begin
+                       t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
                end
                default: begin
-                       vns_rhs_array_muxed18 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+                       t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
                end
        endcase
 // synthesis translate_off
-       dummy_d_362 = dummy_s;
+       dummy_d_301 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_363;
+reg dummy_d_302;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed19 <= 1'd0;
-       case (vns_roundrobin2_grant)
+       t_array_muxed5 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed19 <= soc_port_cmd_payload_we;
+                       t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+               end
+               1'd1: begin
+                       t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+               end
+               2'd2: begin
+                       t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+               end
+               2'd3: begin
+                       t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+               end
+               3'd4: begin
+                       t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+               end
+               3'd5: begin
+                       t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+               end
+               3'd6: begin
+                       t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
                end
                default: begin
-                       vns_rhs_array_muxed19 <= soc_cmd_payload_we;
+                       t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_363 = dummy_s;
+       dummy_d_302 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_364;
+reg dummy_d_303;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed20 <= 1'd0;
-       case (vns_roundrobin2_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed20 <= (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed12 <= 21'd0;
+       case (roundrobin0_grant)
                default: begin
-                       vns_rhs_array_muxed20 <= (((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_364 = dummy_s;
+       dummy_d_303 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_365;
+reg dummy_d_304;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed21 <= 21'd0;
-       case (vns_roundrobin3_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed21 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
-               end
+       rhs_array_muxed13 <= 1'd0;
+       case (roundrobin0_grant)
                default: begin
-                       vns_rhs_array_muxed21 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed13 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_365 = dummy_s;
+       dummy_d_304 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_366;
+reg dummy_d_305;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed22 <= 1'd0;
-       case (vns_roundrobin3_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed22 <= soc_port_cmd_payload_we;
-               end
+       rhs_array_muxed14 <= 1'd0;
+       case (roundrobin0_grant)
                default: begin
-                       vns_rhs_array_muxed22 <= soc_cmd_payload_we;
+                       rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_366 = dummy_s;
+       dummy_d_305 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_367;
+reg dummy_d_306;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed23 <= 1'd0;
-       case (vns_roundrobin3_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed23 <= (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed15 <= 21'd0;
+       case (roundrobin1_grant)
                default: begin
-                       vns_rhs_array_muxed23 <= (((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_367 = dummy_s;
+       dummy_d_306 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_368;
+reg dummy_d_307;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed24 <= 21'd0;
-       case (vns_roundrobin4_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed24 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
-               end
+       rhs_array_muxed16 <= 1'd0;
+       case (roundrobin1_grant)
                default: begin
-                       vns_rhs_array_muxed24 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed16 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_368 = dummy_s;
+       dummy_d_307 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_369;
+reg dummy_d_308;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed25 <= 1'd0;
-       case (vns_roundrobin4_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed25 <= soc_port_cmd_payload_we;
-               end
+       rhs_array_muxed17 <= 1'd0;
+       case (roundrobin1_grant)
                default: begin
-                       vns_rhs_array_muxed25 <= soc_cmd_payload_we;
+                       rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_369 = dummy_s;
+       dummy_d_308 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_370;
+reg dummy_d_309;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed26 <= 1'd0;
-       case (vns_roundrobin4_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed26 <= (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed18 <= 21'd0;
+       case (roundrobin2_grant)
                default: begin
-                       vns_rhs_array_muxed26 <= (((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_370 = dummy_s;
+       dummy_d_309 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_371;
+reg dummy_d_310;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed27 <= 21'd0;
-       case (vns_roundrobin5_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed27 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
-               end
+       rhs_array_muxed19 <= 1'd0;
+       case (roundrobin2_grant)
                default: begin
-                       vns_rhs_array_muxed27 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed19 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_371 = dummy_s;
+       dummy_d_310 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_372;
+reg dummy_d_311;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed28 <= 1'd0;
-       case (vns_roundrobin5_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed28 <= soc_port_cmd_payload_we;
-               end
+       rhs_array_muxed20 <= 1'd0;
+       case (roundrobin2_grant)
                default: begin
-                       vns_rhs_array_muxed28 <= soc_cmd_payload_we;
+                       rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_372 = dummy_s;
+       dummy_d_311 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_373;
+reg dummy_d_312;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed29 <= 1'd0;
-       case (vns_roundrobin5_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed29 <= (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed21 <= 21'd0;
+       case (roundrobin3_grant)
                default: begin
-                       vns_rhs_array_muxed29 <= (((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_373 = dummy_s;
+       dummy_d_312 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_374;
+reg dummy_d_313;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed30 <= 21'd0;
-       case (vns_roundrobin6_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed30 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
-               end
+       rhs_array_muxed22 <= 1'd0;
+       case (roundrobin3_grant)
                default: begin
-                       vns_rhs_array_muxed30 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed22 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_374 = dummy_s;
+       dummy_d_313 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_375;
+reg dummy_d_314;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed31 <= 1'd0;
-       case (vns_roundrobin6_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed31 <= soc_port_cmd_payload_we;
-               end
+       rhs_array_muxed23 <= 1'd0;
+       case (roundrobin3_grant)
                default: begin
-                       vns_rhs_array_muxed31 <= soc_cmd_payload_we;
+                       rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_375 = dummy_s;
+       dummy_d_314 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_376;
+reg dummy_d_315;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed32 <= 1'd0;
-       case (vns_roundrobin6_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed32 <= (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed24 <= 21'd0;
+       case (roundrobin4_grant)
                default: begin
-                       vns_rhs_array_muxed32 <= (((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_376 = dummy_s;
+       dummy_d_315 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_377;
+reg dummy_d_316;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed33 <= 21'd0;
-       case (vns_roundrobin7_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed33 <= {soc_port_cmd_payload_addr[23:10], soc_port_cmd_payload_addr[6:0]};
-               end
+       rhs_array_muxed25 <= 1'd0;
+       case (roundrobin4_grant)
                default: begin
-                       vns_rhs_array_muxed33 <= {soc_cmd_payload_addr[23:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed25 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_377 = dummy_s;
+       dummy_d_316 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_378;
+reg dummy_d_317;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed34 <= 1'd0;
-       case (vns_roundrobin7_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed34 <= soc_port_cmd_payload_we;
-               end
+       rhs_array_muxed26 <= 1'd0;
+       case (roundrobin4_grant)
                default: begin
-                       vns_rhs_array_muxed34 <= soc_cmd_payload_we;
+                       rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_378 = dummy_s;
+       dummy_d_317 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_379;
+reg dummy_d_318;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed35 <= 1'd0;
-       case (vns_roundrobin7_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed35 <= (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed27 <= 21'd0;
+       case (roundrobin5_grant)
                default: begin
-                       vns_rhs_array_muxed35 <= (((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_379 = dummy_s;
+       dummy_d_318 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_380;
+reg dummy_d_319;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed36 <= 30'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed36 <= soc_litedramcore_cpu_ibus_adr;
-               end
+       rhs_array_muxed28 <= 1'd0;
+       case (roundrobin5_grant)
                default: begin
-                       vns_rhs_array_muxed36 <= soc_litedramcore_cpu_dbus_adr;
+                       rhs_array_muxed28 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_380 = dummy_s;
+       dummy_d_319 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_381;
+reg dummy_d_320;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed37 <= 32'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed37 <= soc_litedramcore_cpu_ibus_dat_w;
-               end
+       rhs_array_muxed29 <= 1'd0;
+       case (roundrobin5_grant)
                default: begin
-                       vns_rhs_array_muxed37 <= soc_litedramcore_cpu_dbus_dat_w;
+                       rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_381 = dummy_s;
+       dummy_d_320 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_382;
+reg dummy_d_321;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed38 <= 4'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed38 <= soc_litedramcore_cpu_ibus_sel;
-               end
+       rhs_array_muxed30 <= 21'd0;
+       case (roundrobin6_grant)
                default: begin
-                       vns_rhs_array_muxed38 <= soc_litedramcore_cpu_dbus_sel;
+                       rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_382 = dummy_s;
+       dummy_d_321 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_383;
+reg dummy_d_322;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed39 <= 1'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed39 <= soc_litedramcore_cpu_ibus_cyc;
-               end
+       rhs_array_muxed31 <= 1'd0;
+       case (roundrobin6_grant)
                default: begin
-                       vns_rhs_array_muxed39 <= soc_litedramcore_cpu_dbus_cyc;
+                       rhs_array_muxed31 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_383 = dummy_s;
+       dummy_d_322 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_384;
+reg dummy_d_323;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed40 <= 1'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed40 <= soc_litedramcore_cpu_ibus_stb;
-               end
+       rhs_array_muxed32 <= 1'd0;
+       case (roundrobin6_grant)
                default: begin
-                       vns_rhs_array_muxed40 <= soc_litedramcore_cpu_dbus_stb;
+                       rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_384 = dummy_s;
+       dummy_d_323 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_385;
+reg dummy_d_324;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed41 <= 1'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed41 <= soc_litedramcore_cpu_ibus_we;
-               end
+       rhs_array_muxed33 <= 21'd0;
+       case (roundrobin7_grant)
                default: begin
-                       vns_rhs_array_muxed41 <= soc_litedramcore_cpu_dbus_we;
+                       rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_385 = dummy_s;
+       dummy_d_324 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_386;
+reg dummy_d_325;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed42 <= 3'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed42 <= soc_litedramcore_cpu_ibus_cti;
-               end
+       rhs_array_muxed34 <= 1'd0;
+       case (roundrobin7_grant)
                default: begin
-                       vns_rhs_array_muxed42 <= soc_litedramcore_cpu_dbus_cti;
+                       rhs_array_muxed34 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_386 = dummy_s;
+       dummy_d_325 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_387;
+reg dummy_d_326;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed43 <= 2'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed43 <= soc_litedramcore_cpu_ibus_bte;
-               end
+       rhs_array_muxed35 <= 1'd0;
+       case (roundrobin7_grant)
                default: begin
-                       vns_rhs_array_muxed43 <= soc_litedramcore_cpu_dbus_bte;
+                       rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_387 = dummy_s;
+       dummy_d_326 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_388;
+reg dummy_d_327;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed0 <= 3'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed0 <= 3'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed0 <= soc_sdram_nop_ba[2:0];
+                       array_muxed0 <= litedramcore_nop_ba[2:0];
                end
                1'd1: begin
-                       vns_array_muxed0 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+                       array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
                end
                2'd2: begin
-                       vns_array_muxed0 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+                       array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
                end
                default: begin
-                       vns_array_muxed0 <= soc_sdram_cmd_payload_ba[2:0];
+                       array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
                end
        endcase
 // synthesis translate_off
-       dummy_d_388 = dummy_s;
+       dummy_d_327 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_389;
+reg dummy_d_328;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed1 <= 14'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed1 <= 14'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed1 <= soc_sdram_nop_a;
+                       array_muxed1 <= litedramcore_nop_a;
                end
                1'd1: begin
-                       vns_array_muxed1 <= soc_sdram_choose_cmd_cmd_payload_a;
+                       array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
                end
                2'd2: begin
-                       vns_array_muxed1 <= soc_sdram_choose_req_cmd_payload_a;
+                       array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
                end
                default: begin
-                       vns_array_muxed1 <= soc_sdram_cmd_payload_a;
+                       array_muxed1 <= litedramcore_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_389 = dummy_s;
+       dummy_d_328 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_390;
+reg dummy_d_329;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed2 <= 1'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed2 <= 1'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed2 <= 1'd0;
+                       array_muxed2 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed2 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+                       array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
                end
                2'd2: begin
-                       vns_array_muxed2 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+                       array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
                end
                default: begin
-                       vns_array_muxed2 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+                       array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
                end
        endcase
 // synthesis translate_off
-       dummy_d_390 = dummy_s;
+       dummy_d_329 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_391;
+reg dummy_d_330;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed3 <= 1'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed3 <= 1'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed3 <= 1'd0;
+                       array_muxed3 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed3 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+                       array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
                end
                2'd2: begin
-                       vns_array_muxed3 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+                       array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
                end
                default: begin
-                       vns_array_muxed3 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+                       array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
                end
        endcase
 // synthesis translate_off
-       dummy_d_391 = dummy_s;
+       dummy_d_330 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_392;
+reg dummy_d_331;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed4 <= 1'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed4 <= 1'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed4 <= 1'd0;
+                       array_muxed4 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed4 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+                       array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
                end
                2'd2: begin
-                       vns_array_muxed4 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+                       array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
                end
                default: begin
-                       vns_array_muxed4 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+                       array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
                end
        endcase
 // synthesis translate_off
-       dummy_d_392 = dummy_s;
+       dummy_d_331 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_393;
+reg dummy_d_332;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed5 <= 1'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed5 <= 1'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed5 <= 1'd0;
+                       array_muxed5 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed5 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+                       array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
                end
                2'd2: begin
-                       vns_array_muxed5 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+                       array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
                end
                default: begin
-                       vns_array_muxed5 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+                       array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
                end
        endcase
 // synthesis translate_off
-       dummy_d_393 = dummy_s;
+       dummy_d_332 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_394;
+reg dummy_d_333;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed6 <= 1'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed6 <= 1'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed6 <= 1'd0;
+                       array_muxed6 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed6 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+                       array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
                end
                2'd2: begin
-                       vns_array_muxed6 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+                       array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
                end
                default: begin
-                       vns_array_muxed6 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+                       array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
                end
        endcase
 // synthesis translate_off
-       dummy_d_394 = dummy_s;
+       dummy_d_333 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_395;
+reg dummy_d_334;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed7 <= 3'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed7 <= 3'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed7 <= soc_sdram_nop_ba[2:0];
+                       array_muxed7 <= litedramcore_nop_ba[2:0];
                end
                1'd1: begin
-                       vns_array_muxed7 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+                       array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
                end
                2'd2: begin
-                       vns_array_muxed7 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+                       array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
                end
                default: begin
-                       vns_array_muxed7 <= soc_sdram_cmd_payload_ba[2:0];
+                       array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
                end
        endcase
 // synthesis translate_off
-       dummy_d_395 = dummy_s;
+       dummy_d_334 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_396;
+reg dummy_d_335;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed8 <= 14'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed8 <= 14'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed8 <= soc_sdram_nop_a;
+                       array_muxed8 <= litedramcore_nop_a;
                end
                1'd1: begin
-                       vns_array_muxed8 <= soc_sdram_choose_cmd_cmd_payload_a;
+                       array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
                end
                2'd2: begin
-                       vns_array_muxed8 <= soc_sdram_choose_req_cmd_payload_a;
+                       array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
                end
                default: begin
-                       vns_array_muxed8 <= soc_sdram_cmd_payload_a;
+                       array_muxed8 <= litedramcore_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_396 = dummy_s;
+       dummy_d_335 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_397;
+reg dummy_d_336;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed9 <= 1'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed9 <= 1'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed9 <= 1'd0;
+                       array_muxed9 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed9 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+                       array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
                end
                2'd2: begin
-                       vns_array_muxed9 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+                       array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
                end
                default: begin
-                       vns_array_muxed9 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+                       array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
                end
        endcase
 // synthesis translate_off
-       dummy_d_397 = dummy_s;
+       dummy_d_336 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_398;
+reg dummy_d_337;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed10 <= 1'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed10 <= 1'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed10 <= 1'd0;
+                       array_muxed10 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed10 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+                       array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
                end
                2'd2: begin
-                       vns_array_muxed10 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+                       array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
                end
                default: begin
-                       vns_array_muxed10 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+                       array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
                end
        endcase
 // synthesis translate_off
-       dummy_d_398 = dummy_s;
+       dummy_d_337 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_399;
+reg dummy_d_338;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed11 <= 1'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed11 <= 1'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed11 <= 1'd0;
+                       array_muxed11 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed11 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+                       array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
                end
                2'd2: begin
-                       vns_array_muxed11 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+                       array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
                end
                default: begin
-                       vns_array_muxed11 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+                       array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
                end
        endcase
 // synthesis translate_off
-       dummy_d_399 = dummy_s;
+       dummy_d_338 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_400;
+reg dummy_d_339;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed12 <= 1'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed12 <= 1'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed12 <= 1'd0;
+                       array_muxed12 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed12 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+                       array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
                end
                2'd2: begin
-                       vns_array_muxed12 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+                       array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
                end
                default: begin
-                       vns_array_muxed12 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+                       array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
                end
        endcase
 // synthesis translate_off
-       dummy_d_400 = dummy_s;
+       dummy_d_339 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_401;
+reg dummy_d_340;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed13 <= 1'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed13 <= 1'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed13 <= 1'd0;
+                       array_muxed13 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed13 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+                       array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
                end
                2'd2: begin
-                       vns_array_muxed13 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+                       array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
                end
                default: begin
-                       vns_array_muxed13 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+                       array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
                end
        endcase
 // synthesis translate_off
-       dummy_d_401 = dummy_s;
+       dummy_d_340 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_402;
+reg dummy_d_341;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed14 <= 3'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed14 <= 3'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed14 <= soc_sdram_nop_ba[2:0];
+                       array_muxed14 <= litedramcore_nop_ba[2:0];
                end
                1'd1: begin
-                       vns_array_muxed14 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+                       array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
                end
                2'd2: begin
-                       vns_array_muxed14 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+                       array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
                end
                default: begin
-                       vns_array_muxed14 <= soc_sdram_cmd_payload_ba[2:0];
+                       array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
                end
        endcase
 // synthesis translate_off
-       dummy_d_402 = dummy_s;
+       dummy_d_341 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_403;
+reg dummy_d_342;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed15 <= 14'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed15 <= 14'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed15 <= soc_sdram_nop_a;
+                       array_muxed15 <= litedramcore_nop_a;
                end
                1'd1: begin
-                       vns_array_muxed15 <= soc_sdram_choose_cmd_cmd_payload_a;
+                       array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
                end
                2'd2: begin
-                       vns_array_muxed15 <= soc_sdram_choose_req_cmd_payload_a;
+                       array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
                end
                default: begin
-                       vns_array_muxed15 <= soc_sdram_cmd_payload_a;
+                       array_muxed15 <= litedramcore_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_403 = dummy_s;
+       dummy_d_342 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_404;
+reg dummy_d_343;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed16 <= 1'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed16 <= 1'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed16 <= 1'd0;
+                       array_muxed16 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed16 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+                       array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
                end
                2'd2: begin
-                       vns_array_muxed16 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+                       array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
                end
                default: begin
-                       vns_array_muxed16 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+                       array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
                end
        endcase
 // synthesis translate_off
-       dummy_d_404 = dummy_s;
+       dummy_d_343 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_405;
+reg dummy_d_344;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed17 <= 1'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed17 <= 1'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed17 <= 1'd0;
+                       array_muxed17 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed17 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+                       array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
                end
                2'd2: begin
-                       vns_array_muxed17 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+                       array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
                end
                default: begin
-                       vns_array_muxed17 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+                       array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
                end
        endcase
 // synthesis translate_off
-       dummy_d_405 = dummy_s;
+       dummy_d_344 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_406;
+reg dummy_d_345;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed18 <= 1'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed18 <= 1'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed18 <= 1'd0;
+                       array_muxed18 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed18 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+                       array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
                end
                2'd2: begin
-                       vns_array_muxed18 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+                       array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
                end
                default: begin
-                       vns_array_muxed18 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+                       array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
                end
        endcase
 // synthesis translate_off
-       dummy_d_406 = dummy_s;
+       dummy_d_345 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_407;
+reg dummy_d_346;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed19 <= 1'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed19 <= 1'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed19 <= 1'd0;
+                       array_muxed19 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed19 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+                       array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
                end
                2'd2: begin
-                       vns_array_muxed19 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+                       array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
                end
                default: begin
-                       vns_array_muxed19 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+                       array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
                end
        endcase
 // synthesis translate_off
-       dummy_d_407 = dummy_s;
+       dummy_d_346 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_408;
+reg dummy_d_347;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed20 <= 1'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed20 <= 1'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed20 <= 1'd0;
+                       array_muxed20 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed20 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+                       array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
                end
                2'd2: begin
-                       vns_array_muxed20 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+                       array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
                end
                default: begin
-                       vns_array_muxed20 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+                       array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
                end
        endcase
 // synthesis translate_off
-       dummy_d_408 = dummy_s;
+       dummy_d_347 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_409;
+reg dummy_d_348;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed21 <= 3'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed21 <= 3'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed21 <= soc_sdram_nop_ba[2:0];
+                       array_muxed21 <= litedramcore_nop_ba[2:0];
                end
                1'd1: begin
-                       vns_array_muxed21 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+                       array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
                end
                2'd2: begin
-                       vns_array_muxed21 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+                       array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
                end
                default: begin
-                       vns_array_muxed21 <= soc_sdram_cmd_payload_ba[2:0];
+                       array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
                end
        endcase
 // synthesis translate_off
-       dummy_d_409 = dummy_s;
+       dummy_d_348 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_410;
+reg dummy_d_349;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed22 <= 14'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed22 <= 14'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed22 <= soc_sdram_nop_a;
+                       array_muxed22 <= litedramcore_nop_a;
                end
                1'd1: begin
-                       vns_array_muxed22 <= soc_sdram_choose_cmd_cmd_payload_a;
+                       array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
                end
                2'd2: begin
-                       vns_array_muxed22 <= soc_sdram_choose_req_cmd_payload_a;
+                       array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
                end
                default: begin
-                       vns_array_muxed22 <= soc_sdram_cmd_payload_a;
+                       array_muxed22 <= litedramcore_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_410 = dummy_s;
+       dummy_d_349 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_411;
+reg dummy_d_350;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed23 <= 1'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed23 <= 1'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed23 <= 1'd0;
+                       array_muxed23 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed23 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+                       array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
                end
                2'd2: begin
-                       vns_array_muxed23 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+                       array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
                end
                default: begin
-                       vns_array_muxed23 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+                       array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
                end
        endcase
 // synthesis translate_off
-       dummy_d_411 = dummy_s;
+       dummy_d_350 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_412;
+reg dummy_d_351;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed24 <= 1'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed24 <= 1'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed24 <= 1'd0;
+                       array_muxed24 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed24 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+                       array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
                end
                2'd2: begin
-                       vns_array_muxed24 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+                       array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
                end
                default: begin
-                       vns_array_muxed24 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+                       array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
                end
        endcase
 // synthesis translate_off
-       dummy_d_412 = dummy_s;
+       dummy_d_351 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_413;
+reg dummy_d_352;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed25 <= 1'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed25 <= 1'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed25 <= 1'd0;
+                       array_muxed25 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed25 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+                       array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
                end
                2'd2: begin
-                       vns_array_muxed25 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+                       array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
                end
                default: begin
-                       vns_array_muxed25 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+                       array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
                end
        endcase
 // synthesis translate_off
-       dummy_d_413 = dummy_s;
+       dummy_d_352 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_414;
+reg dummy_d_353;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed26 <= 1'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed26 <= 1'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed26 <= 1'd0;
+                       array_muxed26 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed26 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+                       array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
                end
                2'd2: begin
-                       vns_array_muxed26 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+                       array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
                end
                default: begin
-                       vns_array_muxed26 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+                       array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
                end
        endcase
 // synthesis translate_off
-       dummy_d_414 = dummy_s;
+       dummy_d_353 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_415;
+reg dummy_d_354;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed27 <= 1'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed27 <= 1'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed27 <= 1'd0;
+                       array_muxed27 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed27 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+                       array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
                end
                2'd2: begin
-                       vns_array_muxed27 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+                       array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
                end
                default: begin
-                       vns_array_muxed27 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+                       array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
                end
        endcase
 // synthesis translate_off
-       dummy_d_415 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_rx = vns_regs1;
-assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
-assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
-assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
-assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_iodelay_pll_locked) | soc_iodelay_pll_reset);
-
-always @(posedge iodelay_clk) begin
-       if ((soc_reset_counter != 1'd0)) begin
-               soc_reset_counter <= (soc_reset_counter - 1'd1);
-       end else begin
-               soc_ic_reset <= 1'd0;
-       end
-       if (iodelay_rst) begin
-               soc_reset_counter <= 4'd15;
-               soc_ic_reset <= 1'd1;
-       end
-end
-
-always @(posedge sys_clk) begin
-       if ((soc_litedramcore_soccontroller_bus_errors != 32'd4294967295)) begin
-               if (soc_litedramcore_soccontroller_bus_error) begin
-                       soc_litedramcore_soccontroller_bus_errors <= (soc_litedramcore_soccontroller_bus_errors + 1'd1);
-               end
-       end
-       soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0;
-       if (((soc_litedramcore_litedramcore_ram_bus_cyc & soc_litedramcore_litedramcore_ram_bus_stb) & (~soc_litedramcore_litedramcore_ram_bus_ack))) begin
-               soc_litedramcore_litedramcore_ram_bus_ack <= 1'd1;
-       end
-       soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0;
-       if (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & (~soc_litedramcore_ram_bus_ram_bus_ack))) begin
-               soc_litedramcore_ram_bus_ram_bus_ack <= 1'd1;
-       end
-       soc_litedramcore_sink_ready <= 1'd0;
-       if (((soc_litedramcore_sink_valid & (~soc_litedramcore_tx_busy)) & (~soc_litedramcore_sink_ready))) begin
-               soc_litedramcore_tx_reg <= soc_litedramcore_sink_payload_data;
-               soc_litedramcore_tx_bitcount <= 1'd0;
-               soc_litedramcore_tx_busy <= 1'd1;
-               serial_tx <= 1'd0;
-       end else begin
-               if ((soc_litedramcore_uart_clk_txen & soc_litedramcore_tx_busy)) begin
-                       soc_litedramcore_tx_bitcount <= (soc_litedramcore_tx_bitcount + 1'd1);
-                       if ((soc_litedramcore_tx_bitcount == 4'd8)) begin
-                               serial_tx <= 1'd1;
-                       end else begin
-                               if ((soc_litedramcore_tx_bitcount == 4'd9)) begin
-                                       serial_tx <= 1'd1;
-                                       soc_litedramcore_tx_busy <= 1'd0;
-                                       soc_litedramcore_sink_ready <= 1'd1;
-                               end else begin
-                                       serial_tx <= soc_litedramcore_tx_reg[0];
-                                       soc_litedramcore_tx_reg <= {1'd0, soc_litedramcore_tx_reg[7:1]};
-                               end
-                       end
-               end
-       end
-       if (soc_litedramcore_tx_busy) begin
-               {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= (soc_litedramcore_phase_accumulator_tx + soc_litedramcore_storage);
-       end else begin
-               {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= 1'd0;
-       end
-       soc_litedramcore_source_valid <= 1'd0;
-       soc_litedramcore_rx_r <= soc_litedramcore_rx;
-       if ((~soc_litedramcore_rx_busy)) begin
-               if (((~soc_litedramcore_rx) & soc_litedramcore_rx_r)) begin
-                       soc_litedramcore_rx_busy <= 1'd1;
-                       soc_litedramcore_rx_bitcount <= 1'd0;
-               end
-       end else begin
-               if (soc_litedramcore_uart_clk_rxen) begin
-                       soc_litedramcore_rx_bitcount <= (soc_litedramcore_rx_bitcount + 1'd1);
-                       if ((soc_litedramcore_rx_bitcount == 1'd0)) begin
-                               if (soc_litedramcore_rx) begin
-                                       soc_litedramcore_rx_busy <= 1'd0;
-                               end
-                       end else begin
-                               if ((soc_litedramcore_rx_bitcount == 4'd9)) begin
-                                       soc_litedramcore_rx_busy <= 1'd0;
-                                       if (soc_litedramcore_rx) begin
-                                               soc_litedramcore_source_payload_data <= soc_litedramcore_rx_reg;
-                                               soc_litedramcore_source_valid <= 1'd1;
-                                       end
-                               end else begin
-                                       soc_litedramcore_rx_reg <= {soc_litedramcore_rx, soc_litedramcore_rx_reg[7:1]};
-                               end
-                       end
-               end
-       end
-       if (soc_litedramcore_rx_busy) begin
-               {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= (soc_litedramcore_phase_accumulator_rx + soc_litedramcore_storage);
-       end else begin
-               {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= 32'd2147483648;
-       end
-       if (soc_litedramcore_uart_tx_clear) begin
-               soc_litedramcore_uart_tx_pending <= 1'd0;
-       end
-       soc_litedramcore_uart_tx_old_trigger <= soc_litedramcore_uart_tx_trigger;
-       if (((~soc_litedramcore_uart_tx_trigger) & soc_litedramcore_uart_tx_old_trigger)) begin
-               soc_litedramcore_uart_tx_pending <= 1'd1;
-       end
-       if (soc_litedramcore_uart_rx_clear) begin
-               soc_litedramcore_uart_rx_pending <= 1'd0;
-       end
-       soc_litedramcore_uart_rx_old_trigger <= soc_litedramcore_uart_rx_trigger;
-       if (((~soc_litedramcore_uart_rx_trigger) & soc_litedramcore_uart_rx_old_trigger)) begin
-               soc_litedramcore_uart_rx_pending <= 1'd1;
-       end
-       if (soc_litedramcore_uart_tx_fifo_syncfifo_re) begin
-               soc_litedramcore_uart_tx_fifo_readable <= 1'd1;
-       end else begin
-               if (soc_litedramcore_uart_tx_fifo_re) begin
-                       soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
-               end
-       end
-       if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin
-               soc_litedramcore_uart_tx_fifo_produce <= (soc_litedramcore_uart_tx_fifo_produce + 1'd1);
-       end
-       if (soc_litedramcore_uart_tx_fifo_do_read) begin
-               soc_litedramcore_uart_tx_fifo_consume <= (soc_litedramcore_uart_tx_fifo_consume + 1'd1);
-       end
-       if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin
-               if ((~soc_litedramcore_uart_tx_fifo_do_read)) begin
-                       soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 + 1'd1);
-               end
-       end else begin
-               if (soc_litedramcore_uart_tx_fifo_do_read) begin
-                       soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 - 1'd1);
-               end
-       end
-       if (soc_litedramcore_uart_rx_fifo_syncfifo_re) begin
-               soc_litedramcore_uart_rx_fifo_readable <= 1'd1;
-       end else begin
-               if (soc_litedramcore_uart_rx_fifo_re) begin
-                       soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
-               end
-       end
-       if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin
-               soc_litedramcore_uart_rx_fifo_produce <= (soc_litedramcore_uart_rx_fifo_produce + 1'd1);
-       end
-       if (soc_litedramcore_uart_rx_fifo_do_read) begin
-               soc_litedramcore_uart_rx_fifo_consume <= (soc_litedramcore_uart_rx_fifo_consume + 1'd1);
-       end
-       if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin
-               if ((~soc_litedramcore_uart_rx_fifo_do_read)) begin
-                       soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 + 1'd1);
-               end
-       end else begin
-               if (soc_litedramcore_uart_rx_fifo_do_read) begin
-                       soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 - 1'd1);
-               end
-       end
-       if (soc_litedramcore_uart_reset) begin
-               soc_litedramcore_uart_tx_pending <= 1'd0;
-               soc_litedramcore_uart_tx_old_trigger <= 1'd0;
-               soc_litedramcore_uart_rx_pending <= 1'd0;
-               soc_litedramcore_uart_rx_old_trigger <= 1'd0;
-               soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
-               soc_litedramcore_uart_tx_fifo_level0 <= 5'd0;
-               soc_litedramcore_uart_tx_fifo_produce <= 4'd0;
-               soc_litedramcore_uart_tx_fifo_consume <= 4'd0;
-               soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
-               soc_litedramcore_uart_rx_fifo_level0 <= 5'd0;
-               soc_litedramcore_uart_rx_fifo_produce <= 4'd0;
-               soc_litedramcore_uart_rx_fifo_consume <= 4'd0;
-       end
-       if (soc_litedramcore_timer_en_storage) begin
-               if ((soc_litedramcore_timer_value == 1'd0)) begin
-                       soc_litedramcore_timer_value <= soc_litedramcore_timer_reload_storage;
-               end else begin
-                       soc_litedramcore_timer_value <= (soc_litedramcore_timer_value - 1'd1);
-               end
+       dummy_d_354 = dummy_s;
+// synthesis translate_on
+end
+assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset);
+assign xilinxasyncresetsynchronizerimpl1 = ((~sys_pll_locked) | sys_pll_reset);
+assign xilinxasyncresetsynchronizerimpl2 = ((~sys_pll_locked) | sys_pll_reset);
+assign xilinxasyncresetsynchronizerimpl3 = ((~iodelay_pll_locked) | iodelay_pll_reset);
+
+always @(posedge iodelay_clk) begin
+       if ((reset_counter != 1'd0)) begin
+               reset_counter <= (reset_counter - 1'd1);
        end else begin
-               soc_litedramcore_timer_value <= soc_litedramcore_timer_load_storage;
-       end
-       if (soc_litedramcore_timer_update_value_re) begin
-               soc_litedramcore_timer_value_status <= soc_litedramcore_timer_value;
+               ic_reset <= 1'd0;
        end
-       if (soc_litedramcore_timer_zero_clear) begin
-               soc_litedramcore_timer_zero_pending <= 1'd0;
-       end
-       soc_litedramcore_timer_zero_old_trigger <= soc_litedramcore_timer_zero_trigger;
-       if (((~soc_litedramcore_timer_zero_trigger) & soc_litedramcore_timer_zero_old_trigger)) begin
-               soc_litedramcore_timer_zero_pending <= 1'd1;
+       if (iodelay_rst) begin
+               reset_counter <= 4'd15;
+               ic_reset <= 1'd1;
        end
-       vns_wb2csr_state <= vns_wb2csr_next_state;
-       soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1);
-       soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1);
-       soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en;
-       soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
-       soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
-       soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
-       soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
-       soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en;
-       soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0;
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1);
+end
+
+always @(posedge sys_clk) begin
+       a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1);
+       a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1);
+       a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en;
+       a7ddrphy_dfi_p0_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
+       a7ddrphy_dfi_p1_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
+       a7ddrphy_dfi_p2_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
+       a7ddrphy_dfi_p3_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
+       a7ddrphy_wrdata_en_last <= a7ddrphy_wrdata_en;
+       a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip0_value <= (a7ddrphy_bitslip0_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip0_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip0_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1);
+       a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip1_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip1_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1);
+       a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip2_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip2_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1);
+       a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip3_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip3_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1);
+       a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip4_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip4_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1);
+       a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip5_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip5_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1);
+       a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip6_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip6_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1);
+       a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip7_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip7_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1);
+       a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip8_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip8_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1);
+       a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip9_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip9_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1);
+       a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip10_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip10_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1);
+       a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip11_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip11_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1);
+       a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip12_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip12_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1);
+       a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip13_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip13_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1);
+       a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip14_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip14_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1);
+       a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip15_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip15_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[15:8]};
-       if (soc_sdram_inti_p0_rddata_valid) begin
-               soc_sdram_phaseinjector0_status <= soc_sdram_inti_p0_rddata;
+       a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[15:8]};
+       if (litedramcore_inti_p0_rddata_valid) begin
+               litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata;
        end
-       if (soc_sdram_inti_p1_rddata_valid) begin
-               soc_sdram_phaseinjector1_status <= soc_sdram_inti_p1_rddata;
+       if (litedramcore_inti_p1_rddata_valid) begin
+               litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata;
        end
-       if (soc_sdram_inti_p2_rddata_valid) begin
-               soc_sdram_phaseinjector2_status <= soc_sdram_inti_p2_rddata;
+       if (litedramcore_inti_p2_rddata_valid) begin
+               litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata;
        end
-       if (soc_sdram_inti_p3_rddata_valid) begin
-               soc_sdram_phaseinjector3_status <= soc_sdram_inti_p3_rddata;
+       if (litedramcore_inti_p3_rddata_valid) begin
+               litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata;
        end
-       if ((soc_sdram_timer_wait & (~soc_sdram_timer_done0))) begin
-               soc_sdram_timer_count1 <= (soc_sdram_timer_count1 - 1'd1);
+       if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+               litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
        end else begin
-               soc_sdram_timer_count1 <= 10'd781;
+               litedramcore_timer_count1 <= 10'd781;
        end
-       soc_sdram_postponer_req_o <= 1'd0;
-       if (soc_sdram_postponer_req_i) begin
-               soc_sdram_postponer_count <= (soc_sdram_postponer_count - 1'd1);
-               if ((soc_sdram_postponer_count == 1'd0)) begin
-                       soc_sdram_postponer_count <= 1'd0;
-                       soc_sdram_postponer_req_o <= 1'd1;
+       litedramcore_postponer_req_o <= 1'd0;
+       if (litedramcore_postponer_req_i) begin
+               litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+               if ((litedramcore_postponer_count == 1'd0)) begin
+                       litedramcore_postponer_count <= 1'd0;
+                       litedramcore_postponer_req_o <= 1'd1;
                end
        end
-       if (soc_sdram_sequencer_start0) begin
-               soc_sdram_sequencer_count <= 1'd0;
+       if (litedramcore_sequencer_start0) begin
+               litedramcore_sequencer_count <= 1'd0;
        end else begin
-               if (soc_sdram_sequencer_done1) begin
-                       if ((soc_sdram_sequencer_count != 1'd0)) begin
-                               soc_sdram_sequencer_count <= (soc_sdram_sequencer_count - 1'd1);
-                       end
-               end
-       end
-       soc_sdram_cmd_payload_a <= 1'd0;
-       soc_sdram_cmd_payload_ba <= 1'd0;
-       soc_sdram_cmd_payload_cas <= 1'd0;
-       soc_sdram_cmd_payload_ras <= 1'd0;
-       soc_sdram_cmd_payload_we <= 1'd0;
-       soc_sdram_sequencer_done1 <= 1'd0;
-       if ((soc_sdram_sequencer_start1 & (soc_sdram_sequencer_counter == 1'd0))) begin
-               soc_sdram_cmd_payload_a <= 11'd1024;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd0;
-               soc_sdram_cmd_payload_ras <= 1'd1;
-               soc_sdram_cmd_payload_we <= 1'd1;
-       end
-       if ((soc_sdram_sequencer_counter == 2'd3)) begin
-               soc_sdram_cmd_payload_a <= 1'd0;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd1;
-               soc_sdram_cmd_payload_ras <= 1'd1;
-               soc_sdram_cmd_payload_we <= 1'd0;
-       end
-       if ((soc_sdram_sequencer_counter == 6'd35)) begin
-               soc_sdram_cmd_payload_a <= 1'd0;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd0;
-               soc_sdram_cmd_payload_ras <= 1'd0;
-               soc_sdram_cmd_payload_we <= 1'd0;
-               soc_sdram_sequencer_done1 <= 1'd1;
-       end
-       if ((soc_sdram_sequencer_counter == 6'd35)) begin
-               soc_sdram_sequencer_counter <= 1'd0;
+               if (litedramcore_sequencer_done1) begin
+                       if ((litedramcore_sequencer_count != 1'd0)) begin
+                               litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+                       end
+               end
+       end
+       litedramcore_cmd_payload_a <= 1'd0;
+       litedramcore_cmd_payload_ba <= 1'd0;
+       litedramcore_cmd_payload_cas <= 1'd0;
+       litedramcore_cmd_payload_ras <= 1'd0;
+       litedramcore_cmd_payload_we <= 1'd0;
+       litedramcore_sequencer_done1 <= 1'd0;
+       if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+               litedramcore_cmd_payload_a <= 11'd1024;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd1;
+               litedramcore_cmd_payload_we <= 1'd1;
+       end
+       if ((litedramcore_sequencer_counter == 2'd3)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd1;
+               litedramcore_cmd_payload_ras <= 1'd1;
+               litedramcore_cmd_payload_we <= 1'd0;
+       end
+       if ((litedramcore_sequencer_counter == 6'd35)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd0;
+               litedramcore_cmd_payload_we <= 1'd0;
+               litedramcore_sequencer_done1 <= 1'd1;
+       end
+       if ((litedramcore_sequencer_counter == 6'd35)) begin
+               litedramcore_sequencer_counter <= 1'd0;
        end else begin
-               if ((soc_sdram_sequencer_counter != 1'd0)) begin
-                       soc_sdram_sequencer_counter <= (soc_sdram_sequencer_counter + 1'd1);
+               if ((litedramcore_sequencer_counter != 1'd0)) begin
+                       litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
                end else begin
-                       if (soc_sdram_sequencer_start1) begin
-                               soc_sdram_sequencer_counter <= 1'd1;
+                       if (litedramcore_sequencer_start1) begin
+                               litedramcore_sequencer_counter <= 1'd1;
                        end
                end
        end
-       if ((soc_sdram_zqcs_timer_wait & (~soc_sdram_zqcs_timer_done0))) begin
-               soc_sdram_zqcs_timer_count1 <= (soc_sdram_zqcs_timer_count1 - 1'd1);
+       if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+               litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
        end else begin
-               soc_sdram_zqcs_timer_count1 <= 27'd99999999;
-       end
-       soc_sdram_zqcs_executer_done <= 1'd0;
-       if ((soc_sdram_zqcs_executer_start & (soc_sdram_zqcs_executer_counter == 1'd0))) begin
-               soc_sdram_cmd_payload_a <= 11'd1024;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd0;
-               soc_sdram_cmd_payload_ras <= 1'd1;
-               soc_sdram_cmd_payload_we <= 1'd1;
-       end
-       if ((soc_sdram_zqcs_executer_counter == 2'd3)) begin
-               soc_sdram_cmd_payload_a <= 1'd0;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd0;
-               soc_sdram_cmd_payload_ras <= 1'd0;
-               soc_sdram_cmd_payload_we <= 1'd1;
-       end
-       if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin
-               soc_sdram_cmd_payload_a <= 1'd0;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd0;
-               soc_sdram_cmd_payload_ras <= 1'd0;
-               soc_sdram_cmd_payload_we <= 1'd0;
-               soc_sdram_zqcs_executer_done <= 1'd1;
-       end
-       if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin
-               soc_sdram_zqcs_executer_counter <= 1'd0;
+               litedramcore_zqcs_timer_count1 <= 27'd99999999;
+       end
+       litedramcore_zqcs_executer_done <= 1'd0;
+       if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+               litedramcore_cmd_payload_a <= 11'd1024;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd1;
+               litedramcore_cmd_payload_we <= 1'd1;
+       end
+       if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd0;
+               litedramcore_cmd_payload_we <= 1'd1;
+       end
+       if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd0;
+               litedramcore_cmd_payload_we <= 1'd0;
+               litedramcore_zqcs_executer_done <= 1'd1;
+       end
+       if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+               litedramcore_zqcs_executer_counter <= 1'd0;
        end else begin
-               if ((soc_sdram_zqcs_executer_counter != 1'd0)) begin
-                       soc_sdram_zqcs_executer_counter <= (soc_sdram_zqcs_executer_counter + 1'd1);
+               if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+                       litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
                end else begin
-                       if (soc_sdram_zqcs_executer_start) begin
-                               soc_sdram_zqcs_executer_counter <= 1'd1;
+                       if (litedramcore_zqcs_executer_start) begin
+                               litedramcore_zqcs_executer_counter <= 1'd1;
                        end
                end
        end
-       vns_refresher_state <= vns_refresher_next_state;
-       if (soc_sdram_bankmachine0_row_close) begin
-               soc_sdram_bankmachine0_row_opened <= 1'd0;
+       refresher_state <= refresher_next_state;
+       if (litedramcore_bankmachine0_row_close) begin
+               litedramcore_bankmachine0_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine0_row_open) begin
-                       soc_sdram_bankmachine0_row_opened <= 1'd1;
-                       soc_sdram_bankmachine0_row <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[20:7];
+               if (litedramcore_bankmachine0_row_open) begin
+                       litedramcore_bankmachine0_row_opened <= 1'd1;
+                       litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
                end
        end
-       if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine0_cmd_buffer_source_valid <= soc_sdram_bankmachine0_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine0_cmd_buffer_source_first <= soc_sdram_bankmachine0_cmd_buffer_sink_first;
-               soc_sdram_bankmachine0_cmd_buffer_source_last <= soc_sdram_bankmachine0_cmd_buffer_sink_last;
-               soc_sdram_bankmachine0_cmd_buffer_source_payload_we <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
+               litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
+               litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
+               litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine0_twtpcon_valid) begin
-               soc_sdram_bankmachine0_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine0_twtpcon_valid) begin
+               litedramcore_bankmachine0_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine0_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine0_twtpcon_ready)) begin
-                       soc_sdram_bankmachine0_twtpcon_count <= (soc_sdram_bankmachine0_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine0_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+                       litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine0_trccon_valid) begin
-               soc_sdram_bankmachine0_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine0_trccon_valid) begin
+               litedramcore_bankmachine0_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine0_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine0_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine0_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine0_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine0_trccon_ready)) begin
-                       soc_sdram_bankmachine0_trccon_count <= (soc_sdram_bankmachine0_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine0_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine0_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine0_trccon_ready)) begin
+                       litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine0_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine0_trascon_valid) begin
-               soc_sdram_bankmachine0_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine0_trascon_valid) begin
+               litedramcore_bankmachine0_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine0_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine0_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine0_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine0_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine0_trascon_ready)) begin
-                       soc_sdram_bankmachine0_trascon_count <= (soc_sdram_bankmachine0_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine0_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine0_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine0_trascon_ready)) begin
+                       litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine0_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine0_state <= vns_bankmachine0_next_state;
-       if (soc_sdram_bankmachine1_row_close) begin
-               soc_sdram_bankmachine1_row_opened <= 1'd0;
+       bankmachine0_state <= bankmachine0_next_state;
+       if (litedramcore_bankmachine1_row_close) begin
+               litedramcore_bankmachine1_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine1_row_open) begin
-                       soc_sdram_bankmachine1_row_opened <= 1'd1;
-                       soc_sdram_bankmachine1_row <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[20:7];
+               if (litedramcore_bankmachine1_row_open) begin
+                       litedramcore_bankmachine1_row_opened <= 1'd1;
+                       litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
                end
        end
-       if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine1_cmd_buffer_source_valid <= soc_sdram_bankmachine1_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine1_cmd_buffer_source_first <= soc_sdram_bankmachine1_cmd_buffer_sink_first;
-               soc_sdram_bankmachine1_cmd_buffer_source_last <= soc_sdram_bankmachine1_cmd_buffer_sink_last;
-               soc_sdram_bankmachine1_cmd_buffer_source_payload_we <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
+               litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
+               litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
+               litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine1_twtpcon_valid) begin
-               soc_sdram_bankmachine1_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine1_twtpcon_valid) begin
+               litedramcore_bankmachine1_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine1_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine1_twtpcon_ready)) begin
-                       soc_sdram_bankmachine1_twtpcon_count <= (soc_sdram_bankmachine1_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine1_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+                       litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine1_trccon_valid) begin
-               soc_sdram_bankmachine1_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine1_trccon_valid) begin
+               litedramcore_bankmachine1_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine1_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine1_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine1_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine1_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine1_trccon_ready)) begin
-                       soc_sdram_bankmachine1_trccon_count <= (soc_sdram_bankmachine1_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine1_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine1_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine1_trccon_ready)) begin
+                       litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine1_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine1_trascon_valid) begin
-               soc_sdram_bankmachine1_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine1_trascon_valid) begin
+               litedramcore_bankmachine1_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine1_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine1_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine1_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine1_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine1_trascon_ready)) begin
-                       soc_sdram_bankmachine1_trascon_count <= (soc_sdram_bankmachine1_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine1_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine1_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine1_trascon_ready)) begin
+                       litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine1_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine1_state <= vns_bankmachine1_next_state;
-       if (soc_sdram_bankmachine2_row_close) begin
-               soc_sdram_bankmachine2_row_opened <= 1'd0;
+       bankmachine1_state <= bankmachine1_next_state;
+       if (litedramcore_bankmachine2_row_close) begin
+               litedramcore_bankmachine2_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine2_row_open) begin
-                       soc_sdram_bankmachine2_row_opened <= 1'd1;
-                       soc_sdram_bankmachine2_row <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[20:7];
+               if (litedramcore_bankmachine2_row_open) begin
+                       litedramcore_bankmachine2_row_opened <= 1'd1;
+                       litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
                end
        end
-       if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine2_cmd_buffer_source_valid <= soc_sdram_bankmachine2_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine2_cmd_buffer_source_first <= soc_sdram_bankmachine2_cmd_buffer_sink_first;
-               soc_sdram_bankmachine2_cmd_buffer_source_last <= soc_sdram_bankmachine2_cmd_buffer_sink_last;
-               soc_sdram_bankmachine2_cmd_buffer_source_payload_we <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
+               litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
+               litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
+               litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine2_twtpcon_valid) begin
-               soc_sdram_bankmachine2_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine2_twtpcon_valid) begin
+               litedramcore_bankmachine2_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine2_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine2_twtpcon_ready)) begin
-                       soc_sdram_bankmachine2_twtpcon_count <= (soc_sdram_bankmachine2_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine2_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+                       litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine2_trccon_valid) begin
-               soc_sdram_bankmachine2_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine2_trccon_valid) begin
+               litedramcore_bankmachine2_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine2_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine2_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine2_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine2_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine2_trccon_ready)) begin
-                       soc_sdram_bankmachine2_trccon_count <= (soc_sdram_bankmachine2_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine2_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine2_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine2_trccon_ready)) begin
+                       litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine2_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine2_trascon_valid) begin
-               soc_sdram_bankmachine2_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine2_trascon_valid) begin
+               litedramcore_bankmachine2_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine2_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine2_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine2_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine2_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine2_trascon_ready)) begin
-                       soc_sdram_bankmachine2_trascon_count <= (soc_sdram_bankmachine2_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine2_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine2_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine2_trascon_ready)) begin
+                       litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine2_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine2_state <= vns_bankmachine2_next_state;
-       if (soc_sdram_bankmachine3_row_close) begin
-               soc_sdram_bankmachine3_row_opened <= 1'd0;
+       bankmachine2_state <= bankmachine2_next_state;
+       if (litedramcore_bankmachine3_row_close) begin
+               litedramcore_bankmachine3_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine3_row_open) begin
-                       soc_sdram_bankmachine3_row_opened <= 1'd1;
-                       soc_sdram_bankmachine3_row <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[20:7];
+               if (litedramcore_bankmachine3_row_open) begin
+                       litedramcore_bankmachine3_row_opened <= 1'd1;
+                       litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
                end
        end
-       if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine3_cmd_buffer_source_valid <= soc_sdram_bankmachine3_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine3_cmd_buffer_source_first <= soc_sdram_bankmachine3_cmd_buffer_sink_first;
-               soc_sdram_bankmachine3_cmd_buffer_source_last <= soc_sdram_bankmachine3_cmd_buffer_sink_last;
-               soc_sdram_bankmachine3_cmd_buffer_source_payload_we <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
+               litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
+               litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
+               litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine3_twtpcon_valid) begin
-               soc_sdram_bankmachine3_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine3_twtpcon_valid) begin
+               litedramcore_bankmachine3_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine3_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine3_twtpcon_ready)) begin
-                       soc_sdram_bankmachine3_twtpcon_count <= (soc_sdram_bankmachine3_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine3_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+                       litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine3_trccon_valid) begin
-               soc_sdram_bankmachine3_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine3_trccon_valid) begin
+               litedramcore_bankmachine3_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine3_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine3_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine3_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine3_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine3_trccon_ready)) begin
-                       soc_sdram_bankmachine3_trccon_count <= (soc_sdram_bankmachine3_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine3_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine3_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine3_trccon_ready)) begin
+                       litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine3_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine3_trascon_valid) begin
-               soc_sdram_bankmachine3_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine3_trascon_valid) begin
+               litedramcore_bankmachine3_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine3_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine3_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine3_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine3_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine3_trascon_ready)) begin
-                       soc_sdram_bankmachine3_trascon_count <= (soc_sdram_bankmachine3_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine3_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine3_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine3_trascon_ready)) begin
+                       litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine3_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine3_state <= vns_bankmachine3_next_state;
-       if (soc_sdram_bankmachine4_row_close) begin
-               soc_sdram_bankmachine4_row_opened <= 1'd0;
+       bankmachine3_state <= bankmachine3_next_state;
+       if (litedramcore_bankmachine4_row_close) begin
+               litedramcore_bankmachine4_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine4_row_open) begin
-                       soc_sdram_bankmachine4_row_opened <= 1'd1;
-                       soc_sdram_bankmachine4_row <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[20:7];
+               if (litedramcore_bankmachine4_row_open) begin
+                       litedramcore_bankmachine4_row_opened <= 1'd1;
+                       litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
                end
        end
-       if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine4_cmd_buffer_source_valid <= soc_sdram_bankmachine4_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine4_cmd_buffer_source_first <= soc_sdram_bankmachine4_cmd_buffer_sink_first;
-               soc_sdram_bankmachine4_cmd_buffer_source_last <= soc_sdram_bankmachine4_cmd_buffer_sink_last;
-               soc_sdram_bankmachine4_cmd_buffer_source_payload_we <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
+               litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
+               litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
+               litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine4_twtpcon_valid) begin
-               soc_sdram_bankmachine4_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine4_twtpcon_valid) begin
+               litedramcore_bankmachine4_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine4_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine4_twtpcon_ready)) begin
-                       soc_sdram_bankmachine4_twtpcon_count <= (soc_sdram_bankmachine4_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine4_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+                       litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine4_trccon_valid) begin
-               soc_sdram_bankmachine4_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine4_trccon_valid) begin
+               litedramcore_bankmachine4_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine4_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine4_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine4_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine4_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine4_trccon_ready)) begin
-                       soc_sdram_bankmachine4_trccon_count <= (soc_sdram_bankmachine4_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine4_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine4_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine4_trccon_ready)) begin
+                       litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine4_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine4_trascon_valid) begin
-               soc_sdram_bankmachine4_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine4_trascon_valid) begin
+               litedramcore_bankmachine4_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine4_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine4_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine4_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine4_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine4_trascon_ready)) begin
-                       soc_sdram_bankmachine4_trascon_count <= (soc_sdram_bankmachine4_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine4_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine4_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine4_trascon_ready)) begin
+                       litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine4_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine4_state <= vns_bankmachine4_next_state;
-       if (soc_sdram_bankmachine5_row_close) begin
-               soc_sdram_bankmachine5_row_opened <= 1'd0;
+       bankmachine4_state <= bankmachine4_next_state;
+       if (litedramcore_bankmachine5_row_close) begin
+               litedramcore_bankmachine5_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine5_row_open) begin
-                       soc_sdram_bankmachine5_row_opened <= 1'd1;
-                       soc_sdram_bankmachine5_row <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[20:7];
+               if (litedramcore_bankmachine5_row_open) begin
+                       litedramcore_bankmachine5_row_opened <= 1'd1;
+                       litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
                end
        end
-       if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine5_cmd_buffer_source_valid <= soc_sdram_bankmachine5_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine5_cmd_buffer_source_first <= soc_sdram_bankmachine5_cmd_buffer_sink_first;
-               soc_sdram_bankmachine5_cmd_buffer_source_last <= soc_sdram_bankmachine5_cmd_buffer_sink_last;
-               soc_sdram_bankmachine5_cmd_buffer_source_payload_we <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
+               litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
+               litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
+               litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine5_twtpcon_valid) begin
-               soc_sdram_bankmachine5_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine5_twtpcon_valid) begin
+               litedramcore_bankmachine5_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine5_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine5_twtpcon_ready)) begin
-                       soc_sdram_bankmachine5_twtpcon_count <= (soc_sdram_bankmachine5_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine5_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+                       litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine5_trccon_valid) begin
-               soc_sdram_bankmachine5_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine5_trccon_valid) begin
+               litedramcore_bankmachine5_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine5_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine5_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine5_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine5_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine5_trccon_ready)) begin
-                       soc_sdram_bankmachine5_trccon_count <= (soc_sdram_bankmachine5_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine5_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine5_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine5_trccon_ready)) begin
+                       litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine5_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine5_trascon_valid) begin
-               soc_sdram_bankmachine5_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine5_trascon_valid) begin
+               litedramcore_bankmachine5_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine5_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine5_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine5_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine5_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine5_trascon_ready)) begin
-                       soc_sdram_bankmachine5_trascon_count <= (soc_sdram_bankmachine5_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine5_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine5_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine5_trascon_ready)) begin
+                       litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine5_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine5_state <= vns_bankmachine5_next_state;
-       if (soc_sdram_bankmachine6_row_close) begin
-               soc_sdram_bankmachine6_row_opened <= 1'd0;
+       bankmachine5_state <= bankmachine5_next_state;
+       if (litedramcore_bankmachine6_row_close) begin
+               litedramcore_bankmachine6_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine6_row_open) begin
-                       soc_sdram_bankmachine6_row_opened <= 1'd1;
-                       soc_sdram_bankmachine6_row <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[20:7];
+               if (litedramcore_bankmachine6_row_open) begin
+                       litedramcore_bankmachine6_row_opened <= 1'd1;
+                       litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
                end
        end
-       if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine6_cmd_buffer_source_valid <= soc_sdram_bankmachine6_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine6_cmd_buffer_source_first <= soc_sdram_bankmachine6_cmd_buffer_sink_first;
-               soc_sdram_bankmachine6_cmd_buffer_source_last <= soc_sdram_bankmachine6_cmd_buffer_sink_last;
-               soc_sdram_bankmachine6_cmd_buffer_source_payload_we <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
+               litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
+               litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
+               litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine6_twtpcon_valid) begin
-               soc_sdram_bankmachine6_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine6_twtpcon_valid) begin
+               litedramcore_bankmachine6_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine6_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine6_twtpcon_ready)) begin
-                       soc_sdram_bankmachine6_twtpcon_count <= (soc_sdram_bankmachine6_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine6_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+                       litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine6_trccon_valid) begin
-               soc_sdram_bankmachine6_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine6_trccon_valid) begin
+               litedramcore_bankmachine6_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine6_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine6_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine6_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine6_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine6_trccon_ready)) begin
-                       soc_sdram_bankmachine6_trccon_count <= (soc_sdram_bankmachine6_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine6_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine6_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine6_trccon_ready)) begin
+                       litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine6_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine6_trascon_valid) begin
-               soc_sdram_bankmachine6_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine6_trascon_valid) begin
+               litedramcore_bankmachine6_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine6_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine6_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine6_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine6_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine6_trascon_ready)) begin
-                       soc_sdram_bankmachine6_trascon_count <= (soc_sdram_bankmachine6_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine6_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine6_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine6_trascon_ready)) begin
+                       litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine6_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine6_state <= vns_bankmachine6_next_state;
-       if (soc_sdram_bankmachine7_row_close) begin
-               soc_sdram_bankmachine7_row_opened <= 1'd0;
+       bankmachine6_state <= bankmachine6_next_state;
+       if (litedramcore_bankmachine7_row_close) begin
+               litedramcore_bankmachine7_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine7_row_open) begin
-                       soc_sdram_bankmachine7_row_opened <= 1'd1;
-                       soc_sdram_bankmachine7_row <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[20:7];
+               if (litedramcore_bankmachine7_row_open) begin
+                       litedramcore_bankmachine7_row_opened <= 1'd1;
+                       litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
                end
        end
-       if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine7_cmd_buffer_source_valid <= soc_sdram_bankmachine7_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine7_cmd_buffer_source_first <= soc_sdram_bankmachine7_cmd_buffer_sink_first;
-               soc_sdram_bankmachine7_cmd_buffer_source_last <= soc_sdram_bankmachine7_cmd_buffer_sink_last;
-               soc_sdram_bankmachine7_cmd_buffer_source_payload_we <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
+               litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
+               litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
+               litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine7_twtpcon_valid) begin
-               soc_sdram_bankmachine7_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine7_twtpcon_valid) begin
+               litedramcore_bankmachine7_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine7_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine7_twtpcon_ready)) begin
-                       soc_sdram_bankmachine7_twtpcon_count <= (soc_sdram_bankmachine7_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine7_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+                       litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine7_trccon_valid) begin
-               soc_sdram_bankmachine7_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine7_trccon_valid) begin
+               litedramcore_bankmachine7_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine7_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine7_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine7_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine7_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine7_trccon_ready)) begin
-                       soc_sdram_bankmachine7_trccon_count <= (soc_sdram_bankmachine7_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine7_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine7_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine7_trccon_ready)) begin
+                       litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine7_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine7_trascon_valid) begin
-               soc_sdram_bankmachine7_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine7_trascon_valid) begin
+               litedramcore_bankmachine7_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine7_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine7_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine7_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine7_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine7_trascon_ready)) begin
-                       soc_sdram_bankmachine7_trascon_count <= (soc_sdram_bankmachine7_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine7_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine7_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine7_trascon_ready)) begin
+                       litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine7_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine7_state <= vns_bankmachine7_next_state;
-       if ((~soc_sdram_en0)) begin
-               soc_sdram_time0 <= 5'd31;
+       bankmachine7_state <= bankmachine7_next_state;
+       if ((~litedramcore_en0)) begin
+               litedramcore_time0 <= 5'd31;
        end else begin
-               if ((~soc_sdram_max_time0)) begin
-                       soc_sdram_time0 <= (soc_sdram_time0 - 1'd1);
+               if ((~litedramcore_max_time0)) begin
+                       litedramcore_time0 <= (litedramcore_time0 - 1'd1);
                end
        end
-       if ((~soc_sdram_en1)) begin
-               soc_sdram_time1 <= 4'd15;
+       if ((~litedramcore_en1)) begin
+               litedramcore_time1 <= 4'd15;
        end else begin
-               if ((~soc_sdram_max_time1)) begin
-                       soc_sdram_time1 <= (soc_sdram_time1 - 1'd1);
+               if ((~litedramcore_max_time1)) begin
+                       litedramcore_time1 <= (litedramcore_time1 - 1'd1);
                end
        end
-       if (soc_sdram_choose_cmd_ce) begin
-               case (soc_sdram_choose_cmd_grant)
+       if (litedramcore_choose_cmd_ce) begin
+               case (litedramcore_choose_cmd_grant)
                        1'd0: begin
-                               if (soc_sdram_choose_cmd_request[1]) begin
-                                       soc_sdram_choose_cmd_grant <= 1'd1;
+                               if (litedramcore_choose_cmd_request[1]) begin
+                                       litedramcore_choose_cmd_grant <= 1'd1;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[2]) begin
-                                               soc_sdram_choose_cmd_grant <= 2'd2;
+                                       if (litedramcore_choose_cmd_request[2]) begin
+                                               litedramcore_choose_cmd_grant <= 2'd2;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[3]) begin
-                                                       soc_sdram_choose_cmd_grant <= 2'd3;
+                                               if (litedramcore_choose_cmd_request[3]) begin
+                                                       litedramcore_choose_cmd_grant <= 2'd3;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[4]) begin
-                                                               soc_sdram_choose_cmd_grant <= 3'd4;
+                                                       if (litedramcore_choose_cmd_request[4]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd4;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[5]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 3'd5;
+                                                               if (litedramcore_choose_cmd_request[5]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd5;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[6]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 3'd6;
+                                                                       if (litedramcore_choose_cmd_request[6]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd6;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[7]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 3'd7;
+                                                                               if (litedramcore_choose_cmd_request[7]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd7;
                                                                                end
                                                                        end
                                                                end
@@ -15999,26 +13619,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        1'd1: begin
-                               if (soc_sdram_choose_cmd_request[2]) begin
-                                       soc_sdram_choose_cmd_grant <= 2'd2;
+                               if (litedramcore_choose_cmd_request[2]) begin
+                                       litedramcore_choose_cmd_grant <= 2'd2;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[3]) begin
-                                               soc_sdram_choose_cmd_grant <= 2'd3;
+                                       if (litedramcore_choose_cmd_request[3]) begin
+                                               litedramcore_choose_cmd_grant <= 2'd3;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[4]) begin
-                                                       soc_sdram_choose_cmd_grant <= 3'd4;
+                                               if (litedramcore_choose_cmd_request[4]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd4;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[5]) begin
-                                                               soc_sdram_choose_cmd_grant <= 3'd5;
+                                                       if (litedramcore_choose_cmd_request[5]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd5;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[6]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 3'd6;
+                                                               if (litedramcore_choose_cmd_request[6]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd6;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[7]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 3'd7;
+                                                                       if (litedramcore_choose_cmd_request[7]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd7;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[0]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 1'd0;
+                                                                               if (litedramcore_choose_cmd_request[0]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 1'd0;
                                                                                end
                                                                        end
                                                                end
@@ -16028,26 +13648,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        2'd2: begin
-                               if (soc_sdram_choose_cmd_request[3]) begin
-                                       soc_sdram_choose_cmd_grant <= 2'd3;
+                               if (litedramcore_choose_cmd_request[3]) begin
+                                       litedramcore_choose_cmd_grant <= 2'd3;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[4]) begin
-                                               soc_sdram_choose_cmd_grant <= 3'd4;
+                                       if (litedramcore_choose_cmd_request[4]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd4;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[5]) begin
-                                                       soc_sdram_choose_cmd_grant <= 3'd5;
+                                               if (litedramcore_choose_cmd_request[5]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd5;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[6]) begin
-                                                               soc_sdram_choose_cmd_grant <= 3'd6;
+                                                       if (litedramcore_choose_cmd_request[6]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd6;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[7]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 3'd7;
+                                                               if (litedramcore_choose_cmd_request[7]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd7;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[0]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 1'd0;
+                                                                       if (litedramcore_choose_cmd_request[0]) begin
+                                                                               litedramcore_choose_cmd_grant <= 1'd0;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[1]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 1'd1;
+                                                                               if (litedramcore_choose_cmd_request[1]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 1'd1;
                                                                                end
                                                                        end
                                                                end
@@ -16057,26 +13677,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        2'd3: begin
-                               if (soc_sdram_choose_cmd_request[4]) begin
-                                       soc_sdram_choose_cmd_grant <= 3'd4;
+                               if (litedramcore_choose_cmd_request[4]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd4;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[5]) begin
-                                               soc_sdram_choose_cmd_grant <= 3'd5;
+                                       if (litedramcore_choose_cmd_request[5]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd5;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[6]) begin
-                                                       soc_sdram_choose_cmd_grant <= 3'd6;
+                                               if (litedramcore_choose_cmd_request[6]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd6;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[7]) begin
-                                                               soc_sdram_choose_cmd_grant <= 3'd7;
+                                                       if (litedramcore_choose_cmd_request[7]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd7;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[0]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 1'd0;
+                                                               if (litedramcore_choose_cmd_request[0]) begin
+                                                                       litedramcore_choose_cmd_grant <= 1'd0;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[1]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 1'd1;
+                                                                       if (litedramcore_choose_cmd_request[1]) begin
+                                                                               litedramcore_choose_cmd_grant <= 1'd1;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[2]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 2'd2;
+                                                                               if (litedramcore_choose_cmd_request[2]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 2'd2;
                                                                                end
                                                                        end
                                                                end
@@ -16086,26 +13706,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd4: begin
-                               if (soc_sdram_choose_cmd_request[5]) begin
-                                       soc_sdram_choose_cmd_grant <= 3'd5;
+                               if (litedramcore_choose_cmd_request[5]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd5;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[6]) begin
-                                               soc_sdram_choose_cmd_grant <= 3'd6;
+                                       if (litedramcore_choose_cmd_request[6]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd6;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[7]) begin
-                                                       soc_sdram_choose_cmd_grant <= 3'd7;
+                                               if (litedramcore_choose_cmd_request[7]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd7;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[0]) begin
-                                                               soc_sdram_choose_cmd_grant <= 1'd0;
+                                                       if (litedramcore_choose_cmd_request[0]) begin
+                                                               litedramcore_choose_cmd_grant <= 1'd0;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[1]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 1'd1;
+                                                               if (litedramcore_choose_cmd_request[1]) begin
+                                                                       litedramcore_choose_cmd_grant <= 1'd1;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[2]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 2'd2;
+                                                                       if (litedramcore_choose_cmd_request[2]) begin
+                                                                               litedramcore_choose_cmd_grant <= 2'd2;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[3]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 2'd3;
+                                                                               if (litedramcore_choose_cmd_request[3]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 2'd3;
                                                                                end
                                                                        end
                                                                end
@@ -16115,26 +13735,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd5: begin
-                               if (soc_sdram_choose_cmd_request[6]) begin
-                                       soc_sdram_choose_cmd_grant <= 3'd6;
+                               if (litedramcore_choose_cmd_request[6]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd6;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[7]) begin
-                                               soc_sdram_choose_cmd_grant <= 3'd7;
+                                       if (litedramcore_choose_cmd_request[7]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd7;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[0]) begin
-                                                       soc_sdram_choose_cmd_grant <= 1'd0;
+                                               if (litedramcore_choose_cmd_request[0]) begin
+                                                       litedramcore_choose_cmd_grant <= 1'd0;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[1]) begin
-                                                               soc_sdram_choose_cmd_grant <= 1'd1;
+                                                       if (litedramcore_choose_cmd_request[1]) begin
+                                                               litedramcore_choose_cmd_grant <= 1'd1;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[2]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 2'd2;
+                                                               if (litedramcore_choose_cmd_request[2]) begin
+                                                                       litedramcore_choose_cmd_grant <= 2'd2;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[3]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 2'd3;
+                                                                       if (litedramcore_choose_cmd_request[3]) begin
+                                                                               litedramcore_choose_cmd_grant <= 2'd3;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[4]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 3'd4;
+                                                                               if (litedramcore_choose_cmd_request[4]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd4;
                                                                                end
                                                                        end
                                                                end
@@ -16144,26 +13764,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd6: begin
-                               if (soc_sdram_choose_cmd_request[7]) begin
-                                       soc_sdram_choose_cmd_grant <= 3'd7;
+                               if (litedramcore_choose_cmd_request[7]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd7;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[0]) begin
-                                               soc_sdram_choose_cmd_grant <= 1'd0;
+                                       if (litedramcore_choose_cmd_request[0]) begin
+                                               litedramcore_choose_cmd_grant <= 1'd0;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[1]) begin
-                                                       soc_sdram_choose_cmd_grant <= 1'd1;
+                                               if (litedramcore_choose_cmd_request[1]) begin
+                                                       litedramcore_choose_cmd_grant <= 1'd1;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[2]) begin
-                                                               soc_sdram_choose_cmd_grant <= 2'd2;
+                                                       if (litedramcore_choose_cmd_request[2]) begin
+                                                               litedramcore_choose_cmd_grant <= 2'd2;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[3]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 2'd3;
+                                                               if (litedramcore_choose_cmd_request[3]) begin
+                                                                       litedramcore_choose_cmd_grant <= 2'd3;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[4]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 3'd4;
+                                                                       if (litedramcore_choose_cmd_request[4]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd4;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[5]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 3'd5;
+                                                                               if (litedramcore_choose_cmd_request[5]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd5;
                                                                                end
                                                                        end
                                                                end
@@ -16173,26 +13793,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd7: begin
-                               if (soc_sdram_choose_cmd_request[0]) begin
-                                       soc_sdram_choose_cmd_grant <= 1'd0;
+                               if (litedramcore_choose_cmd_request[0]) begin
+                                       litedramcore_choose_cmd_grant <= 1'd0;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[1]) begin
-                                               soc_sdram_choose_cmd_grant <= 1'd1;
+                                       if (litedramcore_choose_cmd_request[1]) begin
+                                               litedramcore_choose_cmd_grant <= 1'd1;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[2]) begin
-                                                       soc_sdram_choose_cmd_grant <= 2'd2;
+                                               if (litedramcore_choose_cmd_request[2]) begin
+                                                       litedramcore_choose_cmd_grant <= 2'd2;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[3]) begin
-                                                               soc_sdram_choose_cmd_grant <= 2'd3;
+                                                       if (litedramcore_choose_cmd_request[3]) begin
+                                                               litedramcore_choose_cmd_grant <= 2'd3;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[4]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 3'd4;
+                                                               if (litedramcore_choose_cmd_request[4]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd4;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[5]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 3'd5;
+                                                                       if (litedramcore_choose_cmd_request[5]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd5;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[6]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 3'd6;
+                                                                               if (litedramcore_choose_cmd_request[6]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd6;
                                                                                end
                                                                        end
                                                                end
@@ -16203,29 +13823,29 @@ always @(posedge sys_clk) begin
                        end
                endcase
        end
-       if (soc_sdram_choose_req_ce) begin
-               case (soc_sdram_choose_req_grant)
+       if (litedramcore_choose_req_ce) begin
+               case (litedramcore_choose_req_grant)
                        1'd0: begin
-                               if (soc_sdram_choose_req_request[1]) begin
-                                       soc_sdram_choose_req_grant <= 1'd1;
+                               if (litedramcore_choose_req_request[1]) begin
+                                       litedramcore_choose_req_grant <= 1'd1;
                                end else begin
-                                       if (soc_sdram_choose_req_request[2]) begin
-                                               soc_sdram_choose_req_grant <= 2'd2;
+                                       if (litedramcore_choose_req_request[2]) begin
+                                               litedramcore_choose_req_grant <= 2'd2;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[3]) begin
-                                                       soc_sdram_choose_req_grant <= 2'd3;
+                                               if (litedramcore_choose_req_request[3]) begin
+                                                       litedramcore_choose_req_grant <= 2'd3;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[4]) begin
-                                                               soc_sdram_choose_req_grant <= 3'd4;
+                                                       if (litedramcore_choose_req_request[4]) begin
+                                                               litedramcore_choose_req_grant <= 3'd4;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[5]) begin
-                                                                       soc_sdram_choose_req_grant <= 3'd5;
+                                                               if (litedramcore_choose_req_request[5]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd5;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[6]) begin
-                                                                               soc_sdram_choose_req_grant <= 3'd6;
+                                                                       if (litedramcore_choose_req_request[6]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd6;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[7]) begin
-                                                                                       soc_sdram_choose_req_grant <= 3'd7;
+                                                                               if (litedramcore_choose_req_request[7]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd7;
                                                                                end
                                                                        end
                                                                end
@@ -16235,26 +13855,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        1'd1: begin
-                               if (soc_sdram_choose_req_request[2]) begin
-                                       soc_sdram_choose_req_grant <= 2'd2;
+                               if (litedramcore_choose_req_request[2]) begin
+                                       litedramcore_choose_req_grant <= 2'd2;
                                end else begin
-                                       if (soc_sdram_choose_req_request[3]) begin
-                                               soc_sdram_choose_req_grant <= 2'd3;
+                                       if (litedramcore_choose_req_request[3]) begin
+                                               litedramcore_choose_req_grant <= 2'd3;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[4]) begin
-                                                       soc_sdram_choose_req_grant <= 3'd4;
+                                               if (litedramcore_choose_req_request[4]) begin
+                                                       litedramcore_choose_req_grant <= 3'd4;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[5]) begin
-                                                               soc_sdram_choose_req_grant <= 3'd5;
+                                                       if (litedramcore_choose_req_request[5]) begin
+                                                               litedramcore_choose_req_grant <= 3'd5;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[6]) begin
-                                                                       soc_sdram_choose_req_grant <= 3'd6;
+                                                               if (litedramcore_choose_req_request[6]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd6;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[7]) begin
-                                                                               soc_sdram_choose_req_grant <= 3'd7;
+                                                                       if (litedramcore_choose_req_request[7]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd7;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[0]) begin
-                                                                                       soc_sdram_choose_req_grant <= 1'd0;
+                                                                               if (litedramcore_choose_req_request[0]) begin
+                                                                                       litedramcore_choose_req_grant <= 1'd0;
                                                                                end
                                                                        end
                                                                end
@@ -16264,26 +13884,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        2'd2: begin
-                               if (soc_sdram_choose_req_request[3]) begin
-                                       soc_sdram_choose_req_grant <= 2'd3;
+                               if (litedramcore_choose_req_request[3]) begin
+                                       litedramcore_choose_req_grant <= 2'd3;
                                end else begin
-                                       if (soc_sdram_choose_req_request[4]) begin
-                                               soc_sdram_choose_req_grant <= 3'd4;
+                                       if (litedramcore_choose_req_request[4]) begin
+                                               litedramcore_choose_req_grant <= 3'd4;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[5]) begin
-                                                       soc_sdram_choose_req_grant <= 3'd5;
+                                               if (litedramcore_choose_req_request[5]) begin
+                                                       litedramcore_choose_req_grant <= 3'd5;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[6]) begin
-                                                               soc_sdram_choose_req_grant <= 3'd6;
+                                                       if (litedramcore_choose_req_request[6]) begin
+                                                               litedramcore_choose_req_grant <= 3'd6;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[7]) begin
-                                                                       soc_sdram_choose_req_grant <= 3'd7;
+                                                               if (litedramcore_choose_req_request[7]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd7;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[0]) begin
-                                                                               soc_sdram_choose_req_grant <= 1'd0;
+                                                                       if (litedramcore_choose_req_request[0]) begin
+                                                                               litedramcore_choose_req_grant <= 1'd0;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[1]) begin
-                                                                                       soc_sdram_choose_req_grant <= 1'd1;
+                                                                               if (litedramcore_choose_req_request[1]) begin
+                                                                                       litedramcore_choose_req_grant <= 1'd1;
                                                                                end
                                                                        end
                                                                end
@@ -16293,26 +13913,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        2'd3: begin
-                               if (soc_sdram_choose_req_request[4]) begin
-                                       soc_sdram_choose_req_grant <= 3'd4;
+                               if (litedramcore_choose_req_request[4]) begin
+                                       litedramcore_choose_req_grant <= 3'd4;
                                end else begin
-                                       if (soc_sdram_choose_req_request[5]) begin
-                                               soc_sdram_choose_req_grant <= 3'd5;
+                                       if (litedramcore_choose_req_request[5]) begin
+                                               litedramcore_choose_req_grant <= 3'd5;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[6]) begin
-                                                       soc_sdram_choose_req_grant <= 3'd6;
+                                               if (litedramcore_choose_req_request[6]) begin
+                                                       litedramcore_choose_req_grant <= 3'd6;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[7]) begin
-                                                               soc_sdram_choose_req_grant <= 3'd7;
+                                                       if (litedramcore_choose_req_request[7]) begin
+                                                               litedramcore_choose_req_grant <= 3'd7;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[0]) begin
-                                                                       soc_sdram_choose_req_grant <= 1'd0;
+                                                               if (litedramcore_choose_req_request[0]) begin
+                                                                       litedramcore_choose_req_grant <= 1'd0;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[1]) begin
-                                                                               soc_sdram_choose_req_grant <= 1'd1;
+                                                                       if (litedramcore_choose_req_request[1]) begin
+                                                                               litedramcore_choose_req_grant <= 1'd1;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[2]) begin
-                                                                                       soc_sdram_choose_req_grant <= 2'd2;
+                                                                               if (litedramcore_choose_req_request[2]) begin
+                                                                                       litedramcore_choose_req_grant <= 2'd2;
                                                                                end
                                                                        end
                                                                end
@@ -16322,26 +13942,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd4: begin
-                               if (soc_sdram_choose_req_request[5]) begin
-                                       soc_sdram_choose_req_grant <= 3'd5;
+                               if (litedramcore_choose_req_request[5]) begin
+                                       litedramcore_choose_req_grant <= 3'd5;
                                end else begin
-                                       if (soc_sdram_choose_req_request[6]) begin
-                                               soc_sdram_choose_req_grant <= 3'd6;
+                                       if (litedramcore_choose_req_request[6]) begin
+                                               litedramcore_choose_req_grant <= 3'd6;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[7]) begin
-                                                       soc_sdram_choose_req_grant <= 3'd7;
+                                               if (litedramcore_choose_req_request[7]) begin
+                                                       litedramcore_choose_req_grant <= 3'd7;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[0]) begin
-                                                               soc_sdram_choose_req_grant <= 1'd0;
+                                                       if (litedramcore_choose_req_request[0]) begin
+                                                               litedramcore_choose_req_grant <= 1'd0;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[1]) begin
-                                                                       soc_sdram_choose_req_grant <= 1'd1;
+                                                               if (litedramcore_choose_req_request[1]) begin
+                                                                       litedramcore_choose_req_grant <= 1'd1;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[2]) begin
-                                                                               soc_sdram_choose_req_grant <= 2'd2;
+                                                                       if (litedramcore_choose_req_request[2]) begin
+                                                                               litedramcore_choose_req_grant <= 2'd2;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[3]) begin
-                                                                                       soc_sdram_choose_req_grant <= 2'd3;
+                                                                               if (litedramcore_choose_req_request[3]) begin
+                                                                                       litedramcore_choose_req_grant <= 2'd3;
                                                                                end
                                                                        end
                                                                end
@@ -16351,26 +13971,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd5: begin
-                               if (soc_sdram_choose_req_request[6]) begin
-                                       soc_sdram_choose_req_grant <= 3'd6;
+                               if (litedramcore_choose_req_request[6]) begin
+                                       litedramcore_choose_req_grant <= 3'd6;
                                end else begin
-                                       if (soc_sdram_choose_req_request[7]) begin
-                                               soc_sdram_choose_req_grant <= 3'd7;
+                                       if (litedramcore_choose_req_request[7]) begin
+                                               litedramcore_choose_req_grant <= 3'd7;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[0]) begin
-                                                       soc_sdram_choose_req_grant <= 1'd0;
+                                               if (litedramcore_choose_req_request[0]) begin
+                                                       litedramcore_choose_req_grant <= 1'd0;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[1]) begin
-                                                               soc_sdram_choose_req_grant <= 1'd1;
+                                                       if (litedramcore_choose_req_request[1]) begin
+                                                               litedramcore_choose_req_grant <= 1'd1;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[2]) begin
-                                                                       soc_sdram_choose_req_grant <= 2'd2;
+                                                               if (litedramcore_choose_req_request[2]) begin
+                                                                       litedramcore_choose_req_grant <= 2'd2;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[3]) begin
-                                                                               soc_sdram_choose_req_grant <= 2'd3;
+                                                                       if (litedramcore_choose_req_request[3]) begin
+                                                                               litedramcore_choose_req_grant <= 2'd3;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[4]) begin
-                                                                                       soc_sdram_choose_req_grant <= 3'd4;
+                                                                               if (litedramcore_choose_req_request[4]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd4;
                                                                                end
                                                                        end
                                                                end
@@ -16380,26 +14000,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd6: begin
-                               if (soc_sdram_choose_req_request[7]) begin
-                                       soc_sdram_choose_req_grant <= 3'd7;
+                               if (litedramcore_choose_req_request[7]) begin
+                                       litedramcore_choose_req_grant <= 3'd7;
                                end else begin
-                                       if (soc_sdram_choose_req_request[0]) begin
-                                               soc_sdram_choose_req_grant <= 1'd0;
+                                       if (litedramcore_choose_req_request[0]) begin
+                                               litedramcore_choose_req_grant <= 1'd0;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[1]) begin
-                                                       soc_sdram_choose_req_grant <= 1'd1;
+                                               if (litedramcore_choose_req_request[1]) begin
+                                                       litedramcore_choose_req_grant <= 1'd1;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[2]) begin
-                                                               soc_sdram_choose_req_grant <= 2'd2;
+                                                       if (litedramcore_choose_req_request[2]) begin
+                                                               litedramcore_choose_req_grant <= 2'd2;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[3]) begin
-                                                                       soc_sdram_choose_req_grant <= 2'd3;
+                                                               if (litedramcore_choose_req_request[3]) begin
+                                                                       litedramcore_choose_req_grant <= 2'd3;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[4]) begin
-                                                                               soc_sdram_choose_req_grant <= 3'd4;
+                                                                       if (litedramcore_choose_req_request[4]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd4;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[5]) begin
-                                                                                       soc_sdram_choose_req_grant <= 3'd5;
+                                                                               if (litedramcore_choose_req_request[5]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd5;
                                                                                end
                                                                        end
                                                                end
@@ -16409,26 +14029,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd7: begin
-                               if (soc_sdram_choose_req_request[0]) begin
-                                       soc_sdram_choose_req_grant <= 1'd0;
+                               if (litedramcore_choose_req_request[0]) begin
+                                       litedramcore_choose_req_grant <= 1'd0;
                                end else begin
-                                       if (soc_sdram_choose_req_request[1]) begin
-                                               soc_sdram_choose_req_grant <= 1'd1;
+                                       if (litedramcore_choose_req_request[1]) begin
+                                               litedramcore_choose_req_grant <= 1'd1;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[2]) begin
-                                                       soc_sdram_choose_req_grant <= 2'd2;
+                                               if (litedramcore_choose_req_request[2]) begin
+                                                       litedramcore_choose_req_grant <= 2'd2;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[3]) begin
-                                                               soc_sdram_choose_req_grant <= 2'd3;
+                                                       if (litedramcore_choose_req_request[3]) begin
+                                                               litedramcore_choose_req_grant <= 2'd3;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[4]) begin
-                                                                       soc_sdram_choose_req_grant <= 3'd4;
+                                                               if (litedramcore_choose_req_request[4]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd4;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[5]) begin
-                                                                               soc_sdram_choose_req_grant <= 3'd5;
+                                                                       if (litedramcore_choose_req_request[5]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd5;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[6]) begin
-                                                                                       soc_sdram_choose_req_grant <= 3'd6;
+                                                                               if (litedramcore_choose_req_request[6]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd6;
                                                                                end
                                                                        end
                                                                end
@@ -16439,1280 +14059,709 @@ always @(posedge sys_clk) begin
                        end
                endcase
        end
-       soc_sdram_dfi_p0_cs_n <= 1'd0;
-       soc_sdram_dfi_p0_bank <= vns_array_muxed0;
-       soc_sdram_dfi_p0_address <= vns_array_muxed1;
-       soc_sdram_dfi_p0_cas_n <= (~vns_array_muxed2);
-       soc_sdram_dfi_p0_ras_n <= (~vns_array_muxed3);
-       soc_sdram_dfi_p0_we_n <= (~vns_array_muxed4);
-       soc_sdram_dfi_p0_rddata_en <= vns_array_muxed5;
-       soc_sdram_dfi_p0_wrdata_en <= vns_array_muxed6;
-       soc_sdram_dfi_p1_cs_n <= 1'd0;
-       soc_sdram_dfi_p1_bank <= vns_array_muxed7;
-       soc_sdram_dfi_p1_address <= vns_array_muxed8;
-       soc_sdram_dfi_p1_cas_n <= (~vns_array_muxed9);
-       soc_sdram_dfi_p1_ras_n <= (~vns_array_muxed10);
-       soc_sdram_dfi_p1_we_n <= (~vns_array_muxed11);
-       soc_sdram_dfi_p1_rddata_en <= vns_array_muxed12;
-       soc_sdram_dfi_p1_wrdata_en <= vns_array_muxed13;
-       soc_sdram_dfi_p2_cs_n <= 1'd0;
-       soc_sdram_dfi_p2_bank <= vns_array_muxed14;
-       soc_sdram_dfi_p2_address <= vns_array_muxed15;
-       soc_sdram_dfi_p2_cas_n <= (~vns_array_muxed16);
-       soc_sdram_dfi_p2_ras_n <= (~vns_array_muxed17);
-       soc_sdram_dfi_p2_we_n <= (~vns_array_muxed18);
-       soc_sdram_dfi_p2_rddata_en <= vns_array_muxed19;
-       soc_sdram_dfi_p2_wrdata_en <= vns_array_muxed20;
-       soc_sdram_dfi_p3_cs_n <= 1'd0;
-       soc_sdram_dfi_p3_bank <= vns_array_muxed21;
-       soc_sdram_dfi_p3_address <= vns_array_muxed22;
-       soc_sdram_dfi_p3_cas_n <= (~vns_array_muxed23);
-       soc_sdram_dfi_p3_ras_n <= (~vns_array_muxed24);
-       soc_sdram_dfi_p3_we_n <= (~vns_array_muxed25);
-       soc_sdram_dfi_p3_rddata_en <= vns_array_muxed26;
-       soc_sdram_dfi_p3_wrdata_en <= vns_array_muxed27;
-       if (soc_sdram_trrdcon_valid) begin
-               soc_sdram_trrdcon_count <= 1'd1;
+       litedramcore_dfi_p0_cs_n <= 1'd0;
+       litedramcore_dfi_p0_bank <= array_muxed0;
+       litedramcore_dfi_p0_address <= array_muxed1;
+       litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+       litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+       litedramcore_dfi_p0_we_n <= (~array_muxed4);
+       litedramcore_dfi_p0_rddata_en <= array_muxed5;
+       litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+       litedramcore_dfi_p1_cs_n <= 1'd0;
+       litedramcore_dfi_p1_bank <= array_muxed7;
+       litedramcore_dfi_p1_address <= array_muxed8;
+       litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+       litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+       litedramcore_dfi_p1_we_n <= (~array_muxed11);
+       litedramcore_dfi_p1_rddata_en <= array_muxed12;
+       litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+       litedramcore_dfi_p2_cs_n <= 1'd0;
+       litedramcore_dfi_p2_bank <= array_muxed14;
+       litedramcore_dfi_p2_address <= array_muxed15;
+       litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+       litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+       litedramcore_dfi_p2_we_n <= (~array_muxed18);
+       litedramcore_dfi_p2_rddata_en <= array_muxed19;
+       litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+       litedramcore_dfi_p3_cs_n <= 1'd0;
+       litedramcore_dfi_p3_bank <= array_muxed21;
+       litedramcore_dfi_p3_address <= array_muxed22;
+       litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+       litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+       litedramcore_dfi_p3_we_n <= (~array_muxed25);
+       litedramcore_dfi_p3_rddata_en <= array_muxed26;
+       litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+       if (litedramcore_trrdcon_valid) begin
+               litedramcore_trrdcon_count <= 1'd1;
                if (1'd0) begin
-                       soc_sdram_trrdcon_ready <= 1'd1;
+                       litedramcore_trrdcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_trrdcon_ready <= 1'd0;
+                       litedramcore_trrdcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_trrdcon_ready)) begin
-                       soc_sdram_trrdcon_count <= (soc_sdram_trrdcon_count - 1'd1);
-                       if ((soc_sdram_trrdcon_count == 1'd1)) begin
-                               soc_sdram_trrdcon_ready <= 1'd1;
+               if ((~litedramcore_trrdcon_ready)) begin
+                       litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+                       if ((litedramcore_trrdcon_count == 1'd1)) begin
+                               litedramcore_trrdcon_ready <= 1'd1;
                        end
                end
        end
-       soc_sdram_tfawcon_window <= {soc_sdram_tfawcon_window, soc_sdram_tfawcon_valid};
-       if ((soc_sdram_tfawcon_count < 3'd4)) begin
-               if ((soc_sdram_tfawcon_count == 2'd3)) begin
-                       soc_sdram_tfawcon_ready <= (~soc_sdram_tfawcon_valid);
+       litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+       if ((litedramcore_tfawcon_count < 3'd4)) begin
+               if ((litedramcore_tfawcon_count == 2'd3)) begin
+                       litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
                end else begin
-                       soc_sdram_tfawcon_ready <= 1'd1;
+                       litedramcore_tfawcon_ready <= 1'd1;
                end
        end
-       if (soc_sdram_tccdcon_valid) begin
-               soc_sdram_tccdcon_count <= 1'd0;
+       if (litedramcore_tccdcon_valid) begin
+               litedramcore_tccdcon_count <= 1'd0;
                if (1'd1) begin
-                       soc_sdram_tccdcon_ready <= 1'd1;
+                       litedramcore_tccdcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_tccdcon_ready <= 1'd0;
+                       litedramcore_tccdcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_tccdcon_ready)) begin
-                       soc_sdram_tccdcon_count <= (soc_sdram_tccdcon_count - 1'd1);
-                       if ((soc_sdram_tccdcon_count == 1'd1)) begin
-                               soc_sdram_tccdcon_ready <= 1'd1;
+               if ((~litedramcore_tccdcon_ready)) begin
+                       litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+                       if ((litedramcore_tccdcon_count == 1'd1)) begin
+                               litedramcore_tccdcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_twtrcon_valid) begin
-               soc_sdram_twtrcon_count <= 3'd4;
+       if (litedramcore_twtrcon_valid) begin
+               litedramcore_twtrcon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_twtrcon_ready <= 1'd1;
+                       litedramcore_twtrcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_twtrcon_ready <= 1'd0;
-               end
-       end else begin
-               if ((~soc_sdram_twtrcon_ready)) begin
-                       soc_sdram_twtrcon_count <= (soc_sdram_twtrcon_count - 1'd1);
-                       if ((soc_sdram_twtrcon_count == 1'd1)) begin
-                               soc_sdram_twtrcon_ready <= 1'd1;
-                       end
-               end
-       end
-       vns_multiplexer_state <= vns_multiplexer_next_state;
-       vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_wdata_ready));
-       vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0;
-       vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1;
-       vns_new_master_wdata_ready3 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_wdata_ready));
-       vns_new_master_wdata_ready4 <= vns_new_master_wdata_ready3;
-       vns_new_master_wdata_ready5 <= vns_new_master_wdata_ready4;
-       vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_rdata_valid));
-       vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0;
-       vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1;
-       vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2;
-       vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3;
-       vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4;
-       vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5;
-       vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6;
-       vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7;
-       vns_new_master_rdata_valid9 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_rdata_valid));
-       vns_new_master_rdata_valid10 <= vns_new_master_rdata_valid9;
-       vns_new_master_rdata_valid11 <= vns_new_master_rdata_valid10;
-       vns_new_master_rdata_valid12 <= vns_new_master_rdata_valid11;
-       vns_new_master_rdata_valid13 <= vns_new_master_rdata_valid12;
-       vns_new_master_rdata_valid14 <= vns_new_master_rdata_valid13;
-       vns_new_master_rdata_valid15 <= vns_new_master_rdata_valid14;
-       vns_new_master_rdata_valid16 <= vns_new_master_rdata_valid15;
-       vns_new_master_rdata_valid17 <= vns_new_master_rdata_valid16;
-       if (vns_roundrobin0_ce) begin
-               case (vns_roundrobin0_grant)
-                       1'd0: begin
-                               if (vns_roundrobin0_request[1]) begin
-                                       vns_roundrobin0_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin0_request[0]) begin
-                                       vns_roundrobin0_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin1_ce) begin
-               case (vns_roundrobin1_grant)
-                       1'd0: begin
-                               if (vns_roundrobin1_request[1]) begin
-                                       vns_roundrobin1_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin1_request[0]) begin
-                                       vns_roundrobin1_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin2_ce) begin
-               case (vns_roundrobin2_grant)
-                       1'd0: begin
-                               if (vns_roundrobin2_request[1]) begin
-                                       vns_roundrobin2_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin2_request[0]) begin
-                                       vns_roundrobin2_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin3_ce) begin
-               case (vns_roundrobin3_grant)
-                       1'd0: begin
-                               if (vns_roundrobin3_request[1]) begin
-                                       vns_roundrobin3_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin3_request[0]) begin
-                                       vns_roundrobin3_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin4_ce) begin
-               case (vns_roundrobin4_grant)
-                       1'd0: begin
-                               if (vns_roundrobin4_request[1]) begin
-                                       vns_roundrobin4_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin4_request[0]) begin
-                                       vns_roundrobin4_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin5_ce) begin
-               case (vns_roundrobin5_grant)
-                       1'd0: begin
-                               if (vns_roundrobin5_request[1]) begin
-                                       vns_roundrobin5_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin5_request[0]) begin
-                                       vns_roundrobin5_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin6_ce) begin
-               case (vns_roundrobin6_grant)
-                       1'd0: begin
-                               if (vns_roundrobin6_request[1]) begin
-                                       vns_roundrobin6_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin6_request[0]) begin
-                                       vns_roundrobin6_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin7_ce) begin
-               case (vns_roundrobin7_grant)
-                       1'd0: begin
-                               if (vns_roundrobin7_request[1]) begin
-                                       vns_roundrobin7_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin7_request[0]) begin
-                                       vns_roundrobin7_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (soc_counter_reset) begin
-               soc_counter <= 1'd0;
-       end else begin
-               if (soc_counter_ce) begin
-                       soc_counter <= (soc_counter + 1'd1);
-               end
-       end
-       if (soc_address_ce) begin
-               soc_address_q <= soc_address_d;
-       end
-       if (soc_address_reset) begin
-               soc_address_q <= 30'd0;
-       end
-       if (soc_need_refill_ce) begin
-               soc_need_refill_q <= soc_need_refill_d;
-       end
-       if (soc_need_refill_reset) begin
-               soc_need_refill_q <= 1'd1;
-       end
-       vns_converter_state <= vns_converter_next_state;
-       if (soc_cached_datas_ce0) begin
-               soc_cached_datas_flipflop0_q <= soc_cached_datas_flipflop0_d;
-       end
-       if (soc_cached_datas_reset0) begin
-               soc_cached_datas_flipflop0_q <= 32'd0;
-       end
-       if (soc_cached_datas_ce1) begin
-               soc_cached_datas_flipflop1_q <= soc_cached_datas_flipflop1_d;
-       end
-       if (soc_cached_datas_reset1) begin
-               soc_cached_datas_flipflop1_q <= 32'd0;
-       end
-       if (soc_cached_datas_ce2) begin
-               soc_cached_datas_flipflop2_q <= soc_cached_datas_flipflop2_d;
-       end
-       if (soc_cached_datas_reset2) begin
-               soc_cached_datas_flipflop2_q <= 32'd0;
-       end
-       if (soc_cached_datas_ce3) begin
-               soc_cached_datas_flipflop3_q <= soc_cached_datas_flipflop3_d;
-       end
-       if (soc_cached_datas_reset3) begin
-               soc_cached_datas_flipflop3_q <= 32'd0;
-       end
-       if (soc_cached_sels_ce0) begin
-               soc_cached_sels_flipflop0_q <= soc_cached_sels_flipflop0_d;
-       end
-       if (soc_cached_sels_reset0) begin
-               soc_cached_sels_flipflop0_q <= 4'd0;
-       end
-       if (soc_cached_sels_ce1) begin
-               soc_cached_sels_flipflop1_q <= soc_cached_sels_flipflop1_d;
-       end
-       if (soc_cached_sels_reset1) begin
-               soc_cached_sels_flipflop1_q <= 4'd0;
-       end
-       if (soc_cached_sels_ce2) begin
-               soc_cached_sels_flipflop2_q <= soc_cached_sels_flipflop2_d;
-       end
-       if (soc_cached_sels_reset2) begin
-               soc_cached_sels_flipflop2_q <= 4'd0;
-       end
-       if (soc_cached_sels_ce3) begin
-               soc_cached_sels_flipflop3_q <= soc_cached_sels_flipflop3_d;
-       end
-       if (soc_cached_sels_reset3) begin
-               soc_cached_sels_flipflop3_q <= 4'd0;
-       end
-       vns_litedramwishbone2native_state <= vns_litedramwishbone2native_next_state;
-       if (soc_count_next_value_ce) begin
-               soc_count <= soc_count_next_value;
-       end
-       case (vns_grant)
-               1'd0: begin
-                       if ((~vns_request[0])) begin
-                               if (vns_request[1]) begin
-                                       vns_grant <= 1'd1;
-                               end
-                       end
-               end
-               1'd1: begin
-                       if ((~vns_request[1])) begin
-                               if (vns_request[0]) begin
-                                       vns_grant <= 1'd0;
-                               end
-                       end
-               end
-       endcase
-       vns_slave_sel_r <= vns_slave_sel;
-       if (vns_wait) begin
-               if ((~vns_done)) begin
-                       vns_count <= (vns_count - 1'd1);
+                       litedramcore_twtrcon_ready <= 1'd0;
                end
        end else begin
-               vns_count <= 20'd1000000;
-       end
-       vns_interface0_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank0_sel) begin
-               case (vns_interface0_bank_bus_adr[3:0])
-                       1'd0: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_reset0_w;
-                       end
-                       1'd1: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch3_w;
-                       end
-                       2'd2: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch2_w;
-                       end
-                       2'd3: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch1_w;
-                       end
-                       3'd4: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch0_w;
-                       end
-                       3'd5: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors3_w;
-                       end
-                       3'd6: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors2_w;
-                       end
-                       3'd7: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors1_w;
-                       end
-                       4'd8: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors0_w;
-                       end
-               endcase
-       end
-       if (vns_csrbank0_reset0_re) begin
-               soc_litedramcore_soccontroller_reset_storage <= vns_csrbank0_reset0_r;
-       end
-       soc_litedramcore_soccontroller_reset_re <= vns_csrbank0_reset0_re;
-       if (vns_csrbank0_scratch3_re) begin
-               soc_litedramcore_soccontroller_scratch_storage[31:24] <= vns_csrbank0_scratch3_r;
-       end
-       if (vns_csrbank0_scratch2_re) begin
-               soc_litedramcore_soccontroller_scratch_storage[23:16] <= vns_csrbank0_scratch2_r;
-       end
-       if (vns_csrbank0_scratch1_re) begin
-               soc_litedramcore_soccontroller_scratch_storage[15:8] <= vns_csrbank0_scratch1_r;
-       end
-       if (vns_csrbank0_scratch0_re) begin
-               soc_litedramcore_soccontroller_scratch_storage[7:0] <= vns_csrbank0_scratch0_r;
-       end
-       soc_litedramcore_soccontroller_scratch_re <= vns_csrbank0_scratch0_re;
-       vns_interface1_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank1_sel) begin
-               case (vns_interface1_bank_bus_adr[0])
+               if ((~litedramcore_twtrcon_ready)) begin
+                       litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+                       if ((litedramcore_twtrcon_count == 1'd1)) begin
+                               litedramcore_twtrcon_ready <= 1'd1;
+                       end
+               end
+       end
+       multiplexer_state <= multiplexer_next_state;
+       new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+       new_master_wdata_ready1 <= new_master_wdata_ready0;
+       new_master_wdata_ready2 <= new_master_wdata_ready1;
+       new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+       new_master_rdata_valid1 <= new_master_rdata_valid0;
+       new_master_rdata_valid2 <= new_master_rdata_valid1;
+       new_master_rdata_valid3 <= new_master_rdata_valid2;
+       new_master_rdata_valid4 <= new_master_rdata_valid3;
+       new_master_rdata_valid5 <= new_master_rdata_valid4;
+       new_master_rdata_valid6 <= new_master_rdata_valid5;
+       new_master_rdata_valid7 <= new_master_rdata_valid6;
+       new_master_rdata_valid8 <= new_master_rdata_valid7;
+       interface0_bank_bus_dat_r <= 1'd0;
+       if (csrbank0_sel) begin
+               case (interface0_bank_bus_adr[3])
                        1'd0: begin
-                               vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_done0_w;
+                               interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
                        end
                        1'd1: begin
-                               vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_error0_w;
+                               interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
                        end
                endcase
        end
-       if (vns_csrbank1_init_done0_re) begin
-               soc_init_done_storage <= vns_csrbank1_init_done0_r;
+       if (csrbank0_init_done0_re) begin
+               init_done_storage <= csrbank0_init_done0_r;
        end
-       soc_init_done_re <= vns_csrbank1_init_done0_re;
-       if (vns_csrbank1_init_error0_re) begin
-               soc_init_error_storage <= vns_csrbank1_init_error0_r;
+       init_done_re <= csrbank0_init_done0_re;
+       if (csrbank0_init_error0_re) begin
+               init_error_storage <= csrbank0_init_error0_r;
        end
-       soc_init_error_re <= vns_csrbank1_init_error0_re;
-       vns_interface2_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank2_sel) begin
-               case (vns_interface2_bank_bus_adr[3:0])
+       init_error_re <= csrbank0_init_error0_re;
+       interface1_bank_bus_dat_r <= 1'd0;
+       if (csrbank1_sel) begin
+               case (interface1_bank_bus_adr[6:3])
                        1'd0: begin
-                               vns_interface2_bank_bus_dat_r <= vns_csrbank2_half_sys8x_taps0_w;
+                               interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
                        end
                        1'd1: begin
-                               vns_interface2_bank_bus_dat_r <= vns_csrbank2_wlevel_en0_w;
+                               interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
                        end
                        2'd2: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
                        end
                        2'd3: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_cdly_rst_w;
                        end
                        3'd4: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_cdly_inc_w;
                        end
                        3'd5: begin
-                               vns_interface2_bank_bus_dat_r <= vns_csrbank2_dly_sel0_w;
+                               interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
                        end
                        3'd6: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
                        end
                        3'd7: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
                        end
                        4'd8: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
                        end
                        4'd9: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
                        end
                endcase
        end
-       if (vns_csrbank2_half_sys8x_taps0_re) begin
-               soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank2_half_sys8x_taps0_r;
+       if (csrbank1_half_sys8x_taps0_re) begin
+               a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
        end
-       soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank2_half_sys8x_taps0_re;
-       if (vns_csrbank2_wlevel_en0_re) begin
-               soc_a7ddrphy_wlevel_en_storage <= vns_csrbank2_wlevel_en0_r;
+       a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+       if (csrbank1_wlevel_en0_re) begin
+               a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
        end
-       soc_a7ddrphy_wlevel_en_re <= vns_csrbank2_wlevel_en0_re;
-       if (vns_csrbank2_dly_sel0_re) begin
-               soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank2_dly_sel0_r;
+       a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+       if (csrbank1_dly_sel0_re) begin
+               a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
        end
-       soc_a7ddrphy_dly_sel_re <= vns_csrbank2_dly_sel0_re;
-       vns_interface3_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank3_sel) begin
-               case (vns_interface3_bank_bus_adr[5:0])
+       a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+       interface2_bank_bus_dat_r <= 1'd0;
+       if (csrbank2_sel) begin
+               case (interface2_bank_bus_adr[8:3])
                        1'd0: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_control0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
                        end
                        1'd1: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_command0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
                        end
                        2'd2: begin
-                               vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector0_command_issue_w;
+                               interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
                        end
                        2'd3: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w;
                        end
                        3'd4: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
                        end
                        3'd5: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_baddress0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
                        end
                        3'd6: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w;
                        end
                        3'd7: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w;
                        end
                        4'd8: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
                        end
                        4'd9: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
                        end
                        4'd10: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w;
                        end
                        4'd11: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w;
                        end
                        4'd12: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
                        end
                        4'd13: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
                        end
                        4'd14: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_command0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
                        end
                        4'd15: begin
-                               vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector1_command_issue_w;
+                               interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
                        end
                        5'd16: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w;
                        end
                        5'd17: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
                        end
                        5'd18: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_baddress0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
                        end
                        5'd19: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w;
                        end
                        5'd20: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w;
                        end
                        5'd21: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
                        end
                        5'd22: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
                        end
                        5'd23: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w;
                        end
                        5'd24: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w;
                        end
                        5'd25: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
                        end
                        5'd26: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
                        end
                        5'd27: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_command0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
                        end
                        5'd28: begin
-                               vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector2_command_issue_w;
+                               interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
                        end
                        5'd29: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w;
                        end
                        5'd30: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
                        end
                        5'd31: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_baddress0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
                        end
                        6'd32: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w;
                        end
                        6'd33: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w;
                        end
                        6'd34: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w;
                        end
                        6'd35: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
                        end
                        6'd36: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w;
                        end
                        6'd37: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w;
                        end
                        6'd38: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w;
                        end
                        6'd39: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w;
                        end
                        6'd40: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_command0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
                        end
                        6'd41: begin
-                               vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector3_command_issue_w;
+                               interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
                        end
                        6'd42: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w;
                        end
                        6'd43: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
                        end
                        6'd44: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_baddress0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
                        end
                        6'd45: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w;
                        end
                        6'd46: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w;
                        end
                        6'd47: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w;
                        end
                        6'd48: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
                        end
                        6'd49: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w;
                        end
                        6'd50: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w;
                        end
                        6'd51: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w;
                        end
                        6'd52: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w;
                        end
                endcase
        end
-       if (vns_csrbank3_dfii_control0_re) begin
-               soc_sdram_storage[3:0] <= vns_csrbank3_dfii_control0_r;
-       end
-       soc_sdram_re <= vns_csrbank3_dfii_control0_re;
-       if (vns_csrbank3_dfii_pi0_command0_re) begin
-               soc_sdram_phaseinjector0_command_storage[5:0] <= vns_csrbank3_dfii_pi0_command0_r;
-       end
-       soc_sdram_phaseinjector0_command_re <= vns_csrbank3_dfii_pi0_command0_re;
-       if (vns_csrbank3_dfii_pi0_address1_re) begin
-               soc_sdram_phaseinjector0_address_storage[13:8] <= vns_csrbank3_dfii_pi0_address1_r;
-       end
-       if (vns_csrbank3_dfii_pi0_address0_re) begin
-               soc_sdram_phaseinjector0_address_storage[7:0] <= vns_csrbank3_dfii_pi0_address0_r;
-       end
-       soc_sdram_phaseinjector0_address_re <= vns_csrbank3_dfii_pi0_address0_re;
-       if (vns_csrbank3_dfii_pi0_baddress0_re) begin
-               soc_sdram_phaseinjector0_baddress_storage[2:0] <= vns_csrbank3_dfii_pi0_baddress0_r;
-       end
-       soc_sdram_phaseinjector0_baddress_re <= vns_csrbank3_dfii_pi0_baddress0_re;
-       if (vns_csrbank3_dfii_pi0_wrdata3_re) begin
-               soc_sdram_phaseinjector0_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi0_wrdata3_r;
-       end
-       if (vns_csrbank3_dfii_pi0_wrdata2_re) begin
-               soc_sdram_phaseinjector0_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi0_wrdata2_r;
-       end
-       if (vns_csrbank3_dfii_pi0_wrdata1_re) begin
-               soc_sdram_phaseinjector0_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi0_wrdata1_r;
-       end
-       if (vns_csrbank3_dfii_pi0_wrdata0_re) begin
-               soc_sdram_phaseinjector0_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi0_wrdata0_r;
+       if (csrbank2_dfii_control0_re) begin
+               litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
        end
-       soc_sdram_phaseinjector0_wrdata_re <= vns_csrbank3_dfii_pi0_wrdata0_re;
-       if (vns_csrbank3_dfii_pi1_command0_re) begin
-               soc_sdram_phaseinjector1_command_storage[5:0] <= vns_csrbank3_dfii_pi1_command0_r;
+       litedramcore_re <= csrbank2_dfii_control0_re;
+       if (csrbank2_dfii_pi0_command0_re) begin
+               litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
        end
-       soc_sdram_phaseinjector1_command_re <= vns_csrbank3_dfii_pi1_command0_re;
-       if (vns_csrbank3_dfii_pi1_address1_re) begin
-               soc_sdram_phaseinjector1_address_storage[13:8] <= vns_csrbank3_dfii_pi1_address1_r;
+       litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+       if (csrbank2_dfii_pi0_address1_re) begin
+               litedramcore_phaseinjector0_address_storage[13:8] <= csrbank2_dfii_pi0_address1_r;
        end
-       if (vns_csrbank3_dfii_pi1_address0_re) begin
-               soc_sdram_phaseinjector1_address_storage[7:0] <= vns_csrbank3_dfii_pi1_address0_r;
+       if (csrbank2_dfii_pi0_address0_re) begin
+               litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r;
        end
-       soc_sdram_phaseinjector1_address_re <= vns_csrbank3_dfii_pi1_address0_re;
-       if (vns_csrbank3_dfii_pi1_baddress0_re) begin
-               soc_sdram_phaseinjector1_baddress_storage[2:0] <= vns_csrbank3_dfii_pi1_baddress0_r;
+       litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+       if (csrbank2_dfii_pi0_baddress0_re) begin
+               litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
        end
-       soc_sdram_phaseinjector1_baddress_re <= vns_csrbank3_dfii_pi1_baddress0_re;
-       if (vns_csrbank3_dfii_pi1_wrdata3_re) begin
-               soc_sdram_phaseinjector1_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi1_wrdata3_r;
+       litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+       if (csrbank2_dfii_pi0_wrdata3_re) begin
+               litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r;
        end
-       if (vns_csrbank3_dfii_pi1_wrdata2_re) begin
-               soc_sdram_phaseinjector1_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi1_wrdata2_r;
+       if (csrbank2_dfii_pi0_wrdata2_re) begin
+               litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r;
        end
-       if (vns_csrbank3_dfii_pi1_wrdata1_re) begin
-               soc_sdram_phaseinjector1_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi1_wrdata1_r;
+       if (csrbank2_dfii_pi0_wrdata1_re) begin
+               litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r;
        end
-       if (vns_csrbank3_dfii_pi1_wrdata0_re) begin
-               soc_sdram_phaseinjector1_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi1_wrdata0_r;
+       if (csrbank2_dfii_pi0_wrdata0_re) begin
+               litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r;
        end
-       soc_sdram_phaseinjector1_wrdata_re <= vns_csrbank3_dfii_pi1_wrdata0_re;
-       if (vns_csrbank3_dfii_pi2_command0_re) begin
-               soc_sdram_phaseinjector2_command_storage[5:0] <= vns_csrbank3_dfii_pi2_command0_r;
+       litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+       if (csrbank2_dfii_pi1_command0_re) begin
+               litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
        end
-       soc_sdram_phaseinjector2_command_re <= vns_csrbank3_dfii_pi2_command0_re;
-       if (vns_csrbank3_dfii_pi2_address1_re) begin
-               soc_sdram_phaseinjector2_address_storage[13:8] <= vns_csrbank3_dfii_pi2_address1_r;
+       litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+       if (csrbank2_dfii_pi1_address1_re) begin
+               litedramcore_phaseinjector1_address_storage[13:8] <= csrbank2_dfii_pi1_address1_r;
        end
-       if (vns_csrbank3_dfii_pi2_address0_re) begin
-               soc_sdram_phaseinjector2_address_storage[7:0] <= vns_csrbank3_dfii_pi2_address0_r;
+       if (csrbank2_dfii_pi1_address0_re) begin
+               litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r;
        end
-       soc_sdram_phaseinjector2_address_re <= vns_csrbank3_dfii_pi2_address0_re;
-       if (vns_csrbank3_dfii_pi2_baddress0_re) begin
-               soc_sdram_phaseinjector2_baddress_storage[2:0] <= vns_csrbank3_dfii_pi2_baddress0_r;
+       litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+       if (csrbank2_dfii_pi1_baddress0_re) begin
+               litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
        end
-       soc_sdram_phaseinjector2_baddress_re <= vns_csrbank3_dfii_pi2_baddress0_re;
-       if (vns_csrbank3_dfii_pi2_wrdata3_re) begin
-               soc_sdram_phaseinjector2_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi2_wrdata3_r;
+       litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+       if (csrbank2_dfii_pi1_wrdata3_re) begin
+               litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r;
        end
-       if (vns_csrbank3_dfii_pi2_wrdata2_re) begin
-               soc_sdram_phaseinjector2_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi2_wrdata2_r;
-       end
-       if (vns_csrbank3_dfii_pi2_wrdata1_re) begin
-               soc_sdram_phaseinjector2_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi2_wrdata1_r;
-       end
-       if (vns_csrbank3_dfii_pi2_wrdata0_re) begin
-               soc_sdram_phaseinjector2_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi2_wrdata0_r;
-       end
-       soc_sdram_phaseinjector2_wrdata_re <= vns_csrbank3_dfii_pi2_wrdata0_re;
-       if (vns_csrbank3_dfii_pi3_command0_re) begin
-               soc_sdram_phaseinjector3_command_storage[5:0] <= vns_csrbank3_dfii_pi3_command0_r;
-       end
-       soc_sdram_phaseinjector3_command_re <= vns_csrbank3_dfii_pi3_command0_re;
-       if (vns_csrbank3_dfii_pi3_address1_re) begin
-               soc_sdram_phaseinjector3_address_storage[13:8] <= vns_csrbank3_dfii_pi3_address1_r;
-       end
-       if (vns_csrbank3_dfii_pi3_address0_re) begin
-               soc_sdram_phaseinjector3_address_storage[7:0] <= vns_csrbank3_dfii_pi3_address0_r;
-       end
-       soc_sdram_phaseinjector3_address_re <= vns_csrbank3_dfii_pi3_address0_re;
-       if (vns_csrbank3_dfii_pi3_baddress0_re) begin
-               soc_sdram_phaseinjector3_baddress_storage[2:0] <= vns_csrbank3_dfii_pi3_baddress0_r;
-       end
-       soc_sdram_phaseinjector3_baddress_re <= vns_csrbank3_dfii_pi3_baddress0_re;
-       if (vns_csrbank3_dfii_pi3_wrdata3_re) begin
-               soc_sdram_phaseinjector3_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi3_wrdata3_r;
-       end
-       if (vns_csrbank3_dfii_pi3_wrdata2_re) begin
-               soc_sdram_phaseinjector3_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi3_wrdata2_r;
-       end
-       if (vns_csrbank3_dfii_pi3_wrdata1_re) begin
-               soc_sdram_phaseinjector3_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi3_wrdata1_r;
-       end
-       if (vns_csrbank3_dfii_pi3_wrdata0_re) begin
-               soc_sdram_phaseinjector3_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi3_wrdata0_r;
-       end
-       soc_sdram_phaseinjector3_wrdata_re <= vns_csrbank3_dfii_pi3_wrdata0_re;
-       vns_interface4_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank4_sel) begin
-               case (vns_interface4_bank_bus_adr[4:0])
-                       1'd0: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_load3_w;
-                       end
-                       1'd1: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_load2_w;
-                       end
-                       2'd2: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_load1_w;
-                       end
-                       2'd3: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_load0_w;
-                       end
-                       3'd4: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload3_w;
-                       end
-                       3'd5: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload2_w;
-                       end
-                       3'd6: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload1_w;
-                       end
-                       3'd7: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload0_w;
-                       end
-                       4'd8: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_en0_w;
-                       end
-                       4'd9: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_update_value0_w;
-                       end
-                       4'd10: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_value3_w;
-                       end
-                       4'd11: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_value2_w;
-                       end
-                       4'd12: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_value1_w;
-                       end
-                       4'd13: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_value0_w;
-                       end
-                       4'd14: begin
-                               vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_status_w;
-                       end
-                       4'd15: begin
-                               vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_pending_w;
-                       end
-                       5'd16: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_ev_enable0_w;
-                       end
-               endcase
+       if (csrbank2_dfii_pi1_wrdata2_re) begin
+               litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r;
        end
-       if (vns_csrbank4_load3_re) begin
-               soc_litedramcore_timer_load_storage[31:24] <= vns_csrbank4_load3_r;
+       if (csrbank2_dfii_pi1_wrdata1_re) begin
+               litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r;
        end
-       if (vns_csrbank4_load2_re) begin
-               soc_litedramcore_timer_load_storage[23:16] <= vns_csrbank4_load2_r;
+       if (csrbank2_dfii_pi1_wrdata0_re) begin
+               litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r;
        end
-       if (vns_csrbank4_load1_re) begin
-               soc_litedramcore_timer_load_storage[15:8] <= vns_csrbank4_load1_r;
+       litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+       if (csrbank2_dfii_pi2_command0_re) begin
+               litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
        end
-       if (vns_csrbank4_load0_re) begin
-               soc_litedramcore_timer_load_storage[7:0] <= vns_csrbank4_load0_r;
+       litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+       if (csrbank2_dfii_pi2_address1_re) begin
+               litedramcore_phaseinjector2_address_storage[13:8] <= csrbank2_dfii_pi2_address1_r;
        end
-       soc_litedramcore_timer_load_re <= vns_csrbank4_load0_re;
-       if (vns_csrbank4_reload3_re) begin
-               soc_litedramcore_timer_reload_storage[31:24] <= vns_csrbank4_reload3_r;
+       if (csrbank2_dfii_pi2_address0_re) begin
+               litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r;
        end
-       if (vns_csrbank4_reload2_re) begin
-               soc_litedramcore_timer_reload_storage[23:16] <= vns_csrbank4_reload2_r;
+       litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+       if (csrbank2_dfii_pi2_baddress0_re) begin
+               litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
        end
-       if (vns_csrbank4_reload1_re) begin
-               soc_litedramcore_timer_reload_storage[15:8] <= vns_csrbank4_reload1_r;
+       litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+       if (csrbank2_dfii_pi2_wrdata3_re) begin
+               litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r;
        end
-       if (vns_csrbank4_reload0_re) begin
-               soc_litedramcore_timer_reload_storage[7:0] <= vns_csrbank4_reload0_r;
+       if (csrbank2_dfii_pi2_wrdata2_re) begin
+               litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r;
        end
-       soc_litedramcore_timer_reload_re <= vns_csrbank4_reload0_re;
-       if (vns_csrbank4_en0_re) begin
-               soc_litedramcore_timer_en_storage <= vns_csrbank4_en0_r;
+       if (csrbank2_dfii_pi2_wrdata1_re) begin
+               litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r;
        end
-       soc_litedramcore_timer_en_re <= vns_csrbank4_en0_re;
-       if (vns_csrbank4_update_value0_re) begin
-               soc_litedramcore_timer_update_value_storage <= vns_csrbank4_update_value0_r;
+       if (csrbank2_dfii_pi2_wrdata0_re) begin
+               litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r;
        end
-       soc_litedramcore_timer_update_value_re <= vns_csrbank4_update_value0_re;
-       if (vns_csrbank4_ev_enable0_re) begin
-               soc_litedramcore_timer_eventmanager_storage <= vns_csrbank4_ev_enable0_r;
+       litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+       if (csrbank2_dfii_pi3_command0_re) begin
+               litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
        end
-       soc_litedramcore_timer_eventmanager_re <= vns_csrbank4_ev_enable0_re;
-       vns_interface5_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank5_sel) begin
-               case (vns_interface5_bank_bus_adr[2:0])
-                       1'd0: begin
-                               vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_rxtx_w;
-                       end
-                       1'd1: begin
-                               vns_interface5_bank_bus_dat_r <= vns_csrbank5_txfull_w;
-                       end
-                       2'd2: begin
-                               vns_interface5_bank_bus_dat_r <= vns_csrbank5_rxempty_w;
-                       end
-                       2'd3: begin
-                               vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_status_w;
-                       end
-                       3'd4: begin
-                               vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_pending_w;
-                       end
-                       3'd5: begin
-                               vns_interface5_bank_bus_dat_r <= vns_csrbank5_ev_enable0_w;
-                       end
-               endcase
+       litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+       if (csrbank2_dfii_pi3_address1_re) begin
+               litedramcore_phaseinjector3_address_storage[13:8] <= csrbank2_dfii_pi3_address1_r;
        end
-       if (vns_csrbank5_ev_enable0_re) begin
-               soc_litedramcore_uart_eventmanager_storage[1:0] <= vns_csrbank5_ev_enable0_r;
+       if (csrbank2_dfii_pi3_address0_re) begin
+               litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r;
        end
-       soc_litedramcore_uart_eventmanager_re <= vns_csrbank5_ev_enable0_re;
-       vns_interface6_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank6_sel) begin
-               case (vns_interface6_bank_bus_adr[1:0])
-                       1'd0: begin
-                               vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word3_w;
-                       end
-                       1'd1: begin
-                               vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word2_w;
-                       end
-                       2'd2: begin
-                               vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word1_w;
-                       end
-                       2'd3: begin
-                               vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word0_w;
-                       end
-               endcase
+       litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+       if (csrbank2_dfii_pi3_baddress0_re) begin
+               litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
        end
-       if (vns_csrbank6_tuning_word3_re) begin
-               soc_litedramcore_storage[31:24] <= vns_csrbank6_tuning_word3_r;
+       litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+       if (csrbank2_dfii_pi3_wrdata3_re) begin
+               litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r;
        end
-       if (vns_csrbank6_tuning_word2_re) begin
-               soc_litedramcore_storage[23:16] <= vns_csrbank6_tuning_word2_r;
+       if (csrbank2_dfii_pi3_wrdata2_re) begin
+               litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r;
        end
-       if (vns_csrbank6_tuning_word1_re) begin
-               soc_litedramcore_storage[15:8] <= vns_csrbank6_tuning_word1_r;
+       if (csrbank2_dfii_pi3_wrdata1_re) begin
+               litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r;
        end
-       if (vns_csrbank6_tuning_word0_re) begin
-               soc_litedramcore_storage[7:0] <= vns_csrbank6_tuning_word0_r;
+       if (csrbank2_dfii_pi3_wrdata0_re) begin
+               litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r;
        end
-       soc_litedramcore_re <= vns_csrbank6_tuning_word0_re;
+       litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
        if (sys_rst) begin
-               soc_litedramcore_soccontroller_reset_storage <= 1'd0;
-               soc_litedramcore_soccontroller_reset_re <= 1'd0;
-               soc_litedramcore_soccontroller_scratch_storage <= 32'd305419896;
-               soc_litedramcore_soccontroller_scratch_re <= 1'd0;
-               soc_litedramcore_soccontroller_bus_errors <= 32'd0;
-               soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0;
-               soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0;
-               serial_tx <= 1'd1;
-               soc_litedramcore_storage <= 32'd4947802;
-               soc_litedramcore_re <= 1'd0;
-               soc_litedramcore_sink_ready <= 1'd0;
-               soc_litedramcore_uart_clk_txen <= 1'd0;
-               soc_litedramcore_tx_busy <= 1'd0;
-               soc_litedramcore_source_valid <= 1'd0;
-               soc_litedramcore_uart_clk_rxen <= 1'd0;
-               soc_litedramcore_rx_r <= 1'd0;
-               soc_litedramcore_rx_busy <= 1'd0;
-               soc_litedramcore_uart_tx_pending <= 1'd0;
-               soc_litedramcore_uart_tx_old_trigger <= 1'd0;
-               soc_litedramcore_uart_rx_pending <= 1'd0;
-               soc_litedramcore_uart_rx_old_trigger <= 1'd0;
-               soc_litedramcore_uart_eventmanager_storage <= 2'd0;
-               soc_litedramcore_uart_eventmanager_re <= 1'd0;
-               soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
-               soc_litedramcore_uart_tx_fifo_level0 <= 5'd0;
-               soc_litedramcore_uart_tx_fifo_produce <= 4'd0;
-               soc_litedramcore_uart_tx_fifo_consume <= 4'd0;
-               soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
-               soc_litedramcore_uart_rx_fifo_level0 <= 5'd0;
-               soc_litedramcore_uart_rx_fifo_produce <= 4'd0;
-               soc_litedramcore_uart_rx_fifo_consume <= 4'd0;
-               soc_litedramcore_timer_load_storage <= 32'd0;
-               soc_litedramcore_timer_load_re <= 1'd0;
-               soc_litedramcore_timer_reload_storage <= 32'd0;
-               soc_litedramcore_timer_reload_re <= 1'd0;
-               soc_litedramcore_timer_en_storage <= 1'd0;
-               soc_litedramcore_timer_en_re <= 1'd0;
-               soc_litedramcore_timer_update_value_storage <= 1'd0;
-               soc_litedramcore_timer_update_value_re <= 1'd0;
-               soc_litedramcore_timer_value_status <= 32'd0;
-               soc_litedramcore_timer_zero_pending <= 1'd0;
-               soc_litedramcore_timer_zero_old_trigger <= 1'd0;
-               soc_litedramcore_timer_eventmanager_storage <= 1'd0;
-               soc_litedramcore_timer_eventmanager_re <= 1'd0;
-               soc_litedramcore_timer_value <= 32'd0;
-               soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-               soc_a7ddrphy_half_sys8x_taps_re <= 1'd0;
-               soc_a7ddrphy_wlevel_en_storage <= 1'd0;
-               soc_a7ddrphy_wlevel_en_re <= 1'd0;
-               soc_a7ddrphy_dly_sel_storage <= 2'd0;
-               soc_a7ddrphy_dly_sel_re <= 1'd0;
-               soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
-               soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
-               soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
-               soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
-               soc_a7ddrphy_dqs_oe_delayed <= 1'd0;
-               soc_a7ddrphy_dqspattern_o1 <= 8'd0;
-               soc_a7ddrphy_dq_oe_delayed <= 1'd0;
-               soc_a7ddrphy_bitslip0_value <= 3'd0;
-               soc_a7ddrphy_bitslip1_value <= 3'd0;
-               soc_a7ddrphy_bitslip2_value <= 3'd0;
-               soc_a7ddrphy_bitslip3_value <= 3'd0;
-               soc_a7ddrphy_bitslip4_value <= 3'd0;
-               soc_a7ddrphy_bitslip5_value <= 3'd0;
-               soc_a7ddrphy_bitslip6_value <= 3'd0;
-               soc_a7ddrphy_bitslip7_value <= 3'd0;
-               soc_a7ddrphy_bitslip8_value <= 3'd0;
-               soc_a7ddrphy_bitslip9_value <= 3'd0;
-               soc_a7ddrphy_bitslip10_value <= 3'd0;
-               soc_a7ddrphy_bitslip11_value <= 3'd0;
-               soc_a7ddrphy_bitslip12_value <= 3'd0;
-               soc_a7ddrphy_bitslip13_value <= 3'd0;
-               soc_a7ddrphy_bitslip14_value <= 3'd0;
-               soc_a7ddrphy_bitslip15_value <= 3'd0;
-               soc_a7ddrphy_rddata_en_last <= 8'd0;
-               soc_a7ddrphy_wrdata_en_last <= 4'd0;
-               soc_sdram_storage <= 4'd0;
-               soc_sdram_re <= 1'd0;
-               soc_sdram_phaseinjector0_command_storage <= 6'd0;
-               soc_sdram_phaseinjector0_command_re <= 1'd0;
-               soc_sdram_phaseinjector0_address_re <= 1'd0;
-               soc_sdram_phaseinjector0_baddress_re <= 1'd0;
-               soc_sdram_phaseinjector0_wrdata_re <= 1'd0;
-               soc_sdram_phaseinjector0_status <= 32'd0;
-               soc_sdram_phaseinjector1_command_storage <= 6'd0;
-               soc_sdram_phaseinjector1_command_re <= 1'd0;
-               soc_sdram_phaseinjector1_address_re <= 1'd0;
-               soc_sdram_phaseinjector1_baddress_re <= 1'd0;
-               soc_sdram_phaseinjector1_wrdata_re <= 1'd0;
-               soc_sdram_phaseinjector1_status <= 32'd0;
-               soc_sdram_phaseinjector2_command_storage <= 6'd0;
-               soc_sdram_phaseinjector2_command_re <= 1'd0;
-               soc_sdram_phaseinjector2_address_re <= 1'd0;
-               soc_sdram_phaseinjector2_baddress_re <= 1'd0;
-               soc_sdram_phaseinjector2_wrdata_re <= 1'd0;
-               soc_sdram_phaseinjector2_status <= 32'd0;
-               soc_sdram_phaseinjector3_command_storage <= 6'd0;
-               soc_sdram_phaseinjector3_command_re <= 1'd0;
-               soc_sdram_phaseinjector3_address_re <= 1'd0;
-               soc_sdram_phaseinjector3_baddress_re <= 1'd0;
-               soc_sdram_phaseinjector3_wrdata_re <= 1'd0;
-               soc_sdram_phaseinjector3_status <= 32'd0;
-               soc_sdram_dfi_p0_address <= 14'd0;
-               soc_sdram_dfi_p0_bank <= 3'd0;
-               soc_sdram_dfi_p0_cas_n <= 1'd1;
-               soc_sdram_dfi_p0_cs_n <= 1'd1;
-               soc_sdram_dfi_p0_ras_n <= 1'd1;
-               soc_sdram_dfi_p0_we_n <= 1'd1;
-               soc_sdram_dfi_p0_wrdata_en <= 1'd0;
-               soc_sdram_dfi_p0_rddata_en <= 1'd0;
-               soc_sdram_dfi_p1_address <= 14'd0;
-               soc_sdram_dfi_p1_bank <= 3'd0;
-               soc_sdram_dfi_p1_cas_n <= 1'd1;
-               soc_sdram_dfi_p1_cs_n <= 1'd1;
-               soc_sdram_dfi_p1_ras_n <= 1'd1;
-               soc_sdram_dfi_p1_we_n <= 1'd1;
-               soc_sdram_dfi_p1_wrdata_en <= 1'd0;
-               soc_sdram_dfi_p1_rddata_en <= 1'd0;
-               soc_sdram_dfi_p2_address <= 14'd0;
-               soc_sdram_dfi_p2_bank <= 3'd0;
-               soc_sdram_dfi_p2_cas_n <= 1'd1;
-               soc_sdram_dfi_p2_cs_n <= 1'd1;
-               soc_sdram_dfi_p2_ras_n <= 1'd1;
-               soc_sdram_dfi_p2_we_n <= 1'd1;
-               soc_sdram_dfi_p2_wrdata_en <= 1'd0;
-               soc_sdram_dfi_p2_rddata_en <= 1'd0;
-               soc_sdram_dfi_p3_address <= 14'd0;
-               soc_sdram_dfi_p3_bank <= 3'd0;
-               soc_sdram_dfi_p3_cas_n <= 1'd1;
-               soc_sdram_dfi_p3_cs_n <= 1'd1;
-               soc_sdram_dfi_p3_ras_n <= 1'd1;
-               soc_sdram_dfi_p3_we_n <= 1'd1;
-               soc_sdram_dfi_p3_wrdata_en <= 1'd0;
-               soc_sdram_dfi_p3_rddata_en <= 1'd0;
-               soc_sdram_timer_count1 <= 10'd781;
-               soc_sdram_postponer_req_o <= 1'd0;
-               soc_sdram_postponer_count <= 1'd0;
-               soc_sdram_sequencer_done1 <= 1'd0;
-               soc_sdram_sequencer_counter <= 6'd0;
-               soc_sdram_sequencer_count <= 1'd0;
-               soc_sdram_zqcs_timer_count1 <= 27'd99999999;
-               soc_sdram_zqcs_executer_done <= 1'd0;
-               soc_sdram_zqcs_executer_counter <= 5'd0;
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine0_row <= 14'd0;
-               soc_sdram_bankmachine0_row_opened <= 1'd0;
-               soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine0_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine0_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine0_trccon_count <= 3'd0;
-               soc_sdram_bankmachine0_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine0_trascon_count <= 3'd0;
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine1_row <= 14'd0;
-               soc_sdram_bankmachine1_row_opened <= 1'd0;
-               soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine1_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine1_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine1_trccon_count <= 3'd0;
-               soc_sdram_bankmachine1_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine1_trascon_count <= 3'd0;
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine2_row <= 14'd0;
-               soc_sdram_bankmachine2_row_opened <= 1'd0;
-               soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine2_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine2_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine2_trccon_count <= 3'd0;
-               soc_sdram_bankmachine2_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine2_trascon_count <= 3'd0;
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine3_row <= 14'd0;
-               soc_sdram_bankmachine3_row_opened <= 1'd0;
-               soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine3_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine3_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine3_trccon_count <= 3'd0;
-               soc_sdram_bankmachine3_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine3_trascon_count <= 3'd0;
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine4_row <= 14'd0;
-               soc_sdram_bankmachine4_row_opened <= 1'd0;
-               soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine4_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine4_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine4_trccon_count <= 3'd0;
-               soc_sdram_bankmachine4_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine4_trascon_count <= 3'd0;
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine5_row <= 14'd0;
-               soc_sdram_bankmachine5_row_opened <= 1'd0;
-               soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine5_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine5_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine5_trccon_count <= 3'd0;
-               soc_sdram_bankmachine5_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine5_trascon_count <= 3'd0;
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine6_row <= 14'd0;
-               soc_sdram_bankmachine6_row_opened <= 1'd0;
-               soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine6_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine6_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine6_trccon_count <= 3'd0;
-               soc_sdram_bankmachine6_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine6_trascon_count <= 3'd0;
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine7_row <= 14'd0;
-               soc_sdram_bankmachine7_row_opened <= 1'd0;
-               soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine7_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine7_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine7_trccon_count <= 3'd0;
-               soc_sdram_bankmachine7_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine7_trascon_count <= 3'd0;
-               soc_sdram_choose_cmd_grant <= 3'd0;
-               soc_sdram_choose_req_grant <= 3'd0;
-               soc_sdram_trrdcon_ready <= 1'd1;
-               soc_sdram_trrdcon_count <= 1'd0;
-               soc_sdram_tfawcon_ready <= 1'd1;
-               soc_sdram_tfawcon_window <= 5'd0;
-               soc_sdram_tccdcon_ready <= 1'd1;
-               soc_sdram_tccdcon_count <= 1'd0;
-               soc_sdram_twtrcon_ready <= 1'd1;
-               soc_sdram_twtrcon_count <= 3'd0;
-               soc_sdram_time0 <= 5'd0;
-               soc_sdram_time1 <= 4'd0;
-               soc_address_q <= 30'd0;
-               soc_counter <= 2'd0;
-               soc_need_refill_q <= 1'd1;
-               soc_cached_datas_flipflop0_q <= 32'd0;
-               soc_cached_datas_flipflop1_q <= 32'd0;
-               soc_cached_datas_flipflop2_q <= 32'd0;
-               soc_cached_datas_flipflop3_q <= 32'd0;
-               soc_cached_sels_flipflop0_q <= 4'd0;
-               soc_cached_sels_flipflop1_q <= 4'd0;
-               soc_cached_sels_flipflop2_q <= 4'd0;
-               soc_cached_sels_flipflop3_q <= 4'd0;
-               soc_count <= 1'd0;
-               soc_init_done_storage <= 1'd0;
-               soc_init_done_re <= 1'd0;
-               soc_init_error_storage <= 1'd0;
-               soc_init_error_re <= 1'd0;
-               vns_wb2csr_state <= 1'd0;
-               vns_refresher_state <= 2'd0;
-               vns_bankmachine0_state <= 4'd0;
-               vns_bankmachine1_state <= 4'd0;
-               vns_bankmachine2_state <= 4'd0;
-               vns_bankmachine3_state <= 4'd0;
-               vns_bankmachine4_state <= 4'd0;
-               vns_bankmachine5_state <= 4'd0;
-               vns_bankmachine6_state <= 4'd0;
-               vns_bankmachine7_state <= 4'd0;
-               vns_multiplexer_state <= 4'd0;
-               vns_roundrobin0_grant <= 1'd0;
-               vns_roundrobin1_grant <= 1'd0;
-               vns_roundrobin2_grant <= 1'd0;
-               vns_roundrobin3_grant <= 1'd0;
-               vns_roundrobin4_grant <= 1'd0;
-               vns_roundrobin5_grant <= 1'd0;
-               vns_roundrobin6_grant <= 1'd0;
-               vns_roundrobin7_grant <= 1'd0;
-               vns_new_master_wdata_ready0 <= 1'd0;
-               vns_new_master_wdata_ready1 <= 1'd0;
-               vns_new_master_wdata_ready2 <= 1'd0;
-               vns_new_master_wdata_ready3 <= 1'd0;
-               vns_new_master_wdata_ready4 <= 1'd0;
-               vns_new_master_wdata_ready5 <= 1'd0;
-               vns_new_master_rdata_valid0 <= 1'd0;
-               vns_new_master_rdata_valid1 <= 1'd0;
-               vns_new_master_rdata_valid2 <= 1'd0;
-               vns_new_master_rdata_valid3 <= 1'd0;
-               vns_new_master_rdata_valid4 <= 1'd0;
-               vns_new_master_rdata_valid5 <= 1'd0;
-               vns_new_master_rdata_valid6 <= 1'd0;
-               vns_new_master_rdata_valid7 <= 1'd0;
-               vns_new_master_rdata_valid8 <= 1'd0;
-               vns_new_master_rdata_valid9 <= 1'd0;
-               vns_new_master_rdata_valid10 <= 1'd0;
-               vns_new_master_rdata_valid11 <= 1'd0;
-               vns_new_master_rdata_valid12 <= 1'd0;
-               vns_new_master_rdata_valid13 <= 1'd0;
-               vns_new_master_rdata_valid14 <= 1'd0;
-               vns_new_master_rdata_valid15 <= 1'd0;
-               vns_new_master_rdata_valid16 <= 1'd0;
-               vns_new_master_rdata_valid17 <= 1'd0;
-               vns_converter_state <= 3'd0;
-               vns_litedramwishbone2native_state <= 2'd0;
-               vns_grant <= 1'd0;
-               vns_slave_sel_r <= 4'd0;
-               vns_count <= 20'd1000000;
-       end
-       vns_regs0 <= serial_rx;
-       vns_regs1 <= vns_regs0;
-end
-
-reg [31:0] mem[0:6143];
-reg [31:0] memdat;
-always @(posedge sys_clk) begin
-       memdat <= mem[soc_litedramcore_litedramcore_adr];
-end
-
-assign soc_litedramcore_litedramcore_dat_r = memdat;
-
-initial begin
-       $readmemh("litedram_core.init", mem);
-end
-
-reg [31:0] mem_1[0:1023];
-reg [9:0] memadr;
-always @(posedge sys_clk) begin
-       if (soc_litedramcore_ram_we[0])
-               mem_1[soc_litedramcore_ram_adr][7:0] <= soc_litedramcore_ram_dat_w[7:0];
-       if (soc_litedramcore_ram_we[1])
-               mem_1[soc_litedramcore_ram_adr][15:8] <= soc_litedramcore_ram_dat_w[15:8];
-       if (soc_litedramcore_ram_we[2])
-               mem_1[soc_litedramcore_ram_adr][23:16] <= soc_litedramcore_ram_dat_w[23:16];
-       if (soc_litedramcore_ram_we[3])
-               mem_1[soc_litedramcore_ram_adr][31:24] <= soc_litedramcore_ram_dat_w[31:24];
-       memadr <= soc_litedramcore_ram_adr;
-end
-
-assign soc_litedramcore_ram_dat_r = mem_1[memadr];
-
-initial begin
-       $readmemh("mem_1.init", mem_1);
-end
-
-reg [9:0] storage[0:15];
-reg [9:0] memdat_1;
-reg [9:0] memdat_2;
-always @(posedge sys_clk) begin
-       if (soc_litedramcore_uart_tx_fifo_wrport_we)
-               storage[soc_litedramcore_uart_tx_fifo_wrport_adr] <= soc_litedramcore_uart_tx_fifo_wrport_dat_w;
-       memdat_1 <= storage[soc_litedramcore_uart_tx_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-       if (soc_litedramcore_uart_tx_fifo_rdport_re)
-               memdat_2 <= storage[soc_litedramcore_uart_tx_fifo_rdport_adr];
-end
-
-assign soc_litedramcore_uart_tx_fifo_wrport_dat_r = memdat_1;
-assign soc_litedramcore_uart_tx_fifo_rdport_dat_r = memdat_2;
-
-reg [9:0] storage_1[0:15];
-reg [9:0] memdat_3;
-reg [9:0] memdat_4;
-always @(posedge sys_clk) begin
-       if (soc_litedramcore_uart_rx_fifo_wrport_we)
-               storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr] <= soc_litedramcore_uart_rx_fifo_wrport_dat_w;
-       memdat_3 <= storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-       if (soc_litedramcore_uart_rx_fifo_rdport_re)
-               memdat_4 <= storage_1[soc_litedramcore_uart_rx_fifo_rdport_adr];
+               a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+               a7ddrphy_half_sys8x_taps_re <= 1'd0;
+               a7ddrphy_wlevel_en_storage <= 1'd0;
+               a7ddrphy_wlevel_en_re <= 1'd0;
+               a7ddrphy_dly_sel_storage <= 2'd0;
+               a7ddrphy_dly_sel_re <= 1'd0;
+               a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
+               a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
+               a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
+               a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
+               a7ddrphy_dqs_oe_delayed <= 1'd0;
+               a7ddrphy_dqspattern_o1 <= 8'd0;
+               a7ddrphy_dq_oe_delayed <= 1'd0;
+               a7ddrphy_bitslip0_value <= 3'd0;
+               a7ddrphy_bitslip1_value <= 3'd0;
+               a7ddrphy_bitslip2_value <= 3'd0;
+               a7ddrphy_bitslip3_value <= 3'd0;
+               a7ddrphy_bitslip4_value <= 3'd0;
+               a7ddrphy_bitslip5_value <= 3'd0;
+               a7ddrphy_bitslip6_value <= 3'd0;
+               a7ddrphy_bitslip7_value <= 3'd0;
+               a7ddrphy_bitslip8_value <= 3'd0;
+               a7ddrphy_bitslip9_value <= 3'd0;
+               a7ddrphy_bitslip10_value <= 3'd0;
+               a7ddrphy_bitslip11_value <= 3'd0;
+               a7ddrphy_bitslip12_value <= 3'd0;
+               a7ddrphy_bitslip13_value <= 3'd0;
+               a7ddrphy_bitslip14_value <= 3'd0;
+               a7ddrphy_bitslip15_value <= 3'd0;
+               a7ddrphy_rddata_en_last <= 8'd0;
+               a7ddrphy_wrdata_en_last <= 4'd0;
+               litedramcore_storage <= 4'd0;
+               litedramcore_re <= 1'd0;
+               litedramcore_phaseinjector0_command_storage <= 6'd0;
+               litedramcore_phaseinjector0_command_re <= 1'd0;
+               litedramcore_phaseinjector0_address_re <= 1'd0;
+               litedramcore_phaseinjector0_baddress_re <= 1'd0;
+               litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector0_status <= 32'd0;
+               litedramcore_phaseinjector1_command_storage <= 6'd0;
+               litedramcore_phaseinjector1_command_re <= 1'd0;
+               litedramcore_phaseinjector1_address_re <= 1'd0;
+               litedramcore_phaseinjector1_baddress_re <= 1'd0;
+               litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector1_status <= 32'd0;
+               litedramcore_phaseinjector2_command_storage <= 6'd0;
+               litedramcore_phaseinjector2_command_re <= 1'd0;
+               litedramcore_phaseinjector2_address_re <= 1'd0;
+               litedramcore_phaseinjector2_baddress_re <= 1'd0;
+               litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector2_status <= 32'd0;
+               litedramcore_phaseinjector3_command_storage <= 6'd0;
+               litedramcore_phaseinjector3_command_re <= 1'd0;
+               litedramcore_phaseinjector3_address_re <= 1'd0;
+               litedramcore_phaseinjector3_baddress_re <= 1'd0;
+               litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector3_status <= 32'd0;
+               litedramcore_dfi_p0_address <= 14'd0;
+               litedramcore_dfi_p0_bank <= 3'd0;
+               litedramcore_dfi_p0_cas_n <= 1'd1;
+               litedramcore_dfi_p0_cs_n <= 1'd1;
+               litedramcore_dfi_p0_ras_n <= 1'd1;
+               litedramcore_dfi_p0_we_n <= 1'd1;
+               litedramcore_dfi_p0_wrdata_en <= 1'd0;
+               litedramcore_dfi_p0_rddata_en <= 1'd0;
+               litedramcore_dfi_p1_address <= 14'd0;
+               litedramcore_dfi_p1_bank <= 3'd0;
+               litedramcore_dfi_p1_cas_n <= 1'd1;
+               litedramcore_dfi_p1_cs_n <= 1'd1;
+               litedramcore_dfi_p1_ras_n <= 1'd1;
+               litedramcore_dfi_p1_we_n <= 1'd1;
+               litedramcore_dfi_p1_wrdata_en <= 1'd0;
+               litedramcore_dfi_p1_rddata_en <= 1'd0;
+               litedramcore_dfi_p2_address <= 14'd0;
+               litedramcore_dfi_p2_bank <= 3'd0;
+               litedramcore_dfi_p2_cas_n <= 1'd1;
+               litedramcore_dfi_p2_cs_n <= 1'd1;
+               litedramcore_dfi_p2_ras_n <= 1'd1;
+               litedramcore_dfi_p2_we_n <= 1'd1;
+               litedramcore_dfi_p2_wrdata_en <= 1'd0;
+               litedramcore_dfi_p2_rddata_en <= 1'd0;
+               litedramcore_dfi_p3_address <= 14'd0;
+               litedramcore_dfi_p3_bank <= 3'd0;
+               litedramcore_dfi_p3_cas_n <= 1'd1;
+               litedramcore_dfi_p3_cs_n <= 1'd1;
+               litedramcore_dfi_p3_ras_n <= 1'd1;
+               litedramcore_dfi_p3_we_n <= 1'd1;
+               litedramcore_dfi_p3_wrdata_en <= 1'd0;
+               litedramcore_dfi_p3_rddata_en <= 1'd0;
+               litedramcore_timer_count1 <= 10'd781;
+               litedramcore_postponer_req_o <= 1'd0;
+               litedramcore_postponer_count <= 1'd0;
+               litedramcore_sequencer_done1 <= 1'd0;
+               litedramcore_sequencer_counter <= 6'd0;
+               litedramcore_sequencer_count <= 1'd0;
+               litedramcore_zqcs_timer_count1 <= 27'd99999999;
+               litedramcore_zqcs_executer_done <= 1'd0;
+               litedramcore_zqcs_executer_counter <= 5'd0;
+               litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine0_row <= 14'd0;
+               litedramcore_bankmachine0_row_opened <= 1'd0;
+               litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine0_trccon_ready <= 1'd1;
+               litedramcore_bankmachine0_trccon_count <= 3'd0;
+               litedramcore_bankmachine0_trascon_ready <= 1'd1;
+               litedramcore_bankmachine0_trascon_count <= 3'd0;
+               litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine1_row <= 14'd0;
+               litedramcore_bankmachine1_row_opened <= 1'd0;
+               litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine1_trccon_ready <= 1'd1;
+               litedramcore_bankmachine1_trccon_count <= 3'd0;
+               litedramcore_bankmachine1_trascon_ready <= 1'd1;
+               litedramcore_bankmachine1_trascon_count <= 3'd0;
+               litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine2_row <= 14'd0;
+               litedramcore_bankmachine2_row_opened <= 1'd0;
+               litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine2_trccon_ready <= 1'd1;
+               litedramcore_bankmachine2_trccon_count <= 3'd0;
+               litedramcore_bankmachine2_trascon_ready <= 1'd1;
+               litedramcore_bankmachine2_trascon_count <= 3'd0;
+               litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine3_row <= 14'd0;
+               litedramcore_bankmachine3_row_opened <= 1'd0;
+               litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine3_trccon_ready <= 1'd1;
+               litedramcore_bankmachine3_trccon_count <= 3'd0;
+               litedramcore_bankmachine3_trascon_ready <= 1'd1;
+               litedramcore_bankmachine3_trascon_count <= 3'd0;
+               litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine4_row <= 14'd0;
+               litedramcore_bankmachine4_row_opened <= 1'd0;
+               litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine4_trccon_ready <= 1'd1;
+               litedramcore_bankmachine4_trccon_count <= 3'd0;
+               litedramcore_bankmachine4_trascon_ready <= 1'd1;
+               litedramcore_bankmachine4_trascon_count <= 3'd0;
+               litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine5_row <= 14'd0;
+               litedramcore_bankmachine5_row_opened <= 1'd0;
+               litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine5_trccon_ready <= 1'd1;
+               litedramcore_bankmachine5_trccon_count <= 3'd0;
+               litedramcore_bankmachine5_trascon_ready <= 1'd1;
+               litedramcore_bankmachine5_trascon_count <= 3'd0;
+               litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine6_row <= 14'd0;
+               litedramcore_bankmachine6_row_opened <= 1'd0;
+               litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine6_trccon_ready <= 1'd1;
+               litedramcore_bankmachine6_trccon_count <= 3'd0;
+               litedramcore_bankmachine6_trascon_ready <= 1'd1;
+               litedramcore_bankmachine6_trascon_count <= 3'd0;
+               litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine7_row <= 14'd0;
+               litedramcore_bankmachine7_row_opened <= 1'd0;
+               litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine7_trccon_ready <= 1'd1;
+               litedramcore_bankmachine7_trccon_count <= 3'd0;
+               litedramcore_bankmachine7_trascon_ready <= 1'd1;
+               litedramcore_bankmachine7_trascon_count <= 3'd0;
+               litedramcore_choose_cmd_grant <= 3'd0;
+               litedramcore_choose_req_grant <= 3'd0;
+               litedramcore_trrdcon_ready <= 1'd1;
+               litedramcore_trrdcon_count <= 1'd0;
+               litedramcore_tfawcon_ready <= 1'd1;
+               litedramcore_tfawcon_window <= 5'd0;
+               litedramcore_tccdcon_ready <= 1'd1;
+               litedramcore_tccdcon_count <= 1'd0;
+               litedramcore_twtrcon_ready <= 1'd1;
+               litedramcore_twtrcon_count <= 3'd0;
+               litedramcore_time0 <= 5'd0;
+               litedramcore_time1 <= 4'd0;
+               init_done_storage <= 1'd0;
+               init_done_re <= 1'd0;
+               init_error_storage <= 1'd0;
+               init_error_re <= 1'd0;
+               refresher_state <= 2'd0;
+               bankmachine0_state <= 4'd0;
+               bankmachine1_state <= 4'd0;
+               bankmachine2_state <= 4'd0;
+               bankmachine3_state <= 4'd0;
+               bankmachine4_state <= 4'd0;
+               bankmachine5_state <= 4'd0;
+               bankmachine6_state <= 4'd0;
+               bankmachine7_state <= 4'd0;
+               multiplexer_state <= 4'd0;
+               new_master_wdata_ready0 <= 1'd0;
+               new_master_wdata_ready1 <= 1'd0;
+               new_master_wdata_ready2 <= 1'd0;
+               new_master_rdata_valid0 <= 1'd0;
+               new_master_rdata_valid1 <= 1'd0;
+               new_master_rdata_valid2 <= 1'd0;
+               new_master_rdata_valid3 <= 1'd0;
+               new_master_rdata_valid4 <= 1'd0;
+               new_master_rdata_valid5 <= 1'd0;
+               new_master_rdata_valid6 <= 1'd0;
+               new_master_rdata_valid7 <= 1'd0;
+               new_master_rdata_valid8 <= 1'd0;
+       end
 end
 
-assign soc_litedramcore_uart_rx_fifo_wrport_dat_r = memdat_3;
-assign soc_litedramcore_uart_rx_fifo_rdport_dat_r = memdat_4;
-
 BUFG BUFG(
-       .I(soc_s7pll0_clkout0),
-       .O(soc_s7pll0_clkout_buf0)
+       .I(s7pll0_clkout0),
+       .O(s7pll0_clkout_buf0)
 );
 
 BUFG BUFG_1(
-       .I(soc_s7pll0_clkout1),
-       .O(soc_s7pll0_clkout_buf1)
+       .I(s7pll0_clkout1),
+       .O(s7pll0_clkout_buf1)
 );
 
 BUFG BUFG_2(
-       .I(soc_s7pll0_clkout2),
-       .O(soc_s7pll0_clkout_buf2)
+       .I(s7pll0_clkout2),
+       .O(s7pll0_clkout_buf2)
 );
 
 BUFG BUFG_3(
-       .I(soc_s7pll1_clkout),
-       .O(soc_s7pll1_clkout_buf)
+       .I(s7pll1_clkout),
+       .O(s7pll1_clkout_buf)
 );
 
 IDELAYCTRL IDELAYCTRL(
        .REFCLK(iodelay_clk),
-       .RST(soc_ic_reset)
+       .RST(ic_reset)
 );
 
 OSERDESE2 #(
@@ -17734,11 +14783,11 @@ OSERDESE2 #(
        .D8(1'd1),
        .OCE(1'd1),
        .RST(sys_rst),
-       .OQ(soc_a7ddrphy_sd_clk_se_nodelay)
+       .OQ(a7ddrphy_sd_clk_se_nodelay)
 );
 
 OBUFDS OBUFDS(
-       .I(soc_a7ddrphy_sd_clk_se_nodelay),
+       .I(a7ddrphy_sd_clk_se_nodelay),
        .O(ddram_clk_p),
        .OB(ddram_clk_n)
 );
@@ -17752,14 +14801,14 @@ OSERDESE2 #(
 ) OSERDESE2_1 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[0]),
-       .D2(soc_a7ddrphy_dfi_p0_address[0]),
-       .D3(soc_a7ddrphy_dfi_p1_address[0]),
-       .D4(soc_a7ddrphy_dfi_p1_address[0]),
-       .D5(soc_a7ddrphy_dfi_p2_address[0]),
-       .D6(soc_a7ddrphy_dfi_p2_address[0]),
-       .D7(soc_a7ddrphy_dfi_p3_address[0]),
-       .D8(soc_a7ddrphy_dfi_p3_address[0]),
+       .D1(a7ddrphy_dfi_p0_address[0]),
+       .D2(a7ddrphy_dfi_p0_address[0]),
+       .D3(a7ddrphy_dfi_p1_address[0]),
+       .D4(a7ddrphy_dfi_p1_address[0]),
+       .D5(a7ddrphy_dfi_p2_address[0]),
+       .D6(a7ddrphy_dfi_p2_address[0]),
+       .D7(a7ddrphy_dfi_p3_address[0]),
+       .D8(a7ddrphy_dfi_p3_address[0]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[0])
@@ -17774,14 +14823,14 @@ OSERDESE2 #(
 ) OSERDESE2_2 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[1]),
-       .D2(soc_a7ddrphy_dfi_p0_address[1]),
-       .D3(soc_a7ddrphy_dfi_p1_address[1]),
-       .D4(soc_a7ddrphy_dfi_p1_address[1]),
-       .D5(soc_a7ddrphy_dfi_p2_address[1]),
-       .D6(soc_a7ddrphy_dfi_p2_address[1]),
-       .D7(soc_a7ddrphy_dfi_p3_address[1]),
-       .D8(soc_a7ddrphy_dfi_p3_address[1]),
+       .D1(a7ddrphy_dfi_p0_address[1]),
+       .D2(a7ddrphy_dfi_p0_address[1]),
+       .D3(a7ddrphy_dfi_p1_address[1]),
+       .D4(a7ddrphy_dfi_p1_address[1]),
+       .D5(a7ddrphy_dfi_p2_address[1]),
+       .D6(a7ddrphy_dfi_p2_address[1]),
+       .D7(a7ddrphy_dfi_p3_address[1]),
+       .D8(a7ddrphy_dfi_p3_address[1]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[1])
@@ -17796,14 +14845,14 @@ OSERDESE2 #(
 ) OSERDESE2_3 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[2]),
-       .D2(soc_a7ddrphy_dfi_p0_address[2]),
-       .D3(soc_a7ddrphy_dfi_p1_address[2]),
-       .D4(soc_a7ddrphy_dfi_p1_address[2]),
-       .D5(soc_a7ddrphy_dfi_p2_address[2]),
-       .D6(soc_a7ddrphy_dfi_p2_address[2]),
-       .D7(soc_a7ddrphy_dfi_p3_address[2]),
-       .D8(soc_a7ddrphy_dfi_p3_address[2]),
+       .D1(a7ddrphy_dfi_p0_address[2]),
+       .D2(a7ddrphy_dfi_p0_address[2]),
+       .D3(a7ddrphy_dfi_p1_address[2]),
+       .D4(a7ddrphy_dfi_p1_address[2]),
+       .D5(a7ddrphy_dfi_p2_address[2]),
+       .D6(a7ddrphy_dfi_p2_address[2]),
+       .D7(a7ddrphy_dfi_p3_address[2]),
+       .D8(a7ddrphy_dfi_p3_address[2]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[2])
@@ -17818,14 +14867,14 @@ OSERDESE2 #(
 ) OSERDESE2_4 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[3]),
-       .D2(soc_a7ddrphy_dfi_p0_address[3]),
-       .D3(soc_a7ddrphy_dfi_p1_address[3]),
-       .D4(soc_a7ddrphy_dfi_p1_address[3]),
-       .D5(soc_a7ddrphy_dfi_p2_address[3]),
-       .D6(soc_a7ddrphy_dfi_p2_address[3]),
-       .D7(soc_a7ddrphy_dfi_p3_address[3]),
-       .D8(soc_a7ddrphy_dfi_p3_address[3]),
+       .D1(a7ddrphy_dfi_p0_address[3]),
+       .D2(a7ddrphy_dfi_p0_address[3]),
+       .D3(a7ddrphy_dfi_p1_address[3]),
+       .D4(a7ddrphy_dfi_p1_address[3]),
+       .D5(a7ddrphy_dfi_p2_address[3]),
+       .D6(a7ddrphy_dfi_p2_address[3]),
+       .D7(a7ddrphy_dfi_p3_address[3]),
+       .D8(a7ddrphy_dfi_p3_address[3]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[3])
@@ -17840,14 +14889,14 @@ OSERDESE2 #(
 ) OSERDESE2_5 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[4]),
-       .D2(soc_a7ddrphy_dfi_p0_address[4]),
-       .D3(soc_a7ddrphy_dfi_p1_address[4]),
-       .D4(soc_a7ddrphy_dfi_p1_address[4]),
-       .D5(soc_a7ddrphy_dfi_p2_address[4]),
-       .D6(soc_a7ddrphy_dfi_p2_address[4]),
-       .D7(soc_a7ddrphy_dfi_p3_address[4]),
-       .D8(soc_a7ddrphy_dfi_p3_address[4]),
+       .D1(a7ddrphy_dfi_p0_address[4]),
+       .D2(a7ddrphy_dfi_p0_address[4]),
+       .D3(a7ddrphy_dfi_p1_address[4]),
+       .D4(a7ddrphy_dfi_p1_address[4]),
+       .D5(a7ddrphy_dfi_p2_address[4]),
+       .D6(a7ddrphy_dfi_p2_address[4]),
+       .D7(a7ddrphy_dfi_p3_address[4]),
+       .D8(a7ddrphy_dfi_p3_address[4]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[4])
@@ -17862,14 +14911,14 @@ OSERDESE2 #(
 ) OSERDESE2_6 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[5]),
-       .D2(soc_a7ddrphy_dfi_p0_address[5]),
-       .D3(soc_a7ddrphy_dfi_p1_address[5]),
-       .D4(soc_a7ddrphy_dfi_p1_address[5]),
-       .D5(soc_a7ddrphy_dfi_p2_address[5]),
-       .D6(soc_a7ddrphy_dfi_p2_address[5]),
-       .D7(soc_a7ddrphy_dfi_p3_address[5]),
-       .D8(soc_a7ddrphy_dfi_p3_address[5]),
+       .D1(a7ddrphy_dfi_p0_address[5]),
+       .D2(a7ddrphy_dfi_p0_address[5]),
+       .D3(a7ddrphy_dfi_p1_address[5]),
+       .D4(a7ddrphy_dfi_p1_address[5]),
+       .D5(a7ddrphy_dfi_p2_address[5]),
+       .D6(a7ddrphy_dfi_p2_address[5]),
+       .D7(a7ddrphy_dfi_p3_address[5]),
+       .D8(a7ddrphy_dfi_p3_address[5]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[5])
@@ -17884,14 +14933,14 @@ OSERDESE2 #(
 ) OSERDESE2_7 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[6]),
-       .D2(soc_a7ddrphy_dfi_p0_address[6]),
-       .D3(soc_a7ddrphy_dfi_p1_address[6]),
-       .D4(soc_a7ddrphy_dfi_p1_address[6]),
-       .D5(soc_a7ddrphy_dfi_p2_address[6]),
-       .D6(soc_a7ddrphy_dfi_p2_address[6]),
-       .D7(soc_a7ddrphy_dfi_p3_address[6]),
-       .D8(soc_a7ddrphy_dfi_p3_address[6]),
+       .D1(a7ddrphy_dfi_p0_address[6]),
+       .D2(a7ddrphy_dfi_p0_address[6]),
+       .D3(a7ddrphy_dfi_p1_address[6]),
+       .D4(a7ddrphy_dfi_p1_address[6]),
+       .D5(a7ddrphy_dfi_p2_address[6]),
+       .D6(a7ddrphy_dfi_p2_address[6]),
+       .D7(a7ddrphy_dfi_p3_address[6]),
+       .D8(a7ddrphy_dfi_p3_address[6]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[6])
@@ -17906,14 +14955,14 @@ OSERDESE2 #(
 ) OSERDESE2_8 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[7]),
-       .D2(soc_a7ddrphy_dfi_p0_address[7]),
-       .D3(soc_a7ddrphy_dfi_p1_address[7]),
-       .D4(soc_a7ddrphy_dfi_p1_address[7]),
-       .D5(soc_a7ddrphy_dfi_p2_address[7]),
-       .D6(soc_a7ddrphy_dfi_p2_address[7]),
-       .D7(soc_a7ddrphy_dfi_p3_address[7]),
-       .D8(soc_a7ddrphy_dfi_p3_address[7]),
+       .D1(a7ddrphy_dfi_p0_address[7]),
+       .D2(a7ddrphy_dfi_p0_address[7]),
+       .D3(a7ddrphy_dfi_p1_address[7]),
+       .D4(a7ddrphy_dfi_p1_address[7]),
+       .D5(a7ddrphy_dfi_p2_address[7]),
+       .D6(a7ddrphy_dfi_p2_address[7]),
+       .D7(a7ddrphy_dfi_p3_address[7]),
+       .D8(a7ddrphy_dfi_p3_address[7]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[7])
@@ -17928,14 +14977,14 @@ OSERDESE2 #(
 ) OSERDESE2_9 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[8]),
-       .D2(soc_a7ddrphy_dfi_p0_address[8]),
-       .D3(soc_a7ddrphy_dfi_p1_address[8]),
-       .D4(soc_a7ddrphy_dfi_p1_address[8]),
-       .D5(soc_a7ddrphy_dfi_p2_address[8]),
-       .D6(soc_a7ddrphy_dfi_p2_address[8]),
-       .D7(soc_a7ddrphy_dfi_p3_address[8]),
-       .D8(soc_a7ddrphy_dfi_p3_address[8]),
+       .D1(a7ddrphy_dfi_p0_address[8]),
+       .D2(a7ddrphy_dfi_p0_address[8]),
+       .D3(a7ddrphy_dfi_p1_address[8]),
+       .D4(a7ddrphy_dfi_p1_address[8]),
+       .D5(a7ddrphy_dfi_p2_address[8]),
+       .D6(a7ddrphy_dfi_p2_address[8]),
+       .D7(a7ddrphy_dfi_p3_address[8]),
+       .D8(a7ddrphy_dfi_p3_address[8]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[8])
@@ -17950,14 +14999,14 @@ OSERDESE2 #(
 ) OSERDESE2_10 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[9]),
-       .D2(soc_a7ddrphy_dfi_p0_address[9]),
-       .D3(soc_a7ddrphy_dfi_p1_address[9]),
-       .D4(soc_a7ddrphy_dfi_p1_address[9]),
-       .D5(soc_a7ddrphy_dfi_p2_address[9]),
-       .D6(soc_a7ddrphy_dfi_p2_address[9]),
-       .D7(soc_a7ddrphy_dfi_p3_address[9]),
-       .D8(soc_a7ddrphy_dfi_p3_address[9]),
+       .D1(a7ddrphy_dfi_p0_address[9]),
+       .D2(a7ddrphy_dfi_p0_address[9]),
+       .D3(a7ddrphy_dfi_p1_address[9]),
+       .D4(a7ddrphy_dfi_p1_address[9]),
+       .D5(a7ddrphy_dfi_p2_address[9]),
+       .D6(a7ddrphy_dfi_p2_address[9]),
+       .D7(a7ddrphy_dfi_p3_address[9]),
+       .D8(a7ddrphy_dfi_p3_address[9]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[9])
@@ -17972,14 +15021,14 @@ OSERDESE2 #(
 ) OSERDESE2_11 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[10]),
-       .D2(soc_a7ddrphy_dfi_p0_address[10]),
-       .D3(soc_a7ddrphy_dfi_p1_address[10]),
-       .D4(soc_a7ddrphy_dfi_p1_address[10]),
-       .D5(soc_a7ddrphy_dfi_p2_address[10]),
-       .D6(soc_a7ddrphy_dfi_p2_address[10]),
-       .D7(soc_a7ddrphy_dfi_p3_address[10]),
-       .D8(soc_a7ddrphy_dfi_p3_address[10]),
+       .D1(a7ddrphy_dfi_p0_address[10]),
+       .D2(a7ddrphy_dfi_p0_address[10]),
+       .D3(a7ddrphy_dfi_p1_address[10]),
+       .D4(a7ddrphy_dfi_p1_address[10]),
+       .D5(a7ddrphy_dfi_p2_address[10]),
+       .D6(a7ddrphy_dfi_p2_address[10]),
+       .D7(a7ddrphy_dfi_p3_address[10]),
+       .D8(a7ddrphy_dfi_p3_address[10]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[10])
@@ -17994,14 +15043,14 @@ OSERDESE2 #(
 ) OSERDESE2_12 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[11]),
-       .D2(soc_a7ddrphy_dfi_p0_address[11]),
-       .D3(soc_a7ddrphy_dfi_p1_address[11]),
-       .D4(soc_a7ddrphy_dfi_p1_address[11]),
-       .D5(soc_a7ddrphy_dfi_p2_address[11]),
-       .D6(soc_a7ddrphy_dfi_p2_address[11]),
-       .D7(soc_a7ddrphy_dfi_p3_address[11]),
-       .D8(soc_a7ddrphy_dfi_p3_address[11]),
+       .D1(a7ddrphy_dfi_p0_address[11]),
+       .D2(a7ddrphy_dfi_p0_address[11]),
+       .D3(a7ddrphy_dfi_p1_address[11]),
+       .D4(a7ddrphy_dfi_p1_address[11]),
+       .D5(a7ddrphy_dfi_p2_address[11]),
+       .D6(a7ddrphy_dfi_p2_address[11]),
+       .D7(a7ddrphy_dfi_p3_address[11]),
+       .D8(a7ddrphy_dfi_p3_address[11]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[11])
@@ -18016,14 +15065,14 @@ OSERDESE2 #(
 ) OSERDESE2_13 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[12]),
-       .D2(soc_a7ddrphy_dfi_p0_address[12]),
-       .D3(soc_a7ddrphy_dfi_p1_address[12]),
-       .D4(soc_a7ddrphy_dfi_p1_address[12]),
-       .D5(soc_a7ddrphy_dfi_p2_address[12]),
-       .D6(soc_a7ddrphy_dfi_p2_address[12]),
-       .D7(soc_a7ddrphy_dfi_p3_address[12]),
-       .D8(soc_a7ddrphy_dfi_p3_address[12]),
+       .D1(a7ddrphy_dfi_p0_address[12]),
+       .D2(a7ddrphy_dfi_p0_address[12]),
+       .D3(a7ddrphy_dfi_p1_address[12]),
+       .D4(a7ddrphy_dfi_p1_address[12]),
+       .D5(a7ddrphy_dfi_p2_address[12]),
+       .D6(a7ddrphy_dfi_p2_address[12]),
+       .D7(a7ddrphy_dfi_p3_address[12]),
+       .D8(a7ddrphy_dfi_p3_address[12]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[12])
@@ -18038,14 +15087,14 @@ OSERDESE2 #(
 ) OSERDESE2_14 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[13]),
-       .D2(soc_a7ddrphy_dfi_p0_address[13]),
-       .D3(soc_a7ddrphy_dfi_p1_address[13]),
-       .D4(soc_a7ddrphy_dfi_p1_address[13]),
-       .D5(soc_a7ddrphy_dfi_p2_address[13]),
-       .D6(soc_a7ddrphy_dfi_p2_address[13]),
-       .D7(soc_a7ddrphy_dfi_p3_address[13]),
-       .D8(soc_a7ddrphy_dfi_p3_address[13]),
+       .D1(a7ddrphy_dfi_p0_address[13]),
+       .D2(a7ddrphy_dfi_p0_address[13]),
+       .D3(a7ddrphy_dfi_p1_address[13]),
+       .D4(a7ddrphy_dfi_p1_address[13]),
+       .D5(a7ddrphy_dfi_p2_address[13]),
+       .D6(a7ddrphy_dfi_p2_address[13]),
+       .D7(a7ddrphy_dfi_p3_address[13]),
+       .D8(a7ddrphy_dfi_p3_address[13]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[13])
@@ -18060,14 +15109,14 @@ OSERDESE2 #(
 ) OSERDESE2_15 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_bank[0]),
-       .D2(soc_a7ddrphy_dfi_p0_bank[0]),
-       .D3(soc_a7ddrphy_dfi_p1_bank[0]),
-       .D4(soc_a7ddrphy_dfi_p1_bank[0]),
-       .D5(soc_a7ddrphy_dfi_p2_bank[0]),
-       .D6(soc_a7ddrphy_dfi_p2_bank[0]),
-       .D7(soc_a7ddrphy_dfi_p3_bank[0]),
-       .D8(soc_a7ddrphy_dfi_p3_bank[0]),
+       .D1(a7ddrphy_dfi_p0_bank[0]),
+       .D2(a7ddrphy_dfi_p0_bank[0]),
+       .D3(a7ddrphy_dfi_p1_bank[0]),
+       .D4(a7ddrphy_dfi_p1_bank[0]),
+       .D5(a7ddrphy_dfi_p2_bank[0]),
+       .D6(a7ddrphy_dfi_p2_bank[0]),
+       .D7(a7ddrphy_dfi_p3_bank[0]),
+       .D8(a7ddrphy_dfi_p3_bank[0]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_ba[0])
@@ -18082,14 +15131,14 @@ OSERDESE2 #(
 ) OSERDESE2_16 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_bank[1]),
-       .D2(soc_a7ddrphy_dfi_p0_bank[1]),
-       .D3(soc_a7ddrphy_dfi_p1_bank[1]),
-       .D4(soc_a7ddrphy_dfi_p1_bank[1]),
-       .D5(soc_a7ddrphy_dfi_p2_bank[1]),
-       .D6(soc_a7ddrphy_dfi_p2_bank[1]),
-       .D7(soc_a7ddrphy_dfi_p3_bank[1]),
-       .D8(soc_a7ddrphy_dfi_p3_bank[1]),
+       .D1(a7ddrphy_dfi_p0_bank[1]),
+       .D2(a7ddrphy_dfi_p0_bank[1]),
+       .D3(a7ddrphy_dfi_p1_bank[1]),
+       .D4(a7ddrphy_dfi_p1_bank[1]),
+       .D5(a7ddrphy_dfi_p2_bank[1]),
+       .D6(a7ddrphy_dfi_p2_bank[1]),
+       .D7(a7ddrphy_dfi_p3_bank[1]),
+       .D8(a7ddrphy_dfi_p3_bank[1]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_ba[1])
@@ -18104,14 +15153,14 @@ OSERDESE2 #(
 ) OSERDESE2_17 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_bank[2]),
-       .D2(soc_a7ddrphy_dfi_p0_bank[2]),
-       .D3(soc_a7ddrphy_dfi_p1_bank[2]),
-       .D4(soc_a7ddrphy_dfi_p1_bank[2]),
-       .D5(soc_a7ddrphy_dfi_p2_bank[2]),
-       .D6(soc_a7ddrphy_dfi_p2_bank[2]),
-       .D7(soc_a7ddrphy_dfi_p3_bank[2]),
-       .D8(soc_a7ddrphy_dfi_p3_bank[2]),
+       .D1(a7ddrphy_dfi_p0_bank[2]),
+       .D2(a7ddrphy_dfi_p0_bank[2]),
+       .D3(a7ddrphy_dfi_p1_bank[2]),
+       .D4(a7ddrphy_dfi_p1_bank[2]),
+       .D5(a7ddrphy_dfi_p2_bank[2]),
+       .D6(a7ddrphy_dfi_p2_bank[2]),
+       .D7(a7ddrphy_dfi_p3_bank[2]),
+       .D8(a7ddrphy_dfi_p3_bank[2]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_ba[2])
@@ -18126,14 +15175,14 @@ OSERDESE2 #(
 ) OSERDESE2_18 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_ras_n),
-       .D2(soc_a7ddrphy_dfi_p0_ras_n),
-       .D3(soc_a7ddrphy_dfi_p1_ras_n),
-       .D4(soc_a7ddrphy_dfi_p1_ras_n),
-       .D5(soc_a7ddrphy_dfi_p2_ras_n),
-       .D6(soc_a7ddrphy_dfi_p2_ras_n),
-       .D7(soc_a7ddrphy_dfi_p3_ras_n),
-       .D8(soc_a7ddrphy_dfi_p3_ras_n),
+       .D1(a7ddrphy_dfi_p0_ras_n),
+       .D2(a7ddrphy_dfi_p0_ras_n),
+       .D3(a7ddrphy_dfi_p1_ras_n),
+       .D4(a7ddrphy_dfi_p1_ras_n),
+       .D5(a7ddrphy_dfi_p2_ras_n),
+       .D6(a7ddrphy_dfi_p2_ras_n),
+       .D7(a7ddrphy_dfi_p3_ras_n),
+       .D8(a7ddrphy_dfi_p3_ras_n),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_ras_n)
@@ -18148,14 +15197,14 @@ OSERDESE2 #(
 ) OSERDESE2_19 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_cas_n),
-       .D2(soc_a7ddrphy_dfi_p0_cas_n),
-       .D3(soc_a7ddrphy_dfi_p1_cas_n),
-       .D4(soc_a7ddrphy_dfi_p1_cas_n),
-       .D5(soc_a7ddrphy_dfi_p2_cas_n),
-       .D6(soc_a7ddrphy_dfi_p2_cas_n),
-       .D7(soc_a7ddrphy_dfi_p3_cas_n),
-       .D8(soc_a7ddrphy_dfi_p3_cas_n),
+       .D1(a7ddrphy_dfi_p0_cas_n),
+       .D2(a7ddrphy_dfi_p0_cas_n),
+       .D3(a7ddrphy_dfi_p1_cas_n),
+       .D4(a7ddrphy_dfi_p1_cas_n),
+       .D5(a7ddrphy_dfi_p2_cas_n),
+       .D6(a7ddrphy_dfi_p2_cas_n),
+       .D7(a7ddrphy_dfi_p3_cas_n),
+       .D8(a7ddrphy_dfi_p3_cas_n),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_cas_n)
@@ -18170,14 +15219,14 @@ OSERDESE2 #(
 ) OSERDESE2_20 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_we_n),
-       .D2(soc_a7ddrphy_dfi_p0_we_n),
-       .D3(soc_a7ddrphy_dfi_p1_we_n),
-       .D4(soc_a7ddrphy_dfi_p1_we_n),
-       .D5(soc_a7ddrphy_dfi_p2_we_n),
-       .D6(soc_a7ddrphy_dfi_p2_we_n),
-       .D7(soc_a7ddrphy_dfi_p3_we_n),
-       .D8(soc_a7ddrphy_dfi_p3_we_n),
+       .D1(a7ddrphy_dfi_p0_we_n),
+       .D2(a7ddrphy_dfi_p0_we_n),
+       .D3(a7ddrphy_dfi_p1_we_n),
+       .D4(a7ddrphy_dfi_p1_we_n),
+       .D5(a7ddrphy_dfi_p2_we_n),
+       .D6(a7ddrphy_dfi_p2_we_n),
+       .D7(a7ddrphy_dfi_p3_we_n),
+       .D8(a7ddrphy_dfi_p3_we_n),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_we_n)
@@ -18192,14 +15241,14 @@ OSERDESE2 #(
 ) OSERDESE2_21 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_cke),
-       .D2(soc_a7ddrphy_dfi_p0_cke),
-       .D3(soc_a7ddrphy_dfi_p1_cke),
-       .D4(soc_a7ddrphy_dfi_p1_cke),
-       .D5(soc_a7ddrphy_dfi_p2_cke),
-       .D6(soc_a7ddrphy_dfi_p2_cke),
-       .D7(soc_a7ddrphy_dfi_p3_cke),
-       .D8(soc_a7ddrphy_dfi_p3_cke),
+       .D1(a7ddrphy_dfi_p0_cke),
+       .D2(a7ddrphy_dfi_p0_cke),
+       .D3(a7ddrphy_dfi_p1_cke),
+       .D4(a7ddrphy_dfi_p1_cke),
+       .D5(a7ddrphy_dfi_p2_cke),
+       .D6(a7ddrphy_dfi_p2_cke),
+       .D7(a7ddrphy_dfi_p3_cke),
+       .D8(a7ddrphy_dfi_p3_cke),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_cke)
@@ -18214,14 +15263,14 @@ OSERDESE2 #(
 ) OSERDESE2_22 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_odt),
-       .D2(soc_a7ddrphy_dfi_p0_odt),
-       .D3(soc_a7ddrphy_dfi_p1_odt),
-       .D4(soc_a7ddrphy_dfi_p1_odt),
-       .D5(soc_a7ddrphy_dfi_p2_odt),
-       .D6(soc_a7ddrphy_dfi_p2_odt),
-       .D7(soc_a7ddrphy_dfi_p3_odt),
-       .D8(soc_a7ddrphy_dfi_p3_odt),
+       .D1(a7ddrphy_dfi_p0_odt),
+       .D2(a7ddrphy_dfi_p0_odt),
+       .D3(a7ddrphy_dfi_p1_odt),
+       .D4(a7ddrphy_dfi_p1_odt),
+       .D5(a7ddrphy_dfi_p2_odt),
+       .D6(a7ddrphy_dfi_p2_odt),
+       .D7(a7ddrphy_dfi_p3_odt),
+       .D8(a7ddrphy_dfi_p3_odt),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_odt)
@@ -18236,14 +15285,14 @@ OSERDESE2 #(
 ) OSERDESE2_23 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_reset_n),
-       .D2(soc_a7ddrphy_dfi_p0_reset_n),
-       .D3(soc_a7ddrphy_dfi_p1_reset_n),
-       .D4(soc_a7ddrphy_dfi_p1_reset_n),
-       .D5(soc_a7ddrphy_dfi_p2_reset_n),
-       .D6(soc_a7ddrphy_dfi_p2_reset_n),
-       .D7(soc_a7ddrphy_dfi_p3_reset_n),
-       .D8(soc_a7ddrphy_dfi_p3_reset_n),
+       .D1(a7ddrphy_dfi_p0_reset_n),
+       .D2(a7ddrphy_dfi_p0_reset_n),
+       .D3(a7ddrphy_dfi_p1_reset_n),
+       .D4(a7ddrphy_dfi_p1_reset_n),
+       .D5(a7ddrphy_dfi_p2_reset_n),
+       .D6(a7ddrphy_dfi_p2_reset_n),
+       .D7(a7ddrphy_dfi_p3_reset_n),
+       .D8(a7ddrphy_dfi_p3_reset_n),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_reset_n)
@@ -18258,14 +15307,14 @@ OSERDESE2 #(
 ) OSERDESE2_24 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_cs_n),
-       .D2(soc_a7ddrphy_dfi_p0_cs_n),
-       .D3(soc_a7ddrphy_dfi_p1_cs_n),
-       .D4(soc_a7ddrphy_dfi_p1_cs_n),
-       .D5(soc_a7ddrphy_dfi_p2_cs_n),
-       .D6(soc_a7ddrphy_dfi_p2_cs_n),
-       .D7(soc_a7ddrphy_dfi_p3_cs_n),
-       .D8(soc_a7ddrphy_dfi_p3_cs_n),
+       .D1(a7ddrphy_dfi_p0_cs_n),
+       .D2(a7ddrphy_dfi_p0_cs_n),
+       .D3(a7ddrphy_dfi_p1_cs_n),
+       .D4(a7ddrphy_dfi_p1_cs_n),
+       .D5(a7ddrphy_dfi_p2_cs_n),
+       .D6(a7ddrphy_dfi_p2_cs_n),
+       .D7(a7ddrphy_dfi_p3_cs_n),
+       .D8(a7ddrphy_dfi_p3_cs_n),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_cs_n)
@@ -18280,14 +15329,14 @@ OSERDESE2 #(
 ) OSERDESE2_25 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]),
+       .D1(a7ddrphy_dfi_p0_wrdata_mask[0]),
+       .D2(a7ddrphy_dfi_p0_wrdata_mask[2]),
+       .D3(a7ddrphy_dfi_p1_wrdata_mask[0]),
+       .D4(a7ddrphy_dfi_p1_wrdata_mask[2]),
+       .D5(a7ddrphy_dfi_p2_wrdata_mask[0]),
+       .D6(a7ddrphy_dfi_p2_wrdata_mask[2]),
+       .D7(a7ddrphy_dfi_p3_wrdata_mask[0]),
+       .D8(a7ddrphy_dfi_p3_wrdata_mask[2]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_dm[0])
@@ -18302,14 +15351,14 @@ OSERDESE2 #(
 ) OSERDESE2_26 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]),
+       .D1(a7ddrphy_dfi_p0_wrdata_mask[1]),
+       .D2(a7ddrphy_dfi_p0_wrdata_mask[3]),
+       .D3(a7ddrphy_dfi_p1_wrdata_mask[1]),
+       .D4(a7ddrphy_dfi_p1_wrdata_mask[3]),
+       .D5(a7ddrphy_dfi_p2_wrdata_mask[1]),
+       .D6(a7ddrphy_dfi_p2_wrdata_mask[3]),
+       .D7(a7ddrphy_dfi_p3_wrdata_mask[1]),
+       .D8(a7ddrphy_dfi_p3_wrdata_mask[3]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_dm[1])
@@ -18324,21 +15373,21 @@ OSERDESE2 #(
 ) OSERDESE2_27 (
        .CLK(sys4x_dqs_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dqspattern_o1[0]),
-       .D2(soc_a7ddrphy_dqspattern_o1[1]),
-       .D3(soc_a7ddrphy_dqspattern_o1[2]),
-       .D4(soc_a7ddrphy_dqspattern_o1[3]),
-       .D5(soc_a7ddrphy_dqspattern_o1[4]),
-       .D6(soc_a7ddrphy_dqspattern_o1[5]),
-       .D7(soc_a7ddrphy_dqspattern_o1[6]),
-       .D8(soc_a7ddrphy_dqspattern_o1[7]),
+       .D1(a7ddrphy_dqspattern_o1[0]),
+       .D2(a7ddrphy_dqspattern_o1[1]),
+       .D3(a7ddrphy_dqspattern_o1[2]),
+       .D4(a7ddrphy_dqspattern_o1[3]),
+       .D5(a7ddrphy_dqspattern_o1[4]),
+       .D6(a7ddrphy_dqspattern_o1[5]),
+       .D7(a7ddrphy_dqspattern_o1[6]),
+       .D8(a7ddrphy_dqspattern_o1[7]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dqs_oe_delayed)),
+       .T1((~a7ddrphy_dqs_oe_delayed)),
        .TCE(1'd1),
-       .OFB(soc_a7ddrphy0),
-       .OQ(soc_a7ddrphy_dqs_o_no_delay0),
-       .TQ(soc_a7ddrphy_dqs_t0)
+       .OFB(a7ddrphy0),
+       .OQ(a7ddrphy_dqs_o_no_delay0),
+       .TQ(a7ddrphy_dqs_t0)
 );
 
 IDELAYE2 #(
@@ -18351,16 +15400,16 @@ IDELAYE2 #(
        .REFCLK_FREQUENCY(200.0),
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2 (
-       .IDATAIN(soc_a7ddrphy_dqs_i[0]),
-       .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0])
+       .IDATAIN(a7ddrphy_dqs_i[0]),
+       .DATAOUT(a7ddrphy_dqs_i_delayed[0])
 );
 
 IOBUFDS IOBUFDS(
-       .I(soc_a7ddrphy_dqs_o_no_delay0),
-       .T(soc_a7ddrphy_dqs_t0),
+       .I(a7ddrphy_dqs_o_no_delay0),
+       .T(a7ddrphy_dqs_t0),
        .IO(ddram_dqs_p[0]),
        .IOB(ddram_dqs_n[0]),
-       .O(soc_a7ddrphy_dqs_i[0])
+       .O(a7ddrphy_dqs_i[0])
 );
 
 OSERDESE2 #(
@@ -18372,21 +15421,21 @@ OSERDESE2 #(
 ) OSERDESE2_28 (
        .CLK(sys4x_dqs_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dqspattern_o1[0]),
-       .D2(soc_a7ddrphy_dqspattern_o1[1]),
-       .D3(soc_a7ddrphy_dqspattern_o1[2]),
-       .D4(soc_a7ddrphy_dqspattern_o1[3]),
-       .D5(soc_a7ddrphy_dqspattern_o1[4]),
-       .D6(soc_a7ddrphy_dqspattern_o1[5]),
-       .D7(soc_a7ddrphy_dqspattern_o1[6]),
-       .D8(soc_a7ddrphy_dqspattern_o1[7]),
+       .D1(a7ddrphy_dqspattern_o1[0]),
+       .D2(a7ddrphy_dqspattern_o1[1]),
+       .D3(a7ddrphy_dqspattern_o1[2]),
+       .D4(a7ddrphy_dqspattern_o1[3]),
+       .D5(a7ddrphy_dqspattern_o1[4]),
+       .D6(a7ddrphy_dqspattern_o1[5]),
+       .D7(a7ddrphy_dqspattern_o1[6]),
+       .D8(a7ddrphy_dqspattern_o1[7]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dqs_oe_delayed)),
+       .T1((~a7ddrphy_dqs_oe_delayed)),
        .TCE(1'd1),
-       .OFB(soc_a7ddrphy1),
-       .OQ(soc_a7ddrphy_dqs_o_no_delay1),
-       .TQ(soc_a7ddrphy_dqs_t1)
+       .OFB(a7ddrphy1),
+       .OQ(a7ddrphy_dqs_o_no_delay1),
+       .TQ(a7ddrphy_dqs_t1)
 );
 
 IDELAYE2 #(
@@ -18399,16 +15448,16 @@ IDELAYE2 #(
        .REFCLK_FREQUENCY(200.0),
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_1 (
-       .IDATAIN(soc_a7ddrphy_dqs_i[1]),
-       .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1])
+       .IDATAIN(a7ddrphy_dqs_i[1]),
+       .DATAOUT(a7ddrphy_dqs_i_delayed[1])
 );
 
 IOBUFDS IOBUFDS_1(
-       .I(soc_a7ddrphy_dqs_o_no_delay1),
-       .T(soc_a7ddrphy_dqs_t1),
+       .I(a7ddrphy_dqs_o_no_delay1),
+       .T(a7ddrphy_dqs_t1),
        .IO(ddram_dqs_p[1]),
        .IOB(ddram_dqs_n[1]),
-       .O(soc_a7ddrphy_dqs_i[1])
+       .O(a7ddrphy_dqs_i[1])
 );
 
 OSERDESE2 #(
@@ -18420,20 +15469,20 @@ OSERDESE2 #(
 ) OSERDESE2_29 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[0]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[16]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[0]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[16]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[0]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[16]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[0]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[16]),
+       .D1(a7ddrphy_dfi_p0_wrdata[0]),
+       .D2(a7ddrphy_dfi_p0_wrdata[16]),
+       .D3(a7ddrphy_dfi_p1_wrdata[0]),
+       .D4(a7ddrphy_dfi_p1_wrdata[16]),
+       .D5(a7ddrphy_dfi_p2_wrdata[0]),
+       .D6(a7ddrphy_dfi_p2_wrdata[16]),
+       .D7(a7ddrphy_dfi_p3_wrdata[0]),
+       .D8(a7ddrphy_dfi_p3_wrdata[16]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay0),
-       .TQ(soc_a7ddrphy_dq_t0)
+       .OQ(a7ddrphy_dq_o_nodelay0),
+       .TQ(a7ddrphy_dq_t0)
 );
 
 ISERDESE2 #(
@@ -18449,16 +15498,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed0),
+       .DDLY(a7ddrphy_dq_i_delayed0),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data0[7]),
-       .Q2(soc_a7ddrphy_dq_i_data0[6]),
-       .Q3(soc_a7ddrphy_dq_i_data0[5]),
-       .Q4(soc_a7ddrphy_dq_i_data0[4]),
-       .Q5(soc_a7ddrphy_dq_i_data0[3]),
-       .Q6(soc_a7ddrphy_dq_i_data0[2]),
-       .Q7(soc_a7ddrphy_dq_i_data0[1]),
-       .Q8(soc_a7ddrphy_dq_i_data0[0])
+       .Q1(a7ddrphy_dq_i_data0[7]),
+       .Q2(a7ddrphy_dq_i_data0[6]),
+       .Q3(a7ddrphy_dq_i_data0[5]),
+       .Q4(a7ddrphy_dq_i_data0[4]),
+       .Q5(a7ddrphy_dq_i_data0[3]),
+       .Q6(a7ddrphy_dq_i_data0[2]),
+       .Q7(a7ddrphy_dq_i_data0[1]),
+       .Q8(a7ddrphy_dq_i_data0[0])
 );
 
 IDELAYE2 #(
@@ -18472,19 +15521,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_2 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay0),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay0),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed0)
+       .DATAOUT(a7ddrphy_dq_i_delayed0)
 );
 
 IOBUF IOBUF(
-       .I(soc_a7ddrphy_dq_o_nodelay0),
-       .T(soc_a7ddrphy_dq_t0),
+       .I(a7ddrphy_dq_o_nodelay0),
+       .T(a7ddrphy_dq_t0),
        .IO(ddram_dq[0]),
-       .O(soc_a7ddrphy_dq_i_nodelay0)
+       .O(a7ddrphy_dq_i_nodelay0)
 );
 
 OSERDESE2 #(
@@ -18496,20 +15545,20 @@ OSERDESE2 #(
 ) OSERDESE2_30 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[1]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[17]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[1]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[17]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[1]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[17]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[1]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[17]),
+       .D1(a7ddrphy_dfi_p0_wrdata[1]),
+       .D2(a7ddrphy_dfi_p0_wrdata[17]),
+       .D3(a7ddrphy_dfi_p1_wrdata[1]),
+       .D4(a7ddrphy_dfi_p1_wrdata[17]),
+       .D5(a7ddrphy_dfi_p2_wrdata[1]),
+       .D6(a7ddrphy_dfi_p2_wrdata[17]),
+       .D7(a7ddrphy_dfi_p3_wrdata[1]),
+       .D8(a7ddrphy_dfi_p3_wrdata[17]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay1),
-       .TQ(soc_a7ddrphy_dq_t1)
+       .OQ(a7ddrphy_dq_o_nodelay1),
+       .TQ(a7ddrphy_dq_t1)
 );
 
 ISERDESE2 #(
@@ -18525,16 +15574,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed1),
+       .DDLY(a7ddrphy_dq_i_delayed1),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data1[7]),
-       .Q2(soc_a7ddrphy_dq_i_data1[6]),
-       .Q3(soc_a7ddrphy_dq_i_data1[5]),
-       .Q4(soc_a7ddrphy_dq_i_data1[4]),
-       .Q5(soc_a7ddrphy_dq_i_data1[3]),
-       .Q6(soc_a7ddrphy_dq_i_data1[2]),
-       .Q7(soc_a7ddrphy_dq_i_data1[1]),
-       .Q8(soc_a7ddrphy_dq_i_data1[0])
+       .Q1(a7ddrphy_dq_i_data1[7]),
+       .Q2(a7ddrphy_dq_i_data1[6]),
+       .Q3(a7ddrphy_dq_i_data1[5]),
+       .Q4(a7ddrphy_dq_i_data1[4]),
+       .Q5(a7ddrphy_dq_i_data1[3]),
+       .Q6(a7ddrphy_dq_i_data1[2]),
+       .Q7(a7ddrphy_dq_i_data1[1]),
+       .Q8(a7ddrphy_dq_i_data1[0])
 );
 
 IDELAYE2 #(
@@ -18548,19 +15597,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_3 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay1),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay1),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed1)
+       .DATAOUT(a7ddrphy_dq_i_delayed1)
 );
 
 IOBUF IOBUF_1(
-       .I(soc_a7ddrphy_dq_o_nodelay1),
-       .T(soc_a7ddrphy_dq_t1),
+       .I(a7ddrphy_dq_o_nodelay1),
+       .T(a7ddrphy_dq_t1),
        .IO(ddram_dq[1]),
-       .O(soc_a7ddrphy_dq_i_nodelay1)
+       .O(a7ddrphy_dq_i_nodelay1)
 );
 
 OSERDESE2 #(
@@ -18572,20 +15621,20 @@ OSERDESE2 #(
 ) OSERDESE2_31 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[2]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[18]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[2]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[18]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[2]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[18]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[2]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[18]),
+       .D1(a7ddrphy_dfi_p0_wrdata[2]),
+       .D2(a7ddrphy_dfi_p0_wrdata[18]),
+       .D3(a7ddrphy_dfi_p1_wrdata[2]),
+       .D4(a7ddrphy_dfi_p1_wrdata[18]),
+       .D5(a7ddrphy_dfi_p2_wrdata[2]),
+       .D6(a7ddrphy_dfi_p2_wrdata[18]),
+       .D7(a7ddrphy_dfi_p3_wrdata[2]),
+       .D8(a7ddrphy_dfi_p3_wrdata[18]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay2),
-       .TQ(soc_a7ddrphy_dq_t2)
+       .OQ(a7ddrphy_dq_o_nodelay2),
+       .TQ(a7ddrphy_dq_t2)
 );
 
 ISERDESE2 #(
@@ -18601,16 +15650,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed2),
+       .DDLY(a7ddrphy_dq_i_delayed2),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data2[7]),
-       .Q2(soc_a7ddrphy_dq_i_data2[6]),
-       .Q3(soc_a7ddrphy_dq_i_data2[5]),
-       .Q4(soc_a7ddrphy_dq_i_data2[4]),
-       .Q5(soc_a7ddrphy_dq_i_data2[3]),
-       .Q6(soc_a7ddrphy_dq_i_data2[2]),
-       .Q7(soc_a7ddrphy_dq_i_data2[1]),
-       .Q8(soc_a7ddrphy_dq_i_data2[0])
+       .Q1(a7ddrphy_dq_i_data2[7]),
+       .Q2(a7ddrphy_dq_i_data2[6]),
+       .Q3(a7ddrphy_dq_i_data2[5]),
+       .Q4(a7ddrphy_dq_i_data2[4]),
+       .Q5(a7ddrphy_dq_i_data2[3]),
+       .Q6(a7ddrphy_dq_i_data2[2]),
+       .Q7(a7ddrphy_dq_i_data2[1]),
+       .Q8(a7ddrphy_dq_i_data2[0])
 );
 
 IDELAYE2 #(
@@ -18624,19 +15673,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_4 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay2),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay2),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed2)
+       .DATAOUT(a7ddrphy_dq_i_delayed2)
 );
 
 IOBUF IOBUF_2(
-       .I(soc_a7ddrphy_dq_o_nodelay2),
-       .T(soc_a7ddrphy_dq_t2),
+       .I(a7ddrphy_dq_o_nodelay2),
+       .T(a7ddrphy_dq_t2),
        .IO(ddram_dq[2]),
-       .O(soc_a7ddrphy_dq_i_nodelay2)
+       .O(a7ddrphy_dq_i_nodelay2)
 );
 
 OSERDESE2 #(
@@ -18648,20 +15697,20 @@ OSERDESE2 #(
 ) OSERDESE2_32 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[3]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[19]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[3]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[19]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[3]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[19]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[3]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[19]),
+       .D1(a7ddrphy_dfi_p0_wrdata[3]),
+       .D2(a7ddrphy_dfi_p0_wrdata[19]),
+       .D3(a7ddrphy_dfi_p1_wrdata[3]),
+       .D4(a7ddrphy_dfi_p1_wrdata[19]),
+       .D5(a7ddrphy_dfi_p2_wrdata[3]),
+       .D6(a7ddrphy_dfi_p2_wrdata[19]),
+       .D7(a7ddrphy_dfi_p3_wrdata[3]),
+       .D8(a7ddrphy_dfi_p3_wrdata[19]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay3),
-       .TQ(soc_a7ddrphy_dq_t3)
+       .OQ(a7ddrphy_dq_o_nodelay3),
+       .TQ(a7ddrphy_dq_t3)
 );
 
 ISERDESE2 #(
@@ -18677,16 +15726,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed3),
+       .DDLY(a7ddrphy_dq_i_delayed3),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data3[7]),
-       .Q2(soc_a7ddrphy_dq_i_data3[6]),
-       .Q3(soc_a7ddrphy_dq_i_data3[5]),
-       .Q4(soc_a7ddrphy_dq_i_data3[4]),
-       .Q5(soc_a7ddrphy_dq_i_data3[3]),
-       .Q6(soc_a7ddrphy_dq_i_data3[2]),
-       .Q7(soc_a7ddrphy_dq_i_data3[1]),
-       .Q8(soc_a7ddrphy_dq_i_data3[0])
+       .Q1(a7ddrphy_dq_i_data3[7]),
+       .Q2(a7ddrphy_dq_i_data3[6]),
+       .Q3(a7ddrphy_dq_i_data3[5]),
+       .Q4(a7ddrphy_dq_i_data3[4]),
+       .Q5(a7ddrphy_dq_i_data3[3]),
+       .Q6(a7ddrphy_dq_i_data3[2]),
+       .Q7(a7ddrphy_dq_i_data3[1]),
+       .Q8(a7ddrphy_dq_i_data3[0])
 );
 
 IDELAYE2 #(
@@ -18700,19 +15749,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_5 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay3),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay3),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed3)
+       .DATAOUT(a7ddrphy_dq_i_delayed3)
 );
 
 IOBUF IOBUF_3(
-       .I(soc_a7ddrphy_dq_o_nodelay3),
-       .T(soc_a7ddrphy_dq_t3),
+       .I(a7ddrphy_dq_o_nodelay3),
+       .T(a7ddrphy_dq_t3),
        .IO(ddram_dq[3]),
-       .O(soc_a7ddrphy_dq_i_nodelay3)
+       .O(a7ddrphy_dq_i_nodelay3)
 );
 
 OSERDESE2 #(
@@ -18724,20 +15773,20 @@ OSERDESE2 #(
 ) OSERDESE2_33 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[4]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[20]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[4]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[20]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[4]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[20]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[4]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[20]),
+       .D1(a7ddrphy_dfi_p0_wrdata[4]),
+       .D2(a7ddrphy_dfi_p0_wrdata[20]),
+       .D3(a7ddrphy_dfi_p1_wrdata[4]),
+       .D4(a7ddrphy_dfi_p1_wrdata[20]),
+       .D5(a7ddrphy_dfi_p2_wrdata[4]),
+       .D6(a7ddrphy_dfi_p2_wrdata[20]),
+       .D7(a7ddrphy_dfi_p3_wrdata[4]),
+       .D8(a7ddrphy_dfi_p3_wrdata[20]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay4),
-       .TQ(soc_a7ddrphy_dq_t4)
+       .OQ(a7ddrphy_dq_o_nodelay4),
+       .TQ(a7ddrphy_dq_t4)
 );
 
 ISERDESE2 #(
@@ -18753,16 +15802,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed4),
+       .DDLY(a7ddrphy_dq_i_delayed4),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data4[7]),
-       .Q2(soc_a7ddrphy_dq_i_data4[6]),
-       .Q3(soc_a7ddrphy_dq_i_data4[5]),
-       .Q4(soc_a7ddrphy_dq_i_data4[4]),
-       .Q5(soc_a7ddrphy_dq_i_data4[3]),
-       .Q6(soc_a7ddrphy_dq_i_data4[2]),
-       .Q7(soc_a7ddrphy_dq_i_data4[1]),
-       .Q8(soc_a7ddrphy_dq_i_data4[0])
+       .Q1(a7ddrphy_dq_i_data4[7]),
+       .Q2(a7ddrphy_dq_i_data4[6]),
+       .Q3(a7ddrphy_dq_i_data4[5]),
+       .Q4(a7ddrphy_dq_i_data4[4]),
+       .Q5(a7ddrphy_dq_i_data4[3]),
+       .Q6(a7ddrphy_dq_i_data4[2]),
+       .Q7(a7ddrphy_dq_i_data4[1]),
+       .Q8(a7ddrphy_dq_i_data4[0])
 );
 
 IDELAYE2 #(
@@ -18776,19 +15825,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_6 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay4),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay4),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed4)
+       .DATAOUT(a7ddrphy_dq_i_delayed4)
 );
 
 IOBUF IOBUF_4(
-       .I(soc_a7ddrphy_dq_o_nodelay4),
-       .T(soc_a7ddrphy_dq_t4),
+       .I(a7ddrphy_dq_o_nodelay4),
+       .T(a7ddrphy_dq_t4),
        .IO(ddram_dq[4]),
-       .O(soc_a7ddrphy_dq_i_nodelay4)
+       .O(a7ddrphy_dq_i_nodelay4)
 );
 
 OSERDESE2 #(
@@ -18800,20 +15849,20 @@ OSERDESE2 #(
 ) OSERDESE2_34 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[5]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[21]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[5]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[21]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[5]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[21]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[5]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[21]),
+       .D1(a7ddrphy_dfi_p0_wrdata[5]),
+       .D2(a7ddrphy_dfi_p0_wrdata[21]),
+       .D3(a7ddrphy_dfi_p1_wrdata[5]),
+       .D4(a7ddrphy_dfi_p1_wrdata[21]),
+       .D5(a7ddrphy_dfi_p2_wrdata[5]),
+       .D6(a7ddrphy_dfi_p2_wrdata[21]),
+       .D7(a7ddrphy_dfi_p3_wrdata[5]),
+       .D8(a7ddrphy_dfi_p3_wrdata[21]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay5),
-       .TQ(soc_a7ddrphy_dq_t5)
+       .OQ(a7ddrphy_dq_o_nodelay5),
+       .TQ(a7ddrphy_dq_t5)
 );
 
 ISERDESE2 #(
@@ -18829,16 +15878,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed5),
+       .DDLY(a7ddrphy_dq_i_delayed5),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data5[7]),
-       .Q2(soc_a7ddrphy_dq_i_data5[6]),
-       .Q3(soc_a7ddrphy_dq_i_data5[5]),
-       .Q4(soc_a7ddrphy_dq_i_data5[4]),
-       .Q5(soc_a7ddrphy_dq_i_data5[3]),
-       .Q6(soc_a7ddrphy_dq_i_data5[2]),
-       .Q7(soc_a7ddrphy_dq_i_data5[1]),
-       .Q8(soc_a7ddrphy_dq_i_data5[0])
+       .Q1(a7ddrphy_dq_i_data5[7]),
+       .Q2(a7ddrphy_dq_i_data5[6]),
+       .Q3(a7ddrphy_dq_i_data5[5]),
+       .Q4(a7ddrphy_dq_i_data5[4]),
+       .Q5(a7ddrphy_dq_i_data5[3]),
+       .Q6(a7ddrphy_dq_i_data5[2]),
+       .Q7(a7ddrphy_dq_i_data5[1]),
+       .Q8(a7ddrphy_dq_i_data5[0])
 );
 
 IDELAYE2 #(
@@ -18852,19 +15901,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_7 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay5),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay5),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed5)
+       .DATAOUT(a7ddrphy_dq_i_delayed5)
 );
 
 IOBUF IOBUF_5(
-       .I(soc_a7ddrphy_dq_o_nodelay5),
-       .T(soc_a7ddrphy_dq_t5),
+       .I(a7ddrphy_dq_o_nodelay5),
+       .T(a7ddrphy_dq_t5),
        .IO(ddram_dq[5]),
-       .O(soc_a7ddrphy_dq_i_nodelay5)
+       .O(a7ddrphy_dq_i_nodelay5)
 );
 
 OSERDESE2 #(
@@ -18876,20 +15925,20 @@ OSERDESE2 #(
 ) OSERDESE2_35 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[6]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[22]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[6]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[22]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[6]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[22]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[6]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[22]),
+       .D1(a7ddrphy_dfi_p0_wrdata[6]),
+       .D2(a7ddrphy_dfi_p0_wrdata[22]),
+       .D3(a7ddrphy_dfi_p1_wrdata[6]),
+       .D4(a7ddrphy_dfi_p1_wrdata[22]),
+       .D5(a7ddrphy_dfi_p2_wrdata[6]),
+       .D6(a7ddrphy_dfi_p2_wrdata[22]),
+       .D7(a7ddrphy_dfi_p3_wrdata[6]),
+       .D8(a7ddrphy_dfi_p3_wrdata[22]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay6),
-       .TQ(soc_a7ddrphy_dq_t6)
+       .OQ(a7ddrphy_dq_o_nodelay6),
+       .TQ(a7ddrphy_dq_t6)
 );
 
 ISERDESE2 #(
@@ -18905,16 +15954,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed6),
+       .DDLY(a7ddrphy_dq_i_delayed6),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data6[7]),
-       .Q2(soc_a7ddrphy_dq_i_data6[6]),
-       .Q3(soc_a7ddrphy_dq_i_data6[5]),
-       .Q4(soc_a7ddrphy_dq_i_data6[4]),
-       .Q5(soc_a7ddrphy_dq_i_data6[3]),
-       .Q6(soc_a7ddrphy_dq_i_data6[2]),
-       .Q7(soc_a7ddrphy_dq_i_data6[1]),
-       .Q8(soc_a7ddrphy_dq_i_data6[0])
+       .Q1(a7ddrphy_dq_i_data6[7]),
+       .Q2(a7ddrphy_dq_i_data6[6]),
+       .Q3(a7ddrphy_dq_i_data6[5]),
+       .Q4(a7ddrphy_dq_i_data6[4]),
+       .Q5(a7ddrphy_dq_i_data6[3]),
+       .Q6(a7ddrphy_dq_i_data6[2]),
+       .Q7(a7ddrphy_dq_i_data6[1]),
+       .Q8(a7ddrphy_dq_i_data6[0])
 );
 
 IDELAYE2 #(
@@ -18928,19 +15977,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_8 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay6),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay6),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed6)
+       .DATAOUT(a7ddrphy_dq_i_delayed6)
 );
 
 IOBUF IOBUF_6(
-       .I(soc_a7ddrphy_dq_o_nodelay6),
-       .T(soc_a7ddrphy_dq_t6),
+       .I(a7ddrphy_dq_o_nodelay6),
+       .T(a7ddrphy_dq_t6),
        .IO(ddram_dq[6]),
-       .O(soc_a7ddrphy_dq_i_nodelay6)
+       .O(a7ddrphy_dq_i_nodelay6)
 );
 
 OSERDESE2 #(
@@ -18952,20 +16001,20 @@ OSERDESE2 #(
 ) OSERDESE2_36 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[7]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[23]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[7]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[23]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[7]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[23]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[7]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[23]),
+       .D1(a7ddrphy_dfi_p0_wrdata[7]),
+       .D2(a7ddrphy_dfi_p0_wrdata[23]),
+       .D3(a7ddrphy_dfi_p1_wrdata[7]),
+       .D4(a7ddrphy_dfi_p1_wrdata[23]),
+       .D5(a7ddrphy_dfi_p2_wrdata[7]),
+       .D6(a7ddrphy_dfi_p2_wrdata[23]),
+       .D7(a7ddrphy_dfi_p3_wrdata[7]),
+       .D8(a7ddrphy_dfi_p3_wrdata[23]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay7),
-       .TQ(soc_a7ddrphy_dq_t7)
+       .OQ(a7ddrphy_dq_o_nodelay7),
+       .TQ(a7ddrphy_dq_t7)
 );
 
 ISERDESE2 #(
@@ -18981,16 +16030,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed7),
+       .DDLY(a7ddrphy_dq_i_delayed7),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data7[7]),
-       .Q2(soc_a7ddrphy_dq_i_data7[6]),
-       .Q3(soc_a7ddrphy_dq_i_data7[5]),
-       .Q4(soc_a7ddrphy_dq_i_data7[4]),
-       .Q5(soc_a7ddrphy_dq_i_data7[3]),
-       .Q6(soc_a7ddrphy_dq_i_data7[2]),
-       .Q7(soc_a7ddrphy_dq_i_data7[1]),
-       .Q8(soc_a7ddrphy_dq_i_data7[0])
+       .Q1(a7ddrphy_dq_i_data7[7]),
+       .Q2(a7ddrphy_dq_i_data7[6]),
+       .Q3(a7ddrphy_dq_i_data7[5]),
+       .Q4(a7ddrphy_dq_i_data7[4]),
+       .Q5(a7ddrphy_dq_i_data7[3]),
+       .Q6(a7ddrphy_dq_i_data7[2]),
+       .Q7(a7ddrphy_dq_i_data7[1]),
+       .Q8(a7ddrphy_dq_i_data7[0])
 );
 
 IDELAYE2 #(
@@ -19004,19 +16053,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_9 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay7),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay7),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed7)
+       .DATAOUT(a7ddrphy_dq_i_delayed7)
 );
 
 IOBUF IOBUF_7(
-       .I(soc_a7ddrphy_dq_o_nodelay7),
-       .T(soc_a7ddrphy_dq_t7),
+       .I(a7ddrphy_dq_o_nodelay7),
+       .T(a7ddrphy_dq_t7),
        .IO(ddram_dq[7]),
-       .O(soc_a7ddrphy_dq_i_nodelay7)
+       .O(a7ddrphy_dq_i_nodelay7)
 );
 
 OSERDESE2 #(
@@ -19028,20 +16077,20 @@ OSERDESE2 #(
 ) OSERDESE2_37 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[8]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[24]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[8]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[24]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[8]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[24]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[8]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[24]),
+       .D1(a7ddrphy_dfi_p0_wrdata[8]),
+       .D2(a7ddrphy_dfi_p0_wrdata[24]),
+       .D3(a7ddrphy_dfi_p1_wrdata[8]),
+       .D4(a7ddrphy_dfi_p1_wrdata[24]),
+       .D5(a7ddrphy_dfi_p2_wrdata[8]),
+       .D6(a7ddrphy_dfi_p2_wrdata[24]),
+       .D7(a7ddrphy_dfi_p3_wrdata[8]),
+       .D8(a7ddrphy_dfi_p3_wrdata[24]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay8),
-       .TQ(soc_a7ddrphy_dq_t8)
+       .OQ(a7ddrphy_dq_o_nodelay8),
+       .TQ(a7ddrphy_dq_t8)
 );
 
 ISERDESE2 #(
@@ -19057,16 +16106,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed8),
+       .DDLY(a7ddrphy_dq_i_delayed8),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data8[7]),
-       .Q2(soc_a7ddrphy_dq_i_data8[6]),
-       .Q3(soc_a7ddrphy_dq_i_data8[5]),
-       .Q4(soc_a7ddrphy_dq_i_data8[4]),
-       .Q5(soc_a7ddrphy_dq_i_data8[3]),
-       .Q6(soc_a7ddrphy_dq_i_data8[2]),
-       .Q7(soc_a7ddrphy_dq_i_data8[1]),
-       .Q8(soc_a7ddrphy_dq_i_data8[0])
+       .Q1(a7ddrphy_dq_i_data8[7]),
+       .Q2(a7ddrphy_dq_i_data8[6]),
+       .Q3(a7ddrphy_dq_i_data8[5]),
+       .Q4(a7ddrphy_dq_i_data8[4]),
+       .Q5(a7ddrphy_dq_i_data8[3]),
+       .Q6(a7ddrphy_dq_i_data8[2]),
+       .Q7(a7ddrphy_dq_i_data8[1]),
+       .Q8(a7ddrphy_dq_i_data8[0])
 );
 
 IDELAYE2 #(
@@ -19080,19 +16129,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_10 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay8),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay8),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed8)
+       .DATAOUT(a7ddrphy_dq_i_delayed8)
 );
 
 IOBUF IOBUF_8(
-       .I(soc_a7ddrphy_dq_o_nodelay8),
-       .T(soc_a7ddrphy_dq_t8),
+       .I(a7ddrphy_dq_o_nodelay8),
+       .T(a7ddrphy_dq_t8),
        .IO(ddram_dq[8]),
-       .O(soc_a7ddrphy_dq_i_nodelay8)
+       .O(a7ddrphy_dq_i_nodelay8)
 );
 
 OSERDESE2 #(
@@ -19104,20 +16153,20 @@ OSERDESE2 #(
 ) OSERDESE2_38 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[9]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[25]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[9]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[25]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[9]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[25]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[9]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[25]),
+       .D1(a7ddrphy_dfi_p0_wrdata[9]),
+       .D2(a7ddrphy_dfi_p0_wrdata[25]),
+       .D3(a7ddrphy_dfi_p1_wrdata[9]),
+       .D4(a7ddrphy_dfi_p1_wrdata[25]),
+       .D5(a7ddrphy_dfi_p2_wrdata[9]),
+       .D6(a7ddrphy_dfi_p2_wrdata[25]),
+       .D7(a7ddrphy_dfi_p3_wrdata[9]),
+       .D8(a7ddrphy_dfi_p3_wrdata[25]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay9),
-       .TQ(soc_a7ddrphy_dq_t9)
+       .OQ(a7ddrphy_dq_o_nodelay9),
+       .TQ(a7ddrphy_dq_t9)
 );
 
 ISERDESE2 #(
@@ -19133,16 +16182,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed9),
+       .DDLY(a7ddrphy_dq_i_delayed9),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data9[7]),
-       .Q2(soc_a7ddrphy_dq_i_data9[6]),
-       .Q3(soc_a7ddrphy_dq_i_data9[5]),
-       .Q4(soc_a7ddrphy_dq_i_data9[4]),
-       .Q5(soc_a7ddrphy_dq_i_data9[3]),
-       .Q6(soc_a7ddrphy_dq_i_data9[2]),
-       .Q7(soc_a7ddrphy_dq_i_data9[1]),
-       .Q8(soc_a7ddrphy_dq_i_data9[0])
+       .Q1(a7ddrphy_dq_i_data9[7]),
+       .Q2(a7ddrphy_dq_i_data9[6]),
+       .Q3(a7ddrphy_dq_i_data9[5]),
+       .Q4(a7ddrphy_dq_i_data9[4]),
+       .Q5(a7ddrphy_dq_i_data9[3]),
+       .Q6(a7ddrphy_dq_i_data9[2]),
+       .Q7(a7ddrphy_dq_i_data9[1]),
+       .Q8(a7ddrphy_dq_i_data9[0])
 );
 
 IDELAYE2 #(
@@ -19156,19 +16205,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_11 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay9),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay9),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed9)
+       .DATAOUT(a7ddrphy_dq_i_delayed9)
 );
 
 IOBUF IOBUF_9(
-       .I(soc_a7ddrphy_dq_o_nodelay9),
-       .T(soc_a7ddrphy_dq_t9),
+       .I(a7ddrphy_dq_o_nodelay9),
+       .T(a7ddrphy_dq_t9),
        .IO(ddram_dq[9]),
-       .O(soc_a7ddrphy_dq_i_nodelay9)
+       .O(a7ddrphy_dq_i_nodelay9)
 );
 
 OSERDESE2 #(
@@ -19180,20 +16229,20 @@ OSERDESE2 #(
 ) OSERDESE2_39 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[10]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[26]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[10]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[26]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[10]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[26]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[10]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[26]),
+       .D1(a7ddrphy_dfi_p0_wrdata[10]),
+       .D2(a7ddrphy_dfi_p0_wrdata[26]),
+       .D3(a7ddrphy_dfi_p1_wrdata[10]),
+       .D4(a7ddrphy_dfi_p1_wrdata[26]),
+       .D5(a7ddrphy_dfi_p2_wrdata[10]),
+       .D6(a7ddrphy_dfi_p2_wrdata[26]),
+       .D7(a7ddrphy_dfi_p3_wrdata[10]),
+       .D8(a7ddrphy_dfi_p3_wrdata[26]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay10),
-       .TQ(soc_a7ddrphy_dq_t10)
+       .OQ(a7ddrphy_dq_o_nodelay10),
+       .TQ(a7ddrphy_dq_t10)
 );
 
 ISERDESE2 #(
@@ -19209,16 +16258,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed10),
+       .DDLY(a7ddrphy_dq_i_delayed10),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data10[7]),
-       .Q2(soc_a7ddrphy_dq_i_data10[6]),
-       .Q3(soc_a7ddrphy_dq_i_data10[5]),
-       .Q4(soc_a7ddrphy_dq_i_data10[4]),
-       .Q5(soc_a7ddrphy_dq_i_data10[3]),
-       .Q6(soc_a7ddrphy_dq_i_data10[2]),
-       .Q7(soc_a7ddrphy_dq_i_data10[1]),
-       .Q8(soc_a7ddrphy_dq_i_data10[0])
+       .Q1(a7ddrphy_dq_i_data10[7]),
+       .Q2(a7ddrphy_dq_i_data10[6]),
+       .Q3(a7ddrphy_dq_i_data10[5]),
+       .Q4(a7ddrphy_dq_i_data10[4]),
+       .Q5(a7ddrphy_dq_i_data10[3]),
+       .Q6(a7ddrphy_dq_i_data10[2]),
+       .Q7(a7ddrphy_dq_i_data10[1]),
+       .Q8(a7ddrphy_dq_i_data10[0])
 );
 
 IDELAYE2 #(
@@ -19232,19 +16281,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_12 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay10),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay10),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed10)
+       .DATAOUT(a7ddrphy_dq_i_delayed10)
 );
 
 IOBUF IOBUF_10(
-       .I(soc_a7ddrphy_dq_o_nodelay10),
-       .T(soc_a7ddrphy_dq_t10),
+       .I(a7ddrphy_dq_o_nodelay10),
+       .T(a7ddrphy_dq_t10),
        .IO(ddram_dq[10]),
-       .O(soc_a7ddrphy_dq_i_nodelay10)
+       .O(a7ddrphy_dq_i_nodelay10)
 );
 
 OSERDESE2 #(
@@ -19256,20 +16305,20 @@ OSERDESE2 #(
 ) OSERDESE2_40 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[11]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[27]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[11]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[27]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[11]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[27]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[11]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[27]),
+       .D1(a7ddrphy_dfi_p0_wrdata[11]),
+       .D2(a7ddrphy_dfi_p0_wrdata[27]),
+       .D3(a7ddrphy_dfi_p1_wrdata[11]),
+       .D4(a7ddrphy_dfi_p1_wrdata[27]),
+       .D5(a7ddrphy_dfi_p2_wrdata[11]),
+       .D6(a7ddrphy_dfi_p2_wrdata[27]),
+       .D7(a7ddrphy_dfi_p3_wrdata[11]),
+       .D8(a7ddrphy_dfi_p3_wrdata[27]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay11),
-       .TQ(soc_a7ddrphy_dq_t11)
+       .OQ(a7ddrphy_dq_o_nodelay11),
+       .TQ(a7ddrphy_dq_t11)
 );
 
 ISERDESE2 #(
@@ -19285,16 +16334,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed11),
+       .DDLY(a7ddrphy_dq_i_delayed11),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data11[7]),
-       .Q2(soc_a7ddrphy_dq_i_data11[6]),
-       .Q3(soc_a7ddrphy_dq_i_data11[5]),
-       .Q4(soc_a7ddrphy_dq_i_data11[4]),
-       .Q5(soc_a7ddrphy_dq_i_data11[3]),
-       .Q6(soc_a7ddrphy_dq_i_data11[2]),
-       .Q7(soc_a7ddrphy_dq_i_data11[1]),
-       .Q8(soc_a7ddrphy_dq_i_data11[0])
+       .Q1(a7ddrphy_dq_i_data11[7]),
+       .Q2(a7ddrphy_dq_i_data11[6]),
+       .Q3(a7ddrphy_dq_i_data11[5]),
+       .Q4(a7ddrphy_dq_i_data11[4]),
+       .Q5(a7ddrphy_dq_i_data11[3]),
+       .Q6(a7ddrphy_dq_i_data11[2]),
+       .Q7(a7ddrphy_dq_i_data11[1]),
+       .Q8(a7ddrphy_dq_i_data11[0])
 );
 
 IDELAYE2 #(
@@ -19308,19 +16357,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_13 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay11),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay11),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed11)
+       .DATAOUT(a7ddrphy_dq_i_delayed11)
 );
 
 IOBUF IOBUF_11(
-       .I(soc_a7ddrphy_dq_o_nodelay11),
-       .T(soc_a7ddrphy_dq_t11),
+       .I(a7ddrphy_dq_o_nodelay11),
+       .T(a7ddrphy_dq_t11),
        .IO(ddram_dq[11]),
-       .O(soc_a7ddrphy_dq_i_nodelay11)
+       .O(a7ddrphy_dq_i_nodelay11)
 );
 
 OSERDESE2 #(
@@ -19332,20 +16381,20 @@ OSERDESE2 #(
 ) OSERDESE2_41 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[12]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[28]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[12]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[28]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[12]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[28]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[12]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[28]),
+       .D1(a7ddrphy_dfi_p0_wrdata[12]),
+       .D2(a7ddrphy_dfi_p0_wrdata[28]),
+       .D3(a7ddrphy_dfi_p1_wrdata[12]),
+       .D4(a7ddrphy_dfi_p1_wrdata[28]),
+       .D5(a7ddrphy_dfi_p2_wrdata[12]),
+       .D6(a7ddrphy_dfi_p2_wrdata[28]),
+       .D7(a7ddrphy_dfi_p3_wrdata[12]),
+       .D8(a7ddrphy_dfi_p3_wrdata[28]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay12),
-       .TQ(soc_a7ddrphy_dq_t12)
+       .OQ(a7ddrphy_dq_o_nodelay12),
+       .TQ(a7ddrphy_dq_t12)
 );
 
 ISERDESE2 #(
@@ -19361,16 +16410,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed12),
+       .DDLY(a7ddrphy_dq_i_delayed12),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data12[7]),
-       .Q2(soc_a7ddrphy_dq_i_data12[6]),
-       .Q3(soc_a7ddrphy_dq_i_data12[5]),
-       .Q4(soc_a7ddrphy_dq_i_data12[4]),
-       .Q5(soc_a7ddrphy_dq_i_data12[3]),
-       .Q6(soc_a7ddrphy_dq_i_data12[2]),
-       .Q7(soc_a7ddrphy_dq_i_data12[1]),
-       .Q8(soc_a7ddrphy_dq_i_data12[0])
+       .Q1(a7ddrphy_dq_i_data12[7]),
+       .Q2(a7ddrphy_dq_i_data12[6]),
+       .Q3(a7ddrphy_dq_i_data12[5]),
+       .Q4(a7ddrphy_dq_i_data12[4]),
+       .Q5(a7ddrphy_dq_i_data12[3]),
+       .Q6(a7ddrphy_dq_i_data12[2]),
+       .Q7(a7ddrphy_dq_i_data12[1]),
+       .Q8(a7ddrphy_dq_i_data12[0])
 );
 
 IDELAYE2 #(
@@ -19384,19 +16433,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_14 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay12),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay12),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed12)
+       .DATAOUT(a7ddrphy_dq_i_delayed12)
 );
 
 IOBUF IOBUF_12(
-       .I(soc_a7ddrphy_dq_o_nodelay12),
-       .T(soc_a7ddrphy_dq_t12),
+       .I(a7ddrphy_dq_o_nodelay12),
+       .T(a7ddrphy_dq_t12),
        .IO(ddram_dq[12]),
-       .O(soc_a7ddrphy_dq_i_nodelay12)
+       .O(a7ddrphy_dq_i_nodelay12)
 );
 
 OSERDESE2 #(
@@ -19408,20 +16457,20 @@ OSERDESE2 #(
 ) OSERDESE2_42 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[13]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[29]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[13]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[29]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[13]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[29]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[13]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[29]),
+       .D1(a7ddrphy_dfi_p0_wrdata[13]),
+       .D2(a7ddrphy_dfi_p0_wrdata[29]),
+       .D3(a7ddrphy_dfi_p1_wrdata[13]),
+       .D4(a7ddrphy_dfi_p1_wrdata[29]),
+       .D5(a7ddrphy_dfi_p2_wrdata[13]),
+       .D6(a7ddrphy_dfi_p2_wrdata[29]),
+       .D7(a7ddrphy_dfi_p3_wrdata[13]),
+       .D8(a7ddrphy_dfi_p3_wrdata[29]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay13),
-       .TQ(soc_a7ddrphy_dq_t13)
+       .OQ(a7ddrphy_dq_o_nodelay13),
+       .TQ(a7ddrphy_dq_t13)
 );
 
 ISERDESE2 #(
@@ -19437,16 +16486,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed13),
+       .DDLY(a7ddrphy_dq_i_delayed13),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data13[7]),
-       .Q2(soc_a7ddrphy_dq_i_data13[6]),
-       .Q3(soc_a7ddrphy_dq_i_data13[5]),
-       .Q4(soc_a7ddrphy_dq_i_data13[4]),
-       .Q5(soc_a7ddrphy_dq_i_data13[3]),
-       .Q6(soc_a7ddrphy_dq_i_data13[2]),
-       .Q7(soc_a7ddrphy_dq_i_data13[1]),
-       .Q8(soc_a7ddrphy_dq_i_data13[0])
+       .Q1(a7ddrphy_dq_i_data13[7]),
+       .Q2(a7ddrphy_dq_i_data13[6]),
+       .Q3(a7ddrphy_dq_i_data13[5]),
+       .Q4(a7ddrphy_dq_i_data13[4]),
+       .Q5(a7ddrphy_dq_i_data13[3]),
+       .Q6(a7ddrphy_dq_i_data13[2]),
+       .Q7(a7ddrphy_dq_i_data13[1]),
+       .Q8(a7ddrphy_dq_i_data13[0])
 );
 
 IDELAYE2 #(
@@ -19460,19 +16509,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_15 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay13),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay13),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed13)
+       .DATAOUT(a7ddrphy_dq_i_delayed13)
 );
 
 IOBUF IOBUF_13(
-       .I(soc_a7ddrphy_dq_o_nodelay13),
-       .T(soc_a7ddrphy_dq_t13),
+       .I(a7ddrphy_dq_o_nodelay13),
+       .T(a7ddrphy_dq_t13),
        .IO(ddram_dq[13]),
-       .O(soc_a7ddrphy_dq_i_nodelay13)
+       .O(a7ddrphy_dq_i_nodelay13)
 );
 
 OSERDESE2 #(
@@ -19484,20 +16533,20 @@ OSERDESE2 #(
 ) OSERDESE2_43 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[14]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[30]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[14]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[30]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[14]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[30]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[14]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[30]),
+       .D1(a7ddrphy_dfi_p0_wrdata[14]),
+       .D2(a7ddrphy_dfi_p0_wrdata[30]),
+       .D3(a7ddrphy_dfi_p1_wrdata[14]),
+       .D4(a7ddrphy_dfi_p1_wrdata[30]),
+       .D5(a7ddrphy_dfi_p2_wrdata[14]),
+       .D6(a7ddrphy_dfi_p2_wrdata[30]),
+       .D7(a7ddrphy_dfi_p3_wrdata[14]),
+       .D8(a7ddrphy_dfi_p3_wrdata[30]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay14),
-       .TQ(soc_a7ddrphy_dq_t14)
+       .OQ(a7ddrphy_dq_o_nodelay14),
+       .TQ(a7ddrphy_dq_t14)
 );
 
 ISERDESE2 #(
@@ -19513,16 +16562,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed14),
+       .DDLY(a7ddrphy_dq_i_delayed14),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data14[7]),
-       .Q2(soc_a7ddrphy_dq_i_data14[6]),
-       .Q3(soc_a7ddrphy_dq_i_data14[5]),
-       .Q4(soc_a7ddrphy_dq_i_data14[4]),
-       .Q5(soc_a7ddrphy_dq_i_data14[3]),
-       .Q6(soc_a7ddrphy_dq_i_data14[2]),
-       .Q7(soc_a7ddrphy_dq_i_data14[1]),
-       .Q8(soc_a7ddrphy_dq_i_data14[0])
+       .Q1(a7ddrphy_dq_i_data14[7]),
+       .Q2(a7ddrphy_dq_i_data14[6]),
+       .Q3(a7ddrphy_dq_i_data14[5]),
+       .Q4(a7ddrphy_dq_i_data14[4]),
+       .Q5(a7ddrphy_dq_i_data14[3]),
+       .Q6(a7ddrphy_dq_i_data14[2]),
+       .Q7(a7ddrphy_dq_i_data14[1]),
+       .Q8(a7ddrphy_dq_i_data14[0])
 );
 
 IDELAYE2 #(
@@ -19536,19 +16585,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_16 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay14),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay14),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed14)
+       .DATAOUT(a7ddrphy_dq_i_delayed14)
 );
 
 IOBUF IOBUF_14(
-       .I(soc_a7ddrphy_dq_o_nodelay14),
-       .T(soc_a7ddrphy_dq_t14),
+       .I(a7ddrphy_dq_o_nodelay14),
+       .T(a7ddrphy_dq_t14),
        .IO(ddram_dq[14]),
-       .O(soc_a7ddrphy_dq_i_nodelay14)
+       .O(a7ddrphy_dq_i_nodelay14)
 );
 
 OSERDESE2 #(
@@ -19560,20 +16609,20 @@ OSERDESE2 #(
 ) OSERDESE2_44 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[15]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[31]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[15]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[31]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[15]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[31]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[15]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[31]),
+       .D1(a7ddrphy_dfi_p0_wrdata[15]),
+       .D2(a7ddrphy_dfi_p0_wrdata[31]),
+       .D3(a7ddrphy_dfi_p1_wrdata[15]),
+       .D4(a7ddrphy_dfi_p1_wrdata[31]),
+       .D5(a7ddrphy_dfi_p2_wrdata[15]),
+       .D6(a7ddrphy_dfi_p2_wrdata[31]),
+       .D7(a7ddrphy_dfi_p3_wrdata[15]),
+       .D8(a7ddrphy_dfi_p3_wrdata[31]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay15),
-       .TQ(soc_a7ddrphy_dq_t15)
+       .OQ(a7ddrphy_dq_o_nodelay15),
+       .TQ(a7ddrphy_dq_t15)
 );
 
 ISERDESE2 #(
@@ -19589,16 +16638,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed15),
+       .DDLY(a7ddrphy_dq_i_delayed15),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data15[7]),
-       .Q2(soc_a7ddrphy_dq_i_data15[6]),
-       .Q3(soc_a7ddrphy_dq_i_data15[5]),
-       .Q4(soc_a7ddrphy_dq_i_data15[4]),
-       .Q5(soc_a7ddrphy_dq_i_data15[3]),
-       .Q6(soc_a7ddrphy_dq_i_data15[2]),
-       .Q7(soc_a7ddrphy_dq_i_data15[1]),
-       .Q8(soc_a7ddrphy_dq_i_data15[0])
+       .Q1(a7ddrphy_dq_i_data15[7]),
+       .Q2(a7ddrphy_dq_i_data15[6]),
+       .Q3(a7ddrphy_dq_i_data15[5]),
+       .Q4(a7ddrphy_dq_i_data15[4]),
+       .Q5(a7ddrphy_dq_i_data15[3]),
+       .Q6(a7ddrphy_dq_i_data15[2]),
+       .Q7(a7ddrphy_dq_i_data15[1]),
+       .Q8(a7ddrphy_dq_i_data15[0])
 );
 
 IDELAYE2 #(
@@ -19612,163 +16661,132 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_17 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay15),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay15),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed15)
+       .DATAOUT(a7ddrphy_dq_i_delayed15)
 );
 
 IOBUF IOBUF_15(
-       .I(soc_a7ddrphy_dq_o_nodelay15),
-       .T(soc_a7ddrphy_dq_t15),
+       .I(a7ddrphy_dq_o_nodelay15),
+       .T(a7ddrphy_dq_t15),
        .IO(ddram_dq[15]),
-       .O(soc_a7ddrphy_dq_i_nodelay15)
+       .O(a7ddrphy_dq_i_nodelay15)
 );
 
-reg [23:0] storage_2[0:15];
-reg [23:0] memdat_5;
+reg [23:0] storage[0:15];
+reg [23:0] memdat;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
-               storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_5 <= storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+               storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+       memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
-reg [23:0] storage_3[0:15];
-reg [23:0] memdat_6;
+reg [23:0] storage_1[0:15];
+reg [23:0] memdat_1;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
-               storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_6 <= storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+               storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
-reg [23:0] storage_4[0:15];
-reg [23:0] memdat_7;
+reg [23:0] storage_2[0:15];
+reg [23:0] memdat_2;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
-               storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_7 <= storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+               storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
-reg [23:0] storage_5[0:15];
-reg [23:0] memdat_8;
+reg [23:0] storage_3[0:15];
+reg [23:0] memdat_3;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
-               storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_8 <= storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+               storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
-reg [23:0] storage_6[0:15];
-reg [23:0] memdat_9;
+reg [23:0] storage_4[0:15];
+reg [23:0] memdat_4;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we)
-               storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_9 <= storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+               storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
-reg [23:0] storage_7[0:15];
-reg [23:0] memdat_10;
+reg [23:0] storage_5[0:15];
+reg [23:0] memdat_5;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we)
-               storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_10 <= storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+               storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
-reg [23:0] storage_8[0:15];
-reg [23:0] memdat_11;
+reg [23:0] storage_6[0:15];
+reg [23:0] memdat_6;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we)
-               storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_11 <= storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+               storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
-reg [23:0] storage_9[0:15];
-reg [23:0] memdat_12;
+reg [23:0] storage_7[0:15];
+reg [23:0] memdat_7;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we)
-               storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_12 <= storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+               storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr];
-
-VexRiscv VexRiscv(
-       .clk(sys_clk),
-       .dBusWishbone_ACK(soc_litedramcore_cpu_dbus_ack),
-       .dBusWishbone_DAT_MISO(soc_litedramcore_cpu_dbus_dat_r),
-       .dBusWishbone_ERR(soc_litedramcore_cpu_dbus_err),
-       .externalInterruptArray(soc_litedramcore_cpu_interrupt),
-       .externalResetVector(soc_litedramcore_vexriscv),
-       .iBusWishbone_ACK(soc_litedramcore_cpu_ibus_ack),
-       .iBusWishbone_DAT_MISO(soc_litedramcore_cpu_ibus_dat_r),
-       .iBusWishbone_ERR(soc_litedramcore_cpu_ibus_err),
-       .reset((sys_rst | soc_litedramcore_cpu_reset)),
-       .softwareInterrupt(1'd0),
-       .timerInterrupt(1'd0),
-       .dBusWishbone_ADR(soc_litedramcore_cpu_dbus_adr),
-       .dBusWishbone_BTE(soc_litedramcore_cpu_dbus_bte),
-       .dBusWishbone_CTI(soc_litedramcore_cpu_dbus_cti),
-       .dBusWishbone_CYC(soc_litedramcore_cpu_dbus_cyc),
-       .dBusWishbone_DAT_MOSI(soc_litedramcore_cpu_dbus_dat_w),
-       .dBusWishbone_SEL(soc_litedramcore_cpu_dbus_sel),
-       .dBusWishbone_STB(soc_litedramcore_cpu_dbus_stb),
-       .dBusWishbone_WE(soc_litedramcore_cpu_dbus_we),
-       .iBusWishbone_ADR(soc_litedramcore_cpu_ibus_adr),
-       .iBusWishbone_BTE(soc_litedramcore_cpu_ibus_bte),
-       .iBusWishbone_CTI(soc_litedramcore_cpu_ibus_cti),
-       .iBusWishbone_CYC(soc_litedramcore_cpu_ibus_cyc),
-       .iBusWishbone_DAT_MOSI(soc_litedramcore_cpu_ibus_dat_w),
-       .iBusWishbone_SEL(soc_litedramcore_cpu_ibus_sel),
-       .iBusWishbone_STB(soc_litedramcore_cpu_ibus_stb),
-       .iBusWishbone_WE(soc_litedramcore_cpu_ibus_we)
-);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
 PLLE2_ADV #(
        .CLKFBOUT_MULT(5'd16),
@@ -19783,14 +16801,14 @@ PLLE2_ADV #(
        .REF_JITTER1(0.01),
        .STARTUP_WAIT("FALSE")
 ) PLLE2_ADV (
-       .CLKFBIN(vns_pll_fb0),
-       .CLKIN1(soc_s7pll0_clkin),
-       .RST(soc_sys_pll_reset),
-       .CLKFBOUT(vns_pll_fb0),
-       .CLKOUT0(soc_s7pll0_clkout0),
-       .CLKOUT1(soc_s7pll0_clkout1),
-       .CLKOUT2(soc_s7pll0_clkout2),
-       .LOCKED(soc_sys_pll_locked)
+       .CLKFBIN(pll_fb0),
+       .CLKIN1(s7pll0_clkin),
+       .RST(sys_pll_reset),
+       .CLKFBOUT(pll_fb0),
+       .CLKOUT0(s7pll0_clkout0),
+       .CLKOUT1(s7pll0_clkout1),
+       .CLKOUT2(s7pll0_clkout2),
+       .LOCKED(sys_pll_locked)
 );
 
 PLLE2_ADV #(
@@ -19802,12 +16820,12 @@ PLLE2_ADV #(
        .REF_JITTER1(0.01),
        .STARTUP_WAIT("FALSE")
 ) PLLE2_ADV_1 (
-       .CLKFBIN(vns_pll_fb1),
-       .CLKIN1(soc_s7pll1_clkin),
-       .RST(soc_iodelay_pll_reset),
-       .CLKFBOUT(vns_pll_fb1),
-       .CLKOUT0(soc_s7pll1_clkout),
-       .LOCKED(soc_iodelay_pll_locked)
+       .CLKFBIN(pll_fb1),
+       .CLKIN1(s7pll1_clkin),
+       .RST(iodelay_pll_reset),
+       .CLKFBOUT(pll_fb1),
+       .CLKOUT0(s7pll1_clkout),
+       .LOCKED(iodelay_pll_locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -19816,8 +16834,8 @@ PLLE2_ADV #(
        .C(sys_clk),
        .CE(1'd1),
        .D(1'd0),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl0),
-       .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta)
+       .PRE(xilinxasyncresetsynchronizerimpl0),
+       .Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -19825,8 +16843,8 @@ PLLE2_ADV #(
 ) FDPE_1 (
        .C(sys_clk),
        .CE(1'd1),
-       .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl0),
+       .D(xilinxasyncresetsynchronizerimpl0_rst_meta),
+       .PRE(xilinxasyncresetsynchronizerimpl0),
        .Q(sys_rst)
 );
 
@@ -19836,8 +16854,8 @@ PLLE2_ADV #(
        .C(sys4x_clk),
        .CE(1'd1),
        .D(1'd0),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl1),
-       .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta)
+       .PRE(xilinxasyncresetsynchronizerimpl1),
+       .Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -19845,9 +16863,9 @@ PLLE2_ADV #(
 ) FDPE_3 (
        .C(sys4x_clk),
        .CE(1'd1),
-       .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl1),
-       .Q(vns_xilinxasyncresetsynchronizerimpl1_expr)
+       .D(xilinxasyncresetsynchronizerimpl1_rst_meta),
+       .PRE(xilinxasyncresetsynchronizerimpl1),
+       .Q(xilinxasyncresetsynchronizerimpl1_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -19856,8 +16874,8 @@ PLLE2_ADV #(
        .C(sys4x_dqs_clk),
        .CE(1'd1),
        .D(1'd0),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl2),
-       .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta)
+       .PRE(xilinxasyncresetsynchronizerimpl2),
+       .Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -19865,9 +16883,9 @@ PLLE2_ADV #(
 ) FDPE_5 (
        .C(sys4x_dqs_clk),
        .CE(1'd1),
-       .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl2),
-       .Q(vns_xilinxasyncresetsynchronizerimpl2_expr)
+       .D(xilinxasyncresetsynchronizerimpl2_rst_meta),
+       .PRE(xilinxasyncresetsynchronizerimpl2),
+       .Q(xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -19876,8 +16894,8 @@ PLLE2_ADV #(
        .C(iodelay_clk),
        .CE(1'd1),
        .D(1'd0),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl3),
-       .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta)
+       .PRE(xilinxasyncresetsynchronizerimpl3),
+       .Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -19885,8 +16903,8 @@ PLLE2_ADV #(
 ) FDPE_7 (
        .C(iodelay_clk),
        .CE(1'd1),
-       .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl3),
+       .D(xilinxasyncresetsynchronizerimpl3_rst_meta),
+       .PRE(xilinxasyncresetsynchronizerimpl3),
        .Q(iodelay_rst)
 );
 

diff --git a/litedram/generated/nexys-video/init-cpu.txt b/litedram/generated/nexys-video/init-cpu.txt
deleted file mode 100644 (file)
index b0b6e79..0000000
--- a/litedram/generated/nexys-video/init-cpu.txt
+++ /dev/null
@@ -1 +0,0 @@
-vexriscv
\ No newline at end of file

diff --git a/litedram/generated/nexys-video/litedram-wrapper.vhdl b/litedram/generated/nexys-video/litedram-wrapper.vhdl
index 066486651bceb52fa0b46290b33ffda337220103..475e088a8893dca8e30f45d79bc89cdfcffba9a4 100644 (file)
--- a/litedram/generated/nexys-video/litedram-wrapper.vhdl
+++ b/litedram/generated/nexys-video/litedram-wrapper.vhdl
@@ -60,8 +60,6 @@ architecture behaviour of litedram_wrapper is
     component litedram_core port (
        clk                    : in std_ulogic;
        rst                    : in std_ulogic;
-       serial_tx              : out std_ulogic;
-       serial_rx              : in std_ulogic;
        pll_locked             : out std_ulogic;
        ddram_a                : out std_ulogic_vector(DRAM_ALINES-1 downto 0);
        ddram_ba               : out std_ulogic_vector(2 downto 0);
@@ -82,6 +80,10 @@ architecture behaviour of litedram_wrapper is
        init_error             : out std_ulogic;
        user_clk               : out std_ulogic;
        user_rst               : out std_ulogic;
+       csr_port0_adr          : in std_ulogic_vector(13 downto 0);
+       csr_port0_we           : in std_ulogic;
+       csr_port0_dat_w        : in std_ulogic_vector(7 downto 0);
+       csr_port0_dat_r        : out std_ulogic_vector(7 downto 0);
        user_port_native_0_cmd_valid   : in std_ulogic;
        user_port_native_0_cmd_ready   : out std_ulogic;
        user_port_native_0_cmd_we      : in std_ulogic;
@@ -112,17 +114,84 @@ architecture behaviour of litedram_wrapper is
 
     signal dram_user_reset              : std_ulogic;
 
-    type state_t is (CMD, MWRITE, MREAD);
+    signal csr_port0_adr                : std_ulogic_vector(13 downto 0);
+    signal csr_port0_we                 : std_ulogic;
+    signal csr_port0_dat_w              : std_ulogic_vector(7 downto 0);
+    signal csr_port0_dat_r              : std_ulogic_vector(7 downto 0);
+    signal csr_port_read_comb           : std_ulogic_vector(63 downto 0);
+    signal csr_valid                   : std_ulogic;
+    signal csr_write_valid             : std_ulogic;
+
+    signal wb_init_in                   : wishbone_master_out;
+    signal wb_init_out                  : wishbone_slave_out;
+
+    type state_t is (CMD, MWRITE, MREAD, CSR);
     signal state : state_t;
 
+    constant INIT_RAM_SIZE : integer := 16384;
+    constant INIT_RAM_ABITS :integer := 14;
+    constant INIT_RAM_FILE : string := "litedram_core.init";
+
+    type ram_t is array(0 to (INIT_RAM_SIZE / 8) - 1) of std_logic_vector(63 downto 0);
+
+    impure function init_load_ram(name : string) return ram_t is
+       file ram_file : text open read_mode is name;
+       variable temp_word : std_logic_vector(63 downto 0);
+       variable temp_ram : ram_t := (others => (others => '0'));
+       variable ram_line : line;
+    begin
+       for i in 0 to (INIT_RAM_SIZE/8)-1 loop
+           exit when endfile(ram_file);
+           readline(ram_file, ram_line);
+           hread(ram_line, temp_word);
+           temp_ram(i) := temp_word;
+       end loop;
+       return temp_ram;
+    end function;
+
+    signal init_ram : ram_t := init_load_ram(INIT_RAM_FILE);
+
+    attribute ram_style : string;
+    attribute ram_style of init_ram: signal is "block";
+
 begin
 
-    -- Address bit 3 selects the top or bottom half of the data
+    -- BRAM Memory slave
+    init_ram_0: process(system_clk)
+       variable adr : integer;
+    begin
+       if rising_edge(system_clk) then
+           wb_init_out.ack <= '0';
+           if (wb_init_in.cyc and wb_init_in.stb) = '1' then
+               adr := to_integer((unsigned(wb_init_in.adr(INIT_RAM_ABITS-1 downto 3))));
+               if wb_init_in.we = '0' then
+                   wb_init_out.dat <= init_ram(adr);
+               else
+                   for i in 0 to 7 loop
+                       if wb_init_in.sel(i) = '1' then
+                           init_ram(adr)(((i + 1) * 8) - 1 downto i * 8) <=
+                               wb_init_in.dat(((i + 1) * 8) - 1 downto i * 8);
+                       end if;
+                   end loop;
+               end if;
+               wb_init_out.ack <= not wb_init_out.ack;
+           end if;
+       end if;
+    end process;
+
+    wb_init_in.adr <= wb_in.adr;
+    wb_init_in.dat <= wb_in.dat;
+    wb_init_in.sel <= wb_in.sel;
+    wb_init_in.we <= wb_in.we;
+    wb_init_in.stb <= wb_in.stb;
+    wb_init_in.cyc <= wb_in.cyc and wb_is_init;
+
+   -- Address bit 3 selects the top or bottom half of the data
     -- bus (64-bit wishbone vs. 128-bit DRAM interface)
     --
     ad3 <= wb_in.adr(3);
 
-    -- DRAM interface signals
+    -- DRAM data interface signals
     user_port0_cmd_valid <= (wb_in.cyc and wb_in.stb and not wb_is_csr and not wb_is_init)
                            when state = CMD else '0';
     user_port0_cmd_we <= wb_in.we when state = CMD else '0';
@@ -133,18 +202,32 @@ begin
     user_port0_wdata_we <= wb_in.sel & "00000000" when ad3 = '1' else
                           "00000000" & wb_in.sel;
 
-    -- Wishbone out signals. CSR and init memory do nothing, just ack
-    wb_out.ack <= '1' when (wb_is_csr = '1' or wb_is_init = '1') else
+    -- DRAM CSR interface signals. We only support access to the bottom byte
+    csr_valid <= wb_in.cyc and wb_in.stb and wb_is_csr;
+    csr_write_valid <= wb_in.we and wb_in.sel(0);
+    csr_port0_adr <= wb_in.adr(13 downto 0) when wb_is_csr = '1' else (others => '0');
+    csr_port0_dat_w <= wb_in.dat(7 downto 0);
+    csr_port0_we <= (csr_valid and csr_write_valid) when state = CMD else '0';
+
+    -- Wishbone out signals
+    wb_out.ack <= '1' when state = CSR else
+                 wb_init_out.ack when wb_is_init = '1' else
                  user_port0_wdata_ready when state = MWRITE else
                  user_port0_rdata_valid when state = MREAD else '0';
-    wb_out.dat <= (others => '0') when (wb_is_csr = '1' or wb_is_init = '1') else
+
+    csr_port_read_comb <= x"00000000000000" & csr_port0_dat_r;
+    wb_out.dat <= csr_port_read_comb when wb_is_csr = '1' else
+                 wb_init_out.dat when wb_is_init = '1' else
                  user_port0_rdata_data(127 downto 64) when ad3 = '1' else
                  user_port0_rdata_data(63 downto 0);
+    -- We don't do pipelining yet.
     wb_out.stall <= '0' when wb_in.cyc = '0' else not wb_out.ack;
 
-    -- Reset, lift it when init done, no alt core reset
-    system_reset <= dram_user_reset or not init_done;
-    core_alt_reset <= '0';
+    -- Reset ignored, the reset controller use the pll lock signal,
+    -- and alternate core reset address set when DRAM is not initialized.
+    --
+    system_reset <= '0';
+    core_alt_reset <= not init_done;
 
     -- State machine
     sm: process(system_clk)
@@ -156,7 +239,9 @@ begin
            else
                case state is
                when CMD =>
-                   if (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
+                   if csr_valid = '1' then
+                       state <= CSR;
+                   elsif (user_port0_cmd_ready and user_port0_cmd_valid) = '1' then
                        state <= MWRITE when wb_in.we = '1' else MREAD;
                    end if;
                when MWRITE =>
@@ -167,6 +252,8 @@ begin
                    if user_port0_rdata_valid = '1' then
                        state <= CMD;
                    end if;
+               when CSR =>
+                   state <= CMD;
                end case;
            end if;
        end if;
@@ -176,8 +263,6 @@ begin
        port map(
            clk => clk_in,
            rst => rst,
-           serial_tx => serial_tx,
-           serial_rx => serial_rx,
            pll_locked => pll_locked,
            ddram_a => ddram_a,
            ddram_ba => ddram_ba,
@@ -198,6 +283,10 @@ begin
            init_error => init_error,
            user_clk => system_clk,
            user_rst => dram_user_reset,
+           csr_port0_adr => csr_port0_adr,
+           csr_port0_we => csr_port0_we,
+           csr_port0_dat_w => csr_port0_dat_w,
+           csr_port0_dat_r => csr_port0_dat_r,
            user_port_native_0_cmd_valid => user_port0_cmd_valid,
            user_port_native_0_cmd_ready => user_port0_cmd_ready,
            user_port_native_0_cmd_we => user_port0_cmd_we,

diff --git a/litedram/generated/nexys-video/litedram_core.init b/litedram/generated/nexys-video/litedram_core.init
index b1daa3ce65e0f8cd2742d9711834fb38ebd4fd40..d07879f09325e0fe9c85fa3b8d2cf944cbfa0330 100644 (file)
--- a/litedram/generated/nexys-video/litedram_core.init
+++ b/litedram/generated/nexys-video/litedram_core.init
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diff --git a/litedram/generated/nexys-video/litedram_core.v b/litedram/generated/nexys-video/litedram_core.v
index b1c89659402dc270f6a5ca283038b8e0d74550d3..dd74efdd73a6e5456d2bea35f8f5172cb48fbc72 100644 (file)
--- a/litedram/generated/nexys-video/litedram_core.v
+++ b/litedram/generated/nexys-video/litedram_core.v
@@ -1,9 +1,7 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (dc9cfe6) & LiteX (79ee135f) on 2020-05-08 01:29:22
+// Auto-generated by Migen (dc9cfe6) & LiteX (d94db4de) on 2020-05-09 10:54:05
 //--------------------------------------------------------------------------------
 module litedram_core(
-       output reg serial_tx,
-       input wire serial_rx,
        input wire clk,
        input wire rst,
        output wire pll_locked,
@@ -24,6 +22,10 @@ module litedram_core(
        output wire ddram_reset_n,
        output wire init_done,
        output wire init_error,
+       input wire [13:0] csr_port0_adr,
+       input wire csr_port0_we,
+       input wire [7:0] csr_port0_dat_w,
+       output wire [7:0] csr_port0_dat_r,
        output wire user_clk,
        output wire user_rst,
        input wire user_port_native_0_cmd_valid,
@@ -39,2520 +41,2000 @@ module litedram_core(
        output wire [127:0] user_port_native_0_rdata_data
 );
 
-reg soc_litedramcore_soccontroller_reset_storage = 1'd0;
-reg soc_litedramcore_soccontroller_reset_re = 1'd0;
-reg [31:0] soc_litedramcore_soccontroller_scratch_storage = 32'd305419896;
-reg soc_litedramcore_soccontroller_scratch_re = 1'd0;
-wire [31:0] soc_litedramcore_soccontroller_bus_errors_status;
-wire soc_litedramcore_soccontroller_bus_errors_we;
-wire soc_litedramcore_soccontroller_reset;
-wire soc_litedramcore_soccontroller_bus_error;
-reg [31:0] soc_litedramcore_soccontroller_bus_errors = 32'd0;
-wire soc_litedramcore_cpu_reset;
-reg [31:0] soc_litedramcore_cpu_interrupt = 32'd0;
-wire [29:0] soc_litedramcore_cpu_ibus_adr;
-wire [31:0] soc_litedramcore_cpu_ibus_dat_w;
-wire [31:0] soc_litedramcore_cpu_ibus_dat_r;
-wire [3:0] soc_litedramcore_cpu_ibus_sel;
-wire soc_litedramcore_cpu_ibus_cyc;
-wire soc_litedramcore_cpu_ibus_stb;
-wire soc_litedramcore_cpu_ibus_ack;
-wire soc_litedramcore_cpu_ibus_we;
-wire [2:0] soc_litedramcore_cpu_ibus_cti;
-wire [1:0] soc_litedramcore_cpu_ibus_bte;
-wire soc_litedramcore_cpu_ibus_err;
-wire [29:0] soc_litedramcore_cpu_dbus_adr;
-wire [31:0] soc_litedramcore_cpu_dbus_dat_w;
-wire [31:0] soc_litedramcore_cpu_dbus_dat_r;
-wire [3:0] soc_litedramcore_cpu_dbus_sel;
-wire soc_litedramcore_cpu_dbus_cyc;
-wire soc_litedramcore_cpu_dbus_stb;
-wire soc_litedramcore_cpu_dbus_ack;
-wire soc_litedramcore_cpu_dbus_we;
-wire [2:0] soc_litedramcore_cpu_dbus_cti;
-wire [1:0] soc_litedramcore_cpu_dbus_bte;
-wire soc_litedramcore_cpu_dbus_err;
-reg [31:0] soc_litedramcore_vexriscv = 32'd0;
-wire [29:0] soc_litedramcore_litedramcore_ram_bus_adr;
-wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_w;
-wire [31:0] soc_litedramcore_litedramcore_ram_bus_dat_r;
-wire [3:0] soc_litedramcore_litedramcore_ram_bus_sel;
-wire soc_litedramcore_litedramcore_ram_bus_cyc;
-wire soc_litedramcore_litedramcore_ram_bus_stb;
-reg soc_litedramcore_litedramcore_ram_bus_ack = 1'd0;
-wire soc_litedramcore_litedramcore_ram_bus_we;
-wire [2:0] soc_litedramcore_litedramcore_ram_bus_cti;
-wire [1:0] soc_litedramcore_litedramcore_ram_bus_bte;
-reg soc_litedramcore_litedramcore_ram_bus_err = 1'd0;
-wire [12:0] soc_litedramcore_litedramcore_adr;
-wire [31:0] soc_litedramcore_litedramcore_dat_r;
-wire [29:0] soc_litedramcore_ram_bus_ram_bus_adr;
-wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_w;
-wire [31:0] soc_litedramcore_ram_bus_ram_bus_dat_r;
-wire [3:0] soc_litedramcore_ram_bus_ram_bus_sel;
-wire soc_litedramcore_ram_bus_ram_bus_cyc;
-wire soc_litedramcore_ram_bus_ram_bus_stb;
-reg soc_litedramcore_ram_bus_ram_bus_ack = 1'd0;
-wire soc_litedramcore_ram_bus_ram_bus_we;
-wire [2:0] soc_litedramcore_ram_bus_ram_bus_cti;
-wire [1:0] soc_litedramcore_ram_bus_ram_bus_bte;
-reg soc_litedramcore_ram_bus_ram_bus_err = 1'd0;
-wire [9:0] soc_litedramcore_ram_adr;
-wire [31:0] soc_litedramcore_ram_dat_r;
-reg [3:0] soc_litedramcore_ram_we = 4'd0;
-wire [31:0] soc_litedramcore_ram_dat_w;
-reg [31:0] soc_litedramcore_storage = 32'd4947802;
-reg soc_litedramcore_re = 1'd0;
-wire soc_litedramcore_sink_valid;
-reg soc_litedramcore_sink_ready = 1'd0;
-wire soc_litedramcore_sink_first;
-wire soc_litedramcore_sink_last;
-wire [7:0] soc_litedramcore_sink_payload_data;
-reg soc_litedramcore_uart_clk_txen = 1'd0;
-reg [31:0] soc_litedramcore_phase_accumulator_tx = 32'd0;
-reg [7:0] soc_litedramcore_tx_reg = 8'd0;
-reg [3:0] soc_litedramcore_tx_bitcount = 4'd0;
-reg soc_litedramcore_tx_busy = 1'd0;
-reg soc_litedramcore_source_valid = 1'd0;
-wire soc_litedramcore_source_ready;
-reg soc_litedramcore_source_first = 1'd0;
-reg soc_litedramcore_source_last = 1'd0;
-reg [7:0] soc_litedramcore_source_payload_data = 8'd0;
-reg soc_litedramcore_uart_clk_rxen = 1'd0;
-reg [31:0] soc_litedramcore_phase_accumulator_rx = 32'd0;
-wire soc_litedramcore_rx;
-reg soc_litedramcore_rx_r = 1'd0;
-reg [7:0] soc_litedramcore_rx_reg = 8'd0;
-reg [3:0] soc_litedramcore_rx_bitcount = 4'd0;
-reg soc_litedramcore_rx_busy = 1'd0;
-wire soc_litedramcore_uart_rxtx_re;
-wire [7:0] soc_litedramcore_uart_rxtx_r;
-wire soc_litedramcore_uart_rxtx_we;
-wire [7:0] soc_litedramcore_uart_rxtx_w;
-wire soc_litedramcore_uart_txfull_status;
-wire soc_litedramcore_uart_txfull_we;
-wire soc_litedramcore_uart_rxempty_status;
-wire soc_litedramcore_uart_rxempty_we;
-wire soc_litedramcore_uart_irq;
-wire soc_litedramcore_uart_tx_status;
-reg soc_litedramcore_uart_tx_pending = 1'd0;
-wire soc_litedramcore_uart_tx_trigger;
-reg soc_litedramcore_uart_tx_clear = 1'd0;
-reg soc_litedramcore_uart_tx_old_trigger = 1'd0;
-wire soc_litedramcore_uart_rx_status;
-reg soc_litedramcore_uart_rx_pending = 1'd0;
-wire soc_litedramcore_uart_rx_trigger;
-reg soc_litedramcore_uart_rx_clear = 1'd0;
-reg soc_litedramcore_uart_rx_old_trigger = 1'd0;
-wire soc_litedramcore_uart_eventmanager_status_re;
-wire [1:0] soc_litedramcore_uart_eventmanager_status_r;
-wire soc_litedramcore_uart_eventmanager_status_we;
-reg [1:0] soc_litedramcore_uart_eventmanager_status_w = 2'd0;
-wire soc_litedramcore_uart_eventmanager_pending_re;
-wire [1:0] soc_litedramcore_uart_eventmanager_pending_r;
-wire soc_litedramcore_uart_eventmanager_pending_we;
-reg [1:0] soc_litedramcore_uart_eventmanager_pending_w = 2'd0;
-reg [1:0] soc_litedramcore_uart_eventmanager_storage = 2'd0;
-reg soc_litedramcore_uart_eventmanager_re = 1'd0;
-wire soc_litedramcore_uart_uart_sink_valid;
-wire soc_litedramcore_uart_uart_sink_ready;
-wire soc_litedramcore_uart_uart_sink_first;
-wire soc_litedramcore_uart_uart_sink_last;
-wire [7:0] soc_litedramcore_uart_uart_sink_payload_data;
-wire soc_litedramcore_uart_uart_source_valid;
-wire soc_litedramcore_uart_uart_source_ready;
-wire soc_litedramcore_uart_uart_source_first;
-wire soc_litedramcore_uart_uart_source_last;
-wire [7:0] soc_litedramcore_uart_uart_source_payload_data;
-wire soc_litedramcore_uart_tx_fifo_sink_valid;
-wire soc_litedramcore_uart_tx_fifo_sink_ready;
-reg soc_litedramcore_uart_tx_fifo_sink_first = 1'd0;
-reg soc_litedramcore_uart_tx_fifo_sink_last = 1'd0;
-wire [7:0] soc_litedramcore_uart_tx_fifo_sink_payload_data;
-wire soc_litedramcore_uart_tx_fifo_source_valid;
-wire soc_litedramcore_uart_tx_fifo_source_ready;
-wire soc_litedramcore_uart_tx_fifo_source_first;
-wire soc_litedramcore_uart_tx_fifo_source_last;
-wire [7:0] soc_litedramcore_uart_tx_fifo_source_payload_data;
-wire soc_litedramcore_uart_tx_fifo_re;
-reg soc_litedramcore_uart_tx_fifo_readable = 1'd0;
-wire soc_litedramcore_uart_tx_fifo_syncfifo_we;
-wire soc_litedramcore_uart_tx_fifo_syncfifo_writable;
-wire soc_litedramcore_uart_tx_fifo_syncfifo_re;
-wire soc_litedramcore_uart_tx_fifo_syncfifo_readable;
-wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_din;
-wire [9:0] soc_litedramcore_uart_tx_fifo_syncfifo_dout;
-reg [4:0] soc_litedramcore_uart_tx_fifo_level0 = 5'd0;
-reg soc_litedramcore_uart_tx_fifo_replace = 1'd0;
-reg [3:0] soc_litedramcore_uart_tx_fifo_produce = 4'd0;
-reg [3:0] soc_litedramcore_uart_tx_fifo_consume = 4'd0;
-reg [3:0] soc_litedramcore_uart_tx_fifo_wrport_adr = 4'd0;
-wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_r;
-wire soc_litedramcore_uart_tx_fifo_wrport_we;
-wire [9:0] soc_litedramcore_uart_tx_fifo_wrport_dat_w;
-wire soc_litedramcore_uart_tx_fifo_do_read;
-wire [3:0] soc_litedramcore_uart_tx_fifo_rdport_adr;
-wire [9:0] soc_litedramcore_uart_tx_fifo_rdport_dat_r;
-wire soc_litedramcore_uart_tx_fifo_rdport_re;
-wire [4:0] soc_litedramcore_uart_tx_fifo_level1;
-wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_in_payload_data;
-wire soc_litedramcore_uart_tx_fifo_fifo_in_first;
-wire soc_litedramcore_uart_tx_fifo_fifo_in_last;
-wire [7:0] soc_litedramcore_uart_tx_fifo_fifo_out_payload_data;
-wire soc_litedramcore_uart_tx_fifo_fifo_out_first;
-wire soc_litedramcore_uart_tx_fifo_fifo_out_last;
-wire soc_litedramcore_uart_rx_fifo_sink_valid;
-wire soc_litedramcore_uart_rx_fifo_sink_ready;
-wire soc_litedramcore_uart_rx_fifo_sink_first;
-wire soc_litedramcore_uart_rx_fifo_sink_last;
-wire [7:0] soc_litedramcore_uart_rx_fifo_sink_payload_data;
-wire soc_litedramcore_uart_rx_fifo_source_valid;
-wire soc_litedramcore_uart_rx_fifo_source_ready;
-wire soc_litedramcore_uart_rx_fifo_source_first;
-wire soc_litedramcore_uart_rx_fifo_source_last;
-wire [7:0] soc_litedramcore_uart_rx_fifo_source_payload_data;
-wire soc_litedramcore_uart_rx_fifo_re;
-reg soc_litedramcore_uart_rx_fifo_readable = 1'd0;
-wire soc_litedramcore_uart_rx_fifo_syncfifo_we;
-wire soc_litedramcore_uart_rx_fifo_syncfifo_writable;
-wire soc_litedramcore_uart_rx_fifo_syncfifo_re;
-wire soc_litedramcore_uart_rx_fifo_syncfifo_readable;
-wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_din;
-wire [9:0] soc_litedramcore_uart_rx_fifo_syncfifo_dout;
-reg [4:0] soc_litedramcore_uart_rx_fifo_level0 = 5'd0;
-reg soc_litedramcore_uart_rx_fifo_replace = 1'd0;
-reg [3:0] soc_litedramcore_uart_rx_fifo_produce = 4'd0;
-reg [3:0] soc_litedramcore_uart_rx_fifo_consume = 4'd0;
-reg [3:0] soc_litedramcore_uart_rx_fifo_wrport_adr = 4'd0;
-wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_r;
-wire soc_litedramcore_uart_rx_fifo_wrport_we;
-wire [9:0] soc_litedramcore_uart_rx_fifo_wrport_dat_w;
-wire soc_litedramcore_uart_rx_fifo_do_read;
-wire [3:0] soc_litedramcore_uart_rx_fifo_rdport_adr;
-wire [9:0] soc_litedramcore_uart_rx_fifo_rdport_dat_r;
-wire soc_litedramcore_uart_rx_fifo_rdport_re;
-wire [4:0] soc_litedramcore_uart_rx_fifo_level1;
-wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_in_payload_data;
-wire soc_litedramcore_uart_rx_fifo_fifo_in_first;
-wire soc_litedramcore_uart_rx_fifo_fifo_in_last;
-wire [7:0] soc_litedramcore_uart_rx_fifo_fifo_out_payload_data;
-wire soc_litedramcore_uart_rx_fifo_fifo_out_first;
-wire soc_litedramcore_uart_rx_fifo_fifo_out_last;
-reg soc_litedramcore_uart_reset = 1'd0;
-reg [31:0] soc_litedramcore_timer_load_storage = 32'd0;
-reg soc_litedramcore_timer_load_re = 1'd0;
-reg [31:0] soc_litedramcore_timer_reload_storage = 32'd0;
-reg soc_litedramcore_timer_reload_re = 1'd0;
-reg soc_litedramcore_timer_en_storage = 1'd0;
-reg soc_litedramcore_timer_en_re = 1'd0;
-reg soc_litedramcore_timer_update_value_storage = 1'd0;
-reg soc_litedramcore_timer_update_value_re = 1'd0;
-reg [31:0] soc_litedramcore_timer_value_status = 32'd0;
-wire soc_litedramcore_timer_value_we;
-wire soc_litedramcore_timer_irq;
-wire soc_litedramcore_timer_zero_status;
-reg soc_litedramcore_timer_zero_pending = 1'd0;
-wire soc_litedramcore_timer_zero_trigger;
-reg soc_litedramcore_timer_zero_clear = 1'd0;
-reg soc_litedramcore_timer_zero_old_trigger = 1'd0;
-wire soc_litedramcore_timer_eventmanager_status_re;
-wire soc_litedramcore_timer_eventmanager_status_r;
-wire soc_litedramcore_timer_eventmanager_status_we;
-wire soc_litedramcore_timer_eventmanager_status_w;
-wire soc_litedramcore_timer_eventmanager_pending_re;
-wire soc_litedramcore_timer_eventmanager_pending_r;
-wire soc_litedramcore_timer_eventmanager_pending_we;
-wire soc_litedramcore_timer_eventmanager_pending_w;
-reg soc_litedramcore_timer_eventmanager_storage = 1'd0;
-reg soc_litedramcore_timer_eventmanager_re = 1'd0;
-reg [31:0] soc_litedramcore_timer_value = 32'd0;
-reg [13:0] soc_litedramcore_interface_adr = 14'd0;
-reg soc_litedramcore_interface_we = 1'd0;
-wire [7:0] soc_litedramcore_interface_dat_w;
-wire [7:0] soc_litedramcore_interface_dat_r;
-wire [29:0] soc_litedramcore_bus_wishbone_adr;
-wire [31:0] soc_litedramcore_bus_wishbone_dat_w;
-wire [31:0] soc_litedramcore_bus_wishbone_dat_r;
-wire [3:0] soc_litedramcore_bus_wishbone_sel;
-wire soc_litedramcore_bus_wishbone_cyc;
-wire soc_litedramcore_bus_wishbone_stb;
-reg soc_litedramcore_bus_wishbone_ack = 1'd0;
-wire soc_litedramcore_bus_wishbone_we;
-wire [2:0] soc_litedramcore_bus_wishbone_cti;
-wire [1:0] soc_litedramcore_bus_wishbone_bte;
-reg soc_litedramcore_bus_wishbone_err = 1'd0;
 wire sys_clk;
 wire sys_rst;
 wire sys4x_clk;
 wire sys4x_dqs_clk;
 wire iodelay_clk;
 wire iodelay_rst;
-wire soc_sys_pll_reset;
-wire soc_sys_pll_locked;
-wire soc_s7pll0_clkin;
-wire soc_s7pll0_clkout0;
-wire soc_s7pll0_clkout_buf0;
-wire soc_s7pll0_clkout1;
-wire soc_s7pll0_clkout_buf1;
-wire soc_s7pll0_clkout2;
-wire soc_s7pll0_clkout_buf2;
-wire soc_iodelay_pll_reset;
-wire soc_iodelay_pll_locked;
-wire soc_s7pll1_clkin;
-wire soc_s7pll1_clkout;
-wire soc_s7pll1_clkout_buf;
-reg [3:0] soc_reset_counter = 4'd15;
-reg soc_ic_reset = 1'd1;
-reg [4:0] soc_a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg soc_a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg soc_a7ddrphy_wlevel_en_storage = 1'd0;
-reg soc_a7ddrphy_wlevel_en_re = 1'd0;
-wire soc_a7ddrphy_wlevel_strobe_re;
-wire soc_a7ddrphy_wlevel_strobe_r;
-wire soc_a7ddrphy_wlevel_strobe_we;
-reg soc_a7ddrphy_wlevel_strobe_w = 1'd0;
-wire soc_a7ddrphy_cdly_rst_re;
-wire soc_a7ddrphy_cdly_rst_r;
-wire soc_a7ddrphy_cdly_rst_we;
-reg soc_a7ddrphy_cdly_rst_w = 1'd0;
-wire soc_a7ddrphy_cdly_inc_re;
-wire soc_a7ddrphy_cdly_inc_r;
-wire soc_a7ddrphy_cdly_inc_we;
-reg soc_a7ddrphy_cdly_inc_w = 1'd0;
-reg [1:0] soc_a7ddrphy_dly_sel_storage = 2'd0;
-reg soc_a7ddrphy_dly_sel_re = 1'd0;
-wire soc_a7ddrphy_rdly_dq_rst_re;
-wire soc_a7ddrphy_rdly_dq_rst_r;
-wire soc_a7ddrphy_rdly_dq_rst_we;
-reg soc_a7ddrphy_rdly_dq_rst_w = 1'd0;
-wire soc_a7ddrphy_rdly_dq_inc_re;
-wire soc_a7ddrphy_rdly_dq_inc_r;
-wire soc_a7ddrphy_rdly_dq_inc_we;
-reg soc_a7ddrphy_rdly_dq_inc_w = 1'd0;
-wire soc_a7ddrphy_rdly_dq_bitslip_rst_re;
-wire soc_a7ddrphy_rdly_dq_bitslip_rst_r;
-wire soc_a7ddrphy_rdly_dq_bitslip_rst_we;
-reg soc_a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-wire soc_a7ddrphy_rdly_dq_bitslip_re;
-wire soc_a7ddrphy_rdly_dq_bitslip_r;
-wire soc_a7ddrphy_rdly_dq_bitslip_we;
-reg soc_a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-wire [14:0] soc_a7ddrphy_dfi_p0_address;
-wire [2:0] soc_a7ddrphy_dfi_p0_bank;
-wire soc_a7ddrphy_dfi_p0_cas_n;
-wire soc_a7ddrphy_dfi_p0_cs_n;
-wire soc_a7ddrphy_dfi_p0_ras_n;
-wire soc_a7ddrphy_dfi_p0_we_n;
-wire soc_a7ddrphy_dfi_p0_cke;
-wire soc_a7ddrphy_dfi_p0_odt;
-wire soc_a7ddrphy_dfi_p0_reset_n;
-wire soc_a7ddrphy_dfi_p0_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p0_wrdata;
-wire soc_a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p0_wrdata_mask;
-wire soc_a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p0_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p0_rddata_valid = 1'd0;
-wire [14:0] soc_a7ddrphy_dfi_p1_address;
-wire [2:0] soc_a7ddrphy_dfi_p1_bank;
-wire soc_a7ddrphy_dfi_p1_cas_n;
-wire soc_a7ddrphy_dfi_p1_cs_n;
-wire soc_a7ddrphy_dfi_p1_ras_n;
-wire soc_a7ddrphy_dfi_p1_we_n;
-wire soc_a7ddrphy_dfi_p1_cke;
-wire soc_a7ddrphy_dfi_p1_odt;
-wire soc_a7ddrphy_dfi_p1_reset_n;
-wire soc_a7ddrphy_dfi_p1_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p1_wrdata;
-wire soc_a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p1_wrdata_mask;
-wire soc_a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p1_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p1_rddata_valid = 1'd0;
-wire [14:0] soc_a7ddrphy_dfi_p2_address;
-wire [2:0] soc_a7ddrphy_dfi_p2_bank;
-wire soc_a7ddrphy_dfi_p2_cas_n;
-wire soc_a7ddrphy_dfi_p2_cs_n;
-wire soc_a7ddrphy_dfi_p2_ras_n;
-wire soc_a7ddrphy_dfi_p2_we_n;
-wire soc_a7ddrphy_dfi_p2_cke;
-wire soc_a7ddrphy_dfi_p2_odt;
-wire soc_a7ddrphy_dfi_p2_reset_n;
-wire soc_a7ddrphy_dfi_p2_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p2_wrdata;
-wire soc_a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p2_wrdata_mask;
-wire soc_a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p2_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p2_rddata_valid = 1'd0;
-wire [14:0] soc_a7ddrphy_dfi_p3_address;
-wire [2:0] soc_a7ddrphy_dfi_p3_bank;
-wire soc_a7ddrphy_dfi_p3_cas_n;
-wire soc_a7ddrphy_dfi_p3_cs_n;
-wire soc_a7ddrphy_dfi_p3_ras_n;
-wire soc_a7ddrphy_dfi_p3_we_n;
-wire soc_a7ddrphy_dfi_p3_cke;
-wire soc_a7ddrphy_dfi_p3_odt;
-wire soc_a7ddrphy_dfi_p3_reset_n;
-wire soc_a7ddrphy_dfi_p3_act_n;
-wire [31:0] soc_a7ddrphy_dfi_p3_wrdata;
-wire soc_a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] soc_a7ddrphy_dfi_p3_wrdata_mask;
-wire soc_a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] soc_a7ddrphy_dfi_p3_rddata = 32'd0;
-reg soc_a7ddrphy_dfi_p3_rddata_valid = 1'd0;
-wire soc_a7ddrphy_sd_clk_se_nodelay;
-reg soc_a7ddrphy_dqs_oe = 1'd0;
-reg soc_a7ddrphy_dqs_oe_delayed = 1'd0;
-wire soc_a7ddrphy_dqspattern0;
-wire soc_a7ddrphy_dqspattern1;
-reg [7:0] soc_a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] soc_a7ddrphy_dqspattern_o1 = 8'd0;
-wire [1:0] soc_a7ddrphy_dqs_i;
-wire [1:0] soc_a7ddrphy_dqs_i_delayed;
-wire soc_a7ddrphy_dqs_o_no_delay0;
-wire soc_a7ddrphy_dqs_t0;
-wire soc_a7ddrphy0;
-wire soc_a7ddrphy_dqs_o_no_delay1;
-wire soc_a7ddrphy_dqs_t1;
-wire soc_a7ddrphy1;
-wire soc_a7ddrphy_dq_oe;
-reg soc_a7ddrphy_dq_oe_delayed = 1'd0;
-wire soc_a7ddrphy_dq_o_nodelay0;
-wire soc_a7ddrphy_dq_i_nodelay0;
-wire soc_a7ddrphy_dq_i_delayed0;
-wire soc_a7ddrphy_dq_t0;
-wire [7:0] soc_a7ddrphy_dq_i_data0;
-wire [7:0] soc_a7ddrphy_bitslip0_i;
-reg [7:0] soc_a7ddrphy_bitslip0_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip0_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip0_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay1;
-wire soc_a7ddrphy_dq_i_nodelay1;
-wire soc_a7ddrphy_dq_i_delayed1;
-wire soc_a7ddrphy_dq_t1;
-wire [7:0] soc_a7ddrphy_dq_i_data1;
-wire [7:0] soc_a7ddrphy_bitslip1_i;
-reg [7:0] soc_a7ddrphy_bitslip1_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip1_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip1_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay2;
-wire soc_a7ddrphy_dq_i_nodelay2;
-wire soc_a7ddrphy_dq_i_delayed2;
-wire soc_a7ddrphy_dq_t2;
-wire [7:0] soc_a7ddrphy_dq_i_data2;
-wire [7:0] soc_a7ddrphy_bitslip2_i;
-reg [7:0] soc_a7ddrphy_bitslip2_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip2_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip2_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay3;
-wire soc_a7ddrphy_dq_i_nodelay3;
-wire soc_a7ddrphy_dq_i_delayed3;
-wire soc_a7ddrphy_dq_t3;
-wire [7:0] soc_a7ddrphy_dq_i_data3;
-wire [7:0] soc_a7ddrphy_bitslip3_i;
-reg [7:0] soc_a7ddrphy_bitslip3_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip3_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip3_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay4;
-wire soc_a7ddrphy_dq_i_nodelay4;
-wire soc_a7ddrphy_dq_i_delayed4;
-wire soc_a7ddrphy_dq_t4;
-wire [7:0] soc_a7ddrphy_dq_i_data4;
-wire [7:0] soc_a7ddrphy_bitslip4_i;
-reg [7:0] soc_a7ddrphy_bitslip4_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip4_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip4_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay5;
-wire soc_a7ddrphy_dq_i_nodelay5;
-wire soc_a7ddrphy_dq_i_delayed5;
-wire soc_a7ddrphy_dq_t5;
-wire [7:0] soc_a7ddrphy_dq_i_data5;
-wire [7:0] soc_a7ddrphy_bitslip5_i;
-reg [7:0] soc_a7ddrphy_bitslip5_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip5_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip5_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay6;
-wire soc_a7ddrphy_dq_i_nodelay6;
-wire soc_a7ddrphy_dq_i_delayed6;
-wire soc_a7ddrphy_dq_t6;
-wire [7:0] soc_a7ddrphy_dq_i_data6;
-wire [7:0] soc_a7ddrphy_bitslip6_i;
-reg [7:0] soc_a7ddrphy_bitslip6_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip6_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip6_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay7;
-wire soc_a7ddrphy_dq_i_nodelay7;
-wire soc_a7ddrphy_dq_i_delayed7;
-wire soc_a7ddrphy_dq_t7;
-wire [7:0] soc_a7ddrphy_dq_i_data7;
-wire [7:0] soc_a7ddrphy_bitslip7_i;
-reg [7:0] soc_a7ddrphy_bitslip7_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip7_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip7_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay8;
-wire soc_a7ddrphy_dq_i_nodelay8;
-wire soc_a7ddrphy_dq_i_delayed8;
-wire soc_a7ddrphy_dq_t8;
-wire [7:0] soc_a7ddrphy_dq_i_data8;
-wire [7:0] soc_a7ddrphy_bitslip8_i;
-reg [7:0] soc_a7ddrphy_bitslip8_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip8_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip8_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay9;
-wire soc_a7ddrphy_dq_i_nodelay9;
-wire soc_a7ddrphy_dq_i_delayed9;
-wire soc_a7ddrphy_dq_t9;
-wire [7:0] soc_a7ddrphy_dq_i_data9;
-wire [7:0] soc_a7ddrphy_bitslip9_i;
-reg [7:0] soc_a7ddrphy_bitslip9_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip9_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip9_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay10;
-wire soc_a7ddrphy_dq_i_nodelay10;
-wire soc_a7ddrphy_dq_i_delayed10;
-wire soc_a7ddrphy_dq_t10;
-wire [7:0] soc_a7ddrphy_dq_i_data10;
-wire [7:0] soc_a7ddrphy_bitslip10_i;
-reg [7:0] soc_a7ddrphy_bitslip10_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip10_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip10_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay11;
-wire soc_a7ddrphy_dq_i_nodelay11;
-wire soc_a7ddrphy_dq_i_delayed11;
-wire soc_a7ddrphy_dq_t11;
-wire [7:0] soc_a7ddrphy_dq_i_data11;
-wire [7:0] soc_a7ddrphy_bitslip11_i;
-reg [7:0] soc_a7ddrphy_bitslip11_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip11_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip11_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay12;
-wire soc_a7ddrphy_dq_i_nodelay12;
-wire soc_a7ddrphy_dq_i_delayed12;
-wire soc_a7ddrphy_dq_t12;
-wire [7:0] soc_a7ddrphy_dq_i_data12;
-wire [7:0] soc_a7ddrphy_bitslip12_i;
-reg [7:0] soc_a7ddrphy_bitslip12_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip12_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip12_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay13;
-wire soc_a7ddrphy_dq_i_nodelay13;
-wire soc_a7ddrphy_dq_i_delayed13;
-wire soc_a7ddrphy_dq_t13;
-wire [7:0] soc_a7ddrphy_dq_i_data13;
-wire [7:0] soc_a7ddrphy_bitslip13_i;
-reg [7:0] soc_a7ddrphy_bitslip13_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip13_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip13_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay14;
-wire soc_a7ddrphy_dq_i_nodelay14;
-wire soc_a7ddrphy_dq_i_delayed14;
-wire soc_a7ddrphy_dq_t14;
-wire [7:0] soc_a7ddrphy_dq_i_data14;
-wire [7:0] soc_a7ddrphy_bitslip14_i;
-reg [7:0] soc_a7ddrphy_bitslip14_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip14_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip14_r = 16'd0;
-wire soc_a7ddrphy_dq_o_nodelay15;
-wire soc_a7ddrphy_dq_i_nodelay15;
-wire soc_a7ddrphy_dq_i_delayed15;
-wire soc_a7ddrphy_dq_t15;
-wire [7:0] soc_a7ddrphy_dq_i_data15;
-wire [7:0] soc_a7ddrphy_bitslip15_i;
-reg [7:0] soc_a7ddrphy_bitslip15_o = 8'd0;
-reg [2:0] soc_a7ddrphy_bitslip15_value = 3'd0;
-reg [15:0] soc_a7ddrphy_bitslip15_r = 16'd0;
-wire [7:0] soc_a7ddrphy_rddata_en;
-reg [7:0] soc_a7ddrphy_rddata_en_last = 8'd0;
-wire [3:0] soc_a7ddrphy_wrdata_en;
-reg [3:0] soc_a7ddrphy_wrdata_en_last = 4'd0;
-wire [14:0] soc_sdram_inti_p0_address;
-wire [2:0] soc_sdram_inti_p0_bank;
-reg soc_sdram_inti_p0_cas_n = 1'd1;
-reg soc_sdram_inti_p0_cs_n = 1'd1;
-reg soc_sdram_inti_p0_ras_n = 1'd1;
-reg soc_sdram_inti_p0_we_n = 1'd1;
-wire soc_sdram_inti_p0_cke;
-wire soc_sdram_inti_p0_odt;
-wire soc_sdram_inti_p0_reset_n;
-reg soc_sdram_inti_p0_act_n = 1'd1;
-wire [31:0] soc_sdram_inti_p0_wrdata;
-wire soc_sdram_inti_p0_wrdata_en;
-wire [3:0] soc_sdram_inti_p0_wrdata_mask;
-wire soc_sdram_inti_p0_rddata_en;
-reg [31:0] soc_sdram_inti_p0_rddata = 32'd0;
-reg soc_sdram_inti_p0_rddata_valid = 1'd0;
-wire [14:0] soc_sdram_inti_p1_address;
-wire [2:0] soc_sdram_inti_p1_bank;
-reg soc_sdram_inti_p1_cas_n = 1'd1;
-reg soc_sdram_inti_p1_cs_n = 1'd1;
-reg soc_sdram_inti_p1_ras_n = 1'd1;
-reg soc_sdram_inti_p1_we_n = 1'd1;
-wire soc_sdram_inti_p1_cke;
-wire soc_sdram_inti_p1_odt;
-wire soc_sdram_inti_p1_reset_n;
-reg soc_sdram_inti_p1_act_n = 1'd1;
-wire [31:0] soc_sdram_inti_p1_wrdata;
-wire soc_sdram_inti_p1_wrdata_en;
-wire [3:0] soc_sdram_inti_p1_wrdata_mask;
-wire soc_sdram_inti_p1_rddata_en;
-reg [31:0] soc_sdram_inti_p1_rddata = 32'd0;
-reg soc_sdram_inti_p1_rddata_valid = 1'd0;
-wire [14:0] soc_sdram_inti_p2_address;
-wire [2:0] soc_sdram_inti_p2_bank;
-reg soc_sdram_inti_p2_cas_n = 1'd1;
-reg soc_sdram_inti_p2_cs_n = 1'd1;
-reg soc_sdram_inti_p2_ras_n = 1'd1;
-reg soc_sdram_inti_p2_we_n = 1'd1;
-wire soc_sdram_inti_p2_cke;
-wire soc_sdram_inti_p2_odt;
-wire soc_sdram_inti_p2_reset_n;
-reg soc_sdram_inti_p2_act_n = 1'd1;
-wire [31:0] soc_sdram_inti_p2_wrdata;
-wire soc_sdram_inti_p2_wrdata_en;
-wire [3:0] soc_sdram_inti_p2_wrdata_mask;
-wire soc_sdram_inti_p2_rddata_en;
-reg [31:0] soc_sdram_inti_p2_rddata = 32'd0;
-reg soc_sdram_inti_p2_rddata_valid = 1'd0;
-wire [14:0] soc_sdram_inti_p3_address;
-wire [2:0] soc_sdram_inti_p3_bank;
-reg soc_sdram_inti_p3_cas_n = 1'd1;
-reg soc_sdram_inti_p3_cs_n = 1'd1;
-reg soc_sdram_inti_p3_ras_n = 1'd1;
-reg soc_sdram_inti_p3_we_n = 1'd1;
-wire soc_sdram_inti_p3_cke;
-wire soc_sdram_inti_p3_odt;
-wire soc_sdram_inti_p3_reset_n;
-reg soc_sdram_inti_p3_act_n = 1'd1;
-wire [31:0] soc_sdram_inti_p3_wrdata;
-wire soc_sdram_inti_p3_wrdata_en;
-wire [3:0] soc_sdram_inti_p3_wrdata_mask;
-wire soc_sdram_inti_p3_rddata_en;
-reg [31:0] soc_sdram_inti_p3_rddata = 32'd0;
-reg soc_sdram_inti_p3_rddata_valid = 1'd0;
-wire [14:0] soc_sdram_slave_p0_address;
-wire [2:0] soc_sdram_slave_p0_bank;
-wire soc_sdram_slave_p0_cas_n;
-wire soc_sdram_slave_p0_cs_n;
-wire soc_sdram_slave_p0_ras_n;
-wire soc_sdram_slave_p0_we_n;
-wire soc_sdram_slave_p0_cke;
-wire soc_sdram_slave_p0_odt;
-wire soc_sdram_slave_p0_reset_n;
-wire soc_sdram_slave_p0_act_n;
-wire [31:0] soc_sdram_slave_p0_wrdata;
-wire soc_sdram_slave_p0_wrdata_en;
-wire [3:0] soc_sdram_slave_p0_wrdata_mask;
-wire soc_sdram_slave_p0_rddata_en;
-reg [31:0] soc_sdram_slave_p0_rddata = 32'd0;
-reg soc_sdram_slave_p0_rddata_valid = 1'd0;
-wire [14:0] soc_sdram_slave_p1_address;
-wire [2:0] soc_sdram_slave_p1_bank;
-wire soc_sdram_slave_p1_cas_n;
-wire soc_sdram_slave_p1_cs_n;
-wire soc_sdram_slave_p1_ras_n;
-wire soc_sdram_slave_p1_we_n;
-wire soc_sdram_slave_p1_cke;
-wire soc_sdram_slave_p1_odt;
-wire soc_sdram_slave_p1_reset_n;
-wire soc_sdram_slave_p1_act_n;
-wire [31:0] soc_sdram_slave_p1_wrdata;
-wire soc_sdram_slave_p1_wrdata_en;
-wire [3:0] soc_sdram_slave_p1_wrdata_mask;
-wire soc_sdram_slave_p1_rddata_en;
-reg [31:0] soc_sdram_slave_p1_rddata = 32'd0;
-reg soc_sdram_slave_p1_rddata_valid = 1'd0;
-wire [14:0] soc_sdram_slave_p2_address;
-wire [2:0] soc_sdram_slave_p2_bank;
-wire soc_sdram_slave_p2_cas_n;
-wire soc_sdram_slave_p2_cs_n;
-wire soc_sdram_slave_p2_ras_n;
-wire soc_sdram_slave_p2_we_n;
-wire soc_sdram_slave_p2_cke;
-wire soc_sdram_slave_p2_odt;
-wire soc_sdram_slave_p2_reset_n;
-wire soc_sdram_slave_p2_act_n;
-wire [31:0] soc_sdram_slave_p2_wrdata;
-wire soc_sdram_slave_p2_wrdata_en;
-wire [3:0] soc_sdram_slave_p2_wrdata_mask;
-wire soc_sdram_slave_p2_rddata_en;
-reg [31:0] soc_sdram_slave_p2_rddata = 32'd0;
-reg soc_sdram_slave_p2_rddata_valid = 1'd0;
-wire [14:0] soc_sdram_slave_p3_address;
-wire [2:0] soc_sdram_slave_p3_bank;
-wire soc_sdram_slave_p3_cas_n;
-wire soc_sdram_slave_p3_cs_n;
-wire soc_sdram_slave_p3_ras_n;
-wire soc_sdram_slave_p3_we_n;
-wire soc_sdram_slave_p3_cke;
-wire soc_sdram_slave_p3_odt;
-wire soc_sdram_slave_p3_reset_n;
-wire soc_sdram_slave_p3_act_n;
-wire [31:0] soc_sdram_slave_p3_wrdata;
-wire soc_sdram_slave_p3_wrdata_en;
-wire [3:0] soc_sdram_slave_p3_wrdata_mask;
-wire soc_sdram_slave_p3_rddata_en;
-reg [31:0] soc_sdram_slave_p3_rddata = 32'd0;
-reg soc_sdram_slave_p3_rddata_valid = 1'd0;
-reg [14:0] soc_sdram_master_p0_address = 15'd0;
-reg [2:0] soc_sdram_master_p0_bank = 3'd0;
-reg soc_sdram_master_p0_cas_n = 1'd1;
-reg soc_sdram_master_p0_cs_n = 1'd1;
-reg soc_sdram_master_p0_ras_n = 1'd1;
-reg soc_sdram_master_p0_we_n = 1'd1;
-reg soc_sdram_master_p0_cke = 1'd0;
-reg soc_sdram_master_p0_odt = 1'd0;
-reg soc_sdram_master_p0_reset_n = 1'd0;
-reg soc_sdram_master_p0_act_n = 1'd1;
-reg [31:0] soc_sdram_master_p0_wrdata = 32'd0;
-reg soc_sdram_master_p0_wrdata_en = 1'd0;
-reg [3:0] soc_sdram_master_p0_wrdata_mask = 4'd0;
-reg soc_sdram_master_p0_rddata_en = 1'd0;
-wire [31:0] soc_sdram_master_p0_rddata;
-wire soc_sdram_master_p0_rddata_valid;
-reg [14:0] soc_sdram_master_p1_address = 15'd0;
-reg [2:0] soc_sdram_master_p1_bank = 3'd0;
-reg soc_sdram_master_p1_cas_n = 1'd1;
-reg soc_sdram_master_p1_cs_n = 1'd1;
-reg soc_sdram_master_p1_ras_n = 1'd1;
-reg soc_sdram_master_p1_we_n = 1'd1;
-reg soc_sdram_master_p1_cke = 1'd0;
-reg soc_sdram_master_p1_odt = 1'd0;
-reg soc_sdram_master_p1_reset_n = 1'd0;
-reg soc_sdram_master_p1_act_n = 1'd1;
-reg [31:0] soc_sdram_master_p1_wrdata = 32'd0;
-reg soc_sdram_master_p1_wrdata_en = 1'd0;
-reg [3:0] soc_sdram_master_p1_wrdata_mask = 4'd0;
-reg soc_sdram_master_p1_rddata_en = 1'd0;
-wire [31:0] soc_sdram_master_p1_rddata;
-wire soc_sdram_master_p1_rddata_valid;
-reg [14:0] soc_sdram_master_p2_address = 15'd0;
-reg [2:0] soc_sdram_master_p2_bank = 3'd0;
-reg soc_sdram_master_p2_cas_n = 1'd1;
-reg soc_sdram_master_p2_cs_n = 1'd1;
-reg soc_sdram_master_p2_ras_n = 1'd1;
-reg soc_sdram_master_p2_we_n = 1'd1;
-reg soc_sdram_master_p2_cke = 1'd0;
-reg soc_sdram_master_p2_odt = 1'd0;
-reg soc_sdram_master_p2_reset_n = 1'd0;
-reg soc_sdram_master_p2_act_n = 1'd1;
-reg [31:0] soc_sdram_master_p2_wrdata = 32'd0;
-reg soc_sdram_master_p2_wrdata_en = 1'd0;
-reg [3:0] soc_sdram_master_p2_wrdata_mask = 4'd0;
-reg soc_sdram_master_p2_rddata_en = 1'd0;
-wire [31:0] soc_sdram_master_p2_rddata;
-wire soc_sdram_master_p2_rddata_valid;
-reg [14:0] soc_sdram_master_p3_address = 15'd0;
-reg [2:0] soc_sdram_master_p3_bank = 3'd0;
-reg soc_sdram_master_p3_cas_n = 1'd1;
-reg soc_sdram_master_p3_cs_n = 1'd1;
-reg soc_sdram_master_p3_ras_n = 1'd1;
-reg soc_sdram_master_p3_we_n = 1'd1;
-reg soc_sdram_master_p3_cke = 1'd0;
-reg soc_sdram_master_p3_odt = 1'd0;
-reg soc_sdram_master_p3_reset_n = 1'd0;
-reg soc_sdram_master_p3_act_n = 1'd1;
-reg [31:0] soc_sdram_master_p3_wrdata = 32'd0;
-reg soc_sdram_master_p3_wrdata_en = 1'd0;
-reg [3:0] soc_sdram_master_p3_wrdata_mask = 4'd0;
-reg soc_sdram_master_p3_rddata_en = 1'd0;
-wire [31:0] soc_sdram_master_p3_rddata;
-wire soc_sdram_master_p3_rddata_valid;
-reg [3:0] soc_sdram_storage = 4'd0;
-reg soc_sdram_re = 1'd0;
-reg [5:0] soc_sdram_phaseinjector0_command_storage = 6'd0;
-reg soc_sdram_phaseinjector0_command_re = 1'd0;
-wire soc_sdram_phaseinjector0_command_issue_re;
-wire soc_sdram_phaseinjector0_command_issue_r;
-wire soc_sdram_phaseinjector0_command_issue_we;
-reg soc_sdram_phaseinjector0_command_issue_w = 1'd0;
-reg [14:0] soc_sdram_phaseinjector0_address_storage = 15'd0;
-reg soc_sdram_phaseinjector0_address_re = 1'd0;
-reg [2:0] soc_sdram_phaseinjector0_baddress_storage = 3'd0;
-reg soc_sdram_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector0_wrdata_storage = 32'd0;
-reg soc_sdram_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector0_status = 32'd0;
-wire soc_sdram_phaseinjector0_we;
-reg [5:0] soc_sdram_phaseinjector1_command_storage = 6'd0;
-reg soc_sdram_phaseinjector1_command_re = 1'd0;
-wire soc_sdram_phaseinjector1_command_issue_re;
-wire soc_sdram_phaseinjector1_command_issue_r;
-wire soc_sdram_phaseinjector1_command_issue_we;
-reg soc_sdram_phaseinjector1_command_issue_w = 1'd0;
-reg [14:0] soc_sdram_phaseinjector1_address_storage = 15'd0;
-reg soc_sdram_phaseinjector1_address_re = 1'd0;
-reg [2:0] soc_sdram_phaseinjector1_baddress_storage = 3'd0;
-reg soc_sdram_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector1_wrdata_storage = 32'd0;
-reg soc_sdram_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector1_status = 32'd0;
-wire soc_sdram_phaseinjector1_we;
-reg [5:0] soc_sdram_phaseinjector2_command_storage = 6'd0;
-reg soc_sdram_phaseinjector2_command_re = 1'd0;
-wire soc_sdram_phaseinjector2_command_issue_re;
-wire soc_sdram_phaseinjector2_command_issue_r;
-wire soc_sdram_phaseinjector2_command_issue_we;
-reg soc_sdram_phaseinjector2_command_issue_w = 1'd0;
-reg [14:0] soc_sdram_phaseinjector2_address_storage = 15'd0;
-reg soc_sdram_phaseinjector2_address_re = 1'd0;
-reg [2:0] soc_sdram_phaseinjector2_baddress_storage = 3'd0;
-reg soc_sdram_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector2_wrdata_storage = 32'd0;
-reg soc_sdram_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector2_status = 32'd0;
-wire soc_sdram_phaseinjector2_we;
-reg [5:0] soc_sdram_phaseinjector3_command_storage = 6'd0;
-reg soc_sdram_phaseinjector3_command_re = 1'd0;
-wire soc_sdram_phaseinjector3_command_issue_re;
-wire soc_sdram_phaseinjector3_command_issue_r;
-wire soc_sdram_phaseinjector3_command_issue_we;
-reg soc_sdram_phaseinjector3_command_issue_w = 1'd0;
-reg [14:0] soc_sdram_phaseinjector3_address_storage = 15'd0;
-reg soc_sdram_phaseinjector3_address_re = 1'd0;
-reg [2:0] soc_sdram_phaseinjector3_baddress_storage = 3'd0;
-reg soc_sdram_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector3_wrdata_storage = 32'd0;
-reg soc_sdram_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] soc_sdram_phaseinjector3_status = 32'd0;
-wire soc_sdram_phaseinjector3_we;
-wire soc_sdram_interface_bank0_valid;
-wire soc_sdram_interface_bank0_ready;
-wire soc_sdram_interface_bank0_we;
-wire [21:0] soc_sdram_interface_bank0_addr;
-wire soc_sdram_interface_bank0_lock;
-wire soc_sdram_interface_bank0_wdata_ready;
-wire soc_sdram_interface_bank0_rdata_valid;
-wire soc_sdram_interface_bank1_valid;
-wire soc_sdram_interface_bank1_ready;
-wire soc_sdram_interface_bank1_we;
-wire [21:0] soc_sdram_interface_bank1_addr;
-wire soc_sdram_interface_bank1_lock;
-wire soc_sdram_interface_bank1_wdata_ready;
-wire soc_sdram_interface_bank1_rdata_valid;
-wire soc_sdram_interface_bank2_valid;
-wire soc_sdram_interface_bank2_ready;
-wire soc_sdram_interface_bank2_we;
-wire [21:0] soc_sdram_interface_bank2_addr;
-wire soc_sdram_interface_bank2_lock;
-wire soc_sdram_interface_bank2_wdata_ready;
-wire soc_sdram_interface_bank2_rdata_valid;
-wire soc_sdram_interface_bank3_valid;
-wire soc_sdram_interface_bank3_ready;
-wire soc_sdram_interface_bank3_we;
-wire [21:0] soc_sdram_interface_bank3_addr;
-wire soc_sdram_interface_bank3_lock;
-wire soc_sdram_interface_bank3_wdata_ready;
-wire soc_sdram_interface_bank3_rdata_valid;
-wire soc_sdram_interface_bank4_valid;
-wire soc_sdram_interface_bank4_ready;
-wire soc_sdram_interface_bank4_we;
-wire [21:0] soc_sdram_interface_bank4_addr;
-wire soc_sdram_interface_bank4_lock;
-wire soc_sdram_interface_bank4_wdata_ready;
-wire soc_sdram_interface_bank4_rdata_valid;
-wire soc_sdram_interface_bank5_valid;
-wire soc_sdram_interface_bank5_ready;
-wire soc_sdram_interface_bank5_we;
-wire [21:0] soc_sdram_interface_bank5_addr;
-wire soc_sdram_interface_bank5_lock;
-wire soc_sdram_interface_bank5_wdata_ready;
-wire soc_sdram_interface_bank5_rdata_valid;
-wire soc_sdram_interface_bank6_valid;
-wire soc_sdram_interface_bank6_ready;
-wire soc_sdram_interface_bank6_we;
-wire [21:0] soc_sdram_interface_bank6_addr;
-wire soc_sdram_interface_bank6_lock;
-wire soc_sdram_interface_bank6_wdata_ready;
-wire soc_sdram_interface_bank6_rdata_valid;
-wire soc_sdram_interface_bank7_valid;
-wire soc_sdram_interface_bank7_ready;
-wire soc_sdram_interface_bank7_we;
-wire [21:0] soc_sdram_interface_bank7_addr;
-wire soc_sdram_interface_bank7_lock;
-wire soc_sdram_interface_bank7_wdata_ready;
-wire soc_sdram_interface_bank7_rdata_valid;
-reg [127:0] soc_sdram_interface_wdata = 128'd0;
-reg [15:0] soc_sdram_interface_wdata_we = 16'd0;
-wire [127:0] soc_sdram_interface_rdata;
-reg [14:0] soc_sdram_dfi_p0_address = 15'd0;
-reg [2:0] soc_sdram_dfi_p0_bank = 3'd0;
-reg soc_sdram_dfi_p0_cas_n = 1'd1;
-reg soc_sdram_dfi_p0_cs_n = 1'd1;
-reg soc_sdram_dfi_p0_ras_n = 1'd1;
-reg soc_sdram_dfi_p0_we_n = 1'd1;
-wire soc_sdram_dfi_p0_cke;
-wire soc_sdram_dfi_p0_odt;
-wire soc_sdram_dfi_p0_reset_n;
-reg soc_sdram_dfi_p0_act_n = 1'd1;
-wire [31:0] soc_sdram_dfi_p0_wrdata;
-reg soc_sdram_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] soc_sdram_dfi_p0_wrdata_mask;
-reg soc_sdram_dfi_p0_rddata_en = 1'd0;
-wire [31:0] soc_sdram_dfi_p0_rddata;
-wire soc_sdram_dfi_p0_rddata_valid;
-reg [14:0] soc_sdram_dfi_p1_address = 15'd0;
-reg [2:0] soc_sdram_dfi_p1_bank = 3'd0;
-reg soc_sdram_dfi_p1_cas_n = 1'd1;
-reg soc_sdram_dfi_p1_cs_n = 1'd1;
-reg soc_sdram_dfi_p1_ras_n = 1'd1;
-reg soc_sdram_dfi_p1_we_n = 1'd1;
-wire soc_sdram_dfi_p1_cke;
-wire soc_sdram_dfi_p1_odt;
-wire soc_sdram_dfi_p1_reset_n;
-reg soc_sdram_dfi_p1_act_n = 1'd1;
-wire [31:0] soc_sdram_dfi_p1_wrdata;
-reg soc_sdram_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] soc_sdram_dfi_p1_wrdata_mask;
-reg soc_sdram_dfi_p1_rddata_en = 1'd0;
-wire [31:0] soc_sdram_dfi_p1_rddata;
-wire soc_sdram_dfi_p1_rddata_valid;
-reg [14:0] soc_sdram_dfi_p2_address = 15'd0;
-reg [2:0] soc_sdram_dfi_p2_bank = 3'd0;
-reg soc_sdram_dfi_p2_cas_n = 1'd1;
-reg soc_sdram_dfi_p2_cs_n = 1'd1;
-reg soc_sdram_dfi_p2_ras_n = 1'd1;
-reg soc_sdram_dfi_p2_we_n = 1'd1;
-wire soc_sdram_dfi_p2_cke;
-wire soc_sdram_dfi_p2_odt;
-wire soc_sdram_dfi_p2_reset_n;
-reg soc_sdram_dfi_p2_act_n = 1'd1;
-wire [31:0] soc_sdram_dfi_p2_wrdata;
-reg soc_sdram_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] soc_sdram_dfi_p2_wrdata_mask;
-reg soc_sdram_dfi_p2_rddata_en = 1'd0;
-wire [31:0] soc_sdram_dfi_p2_rddata;
-wire soc_sdram_dfi_p2_rddata_valid;
-reg [14:0] soc_sdram_dfi_p3_address = 15'd0;
-reg [2:0] soc_sdram_dfi_p3_bank = 3'd0;
-reg soc_sdram_dfi_p3_cas_n = 1'd1;
-reg soc_sdram_dfi_p3_cs_n = 1'd1;
-reg soc_sdram_dfi_p3_ras_n = 1'd1;
-reg soc_sdram_dfi_p3_we_n = 1'd1;
-wire soc_sdram_dfi_p3_cke;
-wire soc_sdram_dfi_p3_odt;
-wire soc_sdram_dfi_p3_reset_n;
-reg soc_sdram_dfi_p3_act_n = 1'd1;
-wire [31:0] soc_sdram_dfi_p3_wrdata;
-reg soc_sdram_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] soc_sdram_dfi_p3_wrdata_mask;
-reg soc_sdram_dfi_p3_rddata_en = 1'd0;
-wire [31:0] soc_sdram_dfi_p3_rddata;
-wire soc_sdram_dfi_p3_rddata_valid;
-reg soc_sdram_cmd_valid = 1'd0;
-reg soc_sdram_cmd_ready = 1'd0;
-reg soc_sdram_cmd_last = 1'd0;
-reg [14:0] soc_sdram_cmd_payload_a = 15'd0;
-reg [2:0] soc_sdram_cmd_payload_ba = 3'd0;
-reg soc_sdram_cmd_payload_cas = 1'd0;
-reg soc_sdram_cmd_payload_ras = 1'd0;
-reg soc_sdram_cmd_payload_we = 1'd0;
-reg soc_sdram_cmd_payload_is_read = 1'd0;
-reg soc_sdram_cmd_payload_is_write = 1'd0;
-wire soc_sdram_wants_refresh;
-wire soc_sdram_wants_zqcs;
-wire soc_sdram_timer_wait;
-wire soc_sdram_timer_done0;
-wire [9:0] soc_sdram_timer_count0;
-wire soc_sdram_timer_done1;
-reg [9:0] soc_sdram_timer_count1 = 10'd781;
-wire soc_sdram_postponer_req_i;
-reg soc_sdram_postponer_req_o = 1'd0;
-reg soc_sdram_postponer_count = 1'd0;
-reg soc_sdram_sequencer_start0 = 1'd0;
-wire soc_sdram_sequencer_done0;
-wire soc_sdram_sequencer_start1;
-reg soc_sdram_sequencer_done1 = 1'd0;
-reg [5:0] soc_sdram_sequencer_counter = 6'd0;
-reg soc_sdram_sequencer_count = 1'd0;
-wire soc_sdram_zqcs_timer_wait;
-wire soc_sdram_zqcs_timer_done0;
-wire [26:0] soc_sdram_zqcs_timer_count0;
-wire soc_sdram_zqcs_timer_done1;
-reg [26:0] soc_sdram_zqcs_timer_count1 = 27'd99999999;
-reg soc_sdram_zqcs_executer_start = 1'd0;
-reg soc_sdram_zqcs_executer_done = 1'd0;
-reg [4:0] soc_sdram_zqcs_executer_counter = 5'd0;
-wire soc_sdram_bankmachine0_req_valid;
-wire soc_sdram_bankmachine0_req_ready;
-wire soc_sdram_bankmachine0_req_we;
-wire [21:0] soc_sdram_bankmachine0_req_addr;
-wire soc_sdram_bankmachine0_req_lock;
-reg soc_sdram_bankmachine0_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine0_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine0_refresh_req;
-reg soc_sdram_bankmachine0_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine0_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine0_cmd_ready = 1'd0;
-reg [14:0] soc_sdram_bankmachine0_cmd_payload_a = 15'd0;
-wire [2:0] soc_sdram_bankmachine0_cmd_payload_ba;
-reg soc_sdram_bankmachine0_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine0_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine0_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine0_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine0_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine0_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine0_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine0_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine0_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine0_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine0_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] soc_sdram_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] soc_sdram_bankmachine0_row = 15'd0;
-reg soc_sdram_bankmachine0_row_opened = 1'd0;
-wire soc_sdram_bankmachine0_row_hit;
-reg soc_sdram_bankmachine0_row_open = 1'd0;
-reg soc_sdram_bankmachine0_row_close = 1'd0;
-reg soc_sdram_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine0_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine0_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine0_trccon_count = 3'd0;
-wire soc_sdram_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine0_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine0_trascon_count = 3'd0;
-wire soc_sdram_bankmachine1_req_valid;
-wire soc_sdram_bankmachine1_req_ready;
-wire soc_sdram_bankmachine1_req_we;
-wire [21:0] soc_sdram_bankmachine1_req_addr;
-wire soc_sdram_bankmachine1_req_lock;
-reg soc_sdram_bankmachine1_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine1_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine1_refresh_req;
-reg soc_sdram_bankmachine1_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine1_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine1_cmd_ready = 1'd0;
-reg [14:0] soc_sdram_bankmachine1_cmd_payload_a = 15'd0;
-wire [2:0] soc_sdram_bankmachine1_cmd_payload_ba;
-reg soc_sdram_bankmachine1_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine1_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine1_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine1_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine1_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine1_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine1_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine1_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine1_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine1_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine1_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] soc_sdram_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] soc_sdram_bankmachine1_row = 15'd0;
-reg soc_sdram_bankmachine1_row_opened = 1'd0;
-wire soc_sdram_bankmachine1_row_hit;
-reg soc_sdram_bankmachine1_row_open = 1'd0;
-reg soc_sdram_bankmachine1_row_close = 1'd0;
-reg soc_sdram_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine1_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine1_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine1_trccon_count = 3'd0;
-wire soc_sdram_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine1_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine1_trascon_count = 3'd0;
-wire soc_sdram_bankmachine2_req_valid;
-wire soc_sdram_bankmachine2_req_ready;
-wire soc_sdram_bankmachine2_req_we;
-wire [21:0] soc_sdram_bankmachine2_req_addr;
-wire soc_sdram_bankmachine2_req_lock;
-reg soc_sdram_bankmachine2_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine2_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine2_refresh_req;
-reg soc_sdram_bankmachine2_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine2_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine2_cmd_ready = 1'd0;
-reg [14:0] soc_sdram_bankmachine2_cmd_payload_a = 15'd0;
-wire [2:0] soc_sdram_bankmachine2_cmd_payload_ba;
-reg soc_sdram_bankmachine2_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine2_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine2_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine2_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine2_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine2_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine2_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine2_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine2_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine2_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine2_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] soc_sdram_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] soc_sdram_bankmachine2_row = 15'd0;
-reg soc_sdram_bankmachine2_row_opened = 1'd0;
-wire soc_sdram_bankmachine2_row_hit;
-reg soc_sdram_bankmachine2_row_open = 1'd0;
-reg soc_sdram_bankmachine2_row_close = 1'd0;
-reg soc_sdram_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine2_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine2_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine2_trccon_count = 3'd0;
-wire soc_sdram_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine2_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine2_trascon_count = 3'd0;
-wire soc_sdram_bankmachine3_req_valid;
-wire soc_sdram_bankmachine3_req_ready;
-wire soc_sdram_bankmachine3_req_we;
-wire [21:0] soc_sdram_bankmachine3_req_addr;
-wire soc_sdram_bankmachine3_req_lock;
-reg soc_sdram_bankmachine3_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine3_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine3_refresh_req;
-reg soc_sdram_bankmachine3_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine3_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine3_cmd_ready = 1'd0;
-reg [14:0] soc_sdram_bankmachine3_cmd_payload_a = 15'd0;
-wire [2:0] soc_sdram_bankmachine3_cmd_payload_ba;
-reg soc_sdram_bankmachine3_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine3_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine3_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine3_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine3_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine3_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine3_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine3_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine3_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine3_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine3_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] soc_sdram_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] soc_sdram_bankmachine3_row = 15'd0;
-reg soc_sdram_bankmachine3_row_opened = 1'd0;
-wire soc_sdram_bankmachine3_row_hit;
-reg soc_sdram_bankmachine3_row_open = 1'd0;
-reg soc_sdram_bankmachine3_row_close = 1'd0;
-reg soc_sdram_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine3_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine3_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine3_trccon_count = 3'd0;
-wire soc_sdram_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine3_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine3_trascon_count = 3'd0;
-wire soc_sdram_bankmachine4_req_valid;
-wire soc_sdram_bankmachine4_req_ready;
-wire soc_sdram_bankmachine4_req_we;
-wire [21:0] soc_sdram_bankmachine4_req_addr;
-wire soc_sdram_bankmachine4_req_lock;
-reg soc_sdram_bankmachine4_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine4_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine4_refresh_req;
-reg soc_sdram_bankmachine4_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine4_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine4_cmd_ready = 1'd0;
-reg [14:0] soc_sdram_bankmachine4_cmd_payload_a = 15'd0;
-wire [2:0] soc_sdram_bankmachine4_cmd_payload_ba;
-reg soc_sdram_bankmachine4_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine4_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine4_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine4_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine4_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine4_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine4_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine4_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine4_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine4_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine4_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] soc_sdram_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] soc_sdram_bankmachine4_row = 15'd0;
-reg soc_sdram_bankmachine4_row_opened = 1'd0;
-wire soc_sdram_bankmachine4_row_hit;
-reg soc_sdram_bankmachine4_row_open = 1'd0;
-reg soc_sdram_bankmachine4_row_close = 1'd0;
-reg soc_sdram_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine4_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine4_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine4_trccon_count = 3'd0;
-wire soc_sdram_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine4_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine4_trascon_count = 3'd0;
-wire soc_sdram_bankmachine5_req_valid;
-wire soc_sdram_bankmachine5_req_ready;
-wire soc_sdram_bankmachine5_req_we;
-wire [21:0] soc_sdram_bankmachine5_req_addr;
-wire soc_sdram_bankmachine5_req_lock;
-reg soc_sdram_bankmachine5_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine5_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine5_refresh_req;
-reg soc_sdram_bankmachine5_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine5_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine5_cmd_ready = 1'd0;
-reg [14:0] soc_sdram_bankmachine5_cmd_payload_a = 15'd0;
-wire [2:0] soc_sdram_bankmachine5_cmd_payload_ba;
-reg soc_sdram_bankmachine5_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine5_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine5_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine5_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine5_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine5_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine5_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine5_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine5_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine5_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine5_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] soc_sdram_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] soc_sdram_bankmachine5_row = 15'd0;
-reg soc_sdram_bankmachine5_row_opened = 1'd0;
-wire soc_sdram_bankmachine5_row_hit;
-reg soc_sdram_bankmachine5_row_open = 1'd0;
-reg soc_sdram_bankmachine5_row_close = 1'd0;
-reg soc_sdram_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine5_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine5_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine5_trccon_count = 3'd0;
-wire soc_sdram_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine5_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine5_trascon_count = 3'd0;
-wire soc_sdram_bankmachine6_req_valid;
-wire soc_sdram_bankmachine6_req_ready;
-wire soc_sdram_bankmachine6_req_we;
-wire [21:0] soc_sdram_bankmachine6_req_addr;
-wire soc_sdram_bankmachine6_req_lock;
-reg soc_sdram_bankmachine6_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine6_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine6_refresh_req;
-reg soc_sdram_bankmachine6_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine6_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine6_cmd_ready = 1'd0;
-reg [14:0] soc_sdram_bankmachine6_cmd_payload_a = 15'd0;
-wire [2:0] soc_sdram_bankmachine6_cmd_payload_ba;
-reg soc_sdram_bankmachine6_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine6_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine6_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine6_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine6_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine6_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine6_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine6_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine6_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine6_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine6_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] soc_sdram_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] soc_sdram_bankmachine6_row = 15'd0;
-reg soc_sdram_bankmachine6_row_opened = 1'd0;
-wire soc_sdram_bankmachine6_row_hit;
-reg soc_sdram_bankmachine6_row_open = 1'd0;
-reg soc_sdram_bankmachine6_row_close = 1'd0;
-reg soc_sdram_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine6_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine6_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine6_trccon_count = 3'd0;
-wire soc_sdram_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine6_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine6_trascon_count = 3'd0;
-wire soc_sdram_bankmachine7_req_valid;
-wire soc_sdram_bankmachine7_req_ready;
-wire soc_sdram_bankmachine7_req_we;
-wire [21:0] soc_sdram_bankmachine7_req_addr;
-wire soc_sdram_bankmachine7_req_lock;
-reg soc_sdram_bankmachine7_req_wdata_ready = 1'd0;
-reg soc_sdram_bankmachine7_req_rdata_valid = 1'd0;
-wire soc_sdram_bankmachine7_refresh_req;
-reg soc_sdram_bankmachine7_refresh_gnt = 1'd0;
-reg soc_sdram_bankmachine7_cmd_valid = 1'd0;
-reg soc_sdram_bankmachine7_cmd_ready = 1'd0;
-reg [14:0] soc_sdram_bankmachine7_cmd_payload_a = 15'd0;
-wire [2:0] soc_sdram_bankmachine7_cmd_payload_ba;
-reg soc_sdram_bankmachine7_cmd_payload_cas = 1'd0;
-reg soc_sdram_bankmachine7_cmd_payload_ras = 1'd0;
-reg soc_sdram_bankmachine7_cmd_payload_we = 1'd0;
-reg soc_sdram_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg soc_sdram_bankmachine7_cmd_payload_is_read = 1'd0;
-reg soc_sdram_bankmachine7_cmd_payload_is_write = 1'd0;
-reg soc_sdram_bankmachine7_auto_precharge = 1'd0;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg soc_sdram_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire soc_sdram_bankmachine7_cmd_buffer_sink_valid;
-wire soc_sdram_bankmachine7_cmd_buffer_sink_ready;
-wire soc_sdram_bankmachine7_cmd_buffer_sink_first;
-wire soc_sdram_bankmachine7_cmd_buffer_sink_last;
-wire soc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
-wire [21:0] soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
-reg soc_sdram_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire soc_sdram_bankmachine7_cmd_buffer_source_ready;
-reg soc_sdram_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg soc_sdram_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg soc_sdram_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] soc_sdram_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] soc_sdram_bankmachine7_row = 15'd0;
-reg soc_sdram_bankmachine7_row_opened = 1'd0;
-wire soc_sdram_bankmachine7_row_hit;
-reg soc_sdram_bankmachine7_row_open = 1'd0;
-reg soc_sdram_bankmachine7_row_close = 1'd0;
-reg soc_sdram_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire soc_sdram_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine7_twtpcon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine7_twtpcon_count = 3'd0;
-wire soc_sdram_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trccon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine7_trccon_count = 3'd0;
-wire soc_sdram_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg soc_sdram_bankmachine7_trascon_ready = 1'd1;
-reg [2:0] soc_sdram_bankmachine7_trascon_count = 3'd0;
-wire soc_sdram_ras_allowed;
-wire soc_sdram_cas_allowed;
-reg soc_sdram_choose_cmd_want_reads = 1'd0;
-reg soc_sdram_choose_cmd_want_writes = 1'd0;
-reg soc_sdram_choose_cmd_want_cmds = 1'd0;
-reg soc_sdram_choose_cmd_want_activates = 1'd0;
-wire soc_sdram_choose_cmd_cmd_valid;
-reg soc_sdram_choose_cmd_cmd_ready = 1'd0;
-wire [14:0] soc_sdram_choose_cmd_cmd_payload_a;
-wire [2:0] soc_sdram_choose_cmd_cmd_payload_ba;
-reg soc_sdram_choose_cmd_cmd_payload_cas = 1'd0;
-reg soc_sdram_choose_cmd_cmd_payload_ras = 1'd0;
-reg soc_sdram_choose_cmd_cmd_payload_we = 1'd0;
-wire soc_sdram_choose_cmd_cmd_payload_is_cmd;
-wire soc_sdram_choose_cmd_cmd_payload_is_read;
-wire soc_sdram_choose_cmd_cmd_payload_is_write;
-reg [7:0] soc_sdram_choose_cmd_valids = 8'd0;
-wire [7:0] soc_sdram_choose_cmd_request;
-reg [2:0] soc_sdram_choose_cmd_grant = 3'd0;
-wire soc_sdram_choose_cmd_ce;
-reg soc_sdram_choose_req_want_reads = 1'd0;
-reg soc_sdram_choose_req_want_writes = 1'd0;
-reg soc_sdram_choose_req_want_cmds = 1'd0;
-reg soc_sdram_choose_req_want_activates = 1'd0;
-wire soc_sdram_choose_req_cmd_valid;
-reg soc_sdram_choose_req_cmd_ready = 1'd0;
-wire [14:0] soc_sdram_choose_req_cmd_payload_a;
-wire [2:0] soc_sdram_choose_req_cmd_payload_ba;
-reg soc_sdram_choose_req_cmd_payload_cas = 1'd0;
-reg soc_sdram_choose_req_cmd_payload_ras = 1'd0;
-reg soc_sdram_choose_req_cmd_payload_we = 1'd0;
-wire soc_sdram_choose_req_cmd_payload_is_cmd;
-wire soc_sdram_choose_req_cmd_payload_is_read;
-wire soc_sdram_choose_req_cmd_payload_is_write;
-reg [7:0] soc_sdram_choose_req_valids = 8'd0;
-wire [7:0] soc_sdram_choose_req_request;
-reg [2:0] soc_sdram_choose_req_grant = 3'd0;
-wire soc_sdram_choose_req_ce;
-reg [14:0] soc_sdram_nop_a = 15'd0;
-reg [2:0] soc_sdram_nop_ba = 3'd0;
-reg [1:0] soc_sdram_steerer_sel0 = 2'd0;
-reg [1:0] soc_sdram_steerer_sel1 = 2'd0;
-reg [1:0] soc_sdram_steerer_sel2 = 2'd0;
-reg [1:0] soc_sdram_steerer_sel3 = 2'd0;
-reg soc_sdram_steerer0 = 1'd1;
-reg soc_sdram_steerer1 = 1'd1;
-reg soc_sdram_steerer2 = 1'd1;
-reg soc_sdram_steerer3 = 1'd1;
-reg soc_sdram_steerer4 = 1'd1;
-reg soc_sdram_steerer5 = 1'd1;
-reg soc_sdram_steerer6 = 1'd1;
-reg soc_sdram_steerer7 = 1'd1;
-wire soc_sdram_trrdcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_trrdcon_ready = 1'd1;
-reg soc_sdram_trrdcon_count = 1'd0;
-wire soc_sdram_tfawcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_tfawcon_ready = 1'd1;
-wire [2:0] soc_sdram_tfawcon_count;
-reg [4:0] soc_sdram_tfawcon_window = 5'd0;
-wire soc_sdram_tccdcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_tccdcon_ready = 1'd1;
-reg soc_sdram_tccdcon_count = 1'd0;
-wire soc_sdram_twtrcon_valid;
-(* dont_touch = "true" *) reg soc_sdram_twtrcon_ready = 1'd1;
-reg [2:0] soc_sdram_twtrcon_count = 3'd0;
-wire soc_sdram_read_available;
-wire soc_sdram_write_available;
-reg soc_sdram_en0 = 1'd0;
-wire soc_sdram_max_time0;
-reg [4:0] soc_sdram_time0 = 5'd0;
-reg soc_sdram_en1 = 1'd0;
-wire soc_sdram_max_time1;
-reg [3:0] soc_sdram_time1 = 4'd0;
-wire soc_sdram_go_to_refresh;
-reg soc_port_cmd_valid = 1'd0;
-wire soc_port_cmd_ready;
-reg soc_port_cmd_payload_we = 1'd0;
-reg [24:0] soc_port_cmd_payload_addr = 25'd0;
-wire soc_port_wdata_valid;
-wire soc_port_wdata_ready;
-wire soc_port_wdata_first;
-wire soc_port_wdata_last;
-wire [127:0] soc_port_wdata_payload_data;
-wire [15:0] soc_port_wdata_payload_we;
-wire soc_port_rdata_valid;
-wire soc_port_rdata_ready;
-reg soc_port_rdata_first = 1'd0;
-reg soc_port_rdata_last = 1'd0;
-wire [127:0] soc_port_rdata_payload_data;
-wire [29:0] soc_wb_sdram_adr;
-wire [31:0] soc_wb_sdram_dat_w;
-reg [31:0] soc_wb_sdram_dat_r = 32'd0;
-wire [3:0] soc_wb_sdram_sel;
-wire soc_wb_sdram_cyc;
-wire soc_wb_sdram_stb;
-reg soc_wb_sdram_ack = 1'd0;
-wire soc_wb_sdram_we;
-wire [2:0] soc_wb_sdram_cti;
-wire [1:0] soc_wb_sdram_bte;
-reg soc_wb_sdram_err = 1'd0;
-wire [29:0] soc_litedram_wb_adr;
-reg [127:0] soc_litedram_wb_dat_w = 128'd0;
-wire [127:0] soc_litedram_wb_dat_r;
-reg [15:0] soc_litedram_wb_sel = 16'd0;
-reg soc_litedram_wb_cyc = 1'd0;
-reg soc_litedram_wb_stb = 1'd0;
-reg soc_litedram_wb_ack = 1'd0;
-reg soc_litedram_wb_we = 1'd0;
-wire [2:0] soc_litedram_wb_cti;
-reg soc_write = 1'd0;
-reg soc_evict = 1'd0;
-reg soc_refill = 1'd0;
-reg soc_read = 1'd0;
-wire [29:0] soc_address_d;
-reg [29:0] soc_address_q = 30'd0;
-reg soc_address_ce = 1'd0;
-reg soc_address_reset = 1'd0;
-reg [1:0] soc_counter = 2'd0;
-reg soc_counter_ce = 1'd0;
-reg soc_counter_reset = 1'd0;
-wire [1:0] soc_counter_offset;
-wire soc_counter_done;
-wire [127:0] soc_cached_data;
-wire [15:0] soc_cached_sel;
-wire soc_end_of_burst;
-wire soc_need_refill_d;
-reg soc_need_refill_q = 1'd1;
-reg soc_need_refill_ce = 1'd0;
-wire soc_need_refill_reset;
-reg [31:0] soc_cached_datas_flipflop0_d = 32'd0;
-reg [31:0] soc_cached_datas_flipflop0_q = 32'd0;
-reg soc_cached_datas_ce0 = 1'd0;
-reg soc_cached_datas_reset0 = 1'd0;
-reg [31:0] soc_cached_datas_flipflop1_d = 32'd0;
-reg [31:0] soc_cached_datas_flipflop1_q = 32'd0;
-reg soc_cached_datas_ce1 = 1'd0;
-reg soc_cached_datas_reset1 = 1'd0;
-reg [31:0] soc_cached_datas_flipflop2_d = 32'd0;
-reg [31:0] soc_cached_datas_flipflop2_q = 32'd0;
-reg soc_cached_datas_ce2 = 1'd0;
-reg soc_cached_datas_reset2 = 1'd0;
-reg [31:0] soc_cached_datas_flipflop3_d = 32'd0;
-reg [31:0] soc_cached_datas_flipflop3_q = 32'd0;
-reg soc_cached_datas_ce3 = 1'd0;
-reg soc_cached_datas_reset3 = 1'd0;
-wire [3:0] soc_cached_sels_flipflop0_d;
-reg [3:0] soc_cached_sels_flipflop0_q = 4'd0;
-reg soc_cached_sels_ce0 = 1'd0;
-wire soc_cached_sels_reset0;
-wire [3:0] soc_cached_sels_flipflop1_d;
-reg [3:0] soc_cached_sels_flipflop1_q = 4'd0;
-reg soc_cached_sels_ce1 = 1'd0;
-wire soc_cached_sels_reset1;
-wire [3:0] soc_cached_sels_flipflop2_d;
-reg [3:0] soc_cached_sels_flipflop2_q = 4'd0;
-reg soc_cached_sels_ce2 = 1'd0;
-wire soc_cached_sels_reset2;
-wire [3:0] soc_cached_sels_flipflop3_d;
-reg [3:0] soc_cached_sels_flipflop3_q = 4'd0;
-reg soc_cached_sels_ce3 = 1'd0;
-wire soc_cached_sels_reset3;
-reg soc_write_sel0 = 1'd0;
-reg soc_write_sel1 = 1'd0;
-reg soc_write_sel2 = 1'd0;
-reg soc_write_sel3 = 1'd0;
-wire soc_wdata_converter_sink_valid;
-wire soc_wdata_converter_sink_ready;
-reg soc_wdata_converter_sink_first = 1'd0;
-reg soc_wdata_converter_sink_last = 1'd0;
-wire [127:0] soc_wdata_converter_sink_payload_data;
-wire [15:0] soc_wdata_converter_sink_payload_we;
-wire soc_wdata_converter_source_valid;
-wire soc_wdata_converter_source_ready;
-wire soc_wdata_converter_source_first;
-wire soc_wdata_converter_source_last;
-wire [127:0] soc_wdata_converter_source_payload_data;
-wire [15:0] soc_wdata_converter_source_payload_we;
-wire soc_wdata_converter_converter_sink_valid;
-wire soc_wdata_converter_converter_sink_ready;
-wire soc_wdata_converter_converter_sink_first;
-wire soc_wdata_converter_converter_sink_last;
-wire [143:0] soc_wdata_converter_converter_sink_payload_data;
-wire soc_wdata_converter_converter_source_valid;
-wire soc_wdata_converter_converter_source_ready;
-wire soc_wdata_converter_converter_source_first;
-wire soc_wdata_converter_converter_source_last;
-wire [143:0] soc_wdata_converter_converter_source_payload_data;
-wire soc_wdata_converter_converter_source_payload_valid_token_count;
-wire soc_wdata_converter_source_source_valid;
-wire soc_wdata_converter_source_source_ready;
-wire soc_wdata_converter_source_source_first;
-wire soc_wdata_converter_source_source_last;
-wire [143:0] soc_wdata_converter_source_source_payload_data;
-wire soc_rdata_converter_sink_valid;
-wire soc_rdata_converter_sink_ready;
-wire soc_rdata_converter_sink_first;
-wire soc_rdata_converter_sink_last;
-wire [127:0] soc_rdata_converter_sink_payload_data;
-wire soc_rdata_converter_source_valid;
-wire soc_rdata_converter_source_ready;
-wire soc_rdata_converter_source_first;
-wire soc_rdata_converter_source_last;
-wire [127:0] soc_rdata_converter_source_payload_data;
-wire soc_rdata_converter_converter_sink_valid;
-wire soc_rdata_converter_converter_sink_ready;
-wire soc_rdata_converter_converter_sink_first;
-wire soc_rdata_converter_converter_sink_last;
-wire [127:0] soc_rdata_converter_converter_sink_payload_data;
-wire soc_rdata_converter_converter_source_valid;
-wire soc_rdata_converter_converter_source_ready;
-wire soc_rdata_converter_converter_source_first;
-wire soc_rdata_converter_converter_source_last;
-wire [127:0] soc_rdata_converter_converter_source_payload_data;
-wire soc_rdata_converter_converter_source_payload_valid_token_count;
-wire soc_rdata_converter_source_source_valid;
-wire soc_rdata_converter_source_source_ready;
-wire soc_rdata_converter_source_source_first;
-wire soc_rdata_converter_source_source_last;
-wire [127:0] soc_rdata_converter_source_source_payload_data;
-reg soc_count = 1'd0;
-reg soc_init_done_storage = 1'd0;
-reg soc_init_done_re = 1'd0;
-reg soc_init_error_storage = 1'd0;
-reg soc_init_error_re = 1'd0;
-wire soc_cmd_valid;
-wire soc_cmd_ready;
-wire soc_cmd_payload_we;
-wire [24:0] soc_cmd_payload_addr;
-wire soc_wdata_valid;
-wire soc_wdata_ready;
-wire [127:0] soc_wdata_payload_data;
-wire [15:0] soc_wdata_payload_we;
-wire soc_rdata_valid;
-wire soc_rdata_ready;
-wire [127:0] soc_rdata_payload_data;
-reg vns_wb2csr_state = 1'd0;
-reg vns_wb2csr_next_state = 1'd0;
-wire vns_pll_fb0;
-wire vns_pll_fb1;
-reg [1:0] vns_refresher_state = 2'd0;
-reg [1:0] vns_refresher_next_state = 2'd0;
-reg [3:0] vns_bankmachine0_state = 4'd0;
-reg [3:0] vns_bankmachine0_next_state = 4'd0;
-reg [3:0] vns_bankmachine1_state = 4'd0;
-reg [3:0] vns_bankmachine1_next_state = 4'd0;
-reg [3:0] vns_bankmachine2_state = 4'd0;
-reg [3:0] vns_bankmachine2_next_state = 4'd0;
-reg [3:0] vns_bankmachine3_state = 4'd0;
-reg [3:0] vns_bankmachine3_next_state = 4'd0;
-reg [3:0] vns_bankmachine4_state = 4'd0;
-reg [3:0] vns_bankmachine4_next_state = 4'd0;
-reg [3:0] vns_bankmachine5_state = 4'd0;
-reg [3:0] vns_bankmachine5_next_state = 4'd0;
-reg [3:0] vns_bankmachine6_state = 4'd0;
-reg [3:0] vns_bankmachine6_next_state = 4'd0;
-reg [3:0] vns_bankmachine7_state = 4'd0;
-reg [3:0] vns_bankmachine7_next_state = 4'd0;
-reg [3:0] vns_multiplexer_state = 4'd0;
-reg [3:0] vns_multiplexer_next_state = 4'd0;
-wire [1:0] vns_roundrobin0_request;
-reg vns_roundrobin0_grant = 1'd0;
-wire vns_roundrobin0_ce;
-wire [1:0] vns_roundrobin1_request;
-reg vns_roundrobin1_grant = 1'd0;
-wire vns_roundrobin1_ce;
-wire [1:0] vns_roundrobin2_request;
-reg vns_roundrobin2_grant = 1'd0;
-wire vns_roundrobin2_ce;
-wire [1:0] vns_roundrobin3_request;
-reg vns_roundrobin3_grant = 1'd0;
-wire vns_roundrobin3_ce;
-wire [1:0] vns_roundrobin4_request;
-reg vns_roundrobin4_grant = 1'd0;
-wire vns_roundrobin4_ce;
-wire [1:0] vns_roundrobin5_request;
-reg vns_roundrobin5_grant = 1'd0;
-wire vns_roundrobin5_ce;
-wire [1:0] vns_roundrobin6_request;
-reg vns_roundrobin6_grant = 1'd0;
-wire vns_roundrobin6_ce;
-wire [1:0] vns_roundrobin7_request;
-reg vns_roundrobin7_grant = 1'd0;
-wire vns_roundrobin7_ce;
-reg vns_locked0 = 1'd0;
-reg vns_locked1 = 1'd0;
-reg vns_locked2 = 1'd0;
-reg vns_locked3 = 1'd0;
-reg vns_locked4 = 1'd0;
-reg vns_locked5 = 1'd0;
-reg vns_locked6 = 1'd0;
-reg vns_locked7 = 1'd0;
-reg vns_locked8 = 1'd0;
-reg vns_locked9 = 1'd0;
-reg vns_locked10 = 1'd0;
-reg vns_locked11 = 1'd0;
-reg vns_locked12 = 1'd0;
-reg vns_locked13 = 1'd0;
-reg vns_locked14 = 1'd0;
-reg vns_locked15 = 1'd0;
-reg vns_new_master_wdata_ready0 = 1'd0;
-reg vns_new_master_wdata_ready1 = 1'd0;
-reg vns_new_master_wdata_ready2 = 1'd0;
-reg vns_new_master_wdata_ready3 = 1'd0;
-reg vns_new_master_wdata_ready4 = 1'd0;
-reg vns_new_master_wdata_ready5 = 1'd0;
-reg vns_new_master_rdata_valid0 = 1'd0;
-reg vns_new_master_rdata_valid1 = 1'd0;
-reg vns_new_master_rdata_valid2 = 1'd0;
-reg vns_new_master_rdata_valid3 = 1'd0;
-reg vns_new_master_rdata_valid4 = 1'd0;
-reg vns_new_master_rdata_valid5 = 1'd0;
-reg vns_new_master_rdata_valid6 = 1'd0;
-reg vns_new_master_rdata_valid7 = 1'd0;
-reg vns_new_master_rdata_valid8 = 1'd0;
-reg vns_new_master_rdata_valid9 = 1'd0;
-reg vns_new_master_rdata_valid10 = 1'd0;
-reg vns_new_master_rdata_valid11 = 1'd0;
-reg vns_new_master_rdata_valid12 = 1'd0;
-reg vns_new_master_rdata_valid13 = 1'd0;
-reg vns_new_master_rdata_valid14 = 1'd0;
-reg vns_new_master_rdata_valid15 = 1'd0;
-reg vns_new_master_rdata_valid16 = 1'd0;
-reg vns_new_master_rdata_valid17 = 1'd0;
-reg [2:0] vns_converter_state = 3'd0;
-reg [2:0] vns_converter_next_state = 3'd0;
-reg [1:0] vns_litedramwishbone2native_state = 2'd0;
-reg [1:0] vns_litedramwishbone2native_next_state = 2'd0;
-reg soc_count_next_value = 1'd0;
-reg soc_count_next_value_ce = 1'd0;
-wire [29:0] vns_shared_adr;
-wire [31:0] vns_shared_dat_w;
-reg [31:0] vns_shared_dat_r = 32'd0;
-wire [3:0] vns_shared_sel;
-wire vns_shared_cyc;
-wire vns_shared_stb;
-reg vns_shared_ack = 1'd0;
-wire vns_shared_we;
-wire [2:0] vns_shared_cti;
-wire [1:0] vns_shared_bte;
-wire vns_shared_err;
-wire [1:0] vns_request;
-reg vns_grant = 1'd0;
-reg [3:0] vns_slave_sel = 4'd0;
-reg [3:0] vns_slave_sel_r = 4'd0;
-reg vns_error = 1'd0;
-wire vns_wait;
-wire vns_done;
-reg [19:0] vns_count = 20'd1000000;
-wire [13:0] vns_interface0_bank_bus_adr;
-wire vns_interface0_bank_bus_we;
-wire [7:0] vns_interface0_bank_bus_dat_w;
-reg [7:0] vns_interface0_bank_bus_dat_r = 8'd0;
-wire vns_csrbank0_reset0_re;
-wire vns_csrbank0_reset0_r;
-wire vns_csrbank0_reset0_we;
-wire vns_csrbank0_reset0_w;
-wire vns_csrbank0_scratch3_re;
-wire [7:0] vns_csrbank0_scratch3_r;
-wire vns_csrbank0_scratch3_we;
-wire [7:0] vns_csrbank0_scratch3_w;
-wire vns_csrbank0_scratch2_re;
-wire [7:0] vns_csrbank0_scratch2_r;
-wire vns_csrbank0_scratch2_we;
-wire [7:0] vns_csrbank0_scratch2_w;
-wire vns_csrbank0_scratch1_re;
-wire [7:0] vns_csrbank0_scratch1_r;
-wire vns_csrbank0_scratch1_we;
-wire [7:0] vns_csrbank0_scratch1_w;
-wire vns_csrbank0_scratch0_re;
-wire [7:0] vns_csrbank0_scratch0_r;
-wire vns_csrbank0_scratch0_we;
-wire [7:0] vns_csrbank0_scratch0_w;
-wire vns_csrbank0_bus_errors3_re;
-wire [7:0] vns_csrbank0_bus_errors3_r;
-wire vns_csrbank0_bus_errors3_we;
-wire [7:0] vns_csrbank0_bus_errors3_w;
-wire vns_csrbank0_bus_errors2_re;
-wire [7:0] vns_csrbank0_bus_errors2_r;
-wire vns_csrbank0_bus_errors2_we;
-wire [7:0] vns_csrbank0_bus_errors2_w;
-wire vns_csrbank0_bus_errors1_re;
-wire [7:0] vns_csrbank0_bus_errors1_r;
-wire vns_csrbank0_bus_errors1_we;
-wire [7:0] vns_csrbank0_bus_errors1_w;
-wire vns_csrbank0_bus_errors0_re;
-wire [7:0] vns_csrbank0_bus_errors0_r;
-wire vns_csrbank0_bus_errors0_we;
-wire [7:0] vns_csrbank0_bus_errors0_w;
-wire vns_csrbank0_sel;
-wire [13:0] vns_interface1_bank_bus_adr;
-wire vns_interface1_bank_bus_we;
-wire [7:0] vns_interface1_bank_bus_dat_w;
-reg [7:0] vns_interface1_bank_bus_dat_r = 8'd0;
-wire vns_csrbank1_init_done0_re;
-wire vns_csrbank1_init_done0_r;
-wire vns_csrbank1_init_done0_we;
-wire vns_csrbank1_init_done0_w;
-wire vns_csrbank1_init_error0_re;
-wire vns_csrbank1_init_error0_r;
-wire vns_csrbank1_init_error0_we;
-wire vns_csrbank1_init_error0_w;
-wire vns_csrbank1_sel;
-wire [13:0] vns_interface2_bank_bus_adr;
-wire vns_interface2_bank_bus_we;
-wire [7:0] vns_interface2_bank_bus_dat_w;
-reg [7:0] vns_interface2_bank_bus_dat_r = 8'd0;
-wire vns_csrbank2_half_sys8x_taps0_re;
-wire [4:0] vns_csrbank2_half_sys8x_taps0_r;
-wire vns_csrbank2_half_sys8x_taps0_we;
-wire [4:0] vns_csrbank2_half_sys8x_taps0_w;
-wire vns_csrbank2_wlevel_en0_re;
-wire vns_csrbank2_wlevel_en0_r;
-wire vns_csrbank2_wlevel_en0_we;
-wire vns_csrbank2_wlevel_en0_w;
-wire vns_csrbank2_dly_sel0_re;
-wire [1:0] vns_csrbank2_dly_sel0_r;
-wire vns_csrbank2_dly_sel0_we;
-wire [1:0] vns_csrbank2_dly_sel0_w;
-wire vns_csrbank2_sel;
-wire [13:0] vns_interface3_bank_bus_adr;
-wire vns_interface3_bank_bus_we;
-wire [7:0] vns_interface3_bank_bus_dat_w;
-reg [7:0] vns_interface3_bank_bus_dat_r = 8'd0;
-wire vns_csrbank3_dfii_control0_re;
-wire [3:0] vns_csrbank3_dfii_control0_r;
-wire vns_csrbank3_dfii_control0_we;
-wire [3:0] vns_csrbank3_dfii_control0_w;
-wire vns_csrbank3_dfii_pi0_command0_re;
-wire [5:0] vns_csrbank3_dfii_pi0_command0_r;
-wire vns_csrbank3_dfii_pi0_command0_we;
-wire [5:0] vns_csrbank3_dfii_pi0_command0_w;
-wire vns_csrbank3_dfii_pi0_address1_re;
-wire [6:0] vns_csrbank3_dfii_pi0_address1_r;
-wire vns_csrbank3_dfii_pi0_address1_we;
-wire [6:0] vns_csrbank3_dfii_pi0_address1_w;
-wire vns_csrbank3_dfii_pi0_address0_re;
-wire [7:0] vns_csrbank3_dfii_pi0_address0_r;
-wire vns_csrbank3_dfii_pi0_address0_we;
-wire [7:0] vns_csrbank3_dfii_pi0_address0_w;
-wire vns_csrbank3_dfii_pi0_baddress0_re;
-wire [2:0] vns_csrbank3_dfii_pi0_baddress0_r;
-wire vns_csrbank3_dfii_pi0_baddress0_we;
-wire [2:0] vns_csrbank3_dfii_pi0_baddress0_w;
-wire vns_csrbank3_dfii_pi0_wrdata3_re;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_r;
-wire vns_csrbank3_dfii_pi0_wrdata3_we;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata3_w;
-wire vns_csrbank3_dfii_pi0_wrdata2_re;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_r;
-wire vns_csrbank3_dfii_pi0_wrdata2_we;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata2_w;
-wire vns_csrbank3_dfii_pi0_wrdata1_re;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_r;
-wire vns_csrbank3_dfii_pi0_wrdata1_we;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata1_w;
-wire vns_csrbank3_dfii_pi0_wrdata0_re;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_r;
-wire vns_csrbank3_dfii_pi0_wrdata0_we;
-wire [7:0] vns_csrbank3_dfii_pi0_wrdata0_w;
-wire vns_csrbank3_dfii_pi0_rddata3_re;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata3_r;
-wire vns_csrbank3_dfii_pi0_rddata3_we;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata3_w;
-wire vns_csrbank3_dfii_pi0_rddata2_re;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata2_r;
-wire vns_csrbank3_dfii_pi0_rddata2_we;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata2_w;
-wire vns_csrbank3_dfii_pi0_rddata1_re;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata1_r;
-wire vns_csrbank3_dfii_pi0_rddata1_we;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata1_w;
-wire vns_csrbank3_dfii_pi0_rddata0_re;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata0_r;
-wire vns_csrbank3_dfii_pi0_rddata0_we;
-wire [7:0] vns_csrbank3_dfii_pi0_rddata0_w;
-wire vns_csrbank3_dfii_pi1_command0_re;
-wire [5:0] vns_csrbank3_dfii_pi1_command0_r;
-wire vns_csrbank3_dfii_pi1_command0_we;
-wire [5:0] vns_csrbank3_dfii_pi1_command0_w;
-wire vns_csrbank3_dfii_pi1_address1_re;
-wire [6:0] vns_csrbank3_dfii_pi1_address1_r;
-wire vns_csrbank3_dfii_pi1_address1_we;
-wire [6:0] vns_csrbank3_dfii_pi1_address1_w;
-wire vns_csrbank3_dfii_pi1_address0_re;
-wire [7:0] vns_csrbank3_dfii_pi1_address0_r;
-wire vns_csrbank3_dfii_pi1_address0_we;
-wire [7:0] vns_csrbank3_dfii_pi1_address0_w;
-wire vns_csrbank3_dfii_pi1_baddress0_re;
-wire [2:0] vns_csrbank3_dfii_pi1_baddress0_r;
-wire vns_csrbank3_dfii_pi1_baddress0_we;
-wire [2:0] vns_csrbank3_dfii_pi1_baddress0_w;
-wire vns_csrbank3_dfii_pi1_wrdata3_re;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_r;
-wire vns_csrbank3_dfii_pi1_wrdata3_we;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata3_w;
-wire vns_csrbank3_dfii_pi1_wrdata2_re;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_r;
-wire vns_csrbank3_dfii_pi1_wrdata2_we;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata2_w;
-wire vns_csrbank3_dfii_pi1_wrdata1_re;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_r;
-wire vns_csrbank3_dfii_pi1_wrdata1_we;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata1_w;
-wire vns_csrbank3_dfii_pi1_wrdata0_re;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_r;
-wire vns_csrbank3_dfii_pi1_wrdata0_we;
-wire [7:0] vns_csrbank3_dfii_pi1_wrdata0_w;
-wire vns_csrbank3_dfii_pi1_rddata3_re;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata3_r;
-wire vns_csrbank3_dfii_pi1_rddata3_we;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata3_w;
-wire vns_csrbank3_dfii_pi1_rddata2_re;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata2_r;
-wire vns_csrbank3_dfii_pi1_rddata2_we;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata2_w;
-wire vns_csrbank3_dfii_pi1_rddata1_re;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata1_r;
-wire vns_csrbank3_dfii_pi1_rddata1_we;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata1_w;
-wire vns_csrbank3_dfii_pi1_rddata0_re;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata0_r;
-wire vns_csrbank3_dfii_pi1_rddata0_we;
-wire [7:0] vns_csrbank3_dfii_pi1_rddata0_w;
-wire vns_csrbank3_dfii_pi2_command0_re;
-wire [5:0] vns_csrbank3_dfii_pi2_command0_r;
-wire vns_csrbank3_dfii_pi2_command0_we;
-wire [5:0] vns_csrbank3_dfii_pi2_command0_w;
-wire vns_csrbank3_dfii_pi2_address1_re;
-wire [6:0] vns_csrbank3_dfii_pi2_address1_r;
-wire vns_csrbank3_dfii_pi2_address1_we;
-wire [6:0] vns_csrbank3_dfii_pi2_address1_w;
-wire vns_csrbank3_dfii_pi2_address0_re;
-wire [7:0] vns_csrbank3_dfii_pi2_address0_r;
-wire vns_csrbank3_dfii_pi2_address0_we;
-wire [7:0] vns_csrbank3_dfii_pi2_address0_w;
-wire vns_csrbank3_dfii_pi2_baddress0_re;
-wire [2:0] vns_csrbank3_dfii_pi2_baddress0_r;
-wire vns_csrbank3_dfii_pi2_baddress0_we;
-wire [2:0] vns_csrbank3_dfii_pi2_baddress0_w;
-wire vns_csrbank3_dfii_pi2_wrdata3_re;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_r;
-wire vns_csrbank3_dfii_pi2_wrdata3_we;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata3_w;
-wire vns_csrbank3_dfii_pi2_wrdata2_re;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_r;
-wire vns_csrbank3_dfii_pi2_wrdata2_we;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata2_w;
-wire vns_csrbank3_dfii_pi2_wrdata1_re;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_r;
-wire vns_csrbank3_dfii_pi2_wrdata1_we;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata1_w;
-wire vns_csrbank3_dfii_pi2_wrdata0_re;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_r;
-wire vns_csrbank3_dfii_pi2_wrdata0_we;
-wire [7:0] vns_csrbank3_dfii_pi2_wrdata0_w;
-wire vns_csrbank3_dfii_pi2_rddata3_re;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata3_r;
-wire vns_csrbank3_dfii_pi2_rddata3_we;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata3_w;
-wire vns_csrbank3_dfii_pi2_rddata2_re;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata2_r;
-wire vns_csrbank3_dfii_pi2_rddata2_we;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata2_w;
-wire vns_csrbank3_dfii_pi2_rddata1_re;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata1_r;
-wire vns_csrbank3_dfii_pi2_rddata1_we;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata1_w;
-wire vns_csrbank3_dfii_pi2_rddata0_re;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata0_r;
-wire vns_csrbank3_dfii_pi2_rddata0_we;
-wire [7:0] vns_csrbank3_dfii_pi2_rddata0_w;
-wire vns_csrbank3_dfii_pi3_command0_re;
-wire [5:0] vns_csrbank3_dfii_pi3_command0_r;
-wire vns_csrbank3_dfii_pi3_command0_we;
-wire [5:0] vns_csrbank3_dfii_pi3_command0_w;
-wire vns_csrbank3_dfii_pi3_address1_re;
-wire [6:0] vns_csrbank3_dfii_pi3_address1_r;
-wire vns_csrbank3_dfii_pi3_address1_we;
-wire [6:0] vns_csrbank3_dfii_pi3_address1_w;
-wire vns_csrbank3_dfii_pi3_address0_re;
-wire [7:0] vns_csrbank3_dfii_pi3_address0_r;
-wire vns_csrbank3_dfii_pi3_address0_we;
-wire [7:0] vns_csrbank3_dfii_pi3_address0_w;
-wire vns_csrbank3_dfii_pi3_baddress0_re;
-wire [2:0] vns_csrbank3_dfii_pi3_baddress0_r;
-wire vns_csrbank3_dfii_pi3_baddress0_we;
-wire [2:0] vns_csrbank3_dfii_pi3_baddress0_w;
-wire vns_csrbank3_dfii_pi3_wrdata3_re;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_r;
-wire vns_csrbank3_dfii_pi3_wrdata3_we;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata3_w;
-wire vns_csrbank3_dfii_pi3_wrdata2_re;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_r;
-wire vns_csrbank3_dfii_pi3_wrdata2_we;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata2_w;
-wire vns_csrbank3_dfii_pi3_wrdata1_re;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_r;
-wire vns_csrbank3_dfii_pi3_wrdata1_we;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata1_w;
-wire vns_csrbank3_dfii_pi3_wrdata0_re;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_r;
-wire vns_csrbank3_dfii_pi3_wrdata0_we;
-wire [7:0] vns_csrbank3_dfii_pi3_wrdata0_w;
-wire vns_csrbank3_dfii_pi3_rddata3_re;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata3_r;
-wire vns_csrbank3_dfii_pi3_rddata3_we;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata3_w;
-wire vns_csrbank3_dfii_pi3_rddata2_re;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata2_r;
-wire vns_csrbank3_dfii_pi3_rddata2_we;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata2_w;
-wire vns_csrbank3_dfii_pi3_rddata1_re;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata1_r;
-wire vns_csrbank3_dfii_pi3_rddata1_we;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata1_w;
-wire vns_csrbank3_dfii_pi3_rddata0_re;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata0_r;
-wire vns_csrbank3_dfii_pi3_rddata0_we;
-wire [7:0] vns_csrbank3_dfii_pi3_rddata0_w;
-wire vns_csrbank3_sel;
-wire [13:0] vns_interface4_bank_bus_adr;
-wire vns_interface4_bank_bus_we;
-wire [7:0] vns_interface4_bank_bus_dat_w;
-reg [7:0] vns_interface4_bank_bus_dat_r = 8'd0;
-wire vns_csrbank4_load3_re;
-wire [7:0] vns_csrbank4_load3_r;
-wire vns_csrbank4_load3_we;
-wire [7:0] vns_csrbank4_load3_w;
-wire vns_csrbank4_load2_re;
-wire [7:0] vns_csrbank4_load2_r;
-wire vns_csrbank4_load2_we;
-wire [7:0] vns_csrbank4_load2_w;
-wire vns_csrbank4_load1_re;
-wire [7:0] vns_csrbank4_load1_r;
-wire vns_csrbank4_load1_we;
-wire [7:0] vns_csrbank4_load1_w;
-wire vns_csrbank4_load0_re;
-wire [7:0] vns_csrbank4_load0_r;
-wire vns_csrbank4_load0_we;
-wire [7:0] vns_csrbank4_load0_w;
-wire vns_csrbank4_reload3_re;
-wire [7:0] vns_csrbank4_reload3_r;
-wire vns_csrbank4_reload3_we;
-wire [7:0] vns_csrbank4_reload3_w;
-wire vns_csrbank4_reload2_re;
-wire [7:0] vns_csrbank4_reload2_r;
-wire vns_csrbank4_reload2_we;
-wire [7:0] vns_csrbank4_reload2_w;
-wire vns_csrbank4_reload1_re;
-wire [7:0] vns_csrbank4_reload1_r;
-wire vns_csrbank4_reload1_we;
-wire [7:0] vns_csrbank4_reload1_w;
-wire vns_csrbank4_reload0_re;
-wire [7:0] vns_csrbank4_reload0_r;
-wire vns_csrbank4_reload0_we;
-wire [7:0] vns_csrbank4_reload0_w;
-wire vns_csrbank4_en0_re;
-wire vns_csrbank4_en0_r;
-wire vns_csrbank4_en0_we;
-wire vns_csrbank4_en0_w;
-wire vns_csrbank4_update_value0_re;
-wire vns_csrbank4_update_value0_r;
-wire vns_csrbank4_update_value0_we;
-wire vns_csrbank4_update_value0_w;
-wire vns_csrbank4_value3_re;
-wire [7:0] vns_csrbank4_value3_r;
-wire vns_csrbank4_value3_we;
-wire [7:0] vns_csrbank4_value3_w;
-wire vns_csrbank4_value2_re;
-wire [7:0] vns_csrbank4_value2_r;
-wire vns_csrbank4_value2_we;
-wire [7:0] vns_csrbank4_value2_w;
-wire vns_csrbank4_value1_re;
-wire [7:0] vns_csrbank4_value1_r;
-wire vns_csrbank4_value1_we;
-wire [7:0] vns_csrbank4_value1_w;
-wire vns_csrbank4_value0_re;
-wire [7:0] vns_csrbank4_value0_r;
-wire vns_csrbank4_value0_we;
-wire [7:0] vns_csrbank4_value0_w;
-wire vns_csrbank4_ev_enable0_re;
-wire vns_csrbank4_ev_enable0_r;
-wire vns_csrbank4_ev_enable0_we;
-wire vns_csrbank4_ev_enable0_w;
-wire vns_csrbank4_sel;
-wire [13:0] vns_interface5_bank_bus_adr;
-wire vns_interface5_bank_bus_we;
-wire [7:0] vns_interface5_bank_bus_dat_w;
-reg [7:0] vns_interface5_bank_bus_dat_r = 8'd0;
-wire vns_csrbank5_txfull_re;
-wire vns_csrbank5_txfull_r;
-wire vns_csrbank5_txfull_we;
-wire vns_csrbank5_txfull_w;
-wire vns_csrbank5_rxempty_re;
-wire vns_csrbank5_rxempty_r;
-wire vns_csrbank5_rxempty_we;
-wire vns_csrbank5_rxempty_w;
-wire vns_csrbank5_ev_enable0_re;
-wire [1:0] vns_csrbank5_ev_enable0_r;
-wire vns_csrbank5_ev_enable0_we;
-wire [1:0] vns_csrbank5_ev_enable0_w;
-wire vns_csrbank5_sel;
-wire [13:0] vns_interface6_bank_bus_adr;
-wire vns_interface6_bank_bus_we;
-wire [7:0] vns_interface6_bank_bus_dat_w;
-reg [7:0] vns_interface6_bank_bus_dat_r = 8'd0;
-wire vns_csrbank6_tuning_word3_re;
-wire [7:0] vns_csrbank6_tuning_word3_r;
-wire vns_csrbank6_tuning_word3_we;
-wire [7:0] vns_csrbank6_tuning_word3_w;
-wire vns_csrbank6_tuning_word2_re;
-wire [7:0] vns_csrbank6_tuning_word2_r;
-wire vns_csrbank6_tuning_word2_we;
-wire [7:0] vns_csrbank6_tuning_word2_w;
-wire vns_csrbank6_tuning_word1_re;
-wire [7:0] vns_csrbank6_tuning_word1_r;
-wire vns_csrbank6_tuning_word1_we;
-wire [7:0] vns_csrbank6_tuning_word1_w;
-wire vns_csrbank6_tuning_word0_re;
-wire [7:0] vns_csrbank6_tuning_word0_r;
-wire vns_csrbank6_tuning_word0_we;
-wire [7:0] vns_csrbank6_tuning_word0_w;
-wire vns_csrbank6_sel;
-wire [13:0] vns_adr;
-wire vns_we;
-wire [7:0] vns_dat_w;
-wire [7:0] vns_dat_r;
-reg vns_rhs_array_muxed0 = 1'd0;
-reg [14:0] vns_rhs_array_muxed1 = 15'd0;
-reg [2:0] vns_rhs_array_muxed2 = 3'd0;
-reg vns_rhs_array_muxed3 = 1'd0;
-reg vns_rhs_array_muxed4 = 1'd0;
-reg vns_rhs_array_muxed5 = 1'd0;
-reg vns_t_array_muxed0 = 1'd0;
-reg vns_t_array_muxed1 = 1'd0;
-reg vns_t_array_muxed2 = 1'd0;
-reg vns_rhs_array_muxed6 = 1'd0;
-reg [14:0] vns_rhs_array_muxed7 = 15'd0;
-reg [2:0] vns_rhs_array_muxed8 = 3'd0;
-reg vns_rhs_array_muxed9 = 1'd0;
-reg vns_rhs_array_muxed10 = 1'd0;
-reg vns_rhs_array_muxed11 = 1'd0;
-reg vns_t_array_muxed3 = 1'd0;
-reg vns_t_array_muxed4 = 1'd0;
-reg vns_t_array_muxed5 = 1'd0;
-reg [21:0] vns_rhs_array_muxed12 = 22'd0;
-reg vns_rhs_array_muxed13 = 1'd0;
-reg vns_rhs_array_muxed14 = 1'd0;
-reg [21:0] vns_rhs_array_muxed15 = 22'd0;
-reg vns_rhs_array_muxed16 = 1'd0;
-reg vns_rhs_array_muxed17 = 1'd0;
-reg [21:0] vns_rhs_array_muxed18 = 22'd0;
-reg vns_rhs_array_muxed19 = 1'd0;
-reg vns_rhs_array_muxed20 = 1'd0;
-reg [21:0] vns_rhs_array_muxed21 = 22'd0;
-reg vns_rhs_array_muxed22 = 1'd0;
-reg vns_rhs_array_muxed23 = 1'd0;
-reg [21:0] vns_rhs_array_muxed24 = 22'd0;
-reg vns_rhs_array_muxed25 = 1'd0;
-reg vns_rhs_array_muxed26 = 1'd0;
-reg [21:0] vns_rhs_array_muxed27 = 22'd0;
-reg vns_rhs_array_muxed28 = 1'd0;
-reg vns_rhs_array_muxed29 = 1'd0;
-reg [21:0] vns_rhs_array_muxed30 = 22'd0;
-reg vns_rhs_array_muxed31 = 1'd0;
-reg vns_rhs_array_muxed32 = 1'd0;
-reg [21:0] vns_rhs_array_muxed33 = 22'd0;
-reg vns_rhs_array_muxed34 = 1'd0;
-reg vns_rhs_array_muxed35 = 1'd0;
-reg [29:0] vns_rhs_array_muxed36 = 30'd0;
-reg [31:0] vns_rhs_array_muxed37 = 32'd0;
-reg [3:0] vns_rhs_array_muxed38 = 4'd0;
-reg vns_rhs_array_muxed39 = 1'd0;
-reg vns_rhs_array_muxed40 = 1'd0;
-reg vns_rhs_array_muxed41 = 1'd0;
-reg [2:0] vns_rhs_array_muxed42 = 3'd0;
-reg [1:0] vns_rhs_array_muxed43 = 2'd0;
-reg [2:0] vns_array_muxed0 = 3'd0;
-reg [14:0] vns_array_muxed1 = 15'd0;
-reg vns_array_muxed2 = 1'd0;
-reg vns_array_muxed3 = 1'd0;
-reg vns_array_muxed4 = 1'd0;
-reg vns_array_muxed5 = 1'd0;
-reg vns_array_muxed6 = 1'd0;
-reg [2:0] vns_array_muxed7 = 3'd0;
-reg [14:0] vns_array_muxed8 = 15'd0;
-reg vns_array_muxed9 = 1'd0;
-reg vns_array_muxed10 = 1'd0;
-reg vns_array_muxed11 = 1'd0;
-reg vns_array_muxed12 = 1'd0;
-reg vns_array_muxed13 = 1'd0;
-reg [2:0] vns_array_muxed14 = 3'd0;
-reg [14:0] vns_array_muxed15 = 15'd0;
-reg vns_array_muxed16 = 1'd0;
-reg vns_array_muxed17 = 1'd0;
-reg vns_array_muxed18 = 1'd0;
-reg vns_array_muxed19 = 1'd0;
-reg vns_array_muxed20 = 1'd0;
-reg [2:0] vns_array_muxed21 = 3'd0;
-reg [14:0] vns_array_muxed22 = 15'd0;
-reg vns_array_muxed23 = 1'd0;
-reg vns_array_muxed24 = 1'd0;
-reg vns_array_muxed25 = 1'd0;
-reg vns_array_muxed26 = 1'd0;
-reg vns_array_muxed27 = 1'd0;
-(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg vns_regs0 = 1'd0;
-(* async_reg = "true", dont_touch = "true" *) reg vns_regs1 = 1'd0;
-wire vns_xilinxasyncresetsynchronizerimpl0;
-wire vns_xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire vns_xilinxasyncresetsynchronizerimpl1;
-wire vns_xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire vns_xilinxasyncresetsynchronizerimpl1_expr;
-wire vns_xilinxasyncresetsynchronizerimpl2;
-wire vns_xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire vns_xilinxasyncresetsynchronizerimpl2_expr;
-wire vns_xilinxasyncresetsynchronizerimpl3;
-wire vns_xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire sys_pll_reset;
+wire sys_pll_locked;
+wire s7pll0_clkin;
+wire s7pll0_clkout0;
+wire s7pll0_clkout_buf0;
+wire s7pll0_clkout1;
+wire s7pll0_clkout_buf1;
+wire s7pll0_clkout2;
+wire s7pll0_clkout_buf2;
+wire iodelay_pll_reset;
+wire iodelay_pll_locked;
+wire s7pll1_clkin;
+wire s7pll1_clkout;
+wire s7pll1_clkout_buf;
+reg [3:0] reset_counter = 4'd15;
+reg ic_reset = 1'd1;
+reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg a7ddrphy_wlevel_en_storage = 1'd0;
+reg a7ddrphy_wlevel_en_re = 1'd0;
+wire a7ddrphy_wlevel_strobe_re;
+wire a7ddrphy_wlevel_strobe_r;
+wire a7ddrphy_wlevel_strobe_we;
+reg a7ddrphy_wlevel_strobe_w = 1'd0;
+wire a7ddrphy_cdly_rst_re;
+wire a7ddrphy_cdly_rst_r;
+wire a7ddrphy_cdly_rst_we;
+reg a7ddrphy_cdly_rst_w = 1'd0;
+wire a7ddrphy_cdly_inc_re;
+wire a7ddrphy_cdly_inc_r;
+wire a7ddrphy_cdly_inc_we;
+reg a7ddrphy_cdly_inc_w = 1'd0;
+reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
+reg a7ddrphy_dly_sel_re = 1'd0;
+wire a7ddrphy_rdly_dq_rst_re;
+wire a7ddrphy_rdly_dq_rst_r;
+wire a7ddrphy_rdly_dq_rst_we;
+reg a7ddrphy_rdly_dq_rst_w = 1'd0;
+wire a7ddrphy_rdly_dq_inc_re;
+wire a7ddrphy_rdly_dq_inc_r;
+wire a7ddrphy_rdly_dq_inc_we;
+reg a7ddrphy_rdly_dq_inc_w = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_rst_re;
+wire a7ddrphy_rdly_dq_bitslip_rst_r;
+wire a7ddrphy_rdly_dq_bitslip_rst_we;
+reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_re;
+wire a7ddrphy_rdly_dq_bitslip_r;
+wire a7ddrphy_rdly_dq_bitslip_we;
+reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+wire [14:0] a7ddrphy_dfi_p0_address;
+wire [2:0] a7ddrphy_dfi_p0_bank;
+wire a7ddrphy_dfi_p0_cas_n;
+wire a7ddrphy_dfi_p0_cs_n;
+wire a7ddrphy_dfi_p0_ras_n;
+wire a7ddrphy_dfi_p0_we_n;
+wire a7ddrphy_dfi_p0_cke;
+wire a7ddrphy_dfi_p0_odt;
+wire a7ddrphy_dfi_p0_reset_n;
+wire a7ddrphy_dfi_p0_act_n;
+wire [31:0] a7ddrphy_dfi_p0_wrdata;
+wire a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
+wire a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
+reg a7ddrphy_dfi_p0_rddata_valid = 1'd0;
+wire [14:0] a7ddrphy_dfi_p1_address;
+wire [2:0] a7ddrphy_dfi_p1_bank;
+wire a7ddrphy_dfi_p1_cas_n;
+wire a7ddrphy_dfi_p1_cs_n;
+wire a7ddrphy_dfi_p1_ras_n;
+wire a7ddrphy_dfi_p1_we_n;
+wire a7ddrphy_dfi_p1_cke;
+wire a7ddrphy_dfi_p1_odt;
+wire a7ddrphy_dfi_p1_reset_n;
+wire a7ddrphy_dfi_p1_act_n;
+wire [31:0] a7ddrphy_dfi_p1_wrdata;
+wire a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
+wire a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
+reg a7ddrphy_dfi_p1_rddata_valid = 1'd0;
+wire [14:0] a7ddrphy_dfi_p2_address;
+wire [2:0] a7ddrphy_dfi_p2_bank;
+wire a7ddrphy_dfi_p2_cas_n;
+wire a7ddrphy_dfi_p2_cs_n;
+wire a7ddrphy_dfi_p2_ras_n;
+wire a7ddrphy_dfi_p2_we_n;
+wire a7ddrphy_dfi_p2_cke;
+wire a7ddrphy_dfi_p2_odt;
+wire a7ddrphy_dfi_p2_reset_n;
+wire a7ddrphy_dfi_p2_act_n;
+wire [31:0] a7ddrphy_dfi_p2_wrdata;
+wire a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
+wire a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
+reg a7ddrphy_dfi_p2_rddata_valid = 1'd0;
+wire [14:0] a7ddrphy_dfi_p3_address;
+wire [2:0] a7ddrphy_dfi_p3_bank;
+wire a7ddrphy_dfi_p3_cas_n;
+wire a7ddrphy_dfi_p3_cs_n;
+wire a7ddrphy_dfi_p3_ras_n;
+wire a7ddrphy_dfi_p3_we_n;
+wire a7ddrphy_dfi_p3_cke;
+wire a7ddrphy_dfi_p3_odt;
+wire a7ddrphy_dfi_p3_reset_n;
+wire a7ddrphy_dfi_p3_act_n;
+wire [31:0] a7ddrphy_dfi_p3_wrdata;
+wire a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
+wire a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
+reg a7ddrphy_dfi_p3_rddata_valid = 1'd0;
+wire a7ddrphy_sd_clk_se_nodelay;
+reg a7ddrphy_dqs_oe = 1'd0;
+reg a7ddrphy_dqs_oe_delayed = 1'd0;
+wire a7ddrphy_dqspattern0;
+wire a7ddrphy_dqspattern1;
+reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
+wire [1:0] a7ddrphy_dqs_i;
+wire [1:0] a7ddrphy_dqs_i_delayed;
+wire a7ddrphy_dqs_o_no_delay0;
+wire a7ddrphy_dqs_t0;
+wire a7ddrphy0;
+wire a7ddrphy_dqs_o_no_delay1;
+wire a7ddrphy_dqs_t1;
+wire a7ddrphy1;
+wire a7ddrphy_dq_oe;
+reg a7ddrphy_dq_oe_delayed = 1'd0;
+wire a7ddrphy_dq_o_nodelay0;
+wire a7ddrphy_dq_i_nodelay0;
+wire a7ddrphy_dq_i_delayed0;
+wire a7ddrphy_dq_t0;
+wire [7:0] a7ddrphy_dq_i_data0;
+wire [7:0] a7ddrphy_bitslip0_i;
+reg [7:0] a7ddrphy_bitslip0_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip0_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay1;
+wire a7ddrphy_dq_i_nodelay1;
+wire a7ddrphy_dq_i_delayed1;
+wire a7ddrphy_dq_t1;
+wire [7:0] a7ddrphy_dq_i_data1;
+wire [7:0] a7ddrphy_bitslip1_i;
+reg [7:0] a7ddrphy_bitslip1_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip1_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay2;
+wire a7ddrphy_dq_i_nodelay2;
+wire a7ddrphy_dq_i_delayed2;
+wire a7ddrphy_dq_t2;
+wire [7:0] a7ddrphy_dq_i_data2;
+wire [7:0] a7ddrphy_bitslip2_i;
+reg [7:0] a7ddrphy_bitslip2_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip2_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip2_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay3;
+wire a7ddrphy_dq_i_nodelay3;
+wire a7ddrphy_dq_i_delayed3;
+wire a7ddrphy_dq_t3;
+wire [7:0] a7ddrphy_dq_i_data3;
+wire [7:0] a7ddrphy_bitslip3_i;
+reg [7:0] a7ddrphy_bitslip3_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip3_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip3_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay4;
+wire a7ddrphy_dq_i_nodelay4;
+wire a7ddrphy_dq_i_delayed4;
+wire a7ddrphy_dq_t4;
+wire [7:0] a7ddrphy_dq_i_data4;
+wire [7:0] a7ddrphy_bitslip4_i;
+reg [7:0] a7ddrphy_bitslip4_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip4_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip4_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay5;
+wire a7ddrphy_dq_i_nodelay5;
+wire a7ddrphy_dq_i_delayed5;
+wire a7ddrphy_dq_t5;
+wire [7:0] a7ddrphy_dq_i_data5;
+wire [7:0] a7ddrphy_bitslip5_i;
+reg [7:0] a7ddrphy_bitslip5_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip5_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip5_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay6;
+wire a7ddrphy_dq_i_nodelay6;
+wire a7ddrphy_dq_i_delayed6;
+wire a7ddrphy_dq_t6;
+wire [7:0] a7ddrphy_dq_i_data6;
+wire [7:0] a7ddrphy_bitslip6_i;
+reg [7:0] a7ddrphy_bitslip6_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip6_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip6_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay7;
+wire a7ddrphy_dq_i_nodelay7;
+wire a7ddrphy_dq_i_delayed7;
+wire a7ddrphy_dq_t7;
+wire [7:0] a7ddrphy_dq_i_data7;
+wire [7:0] a7ddrphy_bitslip7_i;
+reg [7:0] a7ddrphy_bitslip7_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip7_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip7_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay8;
+wire a7ddrphy_dq_i_nodelay8;
+wire a7ddrphy_dq_i_delayed8;
+wire a7ddrphy_dq_t8;
+wire [7:0] a7ddrphy_dq_i_data8;
+wire [7:0] a7ddrphy_bitslip8_i;
+reg [7:0] a7ddrphy_bitslip8_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip8_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip8_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay9;
+wire a7ddrphy_dq_i_nodelay9;
+wire a7ddrphy_dq_i_delayed9;
+wire a7ddrphy_dq_t9;
+wire [7:0] a7ddrphy_dq_i_data9;
+wire [7:0] a7ddrphy_bitslip9_i;
+reg [7:0] a7ddrphy_bitslip9_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip9_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip9_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay10;
+wire a7ddrphy_dq_i_nodelay10;
+wire a7ddrphy_dq_i_delayed10;
+wire a7ddrphy_dq_t10;
+wire [7:0] a7ddrphy_dq_i_data10;
+wire [7:0] a7ddrphy_bitslip10_i;
+reg [7:0] a7ddrphy_bitslip10_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip10_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip10_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay11;
+wire a7ddrphy_dq_i_nodelay11;
+wire a7ddrphy_dq_i_delayed11;
+wire a7ddrphy_dq_t11;
+wire [7:0] a7ddrphy_dq_i_data11;
+wire [7:0] a7ddrphy_bitslip11_i;
+reg [7:0] a7ddrphy_bitslip11_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip11_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip11_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay12;
+wire a7ddrphy_dq_i_nodelay12;
+wire a7ddrphy_dq_i_delayed12;
+wire a7ddrphy_dq_t12;
+wire [7:0] a7ddrphy_dq_i_data12;
+wire [7:0] a7ddrphy_bitslip12_i;
+reg [7:0] a7ddrphy_bitslip12_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip12_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip12_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay13;
+wire a7ddrphy_dq_i_nodelay13;
+wire a7ddrphy_dq_i_delayed13;
+wire a7ddrphy_dq_t13;
+wire [7:0] a7ddrphy_dq_i_data13;
+wire [7:0] a7ddrphy_bitslip13_i;
+reg [7:0] a7ddrphy_bitslip13_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip13_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip13_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay14;
+wire a7ddrphy_dq_i_nodelay14;
+wire a7ddrphy_dq_i_delayed14;
+wire a7ddrphy_dq_t14;
+wire [7:0] a7ddrphy_dq_i_data14;
+wire [7:0] a7ddrphy_bitslip14_i;
+reg [7:0] a7ddrphy_bitslip14_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip14_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip14_r = 16'd0;
+wire a7ddrphy_dq_o_nodelay15;
+wire a7ddrphy_dq_i_nodelay15;
+wire a7ddrphy_dq_i_delayed15;
+wire a7ddrphy_dq_t15;
+wire [7:0] a7ddrphy_dq_i_data15;
+wire [7:0] a7ddrphy_bitslip15_i;
+reg [7:0] a7ddrphy_bitslip15_o = 8'd0;
+reg [2:0] a7ddrphy_bitslip15_value = 3'd0;
+reg [15:0] a7ddrphy_bitslip15_r = 16'd0;
+wire [7:0] a7ddrphy_rddata_en;
+reg [7:0] a7ddrphy_rddata_en_last = 8'd0;
+wire [3:0] a7ddrphy_wrdata_en;
+reg [3:0] a7ddrphy_wrdata_en_last = 4'd0;
+wire [14:0] litedramcore_inti_p0_address;
+wire [2:0] litedramcore_inti_p0_bank;
+reg litedramcore_inti_p0_cas_n = 1'd1;
+reg litedramcore_inti_p0_cs_n = 1'd1;
+reg litedramcore_inti_p0_ras_n = 1'd1;
+reg litedramcore_inti_p0_we_n = 1'd1;
+wire litedramcore_inti_p0_cke;
+wire litedramcore_inti_p0_odt;
+wire litedramcore_inti_p0_reset_n;
+reg litedramcore_inti_p0_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p0_wrdata;
+wire litedramcore_inti_p0_wrdata_en;
+wire [3:0] litedramcore_inti_p0_wrdata_mask;
+wire litedramcore_inti_p0_rddata_en;
+reg [31:0] litedramcore_inti_p0_rddata = 32'd0;
+reg litedramcore_inti_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_inti_p1_address;
+wire [2:0] litedramcore_inti_p1_bank;
+reg litedramcore_inti_p1_cas_n = 1'd1;
+reg litedramcore_inti_p1_cs_n = 1'd1;
+reg litedramcore_inti_p1_ras_n = 1'd1;
+reg litedramcore_inti_p1_we_n = 1'd1;
+wire litedramcore_inti_p1_cke;
+wire litedramcore_inti_p1_odt;
+wire litedramcore_inti_p1_reset_n;
+reg litedramcore_inti_p1_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p1_wrdata;
+wire litedramcore_inti_p1_wrdata_en;
+wire [3:0] litedramcore_inti_p1_wrdata_mask;
+wire litedramcore_inti_p1_rddata_en;
+reg [31:0] litedramcore_inti_p1_rddata = 32'd0;
+reg litedramcore_inti_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_inti_p2_address;
+wire [2:0] litedramcore_inti_p2_bank;
+reg litedramcore_inti_p2_cas_n = 1'd1;
+reg litedramcore_inti_p2_cs_n = 1'd1;
+reg litedramcore_inti_p2_ras_n = 1'd1;
+reg litedramcore_inti_p2_we_n = 1'd1;
+wire litedramcore_inti_p2_cke;
+wire litedramcore_inti_p2_odt;
+wire litedramcore_inti_p2_reset_n;
+reg litedramcore_inti_p2_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p2_wrdata;
+wire litedramcore_inti_p2_wrdata_en;
+wire [3:0] litedramcore_inti_p2_wrdata_mask;
+wire litedramcore_inti_p2_rddata_en;
+reg [31:0] litedramcore_inti_p2_rddata = 32'd0;
+reg litedramcore_inti_p2_rddata_valid = 1'd0;
+wire [14:0] litedramcore_inti_p3_address;
+wire [2:0] litedramcore_inti_p3_bank;
+reg litedramcore_inti_p3_cas_n = 1'd1;
+reg litedramcore_inti_p3_cs_n = 1'd1;
+reg litedramcore_inti_p3_ras_n = 1'd1;
+reg litedramcore_inti_p3_we_n = 1'd1;
+wire litedramcore_inti_p3_cke;
+wire litedramcore_inti_p3_odt;
+wire litedramcore_inti_p3_reset_n;
+reg litedramcore_inti_p3_act_n = 1'd1;
+wire [31:0] litedramcore_inti_p3_wrdata;
+wire litedramcore_inti_p3_wrdata_en;
+wire [3:0] litedramcore_inti_p3_wrdata_mask;
+wire litedramcore_inti_p3_rddata_en;
+reg [31:0] litedramcore_inti_p3_rddata = 32'd0;
+reg litedramcore_inti_p3_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [14:0] litedramcore_master_p0_address = 15'd0;
+reg [2:0] litedramcore_master_p0_bank = 3'd0;
+reg litedramcore_master_p0_cas_n = 1'd1;
+reg litedramcore_master_p0_cs_n = 1'd1;
+reg litedramcore_master_p0_ras_n = 1'd1;
+reg litedramcore_master_p0_we_n = 1'd1;
+reg litedramcore_master_p0_cke = 1'd0;
+reg litedramcore_master_p0_odt = 1'd0;
+reg litedramcore_master_p0_reset_n = 1'd0;
+reg litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg [14:0] litedramcore_master_p1_address = 15'd0;
+reg [2:0] litedramcore_master_p1_bank = 3'd0;
+reg litedramcore_master_p1_cas_n = 1'd1;
+reg litedramcore_master_p1_cs_n = 1'd1;
+reg litedramcore_master_p1_ras_n = 1'd1;
+reg litedramcore_master_p1_we_n = 1'd1;
+reg litedramcore_master_p1_cke = 1'd0;
+reg litedramcore_master_p1_odt = 1'd0;
+reg litedramcore_master_p1_reset_n = 1'd0;
+reg litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg [14:0] litedramcore_master_p2_address = 15'd0;
+reg [2:0] litedramcore_master_p2_bank = 3'd0;
+reg litedramcore_master_p2_cas_n = 1'd1;
+reg litedramcore_master_p2_cs_n = 1'd1;
+reg litedramcore_master_p2_ras_n = 1'd1;
+reg litedramcore_master_p2_we_n = 1'd1;
+reg litedramcore_master_p2_cke = 1'd0;
+reg litedramcore_master_p2_odt = 1'd0;
+reg litedramcore_master_p2_reset_n = 1'd0;
+reg litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg [14:0] litedramcore_master_p3_address = 15'd0;
+reg [2:0] litedramcore_master_p3_bank = 3'd0;
+reg litedramcore_master_p3_cas_n = 1'd1;
+reg litedramcore_master_p3_cs_n = 1'd1;
+reg litedramcore_master_p3_ras_n = 1'd1;
+reg litedramcore_master_p3_we_n = 1'd1;
+reg litedramcore_master_p3_cke = 1'd0;
+reg litedramcore_master_p3_odt = 1'd0;
+reg litedramcore_master_p3_reset_n = 1'd0;
+reg litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+reg [3:0] litedramcore_storage = 4'd0;
+reg litedramcore_re = 1'd0;
+reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg litedramcore_phaseinjector0_command_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_re;
+wire litedramcore_phaseinjector0_command_issue_r;
+wire litedramcore_phaseinjector0_command_issue_we;
+reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
+reg litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_status = 32'd0;
+wire litedramcore_phaseinjector0_we;
+reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg litedramcore_phaseinjector1_command_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_re;
+wire litedramcore_phaseinjector1_command_issue_r;
+wire litedramcore_phaseinjector1_command_issue_we;
+reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
+reg litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_status = 32'd0;
+wire litedramcore_phaseinjector1_we;
+reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg litedramcore_phaseinjector2_command_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_re;
+wire litedramcore_phaseinjector2_command_issue_r;
+wire litedramcore_phaseinjector2_command_issue_we;
+reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
+reg litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_status = 32'd0;
+wire litedramcore_phaseinjector2_we;
+reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg litedramcore_phaseinjector3_command_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_re;
+wire litedramcore_phaseinjector3_command_issue_r;
+wire litedramcore_phaseinjector3_command_issue_we;
+reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
+reg litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_status = 32'd0;
+wire litedramcore_phaseinjector3_we;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [21:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [21:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [21:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [21:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [21:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [21:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [21:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [21:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg [127:0] litedramcore_interface_wdata = 128'd0;
+reg [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg [14:0] litedramcore_dfi_p0_address = 15'd0;
+reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg litedramcore_dfi_p0_cas_n = 1'd1;
+reg litedramcore_dfi_p0_cs_n = 1'd1;
+reg litedramcore_dfi_p0_ras_n = 1'd1;
+reg litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg [14:0] litedramcore_dfi_p1_address = 15'd0;
+reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg litedramcore_dfi_p1_cas_n = 1'd1;
+reg litedramcore_dfi_p1_cs_n = 1'd1;
+reg litedramcore_dfi_p1_ras_n = 1'd1;
+reg litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg [14:0] litedramcore_dfi_p2_address = 15'd0;
+reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg litedramcore_dfi_p2_cas_n = 1'd1;
+reg litedramcore_dfi_p2_cs_n = 1'd1;
+reg litedramcore_dfi_p2_ras_n = 1'd1;
+reg litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg [14:0] litedramcore_dfi_p3_address = 15'd0;
+reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg litedramcore_dfi_p3_cas_n = 1'd1;
+reg litedramcore_dfi_p3_cs_n = 1'd1;
+reg litedramcore_dfi_p3_ras_n = 1'd1;
+reg litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg litedramcore_cmd_valid = 1'd0;
+reg litedramcore_cmd_ready = 1'd0;
+reg litedramcore_cmd_last = 1'd0;
+reg [14:0] litedramcore_cmd_payload_a = 15'd0;
+reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg litedramcore_cmd_payload_cas = 1'd0;
+reg litedramcore_cmd_payload_ras = 1'd0;
+reg litedramcore_cmd_payload_we = 1'd0;
+reg litedramcore_cmd_payload_is_read = 1'd0;
+reg litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg litedramcore_postponer_req_o = 1'd0;
+reg litedramcore_postponer_count = 1'd0;
+reg litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] litedramcore_sequencer_counter = 6'd0;
+reg litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg litedramcore_zqcs_executer_start = 1'd0;
+reg litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [21:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine0_cmd_buffer_sink_first;
+wire litedramcore_bankmachine0_cmd_buffer_sink_last;
+wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine0_cmd_buffer_source_ready;
+reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine0_row = 15'd0;
+reg litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg litedramcore_bankmachine0_row_open = 1'd0;
+reg litedramcore_bankmachine0_row_close = 1'd0;
+reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [21:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine1_cmd_buffer_sink_first;
+wire litedramcore_bankmachine1_cmd_buffer_sink_last;
+wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine1_cmd_buffer_source_ready;
+reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine1_row = 15'd0;
+reg litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg litedramcore_bankmachine1_row_open = 1'd0;
+reg litedramcore_bankmachine1_row_close = 1'd0;
+reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [21:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine2_cmd_buffer_sink_first;
+wire litedramcore_bankmachine2_cmd_buffer_sink_last;
+wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine2_cmd_buffer_source_ready;
+reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine2_row = 15'd0;
+reg litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg litedramcore_bankmachine2_row_open = 1'd0;
+reg litedramcore_bankmachine2_row_close = 1'd0;
+reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [21:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine3_cmd_buffer_sink_first;
+wire litedramcore_bankmachine3_cmd_buffer_sink_last;
+wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine3_cmd_buffer_source_ready;
+reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine3_row = 15'd0;
+reg litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg litedramcore_bankmachine3_row_open = 1'd0;
+reg litedramcore_bankmachine3_row_close = 1'd0;
+reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [21:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine4_cmd_buffer_sink_first;
+wire litedramcore_bankmachine4_cmd_buffer_sink_last;
+wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine4_cmd_buffer_source_ready;
+reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine4_row = 15'd0;
+reg litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg litedramcore_bankmachine4_row_open = 1'd0;
+reg litedramcore_bankmachine4_row_close = 1'd0;
+reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [21:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine5_cmd_buffer_sink_first;
+wire litedramcore_bankmachine5_cmd_buffer_sink_last;
+wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine5_cmd_buffer_source_ready;
+reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine5_row = 15'd0;
+reg litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg litedramcore_bankmachine5_row_open = 1'd0;
+reg litedramcore_bankmachine5_row_close = 1'd0;
+reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [21:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine6_cmd_buffer_sink_first;
+wire litedramcore_bankmachine6_cmd_buffer_sink_last;
+wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine6_cmd_buffer_source_ready;
+reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine6_row = 15'd0;
+reg litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg litedramcore_bankmachine6_row_open = 1'd0;
+reg litedramcore_bankmachine6_row_close = 1'd0;
+reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [21:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
+reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
+wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
+wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
+wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
+wire litedramcore_bankmachine7_cmd_buffer_sink_first;
+wire litedramcore_bankmachine7_cmd_buffer_sink_last;
+wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
+reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
+wire litedramcore_bankmachine7_cmd_buffer_source_ready;
+reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
+reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine7_row = 15'd0;
+reg litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg litedramcore_bankmachine7_row_open = 1'd0;
+reg litedramcore_bankmachine7_row_close = 1'd0;
+reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd1;
+reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+reg litedramcore_choose_cmd_want_reads = 1'd0;
+reg litedramcore_choose_cmd_want_writes = 1'd0;
+reg litedramcore_choose_cmd_want_cmds = 1'd0;
+reg litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg litedramcore_choose_req_want_reads = 1'd0;
+reg litedramcore_choose_req_want_writes = 1'd0;
+reg litedramcore_choose_req_want_cmds = 1'd0;
+reg litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg litedramcore_choose_req_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg [14:0] litedramcore_nop_a = 15'd0;
+reg [2:0] litedramcore_nop_ba = 3'd0;
+reg [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg litedramcore_steerer0 = 1'd1;
+reg litedramcore_steerer1 = 1'd1;
+reg litedramcore_steerer2 = 1'd1;
+reg litedramcore_steerer3 = 1'd1;
+reg litedramcore_steerer4 = 1'd1;
+reg litedramcore_steerer5 = 1'd1;
+reg litedramcore_steerer6 = 1'd1;
+reg litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd1;
+reg litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd1;
+reg litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd1;
+reg [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg [4:0] litedramcore_time0 = 5'd0;
+reg litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg init_done_storage = 1'd0;
+reg init_done_re = 1'd0;
+reg init_error_storage = 1'd0;
+reg init_error_re = 1'd0;
+wire [13:0] csr_port_adr;
+wire csr_port_we;
+wire [7:0] csr_port_dat_w;
+wire [7:0] csr_port_dat_r;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [24:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+wire pll_fb0;
+wire pll_fb1;
+reg [1:0] refresher_state = 2'd0;
+reg [1:0] refresher_next_state = 2'd0;
+reg [3:0] bankmachine0_state = 4'd0;
+reg [3:0] bankmachine0_next_state = 4'd0;
+reg [3:0] bankmachine1_state = 4'd0;
+reg [3:0] bankmachine1_next_state = 4'd0;
+reg [3:0] bankmachine2_state = 4'd0;
+reg [3:0] bankmachine2_next_state = 4'd0;
+reg [3:0] bankmachine3_state = 4'd0;
+reg [3:0] bankmachine3_next_state = 4'd0;
+reg [3:0] bankmachine4_state = 4'd0;
+reg [3:0] bankmachine4_next_state = 4'd0;
+reg [3:0] bankmachine5_state = 4'd0;
+reg [3:0] bankmachine5_next_state = 4'd0;
+reg [3:0] bankmachine6_state = 4'd0;
+reg [3:0] bankmachine6_next_state = 4'd0;
+reg [3:0] bankmachine7_state = 4'd0;
+reg [3:0] bankmachine7_next_state = 4'd0;
+reg [3:0] multiplexer_state = 4'd0;
+reg [3:0] multiplexer_next_state = 4'd0;
+wire roundrobin0_request;
+wire roundrobin0_grant;
+wire roundrobin0_ce;
+wire roundrobin1_request;
+wire roundrobin1_grant;
+wire roundrobin1_ce;
+wire roundrobin2_request;
+wire roundrobin2_grant;
+wire roundrobin2_ce;
+wire roundrobin3_request;
+wire roundrobin3_grant;
+wire roundrobin3_ce;
+wire roundrobin4_request;
+wire roundrobin4_grant;
+wire roundrobin4_ce;
+wire roundrobin5_request;
+wire roundrobin5_grant;
+wire roundrobin5_ce;
+wire roundrobin6_request;
+wire roundrobin6_grant;
+wire roundrobin6_ce;
+wire roundrobin7_request;
+wire roundrobin7_grant;
+wire roundrobin7_ce;
+reg locked0 = 1'd0;
+reg locked1 = 1'd0;
+reg locked2 = 1'd0;
+reg locked3 = 1'd0;
+reg locked4 = 1'd0;
+reg locked5 = 1'd0;
+reg locked6 = 1'd0;
+reg locked7 = 1'd0;
+reg new_master_wdata_ready0 = 1'd0;
+reg new_master_wdata_ready1 = 1'd0;
+reg new_master_wdata_ready2 = 1'd0;
+reg new_master_rdata_valid0 = 1'd0;
+reg new_master_rdata_valid1 = 1'd0;
+reg new_master_rdata_valid2 = 1'd0;
+reg new_master_rdata_valid3 = 1'd0;
+reg new_master_rdata_valid4 = 1'd0;
+reg new_master_rdata_valid5 = 1'd0;
+reg new_master_rdata_valid6 = 1'd0;
+reg new_master_rdata_valid7 = 1'd0;
+reg new_master_rdata_valid8 = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [7:0] interface0_bank_bus_dat_w;
+reg [7:0] interface0_bank_bus_dat_r = 8'd0;
+wire csrbank0_init_done0_re;
+wire csrbank0_init_done0_r;
+wire csrbank0_init_done0_we;
+wire csrbank0_init_done0_w;
+wire csrbank0_init_error0_re;
+wire csrbank0_init_error0_r;
+wire csrbank0_init_error0_we;
+wire csrbank0_init_error0_w;
+reg csrbank0_sel = 1'd0;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [7:0] interface1_bank_bus_dat_w;
+reg [7:0] interface1_bank_bus_dat_r = 8'd0;
+wire csrbank1_half_sys8x_taps0_re;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+wire csrbank1_half_sys8x_taps0_we;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+wire csrbank1_wlevel_en0_re;
+wire csrbank1_wlevel_en0_r;
+wire csrbank1_wlevel_en0_we;
+wire csrbank1_wlevel_en0_w;
+wire csrbank1_dly_sel0_re;
+wire [1:0] csrbank1_dly_sel0_r;
+wire csrbank1_dly_sel0_we;
+wire [1:0] csrbank1_dly_sel0_w;
+reg csrbank1_sel = 1'd0;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [7:0] interface2_bank_bus_dat_w;
+reg [7:0] interface2_bank_bus_dat_r = 8'd0;
+wire csrbank2_dfii_control0_re;
+wire [3:0] csrbank2_dfii_control0_r;
+wire csrbank2_dfii_control0_we;
+wire [3:0] csrbank2_dfii_control0_w;
+wire csrbank2_dfii_pi0_command0_re;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+wire csrbank2_dfii_pi0_command0_we;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+wire csrbank2_dfii_pi0_address1_re;
+wire [6:0] csrbank2_dfii_pi0_address1_r;
+wire csrbank2_dfii_pi0_address1_we;
+wire [6:0] csrbank2_dfii_pi0_address1_w;
+wire csrbank2_dfii_pi0_address0_re;
+wire [7:0] csrbank2_dfii_pi0_address0_r;
+wire csrbank2_dfii_pi0_address0_we;
+wire [7:0] csrbank2_dfii_pi0_address0_w;
+wire csrbank2_dfii_pi0_baddress0_re;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+wire csrbank2_dfii_pi0_baddress0_we;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+wire csrbank2_dfii_pi0_wrdata3_re;
+wire [7:0] csrbank2_dfii_pi0_wrdata3_r;
+wire csrbank2_dfii_pi0_wrdata3_we;
+wire [7:0] csrbank2_dfii_pi0_wrdata3_w;
+wire csrbank2_dfii_pi0_wrdata2_re;
+wire [7:0] csrbank2_dfii_pi0_wrdata2_r;
+wire csrbank2_dfii_pi0_wrdata2_we;
+wire [7:0] csrbank2_dfii_pi0_wrdata2_w;
+wire csrbank2_dfii_pi0_wrdata1_re;
+wire [7:0] csrbank2_dfii_pi0_wrdata1_r;
+wire csrbank2_dfii_pi0_wrdata1_we;
+wire [7:0] csrbank2_dfii_pi0_wrdata1_w;
+wire csrbank2_dfii_pi0_wrdata0_re;
+wire [7:0] csrbank2_dfii_pi0_wrdata0_r;
+wire csrbank2_dfii_pi0_wrdata0_we;
+wire [7:0] csrbank2_dfii_pi0_wrdata0_w;
+wire csrbank2_dfii_pi0_rddata3_re;
+wire [7:0] csrbank2_dfii_pi0_rddata3_r;
+wire csrbank2_dfii_pi0_rddata3_we;
+wire [7:0] csrbank2_dfii_pi0_rddata3_w;
+wire csrbank2_dfii_pi0_rddata2_re;
+wire [7:0] csrbank2_dfii_pi0_rddata2_r;
+wire csrbank2_dfii_pi0_rddata2_we;
+wire [7:0] csrbank2_dfii_pi0_rddata2_w;
+wire csrbank2_dfii_pi0_rddata1_re;
+wire [7:0] csrbank2_dfii_pi0_rddata1_r;
+wire csrbank2_dfii_pi0_rddata1_we;
+wire [7:0] csrbank2_dfii_pi0_rddata1_w;
+wire csrbank2_dfii_pi0_rddata0_re;
+wire [7:0] csrbank2_dfii_pi0_rddata0_r;
+wire csrbank2_dfii_pi0_rddata0_we;
+wire [7:0] csrbank2_dfii_pi0_rddata0_w;
+wire csrbank2_dfii_pi1_command0_re;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+wire csrbank2_dfii_pi1_command0_we;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+wire csrbank2_dfii_pi1_address1_re;
+wire [6:0] csrbank2_dfii_pi1_address1_r;
+wire csrbank2_dfii_pi1_address1_we;
+wire [6:0] csrbank2_dfii_pi1_address1_w;
+wire csrbank2_dfii_pi1_address0_re;
+wire [7:0] csrbank2_dfii_pi1_address0_r;
+wire csrbank2_dfii_pi1_address0_we;
+wire [7:0] csrbank2_dfii_pi1_address0_w;
+wire csrbank2_dfii_pi1_baddress0_re;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+wire csrbank2_dfii_pi1_baddress0_we;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+wire csrbank2_dfii_pi1_wrdata3_re;
+wire [7:0] csrbank2_dfii_pi1_wrdata3_r;
+wire csrbank2_dfii_pi1_wrdata3_we;
+wire [7:0] csrbank2_dfii_pi1_wrdata3_w;
+wire csrbank2_dfii_pi1_wrdata2_re;
+wire [7:0] csrbank2_dfii_pi1_wrdata2_r;
+wire csrbank2_dfii_pi1_wrdata2_we;
+wire [7:0] csrbank2_dfii_pi1_wrdata2_w;
+wire csrbank2_dfii_pi1_wrdata1_re;
+wire [7:0] csrbank2_dfii_pi1_wrdata1_r;
+wire csrbank2_dfii_pi1_wrdata1_we;
+wire [7:0] csrbank2_dfii_pi1_wrdata1_w;
+wire csrbank2_dfii_pi1_wrdata0_re;
+wire [7:0] csrbank2_dfii_pi1_wrdata0_r;
+wire csrbank2_dfii_pi1_wrdata0_we;
+wire [7:0] csrbank2_dfii_pi1_wrdata0_w;
+wire csrbank2_dfii_pi1_rddata3_re;
+wire [7:0] csrbank2_dfii_pi1_rddata3_r;
+wire csrbank2_dfii_pi1_rddata3_we;
+wire [7:0] csrbank2_dfii_pi1_rddata3_w;
+wire csrbank2_dfii_pi1_rddata2_re;
+wire [7:0] csrbank2_dfii_pi1_rddata2_r;
+wire csrbank2_dfii_pi1_rddata2_we;
+wire [7:0] csrbank2_dfii_pi1_rddata2_w;
+wire csrbank2_dfii_pi1_rddata1_re;
+wire [7:0] csrbank2_dfii_pi1_rddata1_r;
+wire csrbank2_dfii_pi1_rddata1_we;
+wire [7:0] csrbank2_dfii_pi1_rddata1_w;
+wire csrbank2_dfii_pi1_rddata0_re;
+wire [7:0] csrbank2_dfii_pi1_rddata0_r;
+wire csrbank2_dfii_pi1_rddata0_we;
+wire [7:0] csrbank2_dfii_pi1_rddata0_w;
+wire csrbank2_dfii_pi2_command0_re;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+wire csrbank2_dfii_pi2_command0_we;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+wire csrbank2_dfii_pi2_address1_re;
+wire [6:0] csrbank2_dfii_pi2_address1_r;
+wire csrbank2_dfii_pi2_address1_we;
+wire [6:0] csrbank2_dfii_pi2_address1_w;
+wire csrbank2_dfii_pi2_address0_re;
+wire [7:0] csrbank2_dfii_pi2_address0_r;
+wire csrbank2_dfii_pi2_address0_we;
+wire [7:0] csrbank2_dfii_pi2_address0_w;
+wire csrbank2_dfii_pi2_baddress0_re;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+wire csrbank2_dfii_pi2_baddress0_we;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+wire csrbank2_dfii_pi2_wrdata3_re;
+wire [7:0] csrbank2_dfii_pi2_wrdata3_r;
+wire csrbank2_dfii_pi2_wrdata3_we;
+wire [7:0] csrbank2_dfii_pi2_wrdata3_w;
+wire csrbank2_dfii_pi2_wrdata2_re;
+wire [7:0] csrbank2_dfii_pi2_wrdata2_r;
+wire csrbank2_dfii_pi2_wrdata2_we;
+wire [7:0] csrbank2_dfii_pi2_wrdata2_w;
+wire csrbank2_dfii_pi2_wrdata1_re;
+wire [7:0] csrbank2_dfii_pi2_wrdata1_r;
+wire csrbank2_dfii_pi2_wrdata1_we;
+wire [7:0] csrbank2_dfii_pi2_wrdata1_w;
+wire csrbank2_dfii_pi2_wrdata0_re;
+wire [7:0] csrbank2_dfii_pi2_wrdata0_r;
+wire csrbank2_dfii_pi2_wrdata0_we;
+wire [7:0] csrbank2_dfii_pi2_wrdata0_w;
+wire csrbank2_dfii_pi2_rddata3_re;
+wire [7:0] csrbank2_dfii_pi2_rddata3_r;
+wire csrbank2_dfii_pi2_rddata3_we;
+wire [7:0] csrbank2_dfii_pi2_rddata3_w;
+wire csrbank2_dfii_pi2_rddata2_re;
+wire [7:0] csrbank2_dfii_pi2_rddata2_r;
+wire csrbank2_dfii_pi2_rddata2_we;
+wire [7:0] csrbank2_dfii_pi2_rddata2_w;
+wire csrbank2_dfii_pi2_rddata1_re;
+wire [7:0] csrbank2_dfii_pi2_rddata1_r;
+wire csrbank2_dfii_pi2_rddata1_we;
+wire [7:0] csrbank2_dfii_pi2_rddata1_w;
+wire csrbank2_dfii_pi2_rddata0_re;
+wire [7:0] csrbank2_dfii_pi2_rddata0_r;
+wire csrbank2_dfii_pi2_rddata0_we;
+wire [7:0] csrbank2_dfii_pi2_rddata0_w;
+wire csrbank2_dfii_pi3_command0_re;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+wire csrbank2_dfii_pi3_command0_we;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+wire csrbank2_dfii_pi3_address1_re;
+wire [6:0] csrbank2_dfii_pi3_address1_r;
+wire csrbank2_dfii_pi3_address1_we;
+wire [6:0] csrbank2_dfii_pi3_address1_w;
+wire csrbank2_dfii_pi3_address0_re;
+wire [7:0] csrbank2_dfii_pi3_address0_r;
+wire csrbank2_dfii_pi3_address0_we;
+wire [7:0] csrbank2_dfii_pi3_address0_w;
+wire csrbank2_dfii_pi3_baddress0_re;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+wire csrbank2_dfii_pi3_baddress0_we;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+wire csrbank2_dfii_pi3_wrdata3_re;
+wire [7:0] csrbank2_dfii_pi3_wrdata3_r;
+wire csrbank2_dfii_pi3_wrdata3_we;
+wire [7:0] csrbank2_dfii_pi3_wrdata3_w;
+wire csrbank2_dfii_pi3_wrdata2_re;
+wire [7:0] csrbank2_dfii_pi3_wrdata2_r;
+wire csrbank2_dfii_pi3_wrdata2_we;
+wire [7:0] csrbank2_dfii_pi3_wrdata2_w;
+wire csrbank2_dfii_pi3_wrdata1_re;
+wire [7:0] csrbank2_dfii_pi3_wrdata1_r;
+wire csrbank2_dfii_pi3_wrdata1_we;
+wire [7:0] csrbank2_dfii_pi3_wrdata1_w;
+wire csrbank2_dfii_pi3_wrdata0_re;
+wire [7:0] csrbank2_dfii_pi3_wrdata0_r;
+wire csrbank2_dfii_pi3_wrdata0_we;
+wire [7:0] csrbank2_dfii_pi3_wrdata0_w;
+wire csrbank2_dfii_pi3_rddata3_re;
+wire [7:0] csrbank2_dfii_pi3_rddata3_r;
+wire csrbank2_dfii_pi3_rddata3_we;
+wire [7:0] csrbank2_dfii_pi3_rddata3_w;
+wire csrbank2_dfii_pi3_rddata2_re;
+wire [7:0] csrbank2_dfii_pi3_rddata2_r;
+wire csrbank2_dfii_pi3_rddata2_we;
+wire [7:0] csrbank2_dfii_pi3_rddata2_w;
+wire csrbank2_dfii_pi3_rddata1_re;
+wire [7:0] csrbank2_dfii_pi3_rddata1_r;
+wire csrbank2_dfii_pi3_rddata1_we;
+wire [7:0] csrbank2_dfii_pi3_rddata1_w;
+wire csrbank2_dfii_pi3_rddata0_re;
+wire [7:0] csrbank2_dfii_pi3_rddata0_r;
+wire csrbank2_dfii_pi3_rddata0_we;
+wire [7:0] csrbank2_dfii_pi3_rddata0_w;
+reg csrbank2_sel = 1'd0;
+wire [13:0] adr;
+wire we;
+wire [7:0] dat_w;
+wire [7:0] dat_r;
+reg rhs_array_muxed0 = 1'd0;
+reg [14:0] rhs_array_muxed1 = 15'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [14:0] rhs_array_muxed7 = 15'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [21:0] rhs_array_muxed12 = 22'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [21:0] rhs_array_muxed15 = 22'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [21:0] rhs_array_muxed18 = 22'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [21:0] rhs_array_muxed21 = 22'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [21:0] rhs_array_muxed24 = 22'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [21:0] rhs_array_muxed27 = 22'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [21:0] rhs_array_muxed30 = 22'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [21:0] rhs_array_muxed33 = 22'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [14:0] array_muxed1 = 15'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [14:0] array_muxed8 = 15'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+reg [2:0] array_muxed14 = 3'd0;
+reg [14:0] array_muxed15 = 15'd0;
+reg array_muxed16 = 1'd0;
+reg array_muxed17 = 1'd0;
+reg array_muxed18 = 1'd0;
+reg array_muxed19 = 1'd0;
+reg array_muxed20 = 1'd0;
+reg [2:0] array_muxed21 = 3'd0;
+reg [14:0] array_muxed22 = 15'd0;
+reg array_muxed23 = 1'd0;
+reg array_muxed24 = 1'd0;
+reg array_muxed25 = 1'd0;
+reg array_muxed26 = 1'd0;
+reg array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1_expr;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
 
 // synthesis translate_off
 reg dummy_s;
 initial dummy_s <= 1'd0;
 // synthesis translate_on
-assign soc_litedramcore_cpu_reset = soc_litedramcore_soccontroller_reset;
-assign init_done = soc_init_done_storage;
-assign init_error = soc_init_error_storage;
+assign init_done = init_done_storage;
+assign init_error = init_error_storage;
+assign csr_port_adr = csr_port0_adr;
+assign csr_port_we = csr_port0_we;
+assign csr_port_dat_w = csr_port0_dat_w;
+assign csr_port0_dat_r = csr_port_dat_r;
 assign user_clk = sys_clk;
 assign user_rst = sys_rst;
-assign soc_cmd_valid = user_port_native_0_cmd_valid;
-assign user_port_native_0_cmd_ready = soc_cmd_ready;
-assign soc_cmd_payload_we = user_port_native_0_cmd_we;
-assign soc_cmd_payload_addr = user_port_native_0_cmd_addr;
-assign soc_wdata_valid = user_port_native_0_wdata_valid;
-assign user_port_native_0_wdata_ready = soc_wdata_ready;
-assign soc_wdata_payload_we = user_port_native_0_wdata_we;
-assign soc_wdata_payload_data = user_port_native_0_wdata_data;
-assign user_port_native_0_rdata_valid = soc_rdata_valid;
-assign soc_rdata_ready = user_port_native_0_rdata_ready;
-assign user_port_native_0_rdata_data = soc_rdata_payload_data;
-assign soc_litedramcore_soccontroller_bus_error = vns_error;
+assign user_port_cmd_valid = user_port_native_0_cmd_valid;
+assign user_port_native_0_cmd_ready = user_port_cmd_ready;
+assign user_port_cmd_payload_we = user_port_native_0_cmd_we;
+assign user_port_cmd_payload_addr = user_port_native_0_cmd_addr;
+assign user_port_wdata_valid = user_port_native_0_wdata_valid;
+assign user_port_native_0_wdata_ready = user_port_wdata_ready;
+assign user_port_wdata_payload_we = user_port_native_0_wdata_we;
+assign user_port_wdata_payload_data = user_port_native_0_wdata_data;
+assign user_port_native_0_rdata_valid = user_port_rdata_valid;
+assign user_port_rdata_ready = user_port_native_0_rdata_ready;
+assign user_port_native_0_rdata_data = user_port_rdata_payload_data;
+assign sys_pll_reset = rst;
+assign pll_locked = sys_pll_locked;
+assign iodelay_pll_reset = rst;
+assign s7pll0_clkin = clk;
+assign sys_clk = s7pll0_clkout_buf0;
+assign sys4x_clk = s7pll0_clkout_buf1;
+assign sys4x_dqs_clk = s7pll0_clkout_buf2;
+assign s7pll1_clkin = clk;
+assign iodelay_clk = s7pll1_clkout_buf;
+assign a7ddrphy_bitslip0_i = a7ddrphy_dq_i_data0;
 
 // synthesis translate_off
 reg dummy_d;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_cpu_interrupt <= 32'd0;
-       soc_litedramcore_cpu_interrupt[1] <= soc_litedramcore_timer_irq;
-       soc_litedramcore_cpu_interrupt[0] <= soc_litedramcore_uart_irq;
+       a7ddrphy_dfi_p0_rddata <= 32'd0;
+       a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip0_o[0];
+       a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip0_o[1];
+       a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip1_o[0];
+       a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip1_o[1];
+       a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip2_o[0];
+       a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip2_o[1];
+       a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip3_o[0];
+       a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip3_o[1];
+       a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip4_o[0];
+       a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip4_o[1];
+       a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip5_o[0];
+       a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip5_o[1];
+       a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip6_o[0];
+       a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip6_o[1];
+       a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip7_o[0];
+       a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip7_o[1];
+       a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip8_o[0];
+       a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip8_o[1];
+       a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip9_o[0];
+       a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip9_o[1];
+       a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip10_o[0];
+       a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip10_o[1];
+       a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip11_o[0];
+       a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip11_o[1];
+       a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip12_o[0];
+       a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip12_o[1];
+       a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip13_o[0];
+       a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip13_o[1];
+       a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip14_o[0];
+       a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip14_o[1];
+       a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip15_o[0];
+       a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip15_o[1];
 // synthesis translate_off
        dummy_d = dummy_s;
 // synthesis translate_on
 end
-assign soc_litedramcore_soccontroller_reset = soc_litedramcore_soccontroller_reset_re;
-assign soc_litedramcore_soccontroller_bus_errors_status = soc_litedramcore_soccontroller_bus_errors;
-assign soc_litedramcore_litedramcore_adr = soc_litedramcore_litedramcore_ram_bus_adr[12:0];
-assign soc_litedramcore_litedramcore_ram_bus_dat_r = soc_litedramcore_litedramcore_dat_r;
 
 // synthesis translate_off
 reg dummy_d_1;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_ram_we <= 4'd0;
-       soc_litedramcore_ram_we[0] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[0]);
-       soc_litedramcore_ram_we[1] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[1]);
-       soc_litedramcore_ram_we[2] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[2]);
-       soc_litedramcore_ram_we[3] <= (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & soc_litedramcore_ram_bus_ram_bus_we) & soc_litedramcore_ram_bus_ram_bus_sel[3]);
+       a7ddrphy_dfi_p1_rddata <= 32'd0;
+       a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip0_o[2];
+       a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip0_o[3];
+       a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip1_o[2];
+       a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip1_o[3];
+       a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip2_o[2];
+       a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip2_o[3];
+       a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip3_o[2];
+       a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip3_o[3];
+       a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip4_o[2];
+       a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip4_o[3];
+       a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip5_o[2];
+       a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip5_o[3];
+       a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip6_o[2];
+       a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip6_o[3];
+       a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip7_o[2];
+       a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip7_o[3];
+       a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip8_o[2];
+       a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip8_o[3];
+       a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip9_o[2];
+       a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip9_o[3];
+       a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip10_o[2];
+       a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip10_o[3];
+       a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip11_o[2];
+       a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip11_o[3];
+       a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip12_o[2];
+       a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip12_o[3];
+       a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip13_o[2];
+       a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip13_o[3];
+       a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip14_o[2];
+       a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip14_o[3];
+       a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip15_o[2];
+       a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip15_o[3];
 // synthesis translate_off
        dummy_d_1 = dummy_s;
 // synthesis translate_on
 end
-assign soc_litedramcore_ram_adr = soc_litedramcore_ram_bus_ram_bus_adr[9:0];
-assign soc_litedramcore_ram_bus_ram_bus_dat_r = soc_litedramcore_ram_dat_r;
-assign soc_litedramcore_ram_dat_w = soc_litedramcore_ram_bus_ram_bus_dat_w;
-assign soc_litedramcore_uart_uart_sink_valid = soc_litedramcore_source_valid;
-assign soc_litedramcore_source_ready = soc_litedramcore_uart_uart_sink_ready;
-assign soc_litedramcore_uart_uart_sink_first = soc_litedramcore_source_first;
-assign soc_litedramcore_uart_uart_sink_last = soc_litedramcore_source_last;
-assign soc_litedramcore_uart_uart_sink_payload_data = soc_litedramcore_source_payload_data;
-assign soc_litedramcore_sink_valid = soc_litedramcore_uart_uart_source_valid;
-assign soc_litedramcore_uart_uart_source_ready = soc_litedramcore_sink_ready;
-assign soc_litedramcore_sink_first = soc_litedramcore_uart_uart_source_first;
-assign soc_litedramcore_sink_last = soc_litedramcore_uart_uart_source_last;
-assign soc_litedramcore_sink_payload_data = soc_litedramcore_uart_uart_source_payload_data;
-assign soc_litedramcore_uart_tx_fifo_sink_valid = soc_litedramcore_uart_rxtx_re;
-assign soc_litedramcore_uart_tx_fifo_sink_payload_data = soc_litedramcore_uart_rxtx_r;
-assign soc_litedramcore_uart_txfull_status = (~soc_litedramcore_uart_tx_fifo_sink_ready);
-assign soc_litedramcore_uart_uart_source_valid = soc_litedramcore_uart_tx_fifo_source_valid;
-assign soc_litedramcore_uart_tx_fifo_source_ready = soc_litedramcore_uart_uart_source_ready;
-assign soc_litedramcore_uart_uart_source_first = soc_litedramcore_uart_tx_fifo_source_first;
-assign soc_litedramcore_uart_uart_source_last = soc_litedramcore_uart_tx_fifo_source_last;
-assign soc_litedramcore_uart_uart_source_payload_data = soc_litedramcore_uart_tx_fifo_source_payload_data;
-assign soc_litedramcore_uart_tx_trigger = (~soc_litedramcore_uart_tx_fifo_sink_ready);
-assign soc_litedramcore_uart_rx_fifo_sink_valid = soc_litedramcore_uart_uart_sink_valid;
-assign soc_litedramcore_uart_uart_sink_ready = soc_litedramcore_uart_rx_fifo_sink_ready;
-assign soc_litedramcore_uart_rx_fifo_sink_first = soc_litedramcore_uart_uart_sink_first;
-assign soc_litedramcore_uart_rx_fifo_sink_last = soc_litedramcore_uart_uart_sink_last;
-assign soc_litedramcore_uart_rx_fifo_sink_payload_data = soc_litedramcore_uart_uart_sink_payload_data;
-assign soc_litedramcore_uart_rxempty_status = (~soc_litedramcore_uart_rx_fifo_source_valid);
-assign soc_litedramcore_uart_rxtx_w = soc_litedramcore_uart_rx_fifo_source_payload_data;
-assign soc_litedramcore_uart_rx_fifo_source_ready = (soc_litedramcore_uart_rx_clear | (1'd0 & soc_litedramcore_uart_rxtx_we));
-assign soc_litedramcore_uart_rx_trigger = (~soc_litedramcore_uart_rx_fifo_source_valid);
 
 // synthesis translate_off
 reg dummy_d_2;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_uart_eventmanager_status_w <= 2'd0;
-       soc_litedramcore_uart_eventmanager_status_w[0] <= soc_litedramcore_uart_tx_status;
-       soc_litedramcore_uart_eventmanager_status_w[1] <= soc_litedramcore_uart_rx_status;
+       a7ddrphy_dfi_p2_rddata <= 32'd0;
+       a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip0_o[4];
+       a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip0_o[5];
+       a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip1_o[4];
+       a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip1_o[5];
+       a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip2_o[4];
+       a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip2_o[5];
+       a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip3_o[4];
+       a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip3_o[5];
+       a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip4_o[4];
+       a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip4_o[5];
+       a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip5_o[4];
+       a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip5_o[5];
+       a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip6_o[4];
+       a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip6_o[5];
+       a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip7_o[4];
+       a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip7_o[5];
+       a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip8_o[4];
+       a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip8_o[5];
+       a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip9_o[4];
+       a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip9_o[5];
+       a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip10_o[4];
+       a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip10_o[5];
+       a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip11_o[4];
+       a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip11_o[5];
+       a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip12_o[4];
+       a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip12_o[5];
+       a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip13_o[4];
+       a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip13_o[5];
+       a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip14_o[4];
+       a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip14_o[5];
+       a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip15_o[4];
+       a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip15_o[5];
 // synthesis translate_off
        dummy_d_2 = dummy_s;
 // synthesis translate_on
@@ -2562,1302 +2044,1142 @@ end
 reg dummy_d_3;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_uart_tx_clear <= 1'd0;
-       if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[0])) begin
-               soc_litedramcore_uart_tx_clear <= 1'd1;
-       end
+       a7ddrphy_dfi_p3_rddata <= 32'd0;
+       a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip0_o[6];
+       a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip0_o[7];
+       a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip1_o[6];
+       a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip1_o[7];
+       a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip2_o[6];
+       a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip2_o[7];
+       a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip3_o[6];
+       a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip3_o[7];
+       a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip4_o[6];
+       a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip4_o[7];
+       a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip5_o[6];
+       a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip5_o[7];
+       a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip6_o[6];
+       a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip6_o[7];
+       a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip7_o[6];
+       a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip7_o[7];
+       a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip8_o[6];
+       a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip8_o[7];
+       a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip9_o[6];
+       a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip9_o[7];
+       a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip10_o[6];
+       a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip10_o[7];
+       a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip11_o[6];
+       a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip11_o[7];
+       a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip12_o[6];
+       a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip12_o[7];
+       a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip13_o[6];
+       a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip13_o[7];
+       a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip14_o[6];
+       a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip14_o[7];
+       a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip15_o[6];
+       a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip15_o[7];
 // synthesis translate_off
        dummy_d_3 = dummy_s;
 // synthesis translate_on
 end
+assign a7ddrphy_bitslip1_i = a7ddrphy_dq_i_data1;
+assign a7ddrphy_bitslip2_i = a7ddrphy_dq_i_data2;
+assign a7ddrphy_bitslip3_i = a7ddrphy_dq_i_data3;
+assign a7ddrphy_bitslip4_i = a7ddrphy_dq_i_data4;
+assign a7ddrphy_bitslip5_i = a7ddrphy_dq_i_data5;
+assign a7ddrphy_bitslip6_i = a7ddrphy_dq_i_data6;
+assign a7ddrphy_bitslip7_i = a7ddrphy_dq_i_data7;
+assign a7ddrphy_bitslip8_i = a7ddrphy_dq_i_data8;
+assign a7ddrphy_bitslip9_i = a7ddrphy_dq_i_data9;
+assign a7ddrphy_bitslip10_i = a7ddrphy_dq_i_data10;
+assign a7ddrphy_bitslip11_i = a7ddrphy_dq_i_data11;
+assign a7ddrphy_bitslip12_i = a7ddrphy_dq_i_data12;
+assign a7ddrphy_bitslip13_i = a7ddrphy_dq_i_data13;
+assign a7ddrphy_bitslip14_i = a7ddrphy_dq_i_data14;
+assign a7ddrphy_bitslip15_i = a7ddrphy_dq_i_data15;
+assign a7ddrphy_rddata_en = {a7ddrphy_rddata_en_last, a7ddrphy_dfi_p2_rddata_en};
+assign a7ddrphy_wrdata_en = {a7ddrphy_wrdata_en_last, a7ddrphy_dfi_p3_wrdata_en};
+assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en[2];
 
 // synthesis translate_off
 reg dummy_d_4;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_uart_eventmanager_pending_w <= 2'd0;
-       soc_litedramcore_uart_eventmanager_pending_w[0] <= soc_litedramcore_uart_tx_pending;
-       soc_litedramcore_uart_eventmanager_pending_w[1] <= soc_litedramcore_uart_rx_pending;
-// synthesis translate_off
-       dummy_d_4 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_5;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_uart_rx_clear <= 1'd0;
-       if ((soc_litedramcore_uart_eventmanager_pending_re & soc_litedramcore_uart_eventmanager_pending_r[1])) begin
-               soc_litedramcore_uart_rx_clear <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_5 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_uart_irq = ((soc_litedramcore_uart_eventmanager_pending_w[0] & soc_litedramcore_uart_eventmanager_storage[0]) | (soc_litedramcore_uart_eventmanager_pending_w[1] & soc_litedramcore_uart_eventmanager_storage[1]));
-assign soc_litedramcore_uart_tx_status = soc_litedramcore_uart_tx_trigger;
-assign soc_litedramcore_uart_rx_status = soc_litedramcore_uart_rx_trigger;
-assign soc_litedramcore_uart_tx_fifo_syncfifo_din = {soc_litedramcore_uart_tx_fifo_fifo_in_last, soc_litedramcore_uart_tx_fifo_fifo_in_first, soc_litedramcore_uart_tx_fifo_fifo_in_payload_data};
-assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
-assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
-assign {soc_litedramcore_uart_tx_fifo_fifo_out_last, soc_litedramcore_uart_tx_fifo_fifo_out_first, soc_litedramcore_uart_tx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_tx_fifo_syncfifo_dout;
-assign soc_litedramcore_uart_tx_fifo_sink_ready = soc_litedramcore_uart_tx_fifo_syncfifo_writable;
-assign soc_litedramcore_uart_tx_fifo_syncfifo_we = soc_litedramcore_uart_tx_fifo_sink_valid;
-assign soc_litedramcore_uart_tx_fifo_fifo_in_first = soc_litedramcore_uart_tx_fifo_sink_first;
-assign soc_litedramcore_uart_tx_fifo_fifo_in_last = soc_litedramcore_uart_tx_fifo_sink_last;
-assign soc_litedramcore_uart_tx_fifo_fifo_in_payload_data = soc_litedramcore_uart_tx_fifo_sink_payload_data;
-assign soc_litedramcore_uart_tx_fifo_source_valid = soc_litedramcore_uart_tx_fifo_readable;
-assign soc_litedramcore_uart_tx_fifo_source_first = soc_litedramcore_uart_tx_fifo_fifo_out_first;
-assign soc_litedramcore_uart_tx_fifo_source_last = soc_litedramcore_uart_tx_fifo_fifo_out_last;
-assign soc_litedramcore_uart_tx_fifo_source_payload_data = soc_litedramcore_uart_tx_fifo_fifo_out_payload_data;
-assign soc_litedramcore_uart_tx_fifo_re = soc_litedramcore_uart_tx_fifo_source_ready;
-assign soc_litedramcore_uart_tx_fifo_syncfifo_re = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_tx_fifo_readable) | soc_litedramcore_uart_tx_fifo_re));
-assign soc_litedramcore_uart_tx_fifo_level1 = (soc_litedramcore_uart_tx_fifo_level0 + soc_litedramcore_uart_tx_fifo_readable);
-
-// synthesis translate_off
-reg dummy_d_6;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_uart_tx_fifo_wrport_adr <= 4'd0;
-       if (soc_litedramcore_uart_tx_fifo_replace) begin
-               soc_litedramcore_uart_tx_fifo_wrport_adr <= (soc_litedramcore_uart_tx_fifo_produce - 1'd1);
-       end else begin
-               soc_litedramcore_uart_tx_fifo_wrport_adr <= soc_litedramcore_uart_tx_fifo_produce;
-       end
-// synthesis translate_off
-       dummy_d_6 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_uart_tx_fifo_wrport_dat_w = soc_litedramcore_uart_tx_fifo_syncfifo_din;
-assign soc_litedramcore_uart_tx_fifo_wrport_we = (soc_litedramcore_uart_tx_fifo_syncfifo_we & (soc_litedramcore_uart_tx_fifo_syncfifo_writable | soc_litedramcore_uart_tx_fifo_replace));
-assign soc_litedramcore_uart_tx_fifo_do_read = (soc_litedramcore_uart_tx_fifo_syncfifo_readable & soc_litedramcore_uart_tx_fifo_syncfifo_re);
-assign soc_litedramcore_uart_tx_fifo_rdport_adr = soc_litedramcore_uart_tx_fifo_consume;
-assign soc_litedramcore_uart_tx_fifo_syncfifo_dout = soc_litedramcore_uart_tx_fifo_rdport_dat_r;
-assign soc_litedramcore_uart_tx_fifo_rdport_re = soc_litedramcore_uart_tx_fifo_do_read;
-assign soc_litedramcore_uart_tx_fifo_syncfifo_writable = (soc_litedramcore_uart_tx_fifo_level0 != 5'd16);
-assign soc_litedramcore_uart_tx_fifo_syncfifo_readable = (soc_litedramcore_uart_tx_fifo_level0 != 1'd0);
-assign soc_litedramcore_uart_rx_fifo_syncfifo_din = {soc_litedramcore_uart_rx_fifo_fifo_in_last, soc_litedramcore_uart_rx_fifo_fifo_in_first, soc_litedramcore_uart_rx_fifo_fifo_in_payload_data};
-assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
-assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
-assign {soc_litedramcore_uart_rx_fifo_fifo_out_last, soc_litedramcore_uart_rx_fifo_fifo_out_first, soc_litedramcore_uart_rx_fifo_fifo_out_payload_data} = soc_litedramcore_uart_rx_fifo_syncfifo_dout;
-assign soc_litedramcore_uart_rx_fifo_sink_ready = soc_litedramcore_uart_rx_fifo_syncfifo_writable;
-assign soc_litedramcore_uart_rx_fifo_syncfifo_we = soc_litedramcore_uart_rx_fifo_sink_valid;
-assign soc_litedramcore_uart_rx_fifo_fifo_in_first = soc_litedramcore_uart_rx_fifo_sink_first;
-assign soc_litedramcore_uart_rx_fifo_fifo_in_last = soc_litedramcore_uart_rx_fifo_sink_last;
-assign soc_litedramcore_uart_rx_fifo_fifo_in_payload_data = soc_litedramcore_uart_rx_fifo_sink_payload_data;
-assign soc_litedramcore_uart_rx_fifo_source_valid = soc_litedramcore_uart_rx_fifo_readable;
-assign soc_litedramcore_uart_rx_fifo_source_first = soc_litedramcore_uart_rx_fifo_fifo_out_first;
-assign soc_litedramcore_uart_rx_fifo_source_last = soc_litedramcore_uart_rx_fifo_fifo_out_last;
-assign soc_litedramcore_uart_rx_fifo_source_payload_data = soc_litedramcore_uart_rx_fifo_fifo_out_payload_data;
-assign soc_litedramcore_uart_rx_fifo_re = soc_litedramcore_uart_rx_fifo_source_ready;
-assign soc_litedramcore_uart_rx_fifo_syncfifo_re = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & ((~soc_litedramcore_uart_rx_fifo_readable) | soc_litedramcore_uart_rx_fifo_re));
-assign soc_litedramcore_uart_rx_fifo_level1 = (soc_litedramcore_uart_rx_fifo_level0 + soc_litedramcore_uart_rx_fifo_readable);
-
-// synthesis translate_off
-reg dummy_d_7;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_uart_rx_fifo_wrport_adr <= 4'd0;
-       if (soc_litedramcore_uart_rx_fifo_replace) begin
-               soc_litedramcore_uart_rx_fifo_wrport_adr <= (soc_litedramcore_uart_rx_fifo_produce - 1'd1);
-       end else begin
-               soc_litedramcore_uart_rx_fifo_wrport_adr <= soc_litedramcore_uart_rx_fifo_produce;
-       end
-// synthesis translate_off
-       dummy_d_7 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_uart_rx_fifo_wrport_dat_w = soc_litedramcore_uart_rx_fifo_syncfifo_din;
-assign soc_litedramcore_uart_rx_fifo_wrport_we = (soc_litedramcore_uart_rx_fifo_syncfifo_we & (soc_litedramcore_uart_rx_fifo_syncfifo_writable | soc_litedramcore_uart_rx_fifo_replace));
-assign soc_litedramcore_uart_rx_fifo_do_read = (soc_litedramcore_uart_rx_fifo_syncfifo_readable & soc_litedramcore_uart_rx_fifo_syncfifo_re);
-assign soc_litedramcore_uart_rx_fifo_rdport_adr = soc_litedramcore_uart_rx_fifo_consume;
-assign soc_litedramcore_uart_rx_fifo_syncfifo_dout = soc_litedramcore_uart_rx_fifo_rdport_dat_r;
-assign soc_litedramcore_uart_rx_fifo_rdport_re = soc_litedramcore_uart_rx_fifo_do_read;
-assign soc_litedramcore_uart_rx_fifo_syncfifo_writable = (soc_litedramcore_uart_rx_fifo_level0 != 5'd16);
-assign soc_litedramcore_uart_rx_fifo_syncfifo_readable = (soc_litedramcore_uart_rx_fifo_level0 != 1'd0);
-assign soc_litedramcore_timer_zero_trigger = (soc_litedramcore_timer_value != 1'd0);
-assign soc_litedramcore_timer_eventmanager_status_w = soc_litedramcore_timer_zero_status;
-
-// synthesis translate_off
-reg dummy_d_8;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_timer_zero_clear <= 1'd0;
-       if ((soc_litedramcore_timer_eventmanager_pending_re & soc_litedramcore_timer_eventmanager_pending_r)) begin
-               soc_litedramcore_timer_zero_clear <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_8 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_timer_eventmanager_pending_w = soc_litedramcore_timer_zero_pending;
-assign soc_litedramcore_timer_irq = (soc_litedramcore_timer_eventmanager_pending_w & soc_litedramcore_timer_eventmanager_storage);
-assign soc_litedramcore_timer_zero_status = soc_litedramcore_timer_zero_trigger;
-assign soc_litedramcore_interface_dat_w = soc_litedramcore_bus_wishbone_dat_w;
-assign soc_litedramcore_bus_wishbone_dat_r = soc_litedramcore_interface_dat_r;
-
-// synthesis translate_off
-reg dummy_d_9;
-// synthesis translate_on
-always @(*) begin
-       vns_wb2csr_next_state <= 1'd0;
-       vns_wb2csr_next_state <= vns_wb2csr_state;
-       case (vns_wb2csr_state)
-               1'd1: begin
-                       vns_wb2csr_next_state <= 1'd0;
-               end
-               default: begin
-                       if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
-                               vns_wb2csr_next_state <= 1'd1;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_9 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_10;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_interface_adr <= 14'd0;
-       case (vns_wb2csr_state)
-               1'd1: begin
-               end
-               default: begin
-                       if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
-                               soc_litedramcore_interface_adr <= soc_litedramcore_bus_wishbone_adr;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_10 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_11;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_interface_we <= 1'd0;
-       case (vns_wb2csr_state)
-               1'd1: begin
-               end
-               default: begin
-                       if ((soc_litedramcore_bus_wishbone_cyc & soc_litedramcore_bus_wishbone_stb)) begin
-                               soc_litedramcore_interface_we <= soc_litedramcore_bus_wishbone_we;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_11 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_12;
-// synthesis translate_on
-always @(*) begin
-       soc_litedramcore_bus_wishbone_ack <= 1'd0;
-       case (vns_wb2csr_state)
-               1'd1: begin
-                       soc_litedramcore_bus_wishbone_ack <= 1'd1;
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_12 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sys_pll_reset = rst;
-assign pll_locked = soc_sys_pll_locked;
-assign soc_iodelay_pll_reset = rst;
-assign soc_s7pll0_clkin = clk;
-assign sys_clk = soc_s7pll0_clkout_buf0;
-assign sys4x_clk = soc_s7pll0_clkout_buf1;
-assign sys4x_dqs_clk = soc_s7pll0_clkout_buf2;
-assign soc_s7pll1_clkin = clk;
-assign iodelay_clk = soc_s7pll1_clkout_buf;
-assign soc_a7ddrphy_bitslip0_i = soc_a7ddrphy_dq_i_data0;
-
-// synthesis translate_off
-reg dummy_d_13;
-// synthesis translate_on
-always @(*) begin
-       soc_a7ddrphy_dfi_p0_rddata <= 32'd0;
-       soc_a7ddrphy_dfi_p0_rddata[0] <= soc_a7ddrphy_bitslip0_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[16] <= soc_a7ddrphy_bitslip0_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[1] <= soc_a7ddrphy_bitslip1_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[17] <= soc_a7ddrphy_bitslip1_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[2] <= soc_a7ddrphy_bitslip2_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[18] <= soc_a7ddrphy_bitslip2_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[3] <= soc_a7ddrphy_bitslip3_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[19] <= soc_a7ddrphy_bitslip3_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[4] <= soc_a7ddrphy_bitslip4_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[20] <= soc_a7ddrphy_bitslip4_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[5] <= soc_a7ddrphy_bitslip5_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[21] <= soc_a7ddrphy_bitslip5_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[6] <= soc_a7ddrphy_bitslip6_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[22] <= soc_a7ddrphy_bitslip6_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[7] <= soc_a7ddrphy_bitslip7_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[23] <= soc_a7ddrphy_bitslip7_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[8] <= soc_a7ddrphy_bitslip8_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[24] <= soc_a7ddrphy_bitslip8_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[9] <= soc_a7ddrphy_bitslip9_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[25] <= soc_a7ddrphy_bitslip9_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[10] <= soc_a7ddrphy_bitslip10_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[26] <= soc_a7ddrphy_bitslip10_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[11] <= soc_a7ddrphy_bitslip11_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[27] <= soc_a7ddrphy_bitslip11_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[12] <= soc_a7ddrphy_bitslip12_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[28] <= soc_a7ddrphy_bitslip12_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[13] <= soc_a7ddrphy_bitslip13_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[29] <= soc_a7ddrphy_bitslip13_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[14] <= soc_a7ddrphy_bitslip14_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[30] <= soc_a7ddrphy_bitslip14_o[1];
-       soc_a7ddrphy_dfi_p0_rddata[15] <= soc_a7ddrphy_bitslip15_o[0];
-       soc_a7ddrphy_dfi_p0_rddata[31] <= soc_a7ddrphy_bitslip15_o[1];
-// synthesis translate_off
-       dummy_d_13 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_14;
-// synthesis translate_on
-always @(*) begin
-       soc_a7ddrphy_dfi_p1_rddata <= 32'd0;
-       soc_a7ddrphy_dfi_p1_rddata[0] <= soc_a7ddrphy_bitslip0_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[16] <= soc_a7ddrphy_bitslip0_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[1] <= soc_a7ddrphy_bitslip1_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[17] <= soc_a7ddrphy_bitslip1_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[2] <= soc_a7ddrphy_bitslip2_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[18] <= soc_a7ddrphy_bitslip2_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[3] <= soc_a7ddrphy_bitslip3_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[19] <= soc_a7ddrphy_bitslip3_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[4] <= soc_a7ddrphy_bitslip4_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[20] <= soc_a7ddrphy_bitslip4_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[5] <= soc_a7ddrphy_bitslip5_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[21] <= soc_a7ddrphy_bitslip5_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[6] <= soc_a7ddrphy_bitslip6_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[22] <= soc_a7ddrphy_bitslip6_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[7] <= soc_a7ddrphy_bitslip7_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[23] <= soc_a7ddrphy_bitslip7_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[8] <= soc_a7ddrphy_bitslip8_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[24] <= soc_a7ddrphy_bitslip8_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[9] <= soc_a7ddrphy_bitslip9_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[25] <= soc_a7ddrphy_bitslip9_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[10] <= soc_a7ddrphy_bitslip10_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[26] <= soc_a7ddrphy_bitslip10_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[11] <= soc_a7ddrphy_bitslip11_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[27] <= soc_a7ddrphy_bitslip11_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[12] <= soc_a7ddrphy_bitslip12_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[28] <= soc_a7ddrphy_bitslip12_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[13] <= soc_a7ddrphy_bitslip13_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[29] <= soc_a7ddrphy_bitslip13_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[14] <= soc_a7ddrphy_bitslip14_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[30] <= soc_a7ddrphy_bitslip14_o[3];
-       soc_a7ddrphy_dfi_p1_rddata[15] <= soc_a7ddrphy_bitslip15_o[2];
-       soc_a7ddrphy_dfi_p1_rddata[31] <= soc_a7ddrphy_bitslip15_o[3];
-// synthesis translate_off
-       dummy_d_14 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_15;
-// synthesis translate_on
-always @(*) begin
-       soc_a7ddrphy_dfi_p2_rddata <= 32'd0;
-       soc_a7ddrphy_dfi_p2_rddata[0] <= soc_a7ddrphy_bitslip0_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[16] <= soc_a7ddrphy_bitslip0_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[1] <= soc_a7ddrphy_bitslip1_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[17] <= soc_a7ddrphy_bitslip1_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[2] <= soc_a7ddrphy_bitslip2_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[18] <= soc_a7ddrphy_bitslip2_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[3] <= soc_a7ddrphy_bitslip3_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[19] <= soc_a7ddrphy_bitslip3_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[4] <= soc_a7ddrphy_bitslip4_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[20] <= soc_a7ddrphy_bitslip4_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[5] <= soc_a7ddrphy_bitslip5_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[21] <= soc_a7ddrphy_bitslip5_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[6] <= soc_a7ddrphy_bitslip6_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[22] <= soc_a7ddrphy_bitslip6_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[7] <= soc_a7ddrphy_bitslip7_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[23] <= soc_a7ddrphy_bitslip7_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[8] <= soc_a7ddrphy_bitslip8_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[24] <= soc_a7ddrphy_bitslip8_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[9] <= soc_a7ddrphy_bitslip9_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[25] <= soc_a7ddrphy_bitslip9_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[10] <= soc_a7ddrphy_bitslip10_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[26] <= soc_a7ddrphy_bitslip10_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[11] <= soc_a7ddrphy_bitslip11_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[27] <= soc_a7ddrphy_bitslip11_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[12] <= soc_a7ddrphy_bitslip12_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[28] <= soc_a7ddrphy_bitslip12_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[13] <= soc_a7ddrphy_bitslip13_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[29] <= soc_a7ddrphy_bitslip13_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[14] <= soc_a7ddrphy_bitslip14_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[30] <= soc_a7ddrphy_bitslip14_o[5];
-       soc_a7ddrphy_dfi_p2_rddata[15] <= soc_a7ddrphy_bitslip15_o[4];
-       soc_a7ddrphy_dfi_p2_rddata[31] <= soc_a7ddrphy_bitslip15_o[5];
-// synthesis translate_off
-       dummy_d_15 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_16;
-// synthesis translate_on
-always @(*) begin
-       soc_a7ddrphy_dfi_p3_rddata <= 32'd0;
-       soc_a7ddrphy_dfi_p3_rddata[0] <= soc_a7ddrphy_bitslip0_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[16] <= soc_a7ddrphy_bitslip0_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[1] <= soc_a7ddrphy_bitslip1_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[17] <= soc_a7ddrphy_bitslip1_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[2] <= soc_a7ddrphy_bitslip2_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[18] <= soc_a7ddrphy_bitslip2_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[3] <= soc_a7ddrphy_bitslip3_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[19] <= soc_a7ddrphy_bitslip3_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[4] <= soc_a7ddrphy_bitslip4_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[20] <= soc_a7ddrphy_bitslip4_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[5] <= soc_a7ddrphy_bitslip5_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[21] <= soc_a7ddrphy_bitslip5_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[6] <= soc_a7ddrphy_bitslip6_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[22] <= soc_a7ddrphy_bitslip6_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[7] <= soc_a7ddrphy_bitslip7_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[23] <= soc_a7ddrphy_bitslip7_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[8] <= soc_a7ddrphy_bitslip8_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[24] <= soc_a7ddrphy_bitslip8_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[9] <= soc_a7ddrphy_bitslip9_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[25] <= soc_a7ddrphy_bitslip9_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[10] <= soc_a7ddrphy_bitslip10_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[26] <= soc_a7ddrphy_bitslip10_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[11] <= soc_a7ddrphy_bitslip11_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[27] <= soc_a7ddrphy_bitslip11_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[12] <= soc_a7ddrphy_bitslip12_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[28] <= soc_a7ddrphy_bitslip12_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[13] <= soc_a7ddrphy_bitslip13_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[29] <= soc_a7ddrphy_bitslip13_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[14] <= soc_a7ddrphy_bitslip14_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[30] <= soc_a7ddrphy_bitslip14_o[7];
-       soc_a7ddrphy_dfi_p3_rddata[15] <= soc_a7ddrphy_bitslip15_o[6];
-       soc_a7ddrphy_dfi_p3_rddata[31] <= soc_a7ddrphy_bitslip15_o[7];
-// synthesis translate_off
-       dummy_d_16 = dummy_s;
-// synthesis translate_on
-end
-assign soc_a7ddrphy_bitslip1_i = soc_a7ddrphy_dq_i_data1;
-assign soc_a7ddrphy_bitslip2_i = soc_a7ddrphy_dq_i_data2;
-assign soc_a7ddrphy_bitslip3_i = soc_a7ddrphy_dq_i_data3;
-assign soc_a7ddrphy_bitslip4_i = soc_a7ddrphy_dq_i_data4;
-assign soc_a7ddrphy_bitslip5_i = soc_a7ddrphy_dq_i_data5;
-assign soc_a7ddrphy_bitslip6_i = soc_a7ddrphy_dq_i_data6;
-assign soc_a7ddrphy_bitslip7_i = soc_a7ddrphy_dq_i_data7;
-assign soc_a7ddrphy_bitslip8_i = soc_a7ddrphy_dq_i_data8;
-assign soc_a7ddrphy_bitslip9_i = soc_a7ddrphy_dq_i_data9;
-assign soc_a7ddrphy_bitslip10_i = soc_a7ddrphy_dq_i_data10;
-assign soc_a7ddrphy_bitslip11_i = soc_a7ddrphy_dq_i_data11;
-assign soc_a7ddrphy_bitslip12_i = soc_a7ddrphy_dq_i_data12;
-assign soc_a7ddrphy_bitslip13_i = soc_a7ddrphy_dq_i_data13;
-assign soc_a7ddrphy_bitslip14_i = soc_a7ddrphy_dq_i_data14;
-assign soc_a7ddrphy_bitslip15_i = soc_a7ddrphy_dq_i_data15;
-assign soc_a7ddrphy_rddata_en = {soc_a7ddrphy_rddata_en_last, soc_a7ddrphy_dfi_p2_rddata_en};
-assign soc_a7ddrphy_wrdata_en = {soc_a7ddrphy_wrdata_en_last, soc_a7ddrphy_dfi_p3_wrdata_en};
-assign soc_a7ddrphy_dq_oe = soc_a7ddrphy_wrdata_en[2];
-
-// synthesis translate_off
-reg dummy_d_17;
-// synthesis translate_on
-always @(*) begin
-       soc_a7ddrphy_dqs_oe <= 1'd0;
-       if (soc_a7ddrphy_wlevel_en_storage) begin
-               soc_a7ddrphy_dqs_oe <= 1'd1;
+       a7ddrphy_dqs_oe <= 1'd0;
+       if (a7ddrphy_wlevel_en_storage) begin
+               a7ddrphy_dqs_oe <= 1'd1;
        end else begin
-               soc_a7ddrphy_dqs_oe <= soc_a7ddrphy_dq_oe;
+               a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
        end
 // synthesis translate_off
-       dummy_d_17 = dummy_s;
+       dummy_d_4 = dummy_s;
 // synthesis translate_on
 end
-assign soc_a7ddrphy_dqspattern0 = (soc_a7ddrphy_wrdata_en[1] & (~soc_a7ddrphy_wrdata_en[2]));
-assign soc_a7ddrphy_dqspattern1 = (soc_a7ddrphy_wrdata_en[3] & (~soc_a7ddrphy_wrdata_en[2]));
+assign a7ddrphy_dqspattern0 = (a7ddrphy_wrdata_en[1] & (~a7ddrphy_wrdata_en[2]));
+assign a7ddrphy_dqspattern1 = (a7ddrphy_wrdata_en[3] & (~a7ddrphy_wrdata_en[2]));
 
 // synthesis translate_off
-reg dummy_d_18;
+reg dummy_d_5;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_dqspattern_o0 <= 8'd0;
-       soc_a7ddrphy_dqspattern_o0 <= 7'd85;
-       if (soc_a7ddrphy_dqspattern0) begin
-               soc_a7ddrphy_dqspattern_o0 <= 5'd21;
+       a7ddrphy_dqspattern_o0 <= 8'd0;
+       a7ddrphy_dqspattern_o0 <= 7'd85;
+       if (a7ddrphy_dqspattern0) begin
+               a7ddrphy_dqspattern_o0 <= 5'd21;
        end
-       if (soc_a7ddrphy_dqspattern1) begin
-               soc_a7ddrphy_dqspattern_o0 <= 7'd84;
+       if (a7ddrphy_dqspattern1) begin
+               a7ddrphy_dqspattern_o0 <= 7'd84;
        end
-       if (soc_a7ddrphy_wlevel_en_storage) begin
-               soc_a7ddrphy_dqspattern_o0 <= 1'd0;
-               if (soc_a7ddrphy_wlevel_strobe_re) begin
-                       soc_a7ddrphy_dqspattern_o0 <= 1'd1;
+       if (a7ddrphy_wlevel_en_storage) begin
+               a7ddrphy_dqspattern_o0 <= 1'd0;
+               if (a7ddrphy_wlevel_strobe_re) begin
+                       a7ddrphy_dqspattern_o0 <= 1'd1;
                end
        end
 // synthesis translate_off
-       dummy_d_18 = dummy_s;
+       dummy_d_5 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_19;
+reg dummy_d_6;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip0_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip0_value)
+       a7ddrphy_bitslip0_o <= 8'd0;
+       case (a7ddrphy_bitslip0_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[7:0];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[8:1];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[9:2];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[10:3];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[11:4];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[12:5];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[13:6];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip0_o <= soc_a7ddrphy_bitslip0_r[14:7];
+                       a7ddrphy_bitslip0_o <= a7ddrphy_bitslip0_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_19 = dummy_s;
+       dummy_d_6 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_20;
+reg dummy_d_7;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip1_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip1_value)
+       a7ddrphy_bitslip1_o <= 8'd0;
+       case (a7ddrphy_bitslip1_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[7:0];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[8:1];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[9:2];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[10:3];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[11:4];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[12:5];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[13:6];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip1_o <= soc_a7ddrphy_bitslip1_r[14:7];
+                       a7ddrphy_bitslip1_o <= a7ddrphy_bitslip1_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_20 = dummy_s;
+       dummy_d_7 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_21;
+reg dummy_d_8;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip2_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip2_value)
+       a7ddrphy_bitslip2_o <= 8'd0;
+       case (a7ddrphy_bitslip2_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[7:0];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[8:1];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[9:2];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[10:3];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[11:4];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[12:5];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[13:6];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip2_o <= soc_a7ddrphy_bitslip2_r[14:7];
+                       a7ddrphy_bitslip2_o <= a7ddrphy_bitslip2_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_21 = dummy_s;
+       dummy_d_8 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_22;
+reg dummy_d_9;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip3_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip3_value)
+       a7ddrphy_bitslip3_o <= 8'd0;
+       case (a7ddrphy_bitslip3_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[7:0];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[8:1];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[9:2];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[10:3];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[11:4];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[12:5];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[13:6];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip3_o <= soc_a7ddrphy_bitslip3_r[14:7];
+                       a7ddrphy_bitslip3_o <= a7ddrphy_bitslip3_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_22 = dummy_s;
+       dummy_d_9 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_23;
+reg dummy_d_10;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip4_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip4_value)
+       a7ddrphy_bitslip4_o <= 8'd0;
+       case (a7ddrphy_bitslip4_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[7:0];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[8:1];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[9:2];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[10:3];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[11:4];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[12:5];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[13:6];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip4_o <= soc_a7ddrphy_bitslip4_r[14:7];
+                       a7ddrphy_bitslip4_o <= a7ddrphy_bitslip4_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_23 = dummy_s;
+       dummy_d_10 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_24;
+reg dummy_d_11;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip5_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip5_value)
+       a7ddrphy_bitslip5_o <= 8'd0;
+       case (a7ddrphy_bitslip5_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[7:0];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[8:1];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[9:2];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[10:3];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[11:4];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[12:5];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[13:6];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip5_o <= soc_a7ddrphy_bitslip5_r[14:7];
+                       a7ddrphy_bitslip5_o <= a7ddrphy_bitslip5_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_24 = dummy_s;
+       dummy_d_11 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_25;
+reg dummy_d_12;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip6_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip6_value)
+       a7ddrphy_bitslip6_o <= 8'd0;
+       case (a7ddrphy_bitslip6_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[7:0];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[8:1];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[9:2];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[10:3];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[11:4];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[12:5];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[13:6];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip6_o <= soc_a7ddrphy_bitslip6_r[14:7];
+                       a7ddrphy_bitslip6_o <= a7ddrphy_bitslip6_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_25 = dummy_s;
+       dummy_d_12 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_26;
+reg dummy_d_13;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip7_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip7_value)
+       a7ddrphy_bitslip7_o <= 8'd0;
+       case (a7ddrphy_bitslip7_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[7:0];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[8:1];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[9:2];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[10:3];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[11:4];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[12:5];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[13:6];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip7_o <= soc_a7ddrphy_bitslip7_r[14:7];
+                       a7ddrphy_bitslip7_o <= a7ddrphy_bitslip7_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_26 = dummy_s;
+       dummy_d_13 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_27;
+reg dummy_d_14;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip8_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip8_value)
+       a7ddrphy_bitslip8_o <= 8'd0;
+       case (a7ddrphy_bitslip8_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[7:0];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[8:1];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[9:2];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[10:3];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[11:4];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[12:5];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[13:6];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip8_o <= soc_a7ddrphy_bitslip8_r[14:7];
+                       a7ddrphy_bitslip8_o <= a7ddrphy_bitslip8_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_27 = dummy_s;
+       dummy_d_14 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_28;
+reg dummy_d_15;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip9_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip9_value)
+       a7ddrphy_bitslip9_o <= 8'd0;
+       case (a7ddrphy_bitslip9_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[7:0];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[8:1];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[9:2];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[10:3];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[11:4];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[12:5];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[13:6];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip9_o <= soc_a7ddrphy_bitslip9_r[14:7];
+                       a7ddrphy_bitslip9_o <= a7ddrphy_bitslip9_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_28 = dummy_s;
+       dummy_d_15 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_29;
+reg dummy_d_16;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip10_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip10_value)
+       a7ddrphy_bitslip10_o <= 8'd0;
+       case (a7ddrphy_bitslip10_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[7:0];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[8:1];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[9:2];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[10:3];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[11:4];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[12:5];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[13:6];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip10_o <= soc_a7ddrphy_bitslip10_r[14:7];
+                       a7ddrphy_bitslip10_o <= a7ddrphy_bitslip10_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_29 = dummy_s;
+       dummy_d_16 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_30;
+reg dummy_d_17;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip11_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip11_value)
+       a7ddrphy_bitslip11_o <= 8'd0;
+       case (a7ddrphy_bitslip11_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[7:0];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[8:1];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[9:2];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[10:3];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[11:4];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[12:5];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[13:6];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip11_o <= soc_a7ddrphy_bitslip11_r[14:7];
+                       a7ddrphy_bitslip11_o <= a7ddrphy_bitslip11_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_30 = dummy_s;
+       dummy_d_17 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_31;
+reg dummy_d_18;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip12_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip12_value)
+       a7ddrphy_bitslip12_o <= 8'd0;
+       case (a7ddrphy_bitslip12_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[7:0];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[8:1];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[9:2];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[10:3];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[11:4];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[12:5];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[13:6];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip12_o <= soc_a7ddrphy_bitslip12_r[14:7];
+                       a7ddrphy_bitslip12_o <= a7ddrphy_bitslip12_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_31 = dummy_s;
+       dummy_d_18 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_32;
+reg dummy_d_19;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip13_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip13_value)
+       a7ddrphy_bitslip13_o <= 8'd0;
+       case (a7ddrphy_bitslip13_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[7:0];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[8:1];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[9:2];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[10:3];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[11:4];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[12:5];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[13:6];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip13_o <= soc_a7ddrphy_bitslip13_r[14:7];
+                       a7ddrphy_bitslip13_o <= a7ddrphy_bitslip13_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_32 = dummy_s;
+       dummy_d_19 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_33;
+reg dummy_d_20;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip14_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip14_value)
+       a7ddrphy_bitslip14_o <= 8'd0;
+       case (a7ddrphy_bitslip14_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[7:0];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[8:1];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[9:2];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[10:3];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[11:4];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[12:5];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[13:6];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip14_o <= soc_a7ddrphy_bitslip14_r[14:7];
+                       a7ddrphy_bitslip14_o <= a7ddrphy_bitslip14_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_33 = dummy_s;
+       dummy_d_20 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_34;
+reg dummy_d_21;
 // synthesis translate_on
 always @(*) begin
-       soc_a7ddrphy_bitslip15_o <= 8'd0;
-       case (soc_a7ddrphy_bitslip15_value)
+       a7ddrphy_bitslip15_o <= 8'd0;
+       case (a7ddrphy_bitslip15_value)
                1'd0: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[7:0];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[7:0];
                end
                1'd1: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[8:1];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[8:1];
                end
                2'd2: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[9:2];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[9:2];
                end
                2'd3: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[10:3];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[10:3];
                end
                3'd4: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[11:4];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[11:4];
                end
                3'd5: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[12:5];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[12:5];
                end
                3'd6: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[13:6];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[13:6];
                end
                3'd7: begin
-                       soc_a7ddrphy_bitslip15_o <= soc_a7ddrphy_bitslip15_r[14:7];
+                       a7ddrphy_bitslip15_o <= a7ddrphy_bitslip15_r[14:7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_34 = dummy_s;
+       dummy_d_21 = dummy_s;
 // synthesis translate_on
 end
-assign soc_a7ddrphy_dfi_p0_address = soc_sdram_master_p0_address;
-assign soc_a7ddrphy_dfi_p0_bank = soc_sdram_master_p0_bank;
-assign soc_a7ddrphy_dfi_p0_cas_n = soc_sdram_master_p0_cas_n;
-assign soc_a7ddrphy_dfi_p0_cs_n = soc_sdram_master_p0_cs_n;
-assign soc_a7ddrphy_dfi_p0_ras_n = soc_sdram_master_p0_ras_n;
-assign soc_a7ddrphy_dfi_p0_we_n = soc_sdram_master_p0_we_n;
-assign soc_a7ddrphy_dfi_p0_cke = soc_sdram_master_p0_cke;
-assign soc_a7ddrphy_dfi_p0_odt = soc_sdram_master_p0_odt;
-assign soc_a7ddrphy_dfi_p0_reset_n = soc_sdram_master_p0_reset_n;
-assign soc_a7ddrphy_dfi_p0_act_n = soc_sdram_master_p0_act_n;
-assign soc_a7ddrphy_dfi_p0_wrdata = soc_sdram_master_p0_wrdata;
-assign soc_a7ddrphy_dfi_p0_wrdata_en = soc_sdram_master_p0_wrdata_en;
-assign soc_a7ddrphy_dfi_p0_wrdata_mask = soc_sdram_master_p0_wrdata_mask;
-assign soc_a7ddrphy_dfi_p0_rddata_en = soc_sdram_master_p0_rddata_en;
-assign soc_sdram_master_p0_rddata = soc_a7ddrphy_dfi_p0_rddata;
-assign soc_sdram_master_p0_rddata_valid = soc_a7ddrphy_dfi_p0_rddata_valid;
-assign soc_a7ddrphy_dfi_p1_address = soc_sdram_master_p1_address;
-assign soc_a7ddrphy_dfi_p1_bank = soc_sdram_master_p1_bank;
-assign soc_a7ddrphy_dfi_p1_cas_n = soc_sdram_master_p1_cas_n;
-assign soc_a7ddrphy_dfi_p1_cs_n = soc_sdram_master_p1_cs_n;
-assign soc_a7ddrphy_dfi_p1_ras_n = soc_sdram_master_p1_ras_n;
-assign soc_a7ddrphy_dfi_p1_we_n = soc_sdram_master_p1_we_n;
-assign soc_a7ddrphy_dfi_p1_cke = soc_sdram_master_p1_cke;
-assign soc_a7ddrphy_dfi_p1_odt = soc_sdram_master_p1_odt;
-assign soc_a7ddrphy_dfi_p1_reset_n = soc_sdram_master_p1_reset_n;
-assign soc_a7ddrphy_dfi_p1_act_n = soc_sdram_master_p1_act_n;
-assign soc_a7ddrphy_dfi_p1_wrdata = soc_sdram_master_p1_wrdata;
-assign soc_a7ddrphy_dfi_p1_wrdata_en = soc_sdram_master_p1_wrdata_en;
-assign soc_a7ddrphy_dfi_p1_wrdata_mask = soc_sdram_master_p1_wrdata_mask;
-assign soc_a7ddrphy_dfi_p1_rddata_en = soc_sdram_master_p1_rddata_en;
-assign soc_sdram_master_p1_rddata = soc_a7ddrphy_dfi_p1_rddata;
-assign soc_sdram_master_p1_rddata_valid = soc_a7ddrphy_dfi_p1_rddata_valid;
-assign soc_a7ddrphy_dfi_p2_address = soc_sdram_master_p2_address;
-assign soc_a7ddrphy_dfi_p2_bank = soc_sdram_master_p2_bank;
-assign soc_a7ddrphy_dfi_p2_cas_n = soc_sdram_master_p2_cas_n;
-assign soc_a7ddrphy_dfi_p2_cs_n = soc_sdram_master_p2_cs_n;
-assign soc_a7ddrphy_dfi_p2_ras_n = soc_sdram_master_p2_ras_n;
-assign soc_a7ddrphy_dfi_p2_we_n = soc_sdram_master_p2_we_n;
-assign soc_a7ddrphy_dfi_p2_cke = soc_sdram_master_p2_cke;
-assign soc_a7ddrphy_dfi_p2_odt = soc_sdram_master_p2_odt;
-assign soc_a7ddrphy_dfi_p2_reset_n = soc_sdram_master_p2_reset_n;
-assign soc_a7ddrphy_dfi_p2_act_n = soc_sdram_master_p2_act_n;
-assign soc_a7ddrphy_dfi_p2_wrdata = soc_sdram_master_p2_wrdata;
-assign soc_a7ddrphy_dfi_p2_wrdata_en = soc_sdram_master_p2_wrdata_en;
-assign soc_a7ddrphy_dfi_p2_wrdata_mask = soc_sdram_master_p2_wrdata_mask;
-assign soc_a7ddrphy_dfi_p2_rddata_en = soc_sdram_master_p2_rddata_en;
-assign soc_sdram_master_p2_rddata = soc_a7ddrphy_dfi_p2_rddata;
-assign soc_sdram_master_p2_rddata_valid = soc_a7ddrphy_dfi_p2_rddata_valid;
-assign soc_a7ddrphy_dfi_p3_address = soc_sdram_master_p3_address;
-assign soc_a7ddrphy_dfi_p3_bank = soc_sdram_master_p3_bank;
-assign soc_a7ddrphy_dfi_p3_cas_n = soc_sdram_master_p3_cas_n;
-assign soc_a7ddrphy_dfi_p3_cs_n = soc_sdram_master_p3_cs_n;
-assign soc_a7ddrphy_dfi_p3_ras_n = soc_sdram_master_p3_ras_n;
-assign soc_a7ddrphy_dfi_p3_we_n = soc_sdram_master_p3_we_n;
-assign soc_a7ddrphy_dfi_p3_cke = soc_sdram_master_p3_cke;
-assign soc_a7ddrphy_dfi_p3_odt = soc_sdram_master_p3_odt;
-assign soc_a7ddrphy_dfi_p3_reset_n = soc_sdram_master_p3_reset_n;
-assign soc_a7ddrphy_dfi_p3_act_n = soc_sdram_master_p3_act_n;
-assign soc_a7ddrphy_dfi_p3_wrdata = soc_sdram_master_p3_wrdata;
-assign soc_a7ddrphy_dfi_p3_wrdata_en = soc_sdram_master_p3_wrdata_en;
-assign soc_a7ddrphy_dfi_p3_wrdata_mask = soc_sdram_master_p3_wrdata_mask;
-assign soc_a7ddrphy_dfi_p3_rddata_en = soc_sdram_master_p3_rddata_en;
-assign soc_sdram_master_p3_rddata = soc_a7ddrphy_dfi_p3_rddata;
-assign soc_sdram_master_p3_rddata_valid = soc_a7ddrphy_dfi_p3_rddata_valid;
-assign soc_sdram_slave_p0_address = soc_sdram_dfi_p0_address;
-assign soc_sdram_slave_p0_bank = soc_sdram_dfi_p0_bank;
-assign soc_sdram_slave_p0_cas_n = soc_sdram_dfi_p0_cas_n;
-assign soc_sdram_slave_p0_cs_n = soc_sdram_dfi_p0_cs_n;
-assign soc_sdram_slave_p0_ras_n = soc_sdram_dfi_p0_ras_n;
-assign soc_sdram_slave_p0_we_n = soc_sdram_dfi_p0_we_n;
-assign soc_sdram_slave_p0_cke = soc_sdram_dfi_p0_cke;
-assign soc_sdram_slave_p0_odt = soc_sdram_dfi_p0_odt;
-assign soc_sdram_slave_p0_reset_n = soc_sdram_dfi_p0_reset_n;
-assign soc_sdram_slave_p0_act_n = soc_sdram_dfi_p0_act_n;
-assign soc_sdram_slave_p0_wrdata = soc_sdram_dfi_p0_wrdata;
-assign soc_sdram_slave_p0_wrdata_en = soc_sdram_dfi_p0_wrdata_en;
-assign soc_sdram_slave_p0_wrdata_mask = soc_sdram_dfi_p0_wrdata_mask;
-assign soc_sdram_slave_p0_rddata_en = soc_sdram_dfi_p0_rddata_en;
-assign soc_sdram_dfi_p0_rddata = soc_sdram_slave_p0_rddata;
-assign soc_sdram_dfi_p0_rddata_valid = soc_sdram_slave_p0_rddata_valid;
-assign soc_sdram_slave_p1_address = soc_sdram_dfi_p1_address;
-assign soc_sdram_slave_p1_bank = soc_sdram_dfi_p1_bank;
-assign soc_sdram_slave_p1_cas_n = soc_sdram_dfi_p1_cas_n;
-assign soc_sdram_slave_p1_cs_n = soc_sdram_dfi_p1_cs_n;
-assign soc_sdram_slave_p1_ras_n = soc_sdram_dfi_p1_ras_n;
-assign soc_sdram_slave_p1_we_n = soc_sdram_dfi_p1_we_n;
-assign soc_sdram_slave_p1_cke = soc_sdram_dfi_p1_cke;
-assign soc_sdram_slave_p1_odt = soc_sdram_dfi_p1_odt;
-assign soc_sdram_slave_p1_reset_n = soc_sdram_dfi_p1_reset_n;
-assign soc_sdram_slave_p1_act_n = soc_sdram_dfi_p1_act_n;
-assign soc_sdram_slave_p1_wrdata = soc_sdram_dfi_p1_wrdata;
-assign soc_sdram_slave_p1_wrdata_en = soc_sdram_dfi_p1_wrdata_en;
-assign soc_sdram_slave_p1_wrdata_mask = soc_sdram_dfi_p1_wrdata_mask;
-assign soc_sdram_slave_p1_rddata_en = soc_sdram_dfi_p1_rddata_en;
-assign soc_sdram_dfi_p1_rddata = soc_sdram_slave_p1_rddata;
-assign soc_sdram_dfi_p1_rddata_valid = soc_sdram_slave_p1_rddata_valid;
-assign soc_sdram_slave_p2_address = soc_sdram_dfi_p2_address;
-assign soc_sdram_slave_p2_bank = soc_sdram_dfi_p2_bank;
-assign soc_sdram_slave_p2_cas_n = soc_sdram_dfi_p2_cas_n;
-assign soc_sdram_slave_p2_cs_n = soc_sdram_dfi_p2_cs_n;
-assign soc_sdram_slave_p2_ras_n = soc_sdram_dfi_p2_ras_n;
-assign soc_sdram_slave_p2_we_n = soc_sdram_dfi_p2_we_n;
-assign soc_sdram_slave_p2_cke = soc_sdram_dfi_p2_cke;
-assign soc_sdram_slave_p2_odt = soc_sdram_dfi_p2_odt;
-assign soc_sdram_slave_p2_reset_n = soc_sdram_dfi_p2_reset_n;
-assign soc_sdram_slave_p2_act_n = soc_sdram_dfi_p2_act_n;
-assign soc_sdram_slave_p2_wrdata = soc_sdram_dfi_p2_wrdata;
-assign soc_sdram_slave_p2_wrdata_en = soc_sdram_dfi_p2_wrdata_en;
-assign soc_sdram_slave_p2_wrdata_mask = soc_sdram_dfi_p2_wrdata_mask;
-assign soc_sdram_slave_p2_rddata_en = soc_sdram_dfi_p2_rddata_en;
-assign soc_sdram_dfi_p2_rddata = soc_sdram_slave_p2_rddata;
-assign soc_sdram_dfi_p2_rddata_valid = soc_sdram_slave_p2_rddata_valid;
-assign soc_sdram_slave_p3_address = soc_sdram_dfi_p3_address;
-assign soc_sdram_slave_p3_bank = soc_sdram_dfi_p3_bank;
-assign soc_sdram_slave_p3_cas_n = soc_sdram_dfi_p3_cas_n;
-assign soc_sdram_slave_p3_cs_n = soc_sdram_dfi_p3_cs_n;
-assign soc_sdram_slave_p3_ras_n = soc_sdram_dfi_p3_ras_n;
-assign soc_sdram_slave_p3_we_n = soc_sdram_dfi_p3_we_n;
-assign soc_sdram_slave_p3_cke = soc_sdram_dfi_p3_cke;
-assign soc_sdram_slave_p3_odt = soc_sdram_dfi_p3_odt;
-assign soc_sdram_slave_p3_reset_n = soc_sdram_dfi_p3_reset_n;
-assign soc_sdram_slave_p3_act_n = soc_sdram_dfi_p3_act_n;
-assign soc_sdram_slave_p3_wrdata = soc_sdram_dfi_p3_wrdata;
-assign soc_sdram_slave_p3_wrdata_en = soc_sdram_dfi_p3_wrdata_en;
-assign soc_sdram_slave_p3_wrdata_mask = soc_sdram_dfi_p3_wrdata_mask;
-assign soc_sdram_slave_p3_rddata_en = soc_sdram_dfi_p3_rddata_en;
-assign soc_sdram_dfi_p3_rddata = soc_sdram_slave_p3_rddata;
-assign soc_sdram_dfi_p3_rddata_valid = soc_sdram_slave_p3_rddata_valid;
+assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
+assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
+assign a7ddrphy_dfi_p0_cas_n = litedramcore_master_p0_cas_n;
+assign a7ddrphy_dfi_p0_cs_n = litedramcore_master_p0_cs_n;
+assign a7ddrphy_dfi_p0_ras_n = litedramcore_master_p0_ras_n;
+assign a7ddrphy_dfi_p0_we_n = litedramcore_master_p0_we_n;
+assign a7ddrphy_dfi_p0_cke = litedramcore_master_p0_cke;
+assign a7ddrphy_dfi_p0_odt = litedramcore_master_p0_odt;
+assign a7ddrphy_dfi_p0_reset_n = litedramcore_master_p0_reset_n;
+assign a7ddrphy_dfi_p0_act_n = litedramcore_master_p0_act_n;
+assign a7ddrphy_dfi_p0_wrdata = litedramcore_master_p0_wrdata;
+assign a7ddrphy_dfi_p0_wrdata_en = litedramcore_master_p0_wrdata_en;
+assign a7ddrphy_dfi_p0_wrdata_mask = litedramcore_master_p0_wrdata_mask;
+assign a7ddrphy_dfi_p0_rddata_en = litedramcore_master_p0_rddata_en;
+assign litedramcore_master_p0_rddata = a7ddrphy_dfi_p0_rddata;
+assign litedramcore_master_p0_rddata_valid = a7ddrphy_dfi_p0_rddata_valid;
+assign a7ddrphy_dfi_p1_address = litedramcore_master_p1_address;
+assign a7ddrphy_dfi_p1_bank = litedramcore_master_p1_bank;
+assign a7ddrphy_dfi_p1_cas_n = litedramcore_master_p1_cas_n;
+assign a7ddrphy_dfi_p1_cs_n = litedramcore_master_p1_cs_n;
+assign a7ddrphy_dfi_p1_ras_n = litedramcore_master_p1_ras_n;
+assign a7ddrphy_dfi_p1_we_n = litedramcore_master_p1_we_n;
+assign a7ddrphy_dfi_p1_cke = litedramcore_master_p1_cke;
+assign a7ddrphy_dfi_p1_odt = litedramcore_master_p1_odt;
+assign a7ddrphy_dfi_p1_reset_n = litedramcore_master_p1_reset_n;
+assign a7ddrphy_dfi_p1_act_n = litedramcore_master_p1_act_n;
+assign a7ddrphy_dfi_p1_wrdata = litedramcore_master_p1_wrdata;
+assign a7ddrphy_dfi_p1_wrdata_en = litedramcore_master_p1_wrdata_en;
+assign a7ddrphy_dfi_p1_wrdata_mask = litedramcore_master_p1_wrdata_mask;
+assign a7ddrphy_dfi_p1_rddata_en = litedramcore_master_p1_rddata_en;
+assign litedramcore_master_p1_rddata = a7ddrphy_dfi_p1_rddata;
+assign litedramcore_master_p1_rddata_valid = a7ddrphy_dfi_p1_rddata_valid;
+assign a7ddrphy_dfi_p2_address = litedramcore_master_p2_address;
+assign a7ddrphy_dfi_p2_bank = litedramcore_master_p2_bank;
+assign a7ddrphy_dfi_p2_cas_n = litedramcore_master_p2_cas_n;
+assign a7ddrphy_dfi_p2_cs_n = litedramcore_master_p2_cs_n;
+assign a7ddrphy_dfi_p2_ras_n = litedramcore_master_p2_ras_n;
+assign a7ddrphy_dfi_p2_we_n = litedramcore_master_p2_we_n;
+assign a7ddrphy_dfi_p2_cke = litedramcore_master_p2_cke;
+assign a7ddrphy_dfi_p2_odt = litedramcore_master_p2_odt;
+assign a7ddrphy_dfi_p2_reset_n = litedramcore_master_p2_reset_n;
+assign a7ddrphy_dfi_p2_act_n = litedramcore_master_p2_act_n;
+assign a7ddrphy_dfi_p2_wrdata = litedramcore_master_p2_wrdata;
+assign a7ddrphy_dfi_p2_wrdata_en = litedramcore_master_p2_wrdata_en;
+assign a7ddrphy_dfi_p2_wrdata_mask = litedramcore_master_p2_wrdata_mask;
+assign a7ddrphy_dfi_p2_rddata_en = litedramcore_master_p2_rddata_en;
+assign litedramcore_master_p2_rddata = a7ddrphy_dfi_p2_rddata;
+assign litedramcore_master_p2_rddata_valid = a7ddrphy_dfi_p2_rddata_valid;
+assign a7ddrphy_dfi_p3_address = litedramcore_master_p3_address;
+assign a7ddrphy_dfi_p3_bank = litedramcore_master_p3_bank;
+assign a7ddrphy_dfi_p3_cas_n = litedramcore_master_p3_cas_n;
+assign a7ddrphy_dfi_p3_cs_n = litedramcore_master_p3_cs_n;
+assign a7ddrphy_dfi_p3_ras_n = litedramcore_master_p3_ras_n;
+assign a7ddrphy_dfi_p3_we_n = litedramcore_master_p3_we_n;
+assign a7ddrphy_dfi_p3_cke = litedramcore_master_p3_cke;
+assign a7ddrphy_dfi_p3_odt = litedramcore_master_p3_odt;
+assign a7ddrphy_dfi_p3_reset_n = litedramcore_master_p3_reset_n;
+assign a7ddrphy_dfi_p3_act_n = litedramcore_master_p3_act_n;
+assign a7ddrphy_dfi_p3_wrdata = litedramcore_master_p3_wrdata;
+assign a7ddrphy_dfi_p3_wrdata_en = litedramcore_master_p3_wrdata_en;
+assign a7ddrphy_dfi_p3_wrdata_mask = litedramcore_master_p3_wrdata_mask;
+assign a7ddrphy_dfi_p3_rddata_en = litedramcore_master_p3_rddata_en;
+assign litedramcore_master_p3_rddata = a7ddrphy_dfi_p3_rddata;
+assign litedramcore_master_p3_rddata_valid = a7ddrphy_dfi_p3_rddata_valid;
+assign litedramcore_slave_p0_address = litedramcore_dfi_p0_address;
+assign litedramcore_slave_p0_bank = litedramcore_dfi_p0_bank;
+assign litedramcore_slave_p0_cas_n = litedramcore_dfi_p0_cas_n;
+assign litedramcore_slave_p0_cs_n = litedramcore_dfi_p0_cs_n;
+assign litedramcore_slave_p0_ras_n = litedramcore_dfi_p0_ras_n;
+assign litedramcore_slave_p0_we_n = litedramcore_dfi_p0_we_n;
+assign litedramcore_slave_p0_cke = litedramcore_dfi_p0_cke;
+assign litedramcore_slave_p0_odt = litedramcore_dfi_p0_odt;
+assign litedramcore_slave_p0_reset_n = litedramcore_dfi_p0_reset_n;
+assign litedramcore_slave_p0_act_n = litedramcore_dfi_p0_act_n;
+assign litedramcore_slave_p0_wrdata = litedramcore_dfi_p0_wrdata;
+assign litedramcore_slave_p0_wrdata_en = litedramcore_dfi_p0_wrdata_en;
+assign litedramcore_slave_p0_wrdata_mask = litedramcore_dfi_p0_wrdata_mask;
+assign litedramcore_slave_p0_rddata_en = litedramcore_dfi_p0_rddata_en;
+assign litedramcore_dfi_p0_rddata = litedramcore_slave_p0_rddata;
+assign litedramcore_dfi_p0_rddata_valid = litedramcore_slave_p0_rddata_valid;
+assign litedramcore_slave_p1_address = litedramcore_dfi_p1_address;
+assign litedramcore_slave_p1_bank = litedramcore_dfi_p1_bank;
+assign litedramcore_slave_p1_cas_n = litedramcore_dfi_p1_cas_n;
+assign litedramcore_slave_p1_cs_n = litedramcore_dfi_p1_cs_n;
+assign litedramcore_slave_p1_ras_n = litedramcore_dfi_p1_ras_n;
+assign litedramcore_slave_p1_we_n = litedramcore_dfi_p1_we_n;
+assign litedramcore_slave_p1_cke = litedramcore_dfi_p1_cke;
+assign litedramcore_slave_p1_odt = litedramcore_dfi_p1_odt;
+assign litedramcore_slave_p1_reset_n = litedramcore_dfi_p1_reset_n;
+assign litedramcore_slave_p1_act_n = litedramcore_dfi_p1_act_n;
+assign litedramcore_slave_p1_wrdata = litedramcore_dfi_p1_wrdata;
+assign litedramcore_slave_p1_wrdata_en = litedramcore_dfi_p1_wrdata_en;
+assign litedramcore_slave_p1_wrdata_mask = litedramcore_dfi_p1_wrdata_mask;
+assign litedramcore_slave_p1_rddata_en = litedramcore_dfi_p1_rddata_en;
+assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
+assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
+assign litedramcore_slave_p2_address = litedramcore_dfi_p2_address;
+assign litedramcore_slave_p2_bank = litedramcore_dfi_p2_bank;
+assign litedramcore_slave_p2_cas_n = litedramcore_dfi_p2_cas_n;
+assign litedramcore_slave_p2_cs_n = litedramcore_dfi_p2_cs_n;
+assign litedramcore_slave_p2_ras_n = litedramcore_dfi_p2_ras_n;
+assign litedramcore_slave_p2_we_n = litedramcore_dfi_p2_we_n;
+assign litedramcore_slave_p2_cke = litedramcore_dfi_p2_cke;
+assign litedramcore_slave_p2_odt = litedramcore_dfi_p2_odt;
+assign litedramcore_slave_p2_reset_n = litedramcore_dfi_p2_reset_n;
+assign litedramcore_slave_p2_act_n = litedramcore_dfi_p2_act_n;
+assign litedramcore_slave_p2_wrdata = litedramcore_dfi_p2_wrdata;
+assign litedramcore_slave_p2_wrdata_en = litedramcore_dfi_p2_wrdata_en;
+assign litedramcore_slave_p2_wrdata_mask = litedramcore_dfi_p2_wrdata_mask;
+assign litedramcore_slave_p2_rddata_en = litedramcore_dfi_p2_rddata_en;
+assign litedramcore_dfi_p2_rddata = litedramcore_slave_p2_rddata;
+assign litedramcore_dfi_p2_rddata_valid = litedramcore_slave_p2_rddata_valid;
+assign litedramcore_slave_p3_address = litedramcore_dfi_p3_address;
+assign litedramcore_slave_p3_bank = litedramcore_dfi_p3_bank;
+assign litedramcore_slave_p3_cas_n = litedramcore_dfi_p3_cas_n;
+assign litedramcore_slave_p3_cs_n = litedramcore_dfi_p3_cs_n;
+assign litedramcore_slave_p3_ras_n = litedramcore_dfi_p3_ras_n;
+assign litedramcore_slave_p3_we_n = litedramcore_dfi_p3_we_n;
+assign litedramcore_slave_p3_cke = litedramcore_dfi_p3_cke;
+assign litedramcore_slave_p3_odt = litedramcore_dfi_p3_odt;
+assign litedramcore_slave_p3_reset_n = litedramcore_dfi_p3_reset_n;
+assign litedramcore_slave_p3_act_n = litedramcore_dfi_p3_act_n;
+assign litedramcore_slave_p3_wrdata = litedramcore_dfi_p3_wrdata;
+assign litedramcore_slave_p3_wrdata_en = litedramcore_dfi_p3_wrdata_en;
+assign litedramcore_slave_p3_wrdata_mask = litedramcore_dfi_p3_wrdata_mask;
+assign litedramcore_slave_p3_rddata_en = litedramcore_dfi_p3_rddata_en;
+assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
+assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
 
 // synthesis translate_off
-reg dummy_d_35;
+reg dummy_d_22;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_cas_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_cas_n <= soc_sdram_slave_p2_cas_n;
+       litedramcore_master_p2_ras_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
        end else begin
-               soc_sdram_master_p2_cas_n <= soc_sdram_inti_p2_cas_n;
+               litedramcore_master_p2_ras_n <= litedramcore_inti_p2_ras_n;
        end
 // synthesis translate_off
-       dummy_d_35 = dummy_s;
+       dummy_d_22 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_36;
+reg dummy_d_23;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_cs_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_cs_n <= soc_sdram_slave_p2_cs_n;
+       litedramcore_slave_p2_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
        end else begin
-               soc_sdram_master_p2_cs_n <= soc_sdram_inti_p2_cs_n;
        end
 // synthesis translate_off
-       dummy_d_36 = dummy_s;
+       dummy_d_23 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_37;
+reg dummy_d_24;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_ras_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_ras_n <= soc_sdram_slave_p2_ras_n;
+       litedramcore_master_p2_we_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
        end else begin
-               soc_sdram_master_p2_ras_n <= soc_sdram_inti_p2_ras_n;
+               litedramcore_master_p2_we_n <= litedramcore_inti_p2_we_n;
        end
 // synthesis translate_off
-       dummy_d_37 = dummy_s;
+       dummy_d_24 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_38;
+reg dummy_d_25;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p2_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p2_rddata <= soc_sdram_master_p2_rddata;
+       litedramcore_slave_p2_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
        end else begin
        end
 // synthesis translate_off
-       dummy_d_38 = dummy_s;
+       dummy_d_25 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_39;
+reg dummy_d_26;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_we_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_we_n <= soc_sdram_slave_p2_we_n;
+       litedramcore_master_p2_cke <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
        end else begin
-               soc_sdram_master_p2_we_n <= soc_sdram_inti_p2_we_n;
+               litedramcore_master_p2_cke <= litedramcore_inti_p2_cke;
        end
 // synthesis translate_off
-       dummy_d_39 = dummy_s;
+       dummy_d_26 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_40;
+reg dummy_d_27;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p2_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid;
+       litedramcore_master_p2_odt <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
        end else begin
+               litedramcore_master_p2_odt <= litedramcore_inti_p2_odt;
        end
 // synthesis translate_off
-       dummy_d_40 = dummy_s;
+       dummy_d_27 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_41;
+reg dummy_d_28;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_cke <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_cke <= soc_sdram_slave_p2_cke;
+       litedramcore_master_p2_reset_n <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
        end else begin
-               soc_sdram_master_p2_cke <= soc_sdram_inti_p2_cke;
+               litedramcore_master_p2_reset_n <= litedramcore_inti_p2_reset_n;
        end
 // synthesis translate_off
-       dummy_d_41 = dummy_s;
+       dummy_d_28 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_42;
+reg dummy_d_29;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_odt <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_odt <= soc_sdram_slave_p2_odt;
+       litedramcore_master_p2_act_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
        end else begin
-               soc_sdram_master_p2_odt <= soc_sdram_inti_p2_odt;
+               litedramcore_master_p2_act_n <= litedramcore_inti_p2_act_n;
        end
 // synthesis translate_off
-       dummy_d_42 = dummy_s;
+       dummy_d_29 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_43;
+reg dummy_d_30;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_reset_n <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_reset_n <= soc_sdram_slave_p2_reset_n;
+       litedramcore_master_p2_wrdata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
        end else begin
-               soc_sdram_master_p2_reset_n <= soc_sdram_inti_p2_reset_n;
+               litedramcore_master_p2_wrdata <= litedramcore_inti_p2_wrdata;
        end
 // synthesis translate_off
-       dummy_d_43 = dummy_s;
+       dummy_d_30 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_44;
+reg dummy_d_31;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_act_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_act_n <= soc_sdram_slave_p2_act_n;
+       litedramcore_inti_p3_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p2_act_n <= soc_sdram_inti_p2_act_n;
+               litedramcore_inti_p3_rddata <= litedramcore_master_p3_rddata;
        end
 // synthesis translate_off
-       dummy_d_44 = dummy_s;
+       dummy_d_31 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_32;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p2_wrdata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+       end else begin
+               litedramcore_master_p2_wrdata_en <= litedramcore_inti_p2_wrdata_en;
+       end
+// synthesis translate_off
+       dummy_d_32 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_33;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_inti_p3_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
+       end else begin
+               litedramcore_inti_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+       end
+// synthesis translate_off
+       dummy_d_33 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_34;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p2_wrdata_mask <= 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+       end else begin
+               litedramcore_master_p2_wrdata_mask <= litedramcore_inti_p2_wrdata_mask;
+       end
+// synthesis translate_off
+       dummy_d_34 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_35;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p2_rddata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+       end else begin
+               litedramcore_master_p2_rddata_en <= litedramcore_inti_p2_rddata_en;
+       end
+// synthesis translate_off
+       dummy_d_35 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_36;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p3_address <= 15'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+       end else begin
+               litedramcore_master_p3_address <= litedramcore_inti_p3_address;
+       end
+// synthesis translate_off
+       dummy_d_36 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_37;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p3_bank <= 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+       end else begin
+               litedramcore_master_p3_bank <= litedramcore_inti_p3_bank;
+       end
+// synthesis translate_off
+       dummy_d_37 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_38;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p3_cas_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+       end else begin
+               litedramcore_master_p3_cas_n <= litedramcore_inti_p3_cas_n;
+       end
+// synthesis translate_off
+       dummy_d_38 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_39;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p3_cs_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+       end else begin
+               litedramcore_master_p3_cs_n <= litedramcore_inti_p3_cs_n;
+       end
+// synthesis translate_off
+       dummy_d_39 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_40;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p3_ras_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+       end else begin
+               litedramcore_master_p3_ras_n <= litedramcore_inti_p3_ras_n;
+       end
+// synthesis translate_off
+       dummy_d_40 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_41;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_slave_p3_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+       end else begin
+       end
+// synthesis translate_off
+       dummy_d_41 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_42;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p3_we_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+       end else begin
+               litedramcore_master_p3_we_n <= litedramcore_inti_p3_we_n;
+       end
+// synthesis translate_off
+       dummy_d_42 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_43;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_slave_p3_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+       end else begin
+       end
+// synthesis translate_off
+       dummy_d_43 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_44;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_master_p3_cke <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+       end else begin
+               litedramcore_master_p3_cke <= litedramcore_inti_p3_cke;
+       end
+// synthesis translate_off
+       dummy_d_44 = dummy_s;
 // synthesis translate_on
 end
 
@@ -3865,11 +3187,11 @@ end
 reg dummy_d_45;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_wrdata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_wrdata <= soc_sdram_slave_p2_wrdata;
+       litedramcore_master_p3_odt <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
        end else begin
-               soc_sdram_master_p2_wrdata <= soc_sdram_inti_p2_wrdata;
+               litedramcore_master_p3_odt <= litedramcore_inti_p3_odt;
        end
 // synthesis translate_off
        dummy_d_45 = dummy_s;
@@ -3880,10 +3202,11 @@ end
 reg dummy_d_46;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p3_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_master_p3_reset_n <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
        end else begin
-               soc_sdram_inti_p3_rddata <= soc_sdram_master_p3_rddata;
+               litedramcore_master_p3_reset_n <= litedramcore_inti_p3_reset_n;
        end
 // synthesis translate_off
        dummy_d_46 = dummy_s;
@@ -3894,11 +3217,11 @@ end
 reg dummy_d_47;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_wrdata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_wrdata_en <= soc_sdram_slave_p2_wrdata_en;
+       litedramcore_master_p3_act_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
        end else begin
-               soc_sdram_master_p2_wrdata_en <= soc_sdram_inti_p2_wrdata_en;
+               litedramcore_master_p3_act_n <= litedramcore_inti_p3_act_n;
        end
 // synthesis translate_off
        dummy_d_47 = dummy_s;
@@ -3909,10 +3232,11 @@ end
 reg dummy_d_48;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p3_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_master_p3_wrdata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
        end else begin
-               soc_sdram_inti_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid;
+               litedramcore_master_p3_wrdata <= litedramcore_inti_p3_wrdata;
        end
 // synthesis translate_off
        dummy_d_48 = dummy_s;
@@ -3923,11 +3247,10 @@ end
 reg dummy_d_49;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_wrdata_mask <= 4'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_wrdata_mask <= soc_sdram_slave_p2_wrdata_mask;
+       litedramcore_inti_p0_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p2_wrdata_mask <= soc_sdram_inti_p2_wrdata_mask;
+               litedramcore_inti_p0_rddata <= litedramcore_master_p0_rddata;
        end
 // synthesis translate_off
        dummy_d_49 = dummy_s;
@@ -3938,11 +3261,11 @@ end
 reg dummy_d_50;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_rddata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_rddata_en <= soc_sdram_slave_p2_rddata_en;
+       litedramcore_master_p3_wrdata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
        end else begin
-               soc_sdram_master_p2_rddata_en <= soc_sdram_inti_p2_rddata_en;
+               litedramcore_master_p3_wrdata_en <= litedramcore_inti_p3_wrdata_en;
        end
 // synthesis translate_off
        dummy_d_50 = dummy_s;
@@ -3953,11 +3276,10 @@ end
 reg dummy_d_51;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_address <= 15'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_address <= soc_sdram_slave_p3_address;
+       litedramcore_inti_p0_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p3_address <= soc_sdram_inti_p3_address;
+               litedramcore_inti_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
        end
 // synthesis translate_off
        dummy_d_51 = dummy_s;
@@ -3968,11 +3290,11 @@ end
 reg dummy_d_52;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_bank <= 3'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_bank <= soc_sdram_slave_p3_bank;
+       litedramcore_master_p3_wrdata_mask <= 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
        end else begin
-               soc_sdram_master_p3_bank <= soc_sdram_inti_p3_bank;
+               litedramcore_master_p3_wrdata_mask <= litedramcore_inti_p3_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_52 = dummy_s;
@@ -3983,11 +3305,11 @@ end
 reg dummy_d_53;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_cas_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_cas_n <= soc_sdram_slave_p3_cas_n;
+       litedramcore_master_p3_rddata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
        end else begin
-               soc_sdram_master_p3_cas_n <= soc_sdram_inti_p3_cas_n;
+               litedramcore_master_p3_rddata_en <= litedramcore_inti_p3_rddata_en;
        end
 // synthesis translate_off
        dummy_d_53 = dummy_s;
@@ -3998,11 +3320,11 @@ end
 reg dummy_d_54;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_cs_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_cs_n <= soc_sdram_slave_p3_cs_n;
+       litedramcore_master_p0_address <= 15'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_address <= litedramcore_slave_p0_address;
        end else begin
-               soc_sdram_master_p3_cs_n <= soc_sdram_inti_p3_cs_n;
+               litedramcore_master_p0_address <= litedramcore_inti_p0_address;
        end
 // synthesis translate_off
        dummy_d_54 = dummy_s;
@@ -4013,11 +3335,11 @@ end
 reg dummy_d_55;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_ras_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_ras_n <= soc_sdram_slave_p3_ras_n;
+       litedramcore_master_p0_bank <= 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
        end else begin
-               soc_sdram_master_p3_ras_n <= soc_sdram_inti_p3_ras_n;
+               litedramcore_master_p0_bank <= litedramcore_inti_p0_bank;
        end
 // synthesis translate_off
        dummy_d_55 = dummy_s;
@@ -4028,10 +3350,11 @@ end
 reg dummy_d_56;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p3_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p3_rddata <= soc_sdram_master_p3_rddata;
+       litedramcore_master_p0_cas_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
        end else begin
+               litedramcore_master_p0_cas_n <= litedramcore_inti_p0_cas_n;
        end
 // synthesis translate_off
        dummy_d_56 = dummy_s;
@@ -4042,11 +3365,11 @@ end
 reg dummy_d_57;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_we_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_we_n <= soc_sdram_slave_p3_we_n;
+       litedramcore_master_p0_cs_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
        end else begin
-               soc_sdram_master_p3_we_n <= soc_sdram_inti_p3_we_n;
+               litedramcore_master_p0_cs_n <= litedramcore_inti_p0_cs_n;
        end
 // synthesis translate_off
        dummy_d_57 = dummy_s;
@@ -4057,10 +3380,11 @@ end
 reg dummy_d_58;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p3_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p3_rddata_valid <= soc_sdram_master_p3_rddata_valid;
+       litedramcore_master_p0_ras_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
        end else begin
+               litedramcore_master_p0_ras_n <= litedramcore_inti_p0_ras_n;
        end
 // synthesis translate_off
        dummy_d_58 = dummy_s;
@@ -4071,11 +3395,10 @@ end
 reg dummy_d_59;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_cke <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_cke <= soc_sdram_slave_p3_cke;
+       litedramcore_slave_p0_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
        end else begin
-               soc_sdram_master_p3_cke <= soc_sdram_inti_p3_cke;
        end
 // synthesis translate_off
        dummy_d_59 = dummy_s;
@@ -4086,11 +3409,11 @@ end
 reg dummy_d_60;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_odt <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_odt <= soc_sdram_slave_p3_odt;
+       litedramcore_master_p0_we_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
        end else begin
-               soc_sdram_master_p3_odt <= soc_sdram_inti_p3_odt;
+               litedramcore_master_p0_we_n <= litedramcore_inti_p0_we_n;
        end
 // synthesis translate_off
        dummy_d_60 = dummy_s;
@@ -4101,11 +3424,10 @@ end
 reg dummy_d_61;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_reset_n <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_reset_n <= soc_sdram_slave_p3_reset_n;
+       litedramcore_slave_p0_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
        end else begin
-               soc_sdram_master_p3_reset_n <= soc_sdram_inti_p3_reset_n;
        end
 // synthesis translate_off
        dummy_d_61 = dummy_s;
@@ -4116,11 +3438,11 @@ end
 reg dummy_d_62;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_act_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_act_n <= soc_sdram_slave_p3_act_n;
+       litedramcore_master_p0_cke <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
        end else begin
-               soc_sdram_master_p3_act_n <= soc_sdram_inti_p3_act_n;
+               litedramcore_master_p0_cke <= litedramcore_inti_p0_cke;
        end
 // synthesis translate_off
        dummy_d_62 = dummy_s;
@@ -4131,11 +3453,11 @@ end
 reg dummy_d_63;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_wrdata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_wrdata <= soc_sdram_slave_p3_wrdata;
+       litedramcore_master_p0_odt <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
        end else begin
-               soc_sdram_master_p3_wrdata <= soc_sdram_inti_p3_wrdata;
+               litedramcore_master_p0_odt <= litedramcore_inti_p0_odt;
        end
 // synthesis translate_off
        dummy_d_63 = dummy_s;
@@ -4146,10 +3468,11 @@ end
 reg dummy_d_64;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_master_p0_reset_n <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
        end else begin
-               soc_sdram_inti_p0_rddata <= soc_sdram_master_p0_rddata;
+               litedramcore_master_p0_reset_n <= litedramcore_inti_p0_reset_n;
        end
 // synthesis translate_off
        dummy_d_64 = dummy_s;
@@ -4160,11 +3483,11 @@ end
 reg dummy_d_65;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_wrdata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_wrdata_en <= soc_sdram_slave_p3_wrdata_en;
+       litedramcore_master_p0_act_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
        end else begin
-               soc_sdram_master_p3_wrdata_en <= soc_sdram_inti_p3_wrdata_en;
+               litedramcore_master_p0_act_n <= litedramcore_inti_p0_act_n;
        end
 // synthesis translate_off
        dummy_d_65 = dummy_s;
@@ -4175,10 +3498,11 @@ end
 reg dummy_d_66;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_master_p0_wrdata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
        end else begin
-               soc_sdram_inti_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid;
+               litedramcore_master_p0_wrdata <= litedramcore_inti_p0_wrdata;
        end
 // synthesis translate_off
        dummy_d_66 = dummy_s;
@@ -4189,11 +3513,10 @@ end
 reg dummy_d_67;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_wrdata_mask <= 4'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_wrdata_mask <= soc_sdram_slave_p3_wrdata_mask;
+       litedramcore_inti_p1_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p3_wrdata_mask <= soc_sdram_inti_p3_wrdata_mask;
+               litedramcore_inti_p1_rddata <= litedramcore_master_p1_rddata;
        end
 // synthesis translate_off
        dummy_d_67 = dummy_s;
@@ -4204,11 +3527,11 @@ end
 reg dummy_d_68;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p3_rddata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p3_rddata_en <= soc_sdram_slave_p3_rddata_en;
+       litedramcore_master_p0_wrdata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
        end else begin
-               soc_sdram_master_p3_rddata_en <= soc_sdram_inti_p3_rddata_en;
+               litedramcore_master_p0_wrdata_en <= litedramcore_inti_p0_wrdata_en;
        end
 // synthesis translate_off
        dummy_d_68 = dummy_s;
@@ -4219,11 +3542,10 @@ end
 reg dummy_d_69;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_address <= 15'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_address <= soc_sdram_slave_p0_address;
+       litedramcore_inti_p1_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p0_address <= soc_sdram_inti_p0_address;
+               litedramcore_inti_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
        end
 // synthesis translate_off
        dummy_d_69 = dummy_s;
@@ -4234,11 +3556,11 @@ end
 reg dummy_d_70;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_bank <= 3'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_bank <= soc_sdram_slave_p0_bank;
+       litedramcore_master_p0_wrdata_mask <= 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
        end else begin
-               soc_sdram_master_p0_bank <= soc_sdram_inti_p0_bank;
+               litedramcore_master_p0_wrdata_mask <= litedramcore_inti_p0_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_70 = dummy_s;
@@ -4249,11 +3571,11 @@ end
 reg dummy_d_71;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_cas_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_cas_n <= soc_sdram_slave_p0_cas_n;
+       litedramcore_master_p0_rddata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
        end else begin
-               soc_sdram_master_p0_cas_n <= soc_sdram_inti_p0_cas_n;
+               litedramcore_master_p0_rddata_en <= litedramcore_inti_p0_rddata_en;
        end
 // synthesis translate_off
        dummy_d_71 = dummy_s;
@@ -4264,11 +3586,11 @@ end
 reg dummy_d_72;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_cs_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_cs_n <= soc_sdram_slave_p0_cs_n;
+       litedramcore_master_p1_address <= 15'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_address <= litedramcore_slave_p1_address;
        end else begin
-               soc_sdram_master_p0_cs_n <= soc_sdram_inti_p0_cs_n;
+               litedramcore_master_p1_address <= litedramcore_inti_p1_address;
        end
 // synthesis translate_off
        dummy_d_72 = dummy_s;
@@ -4279,11 +3601,11 @@ end
 reg dummy_d_73;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_ras_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_ras_n <= soc_sdram_slave_p0_ras_n;
+       litedramcore_master_p1_bank <= 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
        end else begin
-               soc_sdram_master_p0_ras_n <= soc_sdram_inti_p0_ras_n;
+               litedramcore_master_p1_bank <= litedramcore_inti_p1_bank;
        end
 // synthesis translate_off
        dummy_d_73 = dummy_s;
@@ -4294,10 +3616,11 @@ end
 reg dummy_d_74;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p0_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p0_rddata <= soc_sdram_master_p0_rddata;
+       litedramcore_master_p1_cas_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
        end else begin
+               litedramcore_master_p1_cas_n <= litedramcore_inti_p1_cas_n;
        end
 // synthesis translate_off
        dummy_d_74 = dummy_s;
@@ -4308,11 +3631,11 @@ end
 reg dummy_d_75;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_we_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_we_n <= soc_sdram_slave_p0_we_n;
+       litedramcore_master_p1_cs_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
        end else begin
-               soc_sdram_master_p0_we_n <= soc_sdram_inti_p0_we_n;
+               litedramcore_master_p1_cs_n <= litedramcore_inti_p1_cs_n;
        end
 // synthesis translate_off
        dummy_d_75 = dummy_s;
@@ -4323,10 +3646,11 @@ end
 reg dummy_d_76;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p0_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p0_rddata_valid <= soc_sdram_master_p0_rddata_valid;
+       litedramcore_master_p1_ras_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
        end else begin
+               litedramcore_master_p1_ras_n <= litedramcore_inti_p1_ras_n;
        end
 // synthesis translate_off
        dummy_d_76 = dummy_s;
@@ -4337,11 +3661,10 @@ end
 reg dummy_d_77;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_cke <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_cke <= soc_sdram_slave_p0_cke;
+       litedramcore_slave_p1_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
        end else begin
-               soc_sdram_master_p0_cke <= soc_sdram_inti_p0_cke;
        end
 // synthesis translate_off
        dummy_d_77 = dummy_s;
@@ -4352,11 +3675,11 @@ end
 reg dummy_d_78;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_odt <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_odt <= soc_sdram_slave_p0_odt;
+       litedramcore_master_p1_we_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
        end else begin
-               soc_sdram_master_p0_odt <= soc_sdram_inti_p0_odt;
+               litedramcore_master_p1_we_n <= litedramcore_inti_p1_we_n;
        end
 // synthesis translate_off
        dummy_d_78 = dummy_s;
@@ -4367,11 +3690,10 @@ end
 reg dummy_d_79;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_reset_n <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_reset_n <= soc_sdram_slave_p0_reset_n;
+       litedramcore_slave_p1_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
        end else begin
-               soc_sdram_master_p0_reset_n <= soc_sdram_inti_p0_reset_n;
        end
 // synthesis translate_off
        dummy_d_79 = dummy_s;
@@ -4382,11 +3704,11 @@ end
 reg dummy_d_80;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_act_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_act_n <= soc_sdram_slave_p0_act_n;
+       litedramcore_master_p1_cke <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
        end else begin
-               soc_sdram_master_p0_act_n <= soc_sdram_inti_p0_act_n;
+               litedramcore_master_p1_cke <= litedramcore_inti_p1_cke;
        end
 // synthesis translate_off
        dummy_d_80 = dummy_s;
@@ -4397,11 +3719,11 @@ end
 reg dummy_d_81;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_wrdata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_wrdata <= soc_sdram_slave_p0_wrdata;
+       litedramcore_master_p1_odt <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
        end else begin
-               soc_sdram_master_p0_wrdata <= soc_sdram_inti_p0_wrdata;
+               litedramcore_master_p1_odt <= litedramcore_inti_p1_odt;
        end
 // synthesis translate_off
        dummy_d_81 = dummy_s;
@@ -4412,10 +3734,11 @@ end
 reg dummy_d_82;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_master_p1_reset_n <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
        end else begin
-               soc_sdram_inti_p1_rddata <= soc_sdram_master_p1_rddata;
+               litedramcore_master_p1_reset_n <= litedramcore_inti_p1_reset_n;
        end
 // synthesis translate_off
        dummy_d_82 = dummy_s;
@@ -4426,11 +3749,11 @@ end
 reg dummy_d_83;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_wrdata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_wrdata_en <= soc_sdram_slave_p0_wrdata_en;
+       litedramcore_master_p1_act_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
        end else begin
-               soc_sdram_master_p0_wrdata_en <= soc_sdram_inti_p0_wrdata_en;
+               litedramcore_master_p1_act_n <= litedramcore_inti_p1_act_n;
        end
 // synthesis translate_off
        dummy_d_83 = dummy_s;
@@ -4441,10 +3764,11 @@ end
 reg dummy_d_84;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_master_p1_wrdata <= 32'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
        end else begin
-               soc_sdram_inti_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid;
+               litedramcore_master_p1_wrdata <= litedramcore_inti_p1_wrdata;
        end
 // synthesis translate_off
        dummy_d_84 = dummy_s;
@@ -4455,11 +3779,10 @@ end
 reg dummy_d_85;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_wrdata_mask <= 4'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_wrdata_mask <= soc_sdram_slave_p0_wrdata_mask;
+       litedramcore_inti_p2_rddata <= 32'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p0_wrdata_mask <= soc_sdram_inti_p0_wrdata_mask;
+               litedramcore_inti_p2_rddata <= litedramcore_master_p2_rddata;
        end
 // synthesis translate_off
        dummy_d_85 = dummy_s;
@@ -4470,11 +3793,11 @@ end
 reg dummy_d_86;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p0_rddata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p0_rddata_en <= soc_sdram_slave_p0_rddata_en;
+       litedramcore_master_p1_wrdata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
        end else begin
-               soc_sdram_master_p0_rddata_en <= soc_sdram_inti_p0_rddata_en;
+               litedramcore_master_p1_wrdata_en <= litedramcore_inti_p1_wrdata_en;
        end
 // synthesis translate_off
        dummy_d_86 = dummy_s;
@@ -4485,11 +3808,10 @@ end
 reg dummy_d_87;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_address <= 15'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_address <= soc_sdram_slave_p1_address;
+       litedramcore_inti_p2_rddata_valid <= 1'd0;
+       if (litedramcore_storage[0]) begin
        end else begin
-               soc_sdram_master_p1_address <= soc_sdram_inti_p1_address;
+               litedramcore_inti_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
        end
 // synthesis translate_off
        dummy_d_87 = dummy_s;
@@ -4500,11 +3822,11 @@ end
 reg dummy_d_88;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_bank <= 3'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_bank <= soc_sdram_slave_p1_bank;
+       litedramcore_master_p1_wrdata_mask <= 4'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
        end else begin
-               soc_sdram_master_p1_bank <= soc_sdram_inti_p1_bank;
+               litedramcore_master_p1_wrdata_mask <= litedramcore_inti_p1_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_88 = dummy_s;
@@ -4515,11 +3837,11 @@ end
 reg dummy_d_89;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_cas_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_cas_n <= soc_sdram_slave_p1_cas_n;
+       litedramcore_master_p1_rddata_en <= 1'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
        end else begin
-               soc_sdram_master_p1_cas_n <= soc_sdram_inti_p1_cas_n;
+               litedramcore_master_p1_rddata_en <= litedramcore_inti_p1_rddata_en;
        end
 // synthesis translate_off
        dummy_d_89 = dummy_s;
@@ -4530,11 +3852,11 @@ end
 reg dummy_d_90;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_cs_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_cs_n <= soc_sdram_slave_p1_cs_n;
+       litedramcore_master_p2_address <= 15'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_address <= litedramcore_slave_p2_address;
        end else begin
-               soc_sdram_master_p1_cs_n <= soc_sdram_inti_p1_cs_n;
+               litedramcore_master_p2_address <= litedramcore_inti_p2_address;
        end
 // synthesis translate_off
        dummy_d_90 = dummy_s;
@@ -4545,11 +3867,11 @@ end
 reg dummy_d_91;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_ras_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_ras_n <= soc_sdram_slave_p1_ras_n;
+       litedramcore_master_p2_bank <= 3'd0;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
        end else begin
-               soc_sdram_master_p1_ras_n <= soc_sdram_inti_p1_ras_n;
+               litedramcore_master_p2_bank <= litedramcore_inti_p2_bank;
        end
 // synthesis translate_off
        dummy_d_91 = dummy_s;
@@ -4560,10 +3882,11 @@ end
 reg dummy_d_92;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p1_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p1_rddata <= soc_sdram_master_p1_rddata;
+       litedramcore_master_p2_cas_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
        end else begin
+               litedramcore_master_p2_cas_n <= litedramcore_inti_p2_cas_n;
        end
 // synthesis translate_off
        dummy_d_92 = dummy_s;
@@ -4574,25 +3897,38 @@ end
 reg dummy_d_93;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_we_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_we_n <= soc_sdram_slave_p1_we_n;
+       litedramcore_master_p2_cs_n <= 1'd1;
+       if (litedramcore_storage[0]) begin
+               litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
        end else begin
-               soc_sdram_master_p1_we_n <= soc_sdram_inti_p1_we_n;
+               litedramcore_master_p2_cs_n <= litedramcore_inti_p2_cs_n;
        end
 // synthesis translate_off
        dummy_d_93 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_inti_p0_cke = litedramcore_storage[1];
+assign litedramcore_inti_p1_cke = litedramcore_storage[1];
+assign litedramcore_inti_p2_cke = litedramcore_storage[1];
+assign litedramcore_inti_p3_cke = litedramcore_storage[1];
+assign litedramcore_inti_p0_odt = litedramcore_storage[2];
+assign litedramcore_inti_p1_odt = litedramcore_storage[2];
+assign litedramcore_inti_p2_odt = litedramcore_storage[2];
+assign litedramcore_inti_p3_odt = litedramcore_storage[2];
+assign litedramcore_inti_p0_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p1_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p2_reset_n = litedramcore_storage[3];
+assign litedramcore_inti_p3_reset_n = litedramcore_storage[3];
 
 // synthesis translate_off
 reg dummy_d_94;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_slave_p1_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_slave_p1_rddata_valid <= soc_sdram_master_p1_rddata_valid;
+       litedramcore_inti_p0_ras_n <= 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_ras_n <= (~litedramcore_phaseinjector0_command_storage[3]);
        end else begin
+               litedramcore_inti_p0_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_94 = dummy_s;
@@ -4603,11 +3939,11 @@ end
 reg dummy_d_95;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_cke <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_cke <= soc_sdram_slave_p1_cke;
+       litedramcore_inti_p0_we_n <= 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_we_n <= (~litedramcore_phaseinjector0_command_storage[1]);
        end else begin
-               soc_sdram_master_p1_cke <= soc_sdram_inti_p1_cke;
+               litedramcore_inti_p0_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_95 = dummy_s;
@@ -4618,11 +3954,11 @@ end
 reg dummy_d_96;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_odt <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_odt <= soc_sdram_slave_p1_odt;
+       litedramcore_inti_p0_cas_n <= 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_cas_n <= (~litedramcore_phaseinjector0_command_storage[2]);
        end else begin
-               soc_sdram_master_p1_odt <= soc_sdram_inti_p1_odt;
+               litedramcore_inti_p0_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_96 = dummy_s;
@@ -4633,26 +3969,32 @@ end
 reg dummy_d_97;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_reset_n <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_reset_n <= soc_sdram_slave_p1_reset_n;
+       litedramcore_inti_p0_cs_n <= 1'd1;
+       if (litedramcore_phaseinjector0_command_issue_re) begin
+               litedramcore_inti_p0_cs_n <= {1{(~litedramcore_phaseinjector0_command_storage[0])}};
        end else begin
-               soc_sdram_master_p1_reset_n <= soc_sdram_inti_p1_reset_n;
+               litedramcore_inti_p0_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_97 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_inti_p0_address = litedramcore_phaseinjector0_address_storage;
+assign litedramcore_inti_p0_bank = litedramcore_phaseinjector0_baddress_storage;
+assign litedramcore_inti_p0_wrdata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[4]);
+assign litedramcore_inti_p0_rddata_en = (litedramcore_phaseinjector0_command_issue_re & litedramcore_phaseinjector0_command_storage[5]);
+assign litedramcore_inti_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
+assign litedramcore_inti_p0_wrdata_mask = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_98;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_act_n <= 1'd1;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_act_n <= soc_sdram_slave_p1_act_n;
+       litedramcore_inti_p1_ras_n <= 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_ras_n <= (~litedramcore_phaseinjector1_command_storage[3]);
        end else begin
-               soc_sdram_master_p1_act_n <= soc_sdram_inti_p1_act_n;
+               litedramcore_inti_p1_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_98 = dummy_s;
@@ -4663,11 +4005,11 @@ end
 reg dummy_d_99;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_wrdata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_wrdata <= soc_sdram_slave_p1_wrdata;
+       litedramcore_inti_p1_we_n <= 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_we_n <= (~litedramcore_phaseinjector1_command_storage[1]);
        end else begin
-               soc_sdram_master_p1_wrdata <= soc_sdram_inti_p1_wrdata;
+               litedramcore_inti_p1_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_99 = dummy_s;
@@ -4678,10 +4020,11 @@ end
 reg dummy_d_100;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_rddata <= 32'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_inti_p1_cas_n <= 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_cas_n <= (~litedramcore_phaseinjector1_command_storage[2]);
        end else begin
-               soc_sdram_inti_p2_rddata <= soc_sdram_master_p2_rddata;
+               litedramcore_inti_p1_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_100 = dummy_s;
@@ -4692,25 +4035,32 @@ end
 reg dummy_d_101;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_wrdata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_wrdata_en <= soc_sdram_slave_p1_wrdata_en;
+       litedramcore_inti_p1_cs_n <= 1'd1;
+       if (litedramcore_phaseinjector1_command_issue_re) begin
+               litedramcore_inti_p1_cs_n <= {1{(~litedramcore_phaseinjector1_command_storage[0])}};
        end else begin
-               soc_sdram_master_p1_wrdata_en <= soc_sdram_inti_p1_wrdata_en;
+               litedramcore_inti_p1_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_101 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_inti_p1_address = litedramcore_phaseinjector1_address_storage;
+assign litedramcore_inti_p1_bank = litedramcore_phaseinjector1_baddress_storage;
+assign litedramcore_inti_p1_wrdata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[4]);
+assign litedramcore_inti_p1_rddata_en = (litedramcore_phaseinjector1_command_issue_re & litedramcore_phaseinjector1_command_storage[5]);
+assign litedramcore_inti_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
+assign litedramcore_inti_p1_wrdata_mask = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_102;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_rddata_valid <= 1'd0;
-       if (soc_sdram_storage[0]) begin
+       litedramcore_inti_p2_ras_n <= 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_ras_n <= (~litedramcore_phaseinjector2_command_storage[3]);
        end else begin
-               soc_sdram_inti_p2_rddata_valid <= soc_sdram_master_p2_rddata_valid;
+               litedramcore_inti_p2_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_102 = dummy_s;
@@ -4721,11 +4071,11 @@ end
 reg dummy_d_103;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_wrdata_mask <= 4'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_wrdata_mask <= soc_sdram_slave_p1_wrdata_mask;
+       litedramcore_inti_p2_we_n <= 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_we_n <= (~litedramcore_phaseinjector2_command_storage[1]);
        end else begin
-               soc_sdram_master_p1_wrdata_mask <= soc_sdram_inti_p1_wrdata_mask;
+               litedramcore_inti_p2_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_103 = dummy_s;
@@ -4736,11 +4086,11 @@ end
 reg dummy_d_104;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p1_rddata_en <= 1'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p1_rddata_en <= soc_sdram_slave_p1_rddata_en;
+       litedramcore_inti_p2_cas_n <= 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_cas_n <= (~litedramcore_phaseinjector2_command_storage[2]);
        end else begin
-               soc_sdram_master_p1_rddata_en <= soc_sdram_inti_p1_rddata_en;
+               litedramcore_inti_p2_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_104 = dummy_s;
@@ -4751,53 +4101,47 @@ end
 reg dummy_d_105;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_address <= 15'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_address <= soc_sdram_slave_p2_address;
+       litedramcore_inti_p2_cs_n <= 1'd1;
+       if (litedramcore_phaseinjector2_command_issue_re) begin
+               litedramcore_inti_p2_cs_n <= {1{(~litedramcore_phaseinjector2_command_storage[0])}};
        end else begin
-               soc_sdram_master_p2_address <= soc_sdram_inti_p2_address;
+               litedramcore_inti_p2_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_105 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_inti_p2_address = litedramcore_phaseinjector2_address_storage;
+assign litedramcore_inti_p2_bank = litedramcore_phaseinjector2_baddress_storage;
+assign litedramcore_inti_p2_wrdata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[4]);
+assign litedramcore_inti_p2_rddata_en = (litedramcore_phaseinjector2_command_issue_re & litedramcore_phaseinjector2_command_storage[5]);
+assign litedramcore_inti_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
+assign litedramcore_inti_p2_wrdata_mask = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_106;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_master_p2_bank <= 3'd0;
-       if (soc_sdram_storage[0]) begin
-               soc_sdram_master_p2_bank <= soc_sdram_slave_p2_bank;
+       litedramcore_inti_p3_ras_n <= 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_ras_n <= (~litedramcore_phaseinjector3_command_storage[3]);
        end else begin
-               soc_sdram_master_p2_bank <= soc_sdram_inti_p2_bank;
+               litedramcore_inti_p3_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_106 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_inti_p0_cke = soc_sdram_storage[1];
-assign soc_sdram_inti_p1_cke = soc_sdram_storage[1];
-assign soc_sdram_inti_p2_cke = soc_sdram_storage[1];
-assign soc_sdram_inti_p3_cke = soc_sdram_storage[1];
-assign soc_sdram_inti_p0_odt = soc_sdram_storage[2];
-assign soc_sdram_inti_p1_odt = soc_sdram_storage[2];
-assign soc_sdram_inti_p2_odt = soc_sdram_storage[2];
-assign soc_sdram_inti_p3_odt = soc_sdram_storage[2];
-assign soc_sdram_inti_p0_reset_n = soc_sdram_storage[3];
-assign soc_sdram_inti_p1_reset_n = soc_sdram_storage[3];
-assign soc_sdram_inti_p2_reset_n = soc_sdram_storage[3];
-assign soc_sdram_inti_p3_reset_n = soc_sdram_storage[3];
 
 // synthesis translate_off
 reg dummy_d_107;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_cas_n <= 1'd1;
-       if (soc_sdram_phaseinjector0_command_issue_re) begin
-               soc_sdram_inti_p0_cas_n <= (~soc_sdram_phaseinjector0_command_storage[2]);
+       litedramcore_inti_p3_we_n <= 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_we_n <= (~litedramcore_phaseinjector3_command_storage[1]);
        end else begin
-               soc_sdram_inti_p0_cas_n <= 1'd1;
+               litedramcore_inti_p3_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_107 = dummy_s;
@@ -4808,11 +4152,11 @@ end
 reg dummy_d_108;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_cs_n <= 1'd1;
-       if (soc_sdram_phaseinjector0_command_issue_re) begin
-               soc_sdram_inti_p0_cs_n <= {1{(~soc_sdram_phaseinjector0_command_storage[0])}};
+       litedramcore_inti_p3_cas_n <= 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_cas_n <= (~litedramcore_phaseinjector3_command_storage[2]);
        end else begin
-               soc_sdram_inti_p0_cs_n <= {1{1'd1}};
+               litedramcore_inti_p3_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_108 = dummy_s;
@@ -4823,48 +4167,158 @@ end
 reg dummy_d_109;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_ras_n <= 1'd1;
-       if (soc_sdram_phaseinjector0_command_issue_re) begin
-               soc_sdram_inti_p0_ras_n <= (~soc_sdram_phaseinjector0_command_storage[3]);
+       litedramcore_inti_p3_cs_n <= 1'd1;
+       if (litedramcore_phaseinjector3_command_issue_re) begin
+               litedramcore_inti_p3_cs_n <= {1{(~litedramcore_phaseinjector3_command_storage[0])}};
        end else begin
-               soc_sdram_inti_p0_ras_n <= 1'd1;
+               litedramcore_inti_p3_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_109 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_inti_p3_address = litedramcore_phaseinjector3_address_storage;
+assign litedramcore_inti_p3_bank = litedramcore_phaseinjector3_baddress_storage;
+assign litedramcore_inti_p3_wrdata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[4]);
+assign litedramcore_inti_p3_rddata_en = (litedramcore_phaseinjector3_command_issue_re & litedramcore_phaseinjector3_command_storage[5]);
+assign litedramcore_inti_p3_wrdata = litedramcore_phaseinjector3_wrdata_storage;
+assign litedramcore_inti_p3_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_req_valid = litedramcore_interface_bank0_valid;
+assign litedramcore_interface_bank0_ready = litedramcore_bankmachine0_req_ready;
+assign litedramcore_bankmachine0_req_we = litedramcore_interface_bank0_we;
+assign litedramcore_bankmachine0_req_addr = litedramcore_interface_bank0_addr;
+assign litedramcore_interface_bank0_lock = litedramcore_bankmachine0_req_lock;
+assign litedramcore_interface_bank0_wdata_ready = litedramcore_bankmachine0_req_wdata_ready;
+assign litedramcore_interface_bank0_rdata_valid = litedramcore_bankmachine0_req_rdata_valid;
+assign litedramcore_bankmachine1_req_valid = litedramcore_interface_bank1_valid;
+assign litedramcore_interface_bank1_ready = litedramcore_bankmachine1_req_ready;
+assign litedramcore_bankmachine1_req_we = litedramcore_interface_bank1_we;
+assign litedramcore_bankmachine1_req_addr = litedramcore_interface_bank1_addr;
+assign litedramcore_interface_bank1_lock = litedramcore_bankmachine1_req_lock;
+assign litedramcore_interface_bank1_wdata_ready = litedramcore_bankmachine1_req_wdata_ready;
+assign litedramcore_interface_bank1_rdata_valid = litedramcore_bankmachine1_req_rdata_valid;
+assign litedramcore_bankmachine2_req_valid = litedramcore_interface_bank2_valid;
+assign litedramcore_interface_bank2_ready = litedramcore_bankmachine2_req_ready;
+assign litedramcore_bankmachine2_req_we = litedramcore_interface_bank2_we;
+assign litedramcore_bankmachine2_req_addr = litedramcore_interface_bank2_addr;
+assign litedramcore_interface_bank2_lock = litedramcore_bankmachine2_req_lock;
+assign litedramcore_interface_bank2_wdata_ready = litedramcore_bankmachine2_req_wdata_ready;
+assign litedramcore_interface_bank2_rdata_valid = litedramcore_bankmachine2_req_rdata_valid;
+assign litedramcore_bankmachine3_req_valid = litedramcore_interface_bank3_valid;
+assign litedramcore_interface_bank3_ready = litedramcore_bankmachine3_req_ready;
+assign litedramcore_bankmachine3_req_we = litedramcore_interface_bank3_we;
+assign litedramcore_bankmachine3_req_addr = litedramcore_interface_bank3_addr;
+assign litedramcore_interface_bank3_lock = litedramcore_bankmachine3_req_lock;
+assign litedramcore_interface_bank3_wdata_ready = litedramcore_bankmachine3_req_wdata_ready;
+assign litedramcore_interface_bank3_rdata_valid = litedramcore_bankmachine3_req_rdata_valid;
+assign litedramcore_bankmachine4_req_valid = litedramcore_interface_bank4_valid;
+assign litedramcore_interface_bank4_ready = litedramcore_bankmachine4_req_ready;
+assign litedramcore_bankmachine4_req_we = litedramcore_interface_bank4_we;
+assign litedramcore_bankmachine4_req_addr = litedramcore_interface_bank4_addr;
+assign litedramcore_interface_bank4_lock = litedramcore_bankmachine4_req_lock;
+assign litedramcore_interface_bank4_wdata_ready = litedramcore_bankmachine4_req_wdata_ready;
+assign litedramcore_interface_bank4_rdata_valid = litedramcore_bankmachine4_req_rdata_valid;
+assign litedramcore_bankmachine5_req_valid = litedramcore_interface_bank5_valid;
+assign litedramcore_interface_bank5_ready = litedramcore_bankmachine5_req_ready;
+assign litedramcore_bankmachine5_req_we = litedramcore_interface_bank5_we;
+assign litedramcore_bankmachine5_req_addr = litedramcore_interface_bank5_addr;
+assign litedramcore_interface_bank5_lock = litedramcore_bankmachine5_req_lock;
+assign litedramcore_interface_bank5_wdata_ready = litedramcore_bankmachine5_req_wdata_ready;
+assign litedramcore_interface_bank5_rdata_valid = litedramcore_bankmachine5_req_rdata_valid;
+assign litedramcore_bankmachine6_req_valid = litedramcore_interface_bank6_valid;
+assign litedramcore_interface_bank6_ready = litedramcore_bankmachine6_req_ready;
+assign litedramcore_bankmachine6_req_we = litedramcore_interface_bank6_we;
+assign litedramcore_bankmachine6_req_addr = litedramcore_interface_bank6_addr;
+assign litedramcore_interface_bank6_lock = litedramcore_bankmachine6_req_lock;
+assign litedramcore_interface_bank6_wdata_ready = litedramcore_bankmachine6_req_wdata_ready;
+assign litedramcore_interface_bank6_rdata_valid = litedramcore_bankmachine6_req_rdata_valid;
+assign litedramcore_bankmachine7_req_valid = litedramcore_interface_bank7_valid;
+assign litedramcore_interface_bank7_ready = litedramcore_bankmachine7_req_ready;
+assign litedramcore_bankmachine7_req_we = litedramcore_interface_bank7_we;
+assign litedramcore_bankmachine7_req_addr = litedramcore_interface_bank7_addr;
+assign litedramcore_interface_bank7_lock = litedramcore_bankmachine7_req_lock;
+assign litedramcore_interface_bank7_wdata_ready = litedramcore_bankmachine7_req_wdata_ready;
+assign litedramcore_interface_bank7_rdata_valid = litedramcore_bankmachine7_req_rdata_valid;
+assign litedramcore_timer_wait = (~litedramcore_timer_done0);
+assign litedramcore_postponer_req_i = litedramcore_timer_done0;
+assign litedramcore_wants_refresh = litedramcore_postponer_req_o;
+assign litedramcore_wants_zqcs = litedramcore_zqcs_timer_done0;
+assign litedramcore_zqcs_timer_wait = (~litedramcore_zqcs_executer_done);
+assign litedramcore_timer_done1 = (litedramcore_timer_count1 == 1'd0);
+assign litedramcore_timer_done0 = litedramcore_timer_done1;
+assign litedramcore_timer_count0 = litedramcore_timer_count1;
+assign litedramcore_sequencer_start1 = (litedramcore_sequencer_start0 | (litedramcore_sequencer_count != 1'd0));
+assign litedramcore_sequencer_done0 = (litedramcore_sequencer_done1 & (litedramcore_sequencer_count == 1'd0));
+assign litedramcore_zqcs_timer_done1 = (litedramcore_zqcs_timer_count1 == 1'd0);
+assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
+assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
 
 // synthesis translate_off
 reg dummy_d_110;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p0_we_n <= 1'd1;
-       if (soc_sdram_phaseinjector0_command_issue_re) begin
-               soc_sdram_inti_p0_we_n <= (~soc_sdram_phaseinjector0_command_storage[1]);
-       end else begin
-               soc_sdram_inti_p0_we_n <= 1'd1;
-       end
+       refresher_next_state <= 2'd0;
+       refresher_next_state <= refresher_state;
+       case (refresher_state)
+               1'd1: begin
+                       if (litedramcore_cmd_ready) begin
+                               refresher_next_state <= 2'd2;
+                       end
+               end
+               2'd2: begin
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                                       refresher_next_state <= 2'd3;
+                               end else begin
+                                       refresher_next_state <= 1'd0;
+                               end
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_zqcs_executer_done) begin
+                               refresher_next_state <= 1'd0;
+                       end
+               end
+               default: begin
+                       if (1'd1) begin
+                               if (litedramcore_wants_refresh) begin
+                                       refresher_next_state <= 1'd1;
+                               end
+                       end
+               end
+       endcase
 // synthesis translate_off
        dummy_d_110 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_inti_p0_address = soc_sdram_phaseinjector0_address_storage;
-assign soc_sdram_inti_p0_bank = soc_sdram_phaseinjector0_baddress_storage;
-assign soc_sdram_inti_p0_wrdata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[4]);
-assign soc_sdram_inti_p0_rddata_en = (soc_sdram_phaseinjector0_command_issue_re & soc_sdram_phaseinjector0_command_storage[5]);
-assign soc_sdram_inti_p0_wrdata = soc_sdram_phaseinjector0_wrdata_storage;
-assign soc_sdram_inti_p0_wrdata_mask = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_111;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_cas_n <= 1'd1;
-       if (soc_sdram_phaseinjector1_command_issue_re) begin
-               soc_sdram_inti_p1_cas_n <= (~soc_sdram_phaseinjector1_command_storage[2]);
-       end else begin
-               soc_sdram_inti_p1_cas_n <= 1'd1;
-       end
+       litedramcore_cmd_valid <= 1'd0;
+       case (refresher_state)
+               1'd1: begin
+                       litedramcore_cmd_valid <= 1'd1;
+               end
+               2'd2: begin
+                       litedramcore_cmd_valid <= 1'd1;
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                               end else begin
+                                       litedramcore_cmd_valid <= 1'd0;
+                               end
+                       end
+               end
+               2'd3: begin
+                       litedramcore_cmd_valid <= 1'd1;
+                       if (litedramcore_zqcs_executer_done) begin
+                               litedramcore_cmd_valid <= 1'd0;
+                       end
+               end
+               default: begin
+               end
+       endcase
 // synthesis translate_off
        dummy_d_111 = dummy_s;
 // synthesis translate_on
@@ -4874,12 +4328,23 @@ end
 reg dummy_d_112;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_cs_n <= 1'd1;
-       if (soc_sdram_phaseinjector1_command_issue_re) begin
-               soc_sdram_inti_p1_cs_n <= {1{(~soc_sdram_phaseinjector1_command_storage[0])}};
-       end else begin
-               soc_sdram_inti_p1_cs_n <= {1{1'd1}};
-       end
+       litedramcore_zqcs_executer_start <= 1'd0;
+       case (refresher_state)
+               1'd1: begin
+               end
+               2'd2: begin
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                                       litedramcore_zqcs_executer_start <= 1'd1;
+                               end else begin
+                               end
+                       end
+               end
+               2'd3: begin
+               end
+               default: begin
+               end
+       endcase
 // synthesis translate_off
        dummy_d_112 = dummy_s;
 // synthesis translate_on
@@ -4889,12 +4354,26 @@ end
 reg dummy_d_113;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_ras_n <= 1'd1;
-       if (soc_sdram_phaseinjector1_command_issue_re) begin
-               soc_sdram_inti_p1_ras_n <= (~soc_sdram_phaseinjector1_command_storage[3]);
-       end else begin
-               soc_sdram_inti_p1_ras_n <= 1'd1;
-       end
+       litedramcore_cmd_last <= 1'd0;
+       case (refresher_state)
+               1'd1: begin
+               end
+               2'd2: begin
+                       if (litedramcore_sequencer_done0) begin
+                               if (litedramcore_wants_zqcs) begin
+                               end else begin
+                                       litedramcore_cmd_last <= 1'd1;
+                               end
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_zqcs_executer_done) begin
+                               litedramcore_cmd_last <= 1'd1;
+                       end
+               end
+               default: begin
+               end
+       endcase
 // synthesis translate_off
        dummy_d_113 = dummy_s;
 // synthesis translate_on
@@ -4904,542 +4383,365 @@ end
 reg dummy_d_114;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p1_we_n <= 1'd1;
-       if (soc_sdram_phaseinjector1_command_issue_re) begin
-               soc_sdram_inti_p1_we_n <= (~soc_sdram_phaseinjector1_command_storage[1]);
-       end else begin
-               soc_sdram_inti_p1_we_n <= 1'd1;
-       end
+       litedramcore_sequencer_start0 <= 1'd0;
+       case (refresher_state)
+               1'd1: begin
+                       if (litedramcore_cmd_ready) begin
+                               litedramcore_sequencer_start0 <= 1'd1;
+                       end
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               default: begin
+               end
+       endcase
 // synthesis translate_off
        dummy_d_114 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_inti_p1_address = soc_sdram_phaseinjector1_address_storage;
-assign soc_sdram_inti_p1_bank = soc_sdram_phaseinjector1_baddress_storage;
-assign soc_sdram_inti_p1_wrdata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[4]);
-assign soc_sdram_inti_p1_rddata_en = (soc_sdram_phaseinjector1_command_issue_re & soc_sdram_phaseinjector1_command_storage[5]);
-assign soc_sdram_inti_p1_wrdata = soc_sdram_phaseinjector1_wrdata_storage;
-assign soc_sdram_inti_p1_wrdata_mask = 1'd0;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_115;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_cas_n <= 1'd1;
-       if (soc_sdram_phaseinjector2_command_issue_re) begin
-               soc_sdram_inti_p2_cas_n <= (~soc_sdram_phaseinjector2_command_storage[2]);
+       litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
+       if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+               litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
        end else begin
-               soc_sdram_inti_p2_cas_n <= 1'd1;
+               litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
        end
 // synthesis translate_off
        dummy_d_115 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
+assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
+assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
 
 // synthesis translate_off
 reg dummy_d_116;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_cs_n <= 1'd1;
-       if (soc_sdram_phaseinjector2_command_issue_re) begin
-               soc_sdram_inti_p2_cs_n <= {1{(~soc_sdram_phaseinjector2_command_storage[0])}};
-       end else begin
-               soc_sdram_inti_p2_cs_n <= {1{1'd1}};
+       litedramcore_bankmachine0_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
+                       litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+               end
        end
 // synthesis translate_off
        dummy_d_116 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
 
 // synthesis translate_off
 reg dummy_d_117;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_ras_n <= 1'd1;
-       if (soc_sdram_phaseinjector2_command_issue_re) begin
-               soc_sdram_inti_p2_ras_n <= (~soc_sdram_phaseinjector2_command_storage[3]);
+       litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
        end else begin
-               soc_sdram_inti_p2_ras_n <= 1'd1;
+               litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
        end
 // synthesis translate_off
        dummy_d_117 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
 
 // synthesis translate_off
 reg dummy_d_118;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p2_we_n <= 1'd1;
-       if (soc_sdram_phaseinjector2_command_issue_re) begin
-               soc_sdram_inti_p2_we_n <= (~soc_sdram_phaseinjector2_command_storage[1]);
-       end else begin
-               soc_sdram_inti_p2_we_n <= 1'd1;
-       end
+       bankmachine0_next_state <= 4'd0;
+       bankmachine0_next_state <= bankmachine0_state;
+       case (bankmachine0_state)
+               1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               if (litedramcore_bankmachine0_cmd_ready) begin
+                                       bankmachine0_next_state <= 3'd5;
+                               end
+                       end
+               end
+               2'd2: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               bankmachine0_next_state <= 3'd5;
+                       end
+               end
+               2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               if (litedramcore_bankmachine0_cmd_ready) begin
+                                       bankmachine0_next_state <= 3'd7;
+                               end
+                       end
+               end
+               3'd4: begin
+                       if ((~litedramcore_bankmachine0_refresh_req)) begin
+                               bankmachine0_next_state <= 1'd0;
+                       end
+               end
+               3'd5: begin
+                       bankmachine0_next_state <= 3'd6;
+               end
+               3'd6: begin
+                       bankmachine0_next_state <= 2'd3;
+               end
+               3'd7: begin
+                       bankmachine0_next_state <= 4'd8;
+               end
+               4'd8: begin
+                       bankmachine0_next_state <= 1'd0;
+               end
+               default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                               bankmachine0_next_state <= 3'd4;
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+                                                               bankmachine0_next_state <= 2'd2;
+                                                       end
+                                               end else begin
+                                                       bankmachine0_next_state <= 1'd1;
+                                               end
+                                       end else begin
+                                               bankmachine0_next_state <= 2'd3;
+                                       end
+                               end
+                       end
+               end
+       endcase
 // synthesis translate_off
        dummy_d_118 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_inti_p2_address = soc_sdram_phaseinjector2_address_storage;
-assign soc_sdram_inti_p2_bank = soc_sdram_phaseinjector2_baddress_storage;
-assign soc_sdram_inti_p2_wrdata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[4]);
-assign soc_sdram_inti_p2_rddata_en = (soc_sdram_phaseinjector2_command_issue_re & soc_sdram_phaseinjector2_command_storage[5]);
-assign soc_sdram_inti_p2_wrdata = soc_sdram_phaseinjector2_wrdata_storage;
-assign soc_sdram_inti_p2_wrdata_mask = 1'd0;
 
 // synthesis translate_off
 reg dummy_d_119;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_inti_p3_cas_n <= 1'd1;
-       if (soc_sdram_phaseinjector3_command_issue_re) begin
-               soc_sdram_inti_p3_cas_n <= (~soc_sdram_phaseinjector3_command_storage[2]);
-       end else begin
-               soc_sdram_inti_p3_cas_n <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_119 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_120;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_inti_p3_cs_n <= 1'd1;
-       if (soc_sdram_phaseinjector3_command_issue_re) begin
-               soc_sdram_inti_p3_cs_n <= {1{(~soc_sdram_phaseinjector3_command_storage[0])}};
-       end else begin
-               soc_sdram_inti_p3_cs_n <= {1{1'd1}};
-       end
-// synthesis translate_off
-       dummy_d_120 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_121;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_inti_p3_ras_n <= 1'd1;
-       if (soc_sdram_phaseinjector3_command_issue_re) begin
-               soc_sdram_inti_p3_ras_n <= (~soc_sdram_phaseinjector3_command_storage[3]);
-       end else begin
-               soc_sdram_inti_p3_ras_n <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_121 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_122;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_inti_p3_we_n <= 1'd1;
-       if (soc_sdram_phaseinjector3_command_issue_re) begin
-               soc_sdram_inti_p3_we_n <= (~soc_sdram_phaseinjector3_command_storage[1]);
-       end else begin
-               soc_sdram_inti_p3_we_n <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_122 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_inti_p3_address = soc_sdram_phaseinjector3_address_storage;
-assign soc_sdram_inti_p3_bank = soc_sdram_phaseinjector3_baddress_storage;
-assign soc_sdram_inti_p3_wrdata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[4]);
-assign soc_sdram_inti_p3_rddata_en = (soc_sdram_phaseinjector3_command_issue_re & soc_sdram_phaseinjector3_command_storage[5]);
-assign soc_sdram_inti_p3_wrdata = soc_sdram_phaseinjector3_wrdata_storage;
-assign soc_sdram_inti_p3_wrdata_mask = 1'd0;
-assign soc_sdram_bankmachine0_req_valid = soc_sdram_interface_bank0_valid;
-assign soc_sdram_interface_bank0_ready = soc_sdram_bankmachine0_req_ready;
-assign soc_sdram_bankmachine0_req_we = soc_sdram_interface_bank0_we;
-assign soc_sdram_bankmachine0_req_addr = soc_sdram_interface_bank0_addr;
-assign soc_sdram_interface_bank0_lock = soc_sdram_bankmachine0_req_lock;
-assign soc_sdram_interface_bank0_wdata_ready = soc_sdram_bankmachine0_req_wdata_ready;
-assign soc_sdram_interface_bank0_rdata_valid = soc_sdram_bankmachine0_req_rdata_valid;
-assign soc_sdram_bankmachine1_req_valid = soc_sdram_interface_bank1_valid;
-assign soc_sdram_interface_bank1_ready = soc_sdram_bankmachine1_req_ready;
-assign soc_sdram_bankmachine1_req_we = soc_sdram_interface_bank1_we;
-assign soc_sdram_bankmachine1_req_addr = soc_sdram_interface_bank1_addr;
-assign soc_sdram_interface_bank1_lock = soc_sdram_bankmachine1_req_lock;
-assign soc_sdram_interface_bank1_wdata_ready = soc_sdram_bankmachine1_req_wdata_ready;
-assign soc_sdram_interface_bank1_rdata_valid = soc_sdram_bankmachine1_req_rdata_valid;
-assign soc_sdram_bankmachine2_req_valid = soc_sdram_interface_bank2_valid;
-assign soc_sdram_interface_bank2_ready = soc_sdram_bankmachine2_req_ready;
-assign soc_sdram_bankmachine2_req_we = soc_sdram_interface_bank2_we;
-assign soc_sdram_bankmachine2_req_addr = soc_sdram_interface_bank2_addr;
-assign soc_sdram_interface_bank2_lock = soc_sdram_bankmachine2_req_lock;
-assign soc_sdram_interface_bank2_wdata_ready = soc_sdram_bankmachine2_req_wdata_ready;
-assign soc_sdram_interface_bank2_rdata_valid = soc_sdram_bankmachine2_req_rdata_valid;
-assign soc_sdram_bankmachine3_req_valid = soc_sdram_interface_bank3_valid;
-assign soc_sdram_interface_bank3_ready = soc_sdram_bankmachine3_req_ready;
-assign soc_sdram_bankmachine3_req_we = soc_sdram_interface_bank3_we;
-assign soc_sdram_bankmachine3_req_addr = soc_sdram_interface_bank3_addr;
-assign soc_sdram_interface_bank3_lock = soc_sdram_bankmachine3_req_lock;
-assign soc_sdram_interface_bank3_wdata_ready = soc_sdram_bankmachine3_req_wdata_ready;
-assign soc_sdram_interface_bank3_rdata_valid = soc_sdram_bankmachine3_req_rdata_valid;
-assign soc_sdram_bankmachine4_req_valid = soc_sdram_interface_bank4_valid;
-assign soc_sdram_interface_bank4_ready = soc_sdram_bankmachine4_req_ready;
-assign soc_sdram_bankmachine4_req_we = soc_sdram_interface_bank4_we;
-assign soc_sdram_bankmachine4_req_addr = soc_sdram_interface_bank4_addr;
-assign soc_sdram_interface_bank4_lock = soc_sdram_bankmachine4_req_lock;
-assign soc_sdram_interface_bank4_wdata_ready = soc_sdram_bankmachine4_req_wdata_ready;
-assign soc_sdram_interface_bank4_rdata_valid = soc_sdram_bankmachine4_req_rdata_valid;
-assign soc_sdram_bankmachine5_req_valid = soc_sdram_interface_bank5_valid;
-assign soc_sdram_interface_bank5_ready = soc_sdram_bankmachine5_req_ready;
-assign soc_sdram_bankmachine5_req_we = soc_sdram_interface_bank5_we;
-assign soc_sdram_bankmachine5_req_addr = soc_sdram_interface_bank5_addr;
-assign soc_sdram_interface_bank5_lock = soc_sdram_bankmachine5_req_lock;
-assign soc_sdram_interface_bank5_wdata_ready = soc_sdram_bankmachine5_req_wdata_ready;
-assign soc_sdram_interface_bank5_rdata_valid = soc_sdram_bankmachine5_req_rdata_valid;
-assign soc_sdram_bankmachine6_req_valid = soc_sdram_interface_bank6_valid;
-assign soc_sdram_interface_bank6_ready = soc_sdram_bankmachine6_req_ready;
-assign soc_sdram_bankmachine6_req_we = soc_sdram_interface_bank6_we;
-assign soc_sdram_bankmachine6_req_addr = soc_sdram_interface_bank6_addr;
-assign soc_sdram_interface_bank6_lock = soc_sdram_bankmachine6_req_lock;
-assign soc_sdram_interface_bank6_wdata_ready = soc_sdram_bankmachine6_req_wdata_ready;
-assign soc_sdram_interface_bank6_rdata_valid = soc_sdram_bankmachine6_req_rdata_valid;
-assign soc_sdram_bankmachine7_req_valid = soc_sdram_interface_bank7_valid;
-assign soc_sdram_interface_bank7_ready = soc_sdram_bankmachine7_req_ready;
-assign soc_sdram_bankmachine7_req_we = soc_sdram_interface_bank7_we;
-assign soc_sdram_bankmachine7_req_addr = soc_sdram_interface_bank7_addr;
-assign soc_sdram_interface_bank7_lock = soc_sdram_bankmachine7_req_lock;
-assign soc_sdram_interface_bank7_wdata_ready = soc_sdram_bankmachine7_req_wdata_ready;
-assign soc_sdram_interface_bank7_rdata_valid = soc_sdram_bankmachine7_req_rdata_valid;
-assign soc_sdram_timer_wait = (~soc_sdram_timer_done0);
-assign soc_sdram_postponer_req_i = soc_sdram_timer_done0;
-assign soc_sdram_wants_refresh = soc_sdram_postponer_req_o;
-assign soc_sdram_wants_zqcs = soc_sdram_zqcs_timer_done0;
-assign soc_sdram_zqcs_timer_wait = (~soc_sdram_zqcs_executer_done);
-assign soc_sdram_timer_done1 = (soc_sdram_timer_count1 == 1'd0);
-assign soc_sdram_timer_done0 = soc_sdram_timer_done1;
-assign soc_sdram_timer_count0 = soc_sdram_timer_count1;
-assign soc_sdram_sequencer_start1 = (soc_sdram_sequencer_start0 | (soc_sdram_sequencer_count != 1'd0));
-assign soc_sdram_sequencer_done0 = (soc_sdram_sequencer_done1 & (soc_sdram_sequencer_count == 1'd0));
-assign soc_sdram_zqcs_timer_done1 = (soc_sdram_zqcs_timer_count1 == 1'd0);
-assign soc_sdram_zqcs_timer_done0 = soc_sdram_zqcs_timer_done1;
-assign soc_sdram_zqcs_timer_count0 = soc_sdram_zqcs_timer_count1;
-
-// synthesis translate_off
-reg dummy_d_123;
-// synthesis translate_on
-always @(*) begin
-       vns_refresher_next_state <= 2'd0;
-       vns_refresher_next_state <= vns_refresher_state;
-       case (vns_refresher_state)
+       litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if (soc_sdram_cmd_ready) begin
-                               vns_refresher_next_state <= 2'd2;
-                       end
                end
                2'd2: begin
-                       if (soc_sdram_sequencer_done0) begin
-                               if (soc_sdram_wants_zqcs) begin
-                                       vns_refresher_next_state <= 2'd3;
-                               end else begin
-                                       vns_refresher_next_state <= 1'd0;
-                               end
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_zqcs_executer_done) begin
-                               vns_refresher_next_state <= 1'd0;
-                       end
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
                end
                default: begin
-                       if (1'd1) begin
-                               if (soc_sdram_wants_refresh) begin
-                                       vns_refresher_next_state <= 1'd1;
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_123 = dummy_s;
+       dummy_d_119 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_124;
+reg dummy_d_120;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_sequencer_start0 <= 1'd0;
-       case (vns_refresher_state)
+       litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if (soc_sdram_cmd_ready) begin
-                               soc_sdram_sequencer_start0 <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
                end
-               default: begin
+               3'd4: begin
                end
-       endcase
-// synthesis translate_off
-       dummy_d_124 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_125;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_cmd_valid <= 1'd0;
-       case (vns_refresher_state)
-               1'd1: begin
-                       soc_sdram_cmd_valid <= 1'd1;
+               3'd5: begin
                end
-               2'd2: begin
-                       soc_sdram_cmd_valid <= 1'd1;
-                       if (soc_sdram_sequencer_done0) begin
-                               if (soc_sdram_wants_zqcs) begin
-                               end else begin
-                                       soc_sdram_cmd_valid <= 1'd0;
-                               end
-                       end
+               3'd6: begin
                end
-               2'd3: begin
-                       soc_sdram_cmd_valid <= 1'd1;
-                       if (soc_sdram_zqcs_executer_done) begin
-                               soc_sdram_cmd_valid <= 1'd0;
-                       end
+               3'd7: begin
+               end
+               4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_125 = dummy_s;
+       dummy_d_120 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_126;
+reg dummy_d_121;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_zqcs_executer_start <= 1'd0;
-       case (vns_refresher_state)
+       litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
-                       if (soc_sdram_sequencer_done0) begin
-                               if (soc_sdram_wants_zqcs) begin
-                                       soc_sdram_zqcs_executer_start <= 1'd1;
-                               end else begin
-                               end
-                       end
                end
                2'd3: begin
                end
-               default: begin
+               3'd4: begin
                end
-       endcase
-// synthesis translate_off
-       dummy_d_126 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_127;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_cmd_last <= 1'd0;
-       case (vns_refresher_state)
-               1'd1: begin
+               3'd5: begin
                end
-               2'd2: begin
-                       if (soc_sdram_sequencer_done0) begin
-                               if (soc_sdram_wants_zqcs) begin
-                               end else begin
-                                       soc_sdram_cmd_last <= 1'd1;
-                               end
-                       end
+               3'd6: begin
                end
-               2'd3: begin
-                       if (soc_sdram_zqcs_executer_done) begin
-                               soc_sdram_cmd_last <= 1'd1;
-                       end
+               3'd7: begin
+               end
+               4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_127 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine0_req_valid;
-assign soc_sdram_bankmachine0_req_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine0_req_we;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine0_req_addr;
-assign soc_sdram_bankmachine0_cmd_buffer_sink_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine0_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine0_cmd_buffer_sink_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine0_cmd_buffer_sink_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine0_cmd_buffer_source_ready = (soc_sdram_bankmachine0_req_wdata_ready | soc_sdram_bankmachine0_req_rdata_valid);
-assign soc_sdram_bankmachine0_req_lock = (soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine0_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine0_row_hit = (soc_sdram_bankmachine0_row == soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
-assign soc_sdram_bankmachine0_cmd_payload_ba = 1'd0;
-
-// synthesis translate_off
-reg dummy_d_128;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_a <= 15'd0;
-       if (soc_sdram_bankmachine0_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine0_cmd_payload_a <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7];
-       end else begin
-               soc_sdram_bankmachine0_cmd_payload_a <= ((soc_sdram_bankmachine0_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-       end
-// synthesis translate_off
-       dummy_d_128 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine0_twtpcon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_cmd_payload_is_write);
-assign soc_sdram_bankmachine0_trccon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open);
-assign soc_sdram_bankmachine0_trascon_valid = ((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_ready) & soc_sdram_bankmachine0_row_open);
-
-// synthesis translate_off
-reg dummy_d_129;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine0_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine0_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
-                       soc_sdram_bankmachine0_auto_precharge <= (soc_sdram_bankmachine0_row_close == 1'd0);
-               end
-       end
-// synthesis translate_off
-       dummy_d_129 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_sdram_bankmachine0_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_130;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine0_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
-       end else begin
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine0_cmd_buffer_lookahead_produce;
-       end
-// synthesis translate_off
-       dummy_d_130 = dummy_s;
+       dummy_d_121 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_sdram_bankmachine0_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine0_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_sdram_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine0_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_131;
+reg dummy_d_122;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine0_next_state <= 4'd0;
-       vns_bankmachine0_next_state <= vns_bankmachine0_state;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               if (soc_sdram_bankmachine0_cmd_ready) begin
-                                       vns_bankmachine0_next_state <= 3'd5;
-                               end
-                       end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               vns_bankmachine0_next_state <= 3'd5;
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               if (soc_sdram_bankmachine0_cmd_ready) begin
-                                       vns_bankmachine0_next_state <= 3'd7;
-                               end
-                       end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine0_refresh_req)) begin
-                               vns_bankmachine0_next_state <= 1'd0;
+                       if (litedramcore_bankmachine0_twtpcon_ready) begin
+                               litedramcore_bankmachine0_refresh_gnt <= 1'd1;
                        end
                end
                3'd5: begin
-                       vns_bankmachine0_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine0_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine0_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine0_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
-                               vns_bankmachine0_next_state <= 3'd4;
-                       end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if ((soc_sdram_bankmachine0_cmd_ready & soc_sdram_bankmachine0_auto_precharge)) begin
-                                                               vns_bankmachine0_next_state <= 2'd2;
-                                                       end
-                                               end else begin
-                                                       vns_bankmachine0_next_state <= 1'd1;
-                                               end
-                                       end else begin
-                                               vns_bankmachine0_next_state <= 2'd3;
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_131 = dummy_s;
+       dummy_d_122 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_132;
+reg dummy_d_123;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_valid <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               soc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -5452,15 +4754,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine0_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       litedramcore_bankmachine0_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -5470,23 +4769,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_132 = dummy_s;
+       dummy_d_123 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_133;
+reg dummy_d_124;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_row_open <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               soc_sdram_bankmachine0_row_col_n_addr_sel <= 1'd1;
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_row_open <= 1'd1;
                        end
                end
                3'd4: begin
@@ -5503,30 +4802,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_133 = dummy_s;
+       dummy_d_124 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_134;
+reg dummy_d_125;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_row_close <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-                       end
+                       litedramcore_bankmachine0_row_close <= 1'd1;
                end
                2'd2: begin
+                       litedramcore_bankmachine0_row_close <= 1'd1;
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+                       litedramcore_bankmachine0_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -5540,16 +4835,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_134 = dummy_s;
+       dummy_d_125 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_135;
+reg dummy_d_126;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
@@ -5567,15 +4862,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine0_cmd_payload_is_read <= 1'd1;
-                                                       end
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -5585,21 +4877,24 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_135 = dummy_s;
+       dummy_d_126 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_136;
+reg dummy_d_127;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -5612,39 +4907,30 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine0_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_136 = dummy_s;
+       dummy_d_127 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_137;
+reg dummy_d_128;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -5657,35 +4943,23 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine0_req_wdata_ready <= soc_sdram_bankmachine0_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_137 = dummy_s;
+       dummy_d_128 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_138;
+reg dummy_d_129;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
@@ -5702,14 +4976,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       if (soc_sdram_bankmachine0_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
                                                        end else begin
-                                                               soc_sdram_bankmachine0_req_rdata_valid <= soc_sdram_bankmachine0_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -5720,26 +4994,30 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_138 = dummy_s;
+       dummy_d_129 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_139;
+reg dummy_d_130;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_refresh_gnt <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+                               litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine0_trccon_ready) begin
+                               litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine0_twtpcon_ready) begin
-                               soc_sdram_bankmachine0_refresh_gnt <= 1'd1;
-                       end
+                       litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -5753,27 +5031,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_139 = dummy_s;
+       dummy_d_130 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_140;
+reg dummy_d_131;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_valid <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+       case (bankmachine0_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               soc_sdram_bankmachine0_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               soc_sdram_bankmachine0_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -5786,12 +5058,15 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
+                       if (litedramcore_bankmachine0_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       soc_sdram_bankmachine0_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine0_row_opened) begin
+                                               if (litedramcore_bankmachine0_row_hit) begin
+                                                       if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -5801,135 +5076,176 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_140 = dummy_s;
+       dummy_d_131 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
 
 // synthesis translate_off
-reg dummy_d_141;
+reg dummy_d_132;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_row_open <= 1'd0;
-       case (vns_bankmachine0_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               soc_sdram_bankmachine0_row_open <= 1'd1;
-                       end
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               default: begin
-               end
-       endcase
+       litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+       if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+               litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+       end else begin
+               litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+       end
 // synthesis translate_off
-       dummy_d_141 = dummy_s;
+       dummy_d_132 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
+assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
+assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
 
 // synthesis translate_off
-reg dummy_d_142;
+reg dummy_d_133;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_row_close <= 1'd0;
-       case (vns_bankmachine0_state)
-               1'd1: begin
-                       soc_sdram_bankmachine0_row_close <= 1'd1;
-               end
-               2'd2: begin
-                       soc_sdram_bankmachine0_row_close <= 1'd1;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-                       soc_sdram_bankmachine0_row_close <= 1'd1;
+       litedramcore_bankmachine1_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
+                       litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
                end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               default: begin
-               end
-       endcase
+       end
 // synthesis translate_off
-       dummy_d_142 = dummy_s;
+       dummy_d_133 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
 
 // synthesis translate_off
-reg dummy_d_143;
+reg dummy_d_134;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
+       end else begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
+       end
+// synthesis translate_off
+       dummy_d_134 = dummy_s;
+// synthesis translate_on
+end
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
+
+// synthesis translate_off
+reg dummy_d_135;
+// synthesis translate_on
+always @(*) begin
+       bankmachine1_next_state <= 4'd0;
+       bankmachine1_next_state <= bankmachine1_state;
+       case (bankmachine1_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               if (litedramcore_bankmachine1_cmd_ready) begin
+                                       bankmachine1_next_state <= 3'd5;
+                               end
+                       end
                end
                2'd2: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               bankmachine1_next_state <= 3'd5;
+                       end
                end
                2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               if (litedramcore_bankmachine1_cmd_ready) begin
+                                       bankmachine1_next_state <= 3'd7;
+                               end
+                       end
                end
                3'd4: begin
+                       if ((~litedramcore_bankmachine1_refresh_req)) begin
+                               bankmachine1_next_state <= 1'd0;
+                       end
                end
                3'd5: begin
+                       bankmachine1_next_state <= 3'd6;
                end
                3'd6: begin
+                       bankmachine1_next_state <= 2'd3;
                end
                3'd7: begin
+                       bankmachine1_next_state <= 4'd8;
                end
                4'd8: begin
+                       bankmachine1_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine0_refresh_req) begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                               bankmachine1_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine0_row_opened) begin
-                                               if (soc_sdram_bankmachine0_row_hit) begin
-                                                       soc_sdram_bankmachine0_cmd_payload_cas <= 1'd1;
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+                                                               bankmachine1_next_state <= 2'd2;
+                                                       end
                                                end else begin
+                                                       bankmachine1_next_state <= 1'd1;
                                                end
                                        end else begin
+                                               bankmachine1_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_143 = dummy_s;
+       dummy_d_135 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_144;
+reg dummy_d_136;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine0_state)
+       litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine0_twtpcon_ready & soc_sdram_bankmachine0_trascon_ready)) begin
-                               soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine0_trccon_ready) begin
-                               soc_sdram_bankmachine0_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -5942,182 +5258,87 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_144 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine1_req_valid;
-assign soc_sdram_bankmachine1_req_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine1_req_we;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine1_req_addr;
-assign soc_sdram_bankmachine1_cmd_buffer_sink_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine1_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine1_cmd_buffer_sink_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine1_cmd_buffer_sink_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine1_cmd_buffer_source_ready = (soc_sdram_bankmachine1_req_wdata_ready | soc_sdram_bankmachine1_req_rdata_valid);
-assign soc_sdram_bankmachine1_req_lock = (soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine1_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine1_row_hit = (soc_sdram_bankmachine1_row == soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
-assign soc_sdram_bankmachine1_cmd_payload_ba = 1'd1;
-
-// synthesis translate_off
-reg dummy_d_145;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_a <= 15'd0;
-       if (soc_sdram_bankmachine1_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine1_cmd_payload_a <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7];
-       end else begin
-               soc_sdram_bankmachine1_cmd_payload_a <= ((soc_sdram_bankmachine1_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
-       end
-// synthesis translate_off
-       dummy_d_145 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine1_twtpcon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_cmd_payload_is_write);
-assign soc_sdram_bankmachine1_trccon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open);
-assign soc_sdram_bankmachine1_trascon_valid = ((soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_ready) & soc_sdram_bankmachine1_row_open);
-
-// synthesis translate_off
-reg dummy_d_146;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine1_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine1_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
-                       soc_sdram_bankmachine1_auto_precharge <= (soc_sdram_bankmachine1_row_close == 1'd0);
-               end
-       end
-// synthesis translate_off
-       dummy_d_146 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_sdram_bankmachine1_cmd_buffer_lookahead_source_ready;
-
-// synthesis translate_off
-reg dummy_d_147;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine1_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
-       end else begin
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine1_cmd_buffer_lookahead_produce;
-       end
-// synthesis translate_off
-       dummy_d_147 = dummy_s;
+       dummy_d_136 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_sdram_bankmachine1_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine1_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_sdram_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine1_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_148;
+reg dummy_d_137;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine1_next_state <= 4'd0;
-       vns_bankmachine1_next_state <= vns_bankmachine1_state;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               if (soc_sdram_bankmachine1_cmd_ready) begin
-                                       vns_bankmachine1_next_state <= 3'd5;
-                               end
-                       end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               vns_bankmachine1_next_state <= 3'd5;
-                       end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               if (soc_sdram_bankmachine1_cmd_ready) begin
-                                       vns_bankmachine1_next_state <= 3'd7;
-                               end
-                       end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine1_refresh_req)) begin
-                               vns_bankmachine1_next_state <= 1'd0;
-                       end
                end
                3'd5: begin
-                       vns_bankmachine1_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine1_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine1_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine1_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
-                               vns_bankmachine1_next_state <= 3'd4;
+                       if (litedramcore_bankmachine1_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if ((soc_sdram_bankmachine1_cmd_ready & soc_sdram_bankmachine1_auto_precharge)) begin
-                                                               vns_bankmachine1_next_state <= 2'd2;
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+                                                       end else begin
                                                        end
                                                end else begin
-                                                       vns_bankmachine1_next_state <= 1'd1;
                                                end
                                        end else begin
-                                               vns_bankmachine1_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_148 = dummy_s;
+       dummy_d_137 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_149;
+reg dummy_d_138;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               soc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -6130,42 +5351,24 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine1_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_149 = dummy_s;
+       dummy_d_138 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_150;
+reg dummy_d_139;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               soc_sdram_bankmachine1_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -6178,33 +5381,44 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_150 = dummy_s;
+       dummy_d_139 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_151;
+reg dummy_d_140;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+                       if (litedramcore_bankmachine1_twtpcon_ready) begin
+                               litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -6218,21 +5432,27 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_151 = dummy_s;
+       dummy_d_140 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_152;
+reg dummy_d_141;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_valid <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -6245,15 +5465,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine1_cmd_payload_is_read <= 1'd1;
-                                                       end
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       litedramcore_bankmachine1_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -6263,21 +5480,24 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_152 = dummy_s;
+       dummy_d_141 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_153;
+reg dummy_d_142;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_row_open <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_row_open <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -6290,41 +5510,29 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine1_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_153 = dummy_s;
+       dummy_d_142 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_154;
+reg dummy_d_143;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_row_close <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
+                       litedramcore_bankmachine1_row_close <= 1'd1;
                end
                2'd2: begin
+                       litedramcore_bankmachine1_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       litedramcore_bankmachine1_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -6335,34 +5543,19 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine1_req_wdata_ready <= soc_sdram_bankmachine1_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_154 = dummy_s;
+       dummy_d_143 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_155;
+reg dummy_d_144;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
                end
                2'd2: begin
@@ -6380,15 +5573,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       if (soc_sdram_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine1_req_rdata_valid <= soc_sdram_bankmachine1_cmd_ready;
-                                                       end
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -6398,26 +5588,29 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_155 = dummy_s;
+       dummy_d_144 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_156;
+reg dummy_d_145;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_refresh_gnt <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine1_twtpcon_ready) begin
-                               soc_sdram_bankmachine1_refresh_gnt <= 1'd1;
-                       end
                end
                3'd5: begin
                end
@@ -6431,27 +5624,24 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_156 = dummy_s;
+       dummy_d_145 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_157;
+reg dummy_d_146;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_valid <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               soc_sdram_bankmachine1_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -6464,12 +5654,15 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       soc_sdram_bankmachine1_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+                                                       end else begin
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -6479,26 +5672,30 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_157 = dummy_s;
+       dummy_d_146 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_158;
+reg dummy_d_147;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_row_open <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+                               litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               soc_sdram_bankmachine1_row_open <= 1'd1;
+                       if (litedramcore_bankmachine1_trccon_ready) begin
+                               litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -6512,26 +5709,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_158 = dummy_s;
+       dummy_d_147 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_159;
+reg dummy_d_148;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_row_close <= 1'd0;
-       case (vns_bankmachine1_state)
+       litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+       case (bankmachine1_state)
                1'd1: begin
-                       soc_sdram_bankmachine1_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_sdram_bankmachine1_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine1_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -6542,256 +5736,190 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine1_row_opened) begin
+                                               if (litedramcore_bankmachine1_row_hit) begin
+                                                       if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_159 = dummy_s;
+       dummy_d_148 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
 
 // synthesis translate_off
-reg dummy_d_160;
+reg dummy_d_149;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine1_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               default: begin
-                       if (soc_sdram_bankmachine1_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine1_row_opened) begin
-                                               if (soc_sdram_bankmachine1_row_hit) begin
-                                                       soc_sdram_bankmachine1_cmd_payload_cas <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_160 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_161;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine1_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine1_state)
-               1'd1: begin
-                       if ((soc_sdram_bankmachine1_twtpcon_ready & soc_sdram_bankmachine1_trascon_ready)) begin
-                               soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       if (soc_sdram_bankmachine1_trccon_ready) begin
-                               soc_sdram_bankmachine1_cmd_payload_ras <= 1'd1;
-                       end
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_161 = dummy_s;
-// synthesis translate_on
-end
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine2_req_valid;
-assign soc_sdram_bankmachine2_req_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine2_req_we;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine2_req_addr;
-assign soc_sdram_bankmachine2_cmd_buffer_sink_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine2_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine2_cmd_buffer_sink_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine2_cmd_buffer_sink_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine2_cmd_buffer_source_ready = (soc_sdram_bankmachine2_req_wdata_ready | soc_sdram_bankmachine2_req_rdata_valid);
-assign soc_sdram_bankmachine2_req_lock = (soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine2_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine2_row_hit = (soc_sdram_bankmachine2_row == soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
-assign soc_sdram_bankmachine2_cmd_payload_ba = 2'd2;
-
-// synthesis translate_off
-reg dummy_d_162;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_a <= 15'd0;
-       if (soc_sdram_bankmachine2_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine2_cmd_payload_a <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+       litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
+       if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+               litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
        end else begin
-               soc_sdram_bankmachine2_cmd_payload_a <= ((soc_sdram_bankmachine2_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+               litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
        end
 // synthesis translate_off
-       dummy_d_162 = dummy_s;
+       dummy_d_149 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine2_twtpcon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_cmd_payload_is_write);
-assign soc_sdram_bankmachine2_trccon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open);
-assign soc_sdram_bankmachine2_trascon_valid = ((soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_ready) & soc_sdram_bankmachine2_row_open);
+assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
+assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
+assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
 
 // synthesis translate_off
-reg dummy_d_163;
+reg dummy_d_150;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine2_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
-                       soc_sdram_bankmachine2_auto_precharge <= (soc_sdram_bankmachine2_row_close == 1'd0);
+       litedramcore_bankmachine2_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
+                       litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
                end
        end
 // synthesis translate_off
-       dummy_d_163 = dummy_s;
+       dummy_d_150 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_sdram_bankmachine2_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
 
 // synthesis translate_off
-reg dummy_d_164;
+reg dummy_d_151;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine2_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
+       litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
        end else begin
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine2_cmd_buffer_lookahead_produce;
+               litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
        end
 // synthesis translate_off
-       dummy_d_164 = dummy_s;
+       dummy_d_151 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_sdram_bankmachine2_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine2_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_sdram_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine2_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_165;
+reg dummy_d_152;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine2_next_state <= 4'd0;
-       vns_bankmachine2_next_state <= vns_bankmachine2_state;
-       case (vns_bankmachine2_state)
+       bankmachine2_next_state <= 4'd0;
+       bankmachine2_next_state <= bankmachine2_state;
+       case (bankmachine2_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               if (soc_sdram_bankmachine2_cmd_ready) begin
-                                       vns_bankmachine2_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               if (litedramcore_bankmachine2_cmd_ready) begin
+                                       bankmachine2_next_state <= 3'd5;
                                end
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               vns_bankmachine2_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               bankmachine2_next_state <= 3'd5;
                        end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               if (soc_sdram_bankmachine2_cmd_ready) begin
-                                       vns_bankmachine2_next_state <= 3'd7;
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               if (litedramcore_bankmachine2_cmd_ready) begin
+                                       bankmachine2_next_state <= 3'd7;
                                end
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine2_refresh_req)) begin
-                               vns_bankmachine2_next_state <= 1'd0;
+                       if ((~litedramcore_bankmachine2_refresh_req)) begin
+                               bankmachine2_next_state <= 1'd0;
                        end
                end
                3'd5: begin
-                       vns_bankmachine2_next_state <= 3'd6;
+                       bankmachine2_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine2_next_state <= 2'd3;
+                       bankmachine2_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine2_next_state <= 4'd8;
+                       bankmachine2_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine2_next_state <= 1'd0;
+                       bankmachine2_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
-                               vns_bankmachine2_next_state <= 3'd4;
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                               bankmachine2_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if ((soc_sdram_bankmachine2_cmd_ready & soc_sdram_bankmachine2_auto_precharge)) begin
-                                                               vns_bankmachine2_next_state <= 2'd2;
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+                                                               bankmachine2_next_state <= 2'd2;
                                                        end
                                                end else begin
-                                                       vns_bankmachine2_next_state <= 1'd1;
+                                                       bankmachine2_next_state <= 1'd1;
                                                end
                                        end else begin
-                                               vns_bankmachine2_next_state <= 2'd3;
+                                               bankmachine2_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_165 = dummy_s;
+       dummy_d_152 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_166;
+reg dummy_d_153;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               soc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
-                       end
                end
                2'd2: begin
                end
@@ -6808,13 +5936,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine2_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -6826,24 +5954,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_166 = dummy_s;
+       dummy_d_153 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_167;
+reg dummy_d_154;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               soc_sdram_bankmachine2_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -6856,33 +5981,41 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_167 = dummy_s;
+       dummy_d_154 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_168;
+reg dummy_d_155;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine2_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -6893,19 +6026,34 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_168 = dummy_s;
+       dummy_d_155 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_169;
+reg dummy_d_156;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
@@ -6913,6 +6061,9 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
+                       if (litedramcore_bankmachine2_twtpcon_ready) begin
+                               litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -6923,39 +6074,30 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine2_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_169 = dummy_s;
+       dummy_d_156 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_170;
+reg dummy_d_157;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_valid <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -6968,15 +6110,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine2_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       litedramcore_bankmachine2_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -6986,21 +6125,24 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_170 = dummy_s;
+       dummy_d_157 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_171;
+reg dummy_d_158;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -7013,39 +6155,27 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine2_req_wdata_ready <= soc_sdram_bankmachine2_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_171 = dummy_s;
+       dummy_d_158 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_172;
+reg dummy_d_159;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_row_open <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_row_open <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -7058,44 +6188,29 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       if (soc_sdram_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine2_req_rdata_valid <= soc_sdram_bankmachine2_cmd_ready;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_172 = dummy_s;
+       dummy_d_159 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_173;
+reg dummy_d_160;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_refresh_gnt <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_row_close <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
+                       litedramcore_bankmachine2_row_close <= 1'd1;
                end
                2'd2: begin
+                       litedramcore_bankmachine2_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine2_twtpcon_ready) begin
-                               soc_sdram_bankmachine2_refresh_gnt <= 1'd1;
-                       end
+                       litedramcore_bankmachine2_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -7109,27 +6224,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_173 = dummy_s;
+       dummy_d_160 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_174;
+reg dummy_d_161;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_valid <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               soc_sdram_bankmachine2_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               soc_sdram_bankmachine2_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -7142,12 +6251,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       soc_sdram_bankmachine2_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -7157,23 +6266,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_174 = dummy_s;
+       dummy_d_161 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_175;
+reg dummy_d_162;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_row_open <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               soc_sdram_bankmachine2_row_open <= 1'd1;
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
@@ -7190,26 +6302,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_175 = dummy_s;
+       dummy_d_162 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_176;
+reg dummy_d_163;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_row_close <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       soc_sdram_bankmachine2_row_close <= 1'd1;
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
-                       soc_sdram_bankmachine2_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine2_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -7220,26 +6332,48 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_176 = dummy_s;
+       dummy_d_163 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_177;
+reg dummy_d_164;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+                               litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine2_trccon_ready) begin
+                               litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                3'd4: begin
+                       litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -7250,42 +6384,24 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine2_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine2_row_opened) begin
-                                               if (soc_sdram_bankmachine2_row_hit) begin
-                                                       soc_sdram_bankmachine2_cmd_payload_cas <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_177 = dummy_s;
+       dummy_d_164 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_178;
+reg dummy_d_165;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine2_state)
+       litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+       case (bankmachine2_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine2_twtpcon_ready & soc_sdram_bankmachine2_trascon_ready)) begin
-                               soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine2_trccon_ready) begin
-                               soc_sdram_bankmachine2_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -7298,178 +6414,190 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine2_row_opened) begin
+                                               if (litedramcore_bankmachine2_row_hit) begin
+                                                       if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_178 = dummy_s;
+       dummy_d_165 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine3_req_valid;
-assign soc_sdram_bankmachine3_req_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine3_req_we;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine3_req_addr;
-assign soc_sdram_bankmachine3_cmd_buffer_sink_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine3_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine3_cmd_buffer_sink_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine3_cmd_buffer_sink_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine3_cmd_buffer_source_ready = (soc_sdram_bankmachine3_req_wdata_ready | soc_sdram_bankmachine3_req_rdata_valid);
-assign soc_sdram_bankmachine3_req_lock = (soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine3_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine3_row_hit = (soc_sdram_bankmachine3_row == soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
-assign soc_sdram_bankmachine3_cmd_payload_ba = 2'd3;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
 
 // synthesis translate_off
-reg dummy_d_179;
+reg dummy_d_166;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_a <= 15'd0;
-       if (soc_sdram_bankmachine3_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine3_cmd_payload_a <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+       litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
+       if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+               litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
        end else begin
-               soc_sdram_bankmachine3_cmd_payload_a <= ((soc_sdram_bankmachine3_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+               litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
        end
 // synthesis translate_off
-       dummy_d_179 = dummy_s;
+       dummy_d_166 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine3_twtpcon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_cmd_payload_is_write);
-assign soc_sdram_bankmachine3_trccon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open);
-assign soc_sdram_bankmachine3_trascon_valid = ((soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_ready) & soc_sdram_bankmachine3_row_open);
+assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
+assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
+assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
 
 // synthesis translate_off
-reg dummy_d_180;
+reg dummy_d_167;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine3_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
-                       soc_sdram_bankmachine3_auto_precharge <= (soc_sdram_bankmachine3_row_close == 1'd0);
+       litedramcore_bankmachine3_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
+                       litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
                end
        end
 // synthesis translate_off
-       dummy_d_180 = dummy_s;
+       dummy_d_167 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_sdram_bankmachine3_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
 
 // synthesis translate_off
-reg dummy_d_181;
+reg dummy_d_168;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine3_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
+       litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
        end else begin
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine3_cmd_buffer_lookahead_produce;
+               litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
        end
 // synthesis translate_off
-       dummy_d_181 = dummy_s;
+       dummy_d_168 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_sdram_bankmachine3_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine3_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_sdram_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine3_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_182;
+reg dummy_d_169;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine3_next_state <= 4'd0;
-       vns_bankmachine3_next_state <= vns_bankmachine3_state;
-       case (vns_bankmachine3_state)
+       bankmachine3_next_state <= 4'd0;
+       bankmachine3_next_state <= bankmachine3_state;
+       case (bankmachine3_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               if (soc_sdram_bankmachine3_cmd_ready) begin
-                                       vns_bankmachine3_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               if (litedramcore_bankmachine3_cmd_ready) begin
+                                       bankmachine3_next_state <= 3'd5;
                                end
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               vns_bankmachine3_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               bankmachine3_next_state <= 3'd5;
                        end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               if (soc_sdram_bankmachine3_cmd_ready) begin
-                                       vns_bankmachine3_next_state <= 3'd7;
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               if (litedramcore_bankmachine3_cmd_ready) begin
+                                       bankmachine3_next_state <= 3'd7;
                                end
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine3_refresh_req)) begin
-                               vns_bankmachine3_next_state <= 1'd0;
+                       if ((~litedramcore_bankmachine3_refresh_req)) begin
+                               bankmachine3_next_state <= 1'd0;
                        end
                end
                3'd5: begin
-                       vns_bankmachine3_next_state <= 3'd6;
+                       bankmachine3_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine3_next_state <= 2'd3;
+                       bankmachine3_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine3_next_state <= 4'd8;
+                       bankmachine3_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine3_next_state <= 1'd0;
+                       bankmachine3_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
-                               vns_bankmachine3_next_state <= 3'd4;
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                               bankmachine3_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if ((soc_sdram_bankmachine3_cmd_ready & soc_sdram_bankmachine3_auto_precharge)) begin
-                                                               vns_bankmachine3_next_state <= 2'd2;
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+                                                               bankmachine3_next_state <= 2'd2;
                                                        end
                                                end else begin
-                                                       vns_bankmachine3_next_state <= 1'd1;
+                                                       bankmachine3_next_state <= 1'd1;
                                                end
                                        end else begin
-                                               vns_bankmachine3_next_state <= 2'd3;
+                                               bankmachine3_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_182 = dummy_s;
+       dummy_d_169 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_183;
+reg dummy_d_170;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               soc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
-                       end
                end
                2'd2: begin
                end
@@ -7486,13 +6614,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine3_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -7504,24 +6632,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_183 = dummy_s;
+       dummy_d_170 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_184;
+reg dummy_d_171;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               soc_sdram_bankmachine3_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -7534,33 +6659,41 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_184 = dummy_s;
+       dummy_d_171 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_185;
+reg dummy_d_172;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine3_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -7571,19 +6704,34 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_185 = dummy_s;
+       dummy_d_172 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_186;
+reg dummy_d_173;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
@@ -7591,6 +6739,9 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
+                       if (litedramcore_bankmachine3_twtpcon_ready) begin
+                               litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -7601,39 +6752,30 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine3_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_186 = dummy_s;
+       dummy_d_173 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_187;
+reg dummy_d_174;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_valid <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -7646,15 +6788,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine3_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       litedramcore_bankmachine3_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -7664,21 +6803,24 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_187 = dummy_s;
+       dummy_d_174 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_188;
+reg dummy_d_175;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_row_open <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_row_open <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -7691,41 +6833,29 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine3_req_wdata_ready <= soc_sdram_bankmachine3_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_188 = dummy_s;
+       dummy_d_175 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_189;
+reg dummy_d_176;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_row_close <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
+                       litedramcore_bankmachine3_row_close <= 1'd1;
                end
                2'd2: begin
+                       litedramcore_bankmachine3_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       litedramcore_bankmachine3_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -7736,44 +6866,29 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       if (soc_sdram_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine3_req_rdata_valid <= soc_sdram_bankmachine3_cmd_ready;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_189 = dummy_s;
+       dummy_d_176 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_190;
+reg dummy_d_177;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_refresh_gnt <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine3_twtpcon_ready) begin
-                               soc_sdram_bankmachine3_refresh_gnt <= 1'd1;
-                       end
                end
                3'd5: begin
                end
@@ -7787,27 +6902,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_190 = dummy_s;
+       dummy_d_177 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_191;
+reg dummy_d_178;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_valid <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               soc_sdram_bankmachine3_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               soc_sdram_bankmachine3_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -7820,12 +6929,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       soc_sdram_bankmachine3_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -7835,23 +6944,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_191 = dummy_s;
+       dummy_d_178 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_192;
+reg dummy_d_179;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_row_open <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               soc_sdram_bankmachine3_row_open <= 1'd1;
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
@@ -7868,26 +6980,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_192 = dummy_s;
+       dummy_d_179 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_193;
+reg dummy_d_180;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_row_close <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       soc_sdram_bankmachine3_row_close <= 1'd1;
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
-                       soc_sdram_bankmachine3_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine3_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -7898,26 +7010,48 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_193 = dummy_s;
+       dummy_d_180 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_194;
+reg dummy_d_181;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+                               litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine3_trccon_ready) begin
+                               litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                3'd4: begin
+                       litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -7928,42 +7062,24 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine3_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine3_row_opened) begin
-                                               if (soc_sdram_bankmachine3_row_hit) begin
-                                                       soc_sdram_bankmachine3_cmd_payload_cas <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_194 = dummy_s;
+       dummy_d_181 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_195;
+reg dummy_d_182;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine3_state)
+       litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+       case (bankmachine3_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine3_twtpcon_ready & soc_sdram_bankmachine3_trascon_ready)) begin
-                               soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine3_trccon_ready) begin
-                               soc_sdram_bankmachine3_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -7976,178 +7092,190 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine3_row_opened) begin
+                                               if (litedramcore_bankmachine3_row_hit) begin
+                                                       if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_195 = dummy_s;
+       dummy_d_182 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine4_req_valid;
-assign soc_sdram_bankmachine4_req_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine4_req_we;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine4_req_addr;
-assign soc_sdram_bankmachine4_cmd_buffer_sink_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine4_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine4_cmd_buffer_sink_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine4_cmd_buffer_sink_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine4_cmd_buffer_source_ready = (soc_sdram_bankmachine4_req_wdata_ready | soc_sdram_bankmachine4_req_rdata_valid);
-assign soc_sdram_bankmachine4_req_lock = (soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine4_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine4_row_hit = (soc_sdram_bankmachine4_row == soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
-assign soc_sdram_bankmachine4_cmd_payload_ba = 3'd4;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
 
 // synthesis translate_off
-reg dummy_d_196;
+reg dummy_d_183;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_a <= 15'd0;
-       if (soc_sdram_bankmachine4_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine4_cmd_payload_a <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+       litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
+       if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+               litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
        end else begin
-               soc_sdram_bankmachine4_cmd_payload_a <= ((soc_sdram_bankmachine4_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+               litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
        end
 // synthesis translate_off
-       dummy_d_196 = dummy_s;
+       dummy_d_183 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine4_twtpcon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_cmd_payload_is_write);
-assign soc_sdram_bankmachine4_trccon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open);
-assign soc_sdram_bankmachine4_trascon_valid = ((soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_ready) & soc_sdram_bankmachine4_row_open);
+assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
+assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
+assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
 
 // synthesis translate_off
-reg dummy_d_197;
+reg dummy_d_184;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine4_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
-                       soc_sdram_bankmachine4_auto_precharge <= (soc_sdram_bankmachine4_row_close == 1'd0);
+       litedramcore_bankmachine4_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
+                       litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
                end
        end
 // synthesis translate_off
-       dummy_d_197 = dummy_s;
+       dummy_d_184 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_sdram_bankmachine4_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
 
 // synthesis translate_off
-reg dummy_d_198;
+reg dummy_d_185;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine4_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
+       litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
        end else begin
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine4_cmd_buffer_lookahead_produce;
+               litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
        end
 // synthesis translate_off
-       dummy_d_198 = dummy_s;
+       dummy_d_185 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_sdram_bankmachine4_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine4_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_sdram_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine4_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_199;
+reg dummy_d_186;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine4_next_state <= 4'd0;
-       vns_bankmachine4_next_state <= vns_bankmachine4_state;
-       case (vns_bankmachine4_state)
+       bankmachine4_next_state <= 4'd0;
+       bankmachine4_next_state <= bankmachine4_state;
+       case (bankmachine4_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               if (soc_sdram_bankmachine4_cmd_ready) begin
-                                       vns_bankmachine4_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               if (litedramcore_bankmachine4_cmd_ready) begin
+                                       bankmachine4_next_state <= 3'd5;
                                end
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               vns_bankmachine4_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               bankmachine4_next_state <= 3'd5;
                        end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               if (soc_sdram_bankmachine4_cmd_ready) begin
-                                       vns_bankmachine4_next_state <= 3'd7;
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               if (litedramcore_bankmachine4_cmd_ready) begin
+                                       bankmachine4_next_state <= 3'd7;
                                end
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine4_refresh_req)) begin
-                               vns_bankmachine4_next_state <= 1'd0;
+                       if ((~litedramcore_bankmachine4_refresh_req)) begin
+                               bankmachine4_next_state <= 1'd0;
                        end
                end
                3'd5: begin
-                       vns_bankmachine4_next_state <= 3'd6;
+                       bankmachine4_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine4_next_state <= 2'd3;
+                       bankmachine4_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine4_next_state <= 4'd8;
+                       bankmachine4_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine4_next_state <= 1'd0;
+                       bankmachine4_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
-                               vns_bankmachine4_next_state <= 3'd4;
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                               bankmachine4_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if ((soc_sdram_bankmachine4_cmd_ready & soc_sdram_bankmachine4_auto_precharge)) begin
-                                                               vns_bankmachine4_next_state <= 2'd2;
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+                                                               bankmachine4_next_state <= 2'd2;
                                                        end
                                                end else begin
-                                                       vns_bankmachine4_next_state <= 1'd1;
+                                                       bankmachine4_next_state <= 1'd1;
                                                end
                                        end else begin
-                                               vns_bankmachine4_next_state <= 2'd3;
+                                               bankmachine4_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_199 = dummy_s;
+       dummy_d_186 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_200;
+reg dummy_d_187;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               soc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
-                       end
                end
                2'd2: begin
                end
@@ -8164,13 +7292,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine4_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -8182,24 +7310,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_200 = dummy_s;
+       dummy_d_187 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_201;
+reg dummy_d_188;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               soc_sdram_bankmachine4_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -8212,33 +7337,41 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_201 = dummy_s;
+       dummy_d_188 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_202;
+reg dummy_d_189;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine4_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -8249,19 +7382,34 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_202 = dummy_s;
+       dummy_d_189 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_203;
+reg dummy_d_190;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
@@ -8269,6 +7417,9 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
+                       if (litedramcore_bankmachine4_twtpcon_ready) begin
+                               litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -8279,39 +7430,30 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine4_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_203 = dummy_s;
+       dummy_d_190 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_204;
+reg dummy_d_191;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_valid <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -8324,15 +7466,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine4_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       litedramcore_bankmachine4_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -8342,21 +7481,24 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_204 = dummy_s;
+       dummy_d_191 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_205;
+reg dummy_d_192;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -8369,39 +7511,27 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine4_req_wdata_ready <= soc_sdram_bankmachine4_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_205 = dummy_s;
+       dummy_d_192 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_206;
+reg dummy_d_193;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_row_open <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_row_open <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -8414,44 +7544,29 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       if (soc_sdram_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine4_req_rdata_valid <= soc_sdram_bankmachine4_cmd_ready;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_206 = dummy_s;
+       dummy_d_193 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_207;
+reg dummy_d_194;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_refresh_gnt <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_row_close <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
+                       litedramcore_bankmachine4_row_close <= 1'd1;
                end
                2'd2: begin
+                       litedramcore_bankmachine4_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine4_twtpcon_ready) begin
-                               soc_sdram_bankmachine4_refresh_gnt <= 1'd1;
-                       end
+                       litedramcore_bankmachine4_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -8465,27 +7580,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_207 = dummy_s;
+       dummy_d_194 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_208;
+reg dummy_d_195;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_valid <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               soc_sdram_bankmachine4_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               soc_sdram_bankmachine4_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -8498,12 +7607,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       soc_sdram_bankmachine4_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -8513,23 +7622,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_208 = dummy_s;
+       dummy_d_195 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_209;
+reg dummy_d_196;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_row_open <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               soc_sdram_bankmachine4_row_open <= 1'd1;
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
@@ -8546,26 +7658,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_209 = dummy_s;
+       dummy_d_196 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_210;
+reg dummy_d_197;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_row_close <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       soc_sdram_bankmachine4_row_close <= 1'd1;
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
-                       soc_sdram_bankmachine4_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine4_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -8576,26 +7688,48 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_210 = dummy_s;
+       dummy_d_197 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_211;
+reg dummy_d_198;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+                               litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine4_trccon_ready) begin
+                               litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                3'd4: begin
+                       litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -8606,42 +7740,24 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine4_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine4_row_opened) begin
-                                               if (soc_sdram_bankmachine4_row_hit) begin
-                                                       soc_sdram_bankmachine4_cmd_payload_cas <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_211 = dummy_s;
+       dummy_d_198 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_212;
+reg dummy_d_199;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine4_state)
+       litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+       case (bankmachine4_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine4_twtpcon_ready & soc_sdram_bankmachine4_trascon_ready)) begin
-                               soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine4_trccon_ready) begin
-                               soc_sdram_bankmachine4_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -8654,178 +7770,190 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine4_row_opened) begin
+                                               if (litedramcore_bankmachine4_row_hit) begin
+                                                       if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_212 = dummy_s;
+       dummy_d_199 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine5_req_valid;
-assign soc_sdram_bankmachine5_req_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine5_req_we;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine5_req_addr;
-assign soc_sdram_bankmachine5_cmd_buffer_sink_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine5_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine5_cmd_buffer_sink_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine5_cmd_buffer_sink_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine5_cmd_buffer_source_ready = (soc_sdram_bankmachine5_req_wdata_ready | soc_sdram_bankmachine5_req_rdata_valid);
-assign soc_sdram_bankmachine5_req_lock = (soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine5_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine5_row_hit = (soc_sdram_bankmachine5_row == soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
-assign soc_sdram_bankmachine5_cmd_payload_ba = 3'd5;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
 
 // synthesis translate_off
-reg dummy_d_213;
+reg dummy_d_200;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_a <= 15'd0;
-       if (soc_sdram_bankmachine5_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine5_cmd_payload_a <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+       litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
+       if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+               litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
        end else begin
-               soc_sdram_bankmachine5_cmd_payload_a <= ((soc_sdram_bankmachine5_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+               litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
        end
 // synthesis translate_off
-       dummy_d_213 = dummy_s;
+       dummy_d_200 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine5_twtpcon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_cmd_payload_is_write);
-assign soc_sdram_bankmachine5_trccon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open);
-assign soc_sdram_bankmachine5_trascon_valid = ((soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_ready) & soc_sdram_bankmachine5_row_open);
+assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
+assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
+assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
 
 // synthesis translate_off
-reg dummy_d_214;
+reg dummy_d_201;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine5_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
-                       soc_sdram_bankmachine5_auto_precharge <= (soc_sdram_bankmachine5_row_close == 1'd0);
+       litedramcore_bankmachine5_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
+                       litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
                end
        end
 // synthesis translate_off
-       dummy_d_214 = dummy_s;
+       dummy_d_201 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_sdram_bankmachine5_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
 
 // synthesis translate_off
-reg dummy_d_215;
+reg dummy_d_202;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine5_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
+       litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
        end else begin
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine5_cmd_buffer_lookahead_produce;
+               litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
        end
 // synthesis translate_off
-       dummy_d_215 = dummy_s;
+       dummy_d_202 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_sdram_bankmachine5_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine5_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_sdram_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine5_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_216;
+reg dummy_d_203;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine5_next_state <= 4'd0;
-       vns_bankmachine5_next_state <= vns_bankmachine5_state;
-       case (vns_bankmachine5_state)
+       bankmachine5_next_state <= 4'd0;
+       bankmachine5_next_state <= bankmachine5_state;
+       case (bankmachine5_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               if (soc_sdram_bankmachine5_cmd_ready) begin
-                                       vns_bankmachine5_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               if (litedramcore_bankmachine5_cmd_ready) begin
+                                       bankmachine5_next_state <= 3'd5;
                                end
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               vns_bankmachine5_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               bankmachine5_next_state <= 3'd5;
                        end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               if (soc_sdram_bankmachine5_cmd_ready) begin
-                                       vns_bankmachine5_next_state <= 3'd7;
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               if (litedramcore_bankmachine5_cmd_ready) begin
+                                       bankmachine5_next_state <= 3'd7;
                                end
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine5_refresh_req)) begin
-                               vns_bankmachine5_next_state <= 1'd0;
+                       if ((~litedramcore_bankmachine5_refresh_req)) begin
+                               bankmachine5_next_state <= 1'd0;
                        end
                end
                3'd5: begin
-                       vns_bankmachine5_next_state <= 3'd6;
+                       bankmachine5_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine5_next_state <= 2'd3;
+                       bankmachine5_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine5_next_state <= 4'd8;
+                       bankmachine5_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine5_next_state <= 1'd0;
+                       bankmachine5_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
-                               vns_bankmachine5_next_state <= 3'd4;
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                               bankmachine5_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if ((soc_sdram_bankmachine5_cmd_ready & soc_sdram_bankmachine5_auto_precharge)) begin
-                                                               vns_bankmachine5_next_state <= 2'd2;
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+                                                               bankmachine5_next_state <= 2'd2;
                                                        end
                                                end else begin
-                                                       vns_bankmachine5_next_state <= 1'd1;
+                                                       bankmachine5_next_state <= 1'd1;
                                                end
                                        end else begin
-                                               vns_bankmachine5_next_state <= 2'd3;
+                                               bankmachine5_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_216 = dummy_s;
+       dummy_d_203 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_217;
+reg dummy_d_204;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               soc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
-                       end
                end
                2'd2: begin
                end
@@ -8842,13 +7970,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine5_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -8860,24 +7988,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_217 = dummy_s;
+       dummy_d_204 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_218;
+reg dummy_d_205;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               soc_sdram_bankmachine5_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -8890,33 +8015,41 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_218 = dummy_s;
+       dummy_d_205 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_219;
+reg dummy_d_206;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine5_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -8927,24 +8060,42 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_219 = dummy_s;
+       dummy_d_206 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_220;
+reg dummy_d_207;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -8957,34 +8108,19 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine5_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_220 = dummy_s;
+       dummy_d_207 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_221;
+reg dummy_d_208;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
                end
                2'd2: begin
@@ -8992,6 +8128,9 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
+                       if (litedramcore_bankmachine5_twtpcon_ready) begin
+                               litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -9002,39 +8141,30 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine5_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_221 = dummy_s;
+       dummy_d_208 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_222;
+reg dummy_d_209;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_cmd_valid <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -9047,15 +8177,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine5_req_wdata_ready <= soc_sdram_bankmachine5_cmd_ready;
-                                                       end else begin
-                                                       end
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       litedramcore_bankmachine5_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -9065,21 +8192,24 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_222 = dummy_s;
+       dummy_d_209 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_223;
+reg dummy_d_210;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_row_open <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_row_open <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -9092,44 +8222,29 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       if (soc_sdram_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine5_req_rdata_valid <= soc_sdram_bankmachine5_cmd_ready;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_223 = dummy_s;
+       dummy_d_210 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_224;
+reg dummy_d_211;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_refresh_gnt <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_row_close <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
+                       litedramcore_bankmachine5_row_close <= 1'd1;
                end
                2'd2: begin
+                       litedramcore_bankmachine5_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine5_twtpcon_ready) begin
-                               soc_sdram_bankmachine5_refresh_gnt <= 1'd1;
-                       end
+                       litedramcore_bankmachine5_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -9143,27 +8258,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_224 = dummy_s;
+       dummy_d_211 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_225;
+reg dummy_d_212;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_valid <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               soc_sdram_bankmachine5_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               soc_sdram_bankmachine5_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -9176,12 +8285,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       soc_sdram_bankmachine5_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -9191,23 +8300,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_225 = dummy_s;
+       dummy_d_212 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_226;
+reg dummy_d_213;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_row_open <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               soc_sdram_bankmachine5_row_open <= 1'd1;
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
@@ -9224,26 +8336,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_226 = dummy_s;
+       dummy_d_213 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_227;
+reg dummy_d_214;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_row_close <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       soc_sdram_bankmachine5_row_close <= 1'd1;
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
-                       soc_sdram_bankmachine5_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine5_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -9254,26 +8366,48 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_227 = dummy_s;
+       dummy_d_214 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_228;
+reg dummy_d_215;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+                               litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine5_trccon_ready) begin
+                               litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                3'd4: begin
+                       litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -9284,42 +8418,24 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine5_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine5_row_opened) begin
-                                               if (soc_sdram_bankmachine5_row_hit) begin
-                                                       soc_sdram_bankmachine5_cmd_payload_cas <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_228 = dummy_s;
+       dummy_d_215 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_229;
+reg dummy_d_216;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine5_state)
+       litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+       case (bankmachine5_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine5_twtpcon_ready & soc_sdram_bankmachine5_trascon_ready)) begin
-                               soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine5_trccon_ready) begin
-                               soc_sdram_bankmachine5_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -9332,178 +8448,190 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine5_row_opened) begin
+                                               if (litedramcore_bankmachine5_row_hit) begin
+                                                       if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_229 = dummy_s;
+       dummy_d_216 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine6_req_valid;
-assign soc_sdram_bankmachine6_req_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine6_req_we;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine6_req_addr;
-assign soc_sdram_bankmachine6_cmd_buffer_sink_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine6_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine6_cmd_buffer_sink_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine6_cmd_buffer_sink_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine6_cmd_buffer_source_ready = (soc_sdram_bankmachine6_req_wdata_ready | soc_sdram_bankmachine6_req_rdata_valid);
-assign soc_sdram_bankmachine6_req_lock = (soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine6_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine6_row_hit = (soc_sdram_bankmachine6_row == soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
-assign soc_sdram_bankmachine6_cmd_payload_ba = 3'd6;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
 
 // synthesis translate_off
-reg dummy_d_230;
+reg dummy_d_217;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_a <= 15'd0;
-       if (soc_sdram_bankmachine6_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine6_cmd_payload_a <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+       litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
+       if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+               litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
        end else begin
-               soc_sdram_bankmachine6_cmd_payload_a <= ((soc_sdram_bankmachine6_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+               litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
        end
 // synthesis translate_off
-       dummy_d_230 = dummy_s;
+       dummy_d_217 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine6_twtpcon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_cmd_payload_is_write);
-assign soc_sdram_bankmachine6_trccon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open);
-assign soc_sdram_bankmachine6_trascon_valid = ((soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_ready) & soc_sdram_bankmachine6_row_open);
+assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
+assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
+assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
 
 // synthesis translate_off
-reg dummy_d_231;
+reg dummy_d_218;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine6_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
-                       soc_sdram_bankmachine6_auto_precharge <= (soc_sdram_bankmachine6_row_close == 1'd0);
+       litedramcore_bankmachine6_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
+                       litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
                end
        end
 // synthesis translate_off
-       dummy_d_231 = dummy_s;
+       dummy_d_218 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_sdram_bankmachine6_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
 
 // synthesis translate_off
-reg dummy_d_232;
+reg dummy_d_219;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine6_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
+       litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
        end else begin
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine6_cmd_buffer_lookahead_produce;
+               litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
        end
 // synthesis translate_off
-       dummy_d_232 = dummy_s;
+       dummy_d_219 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_sdram_bankmachine6_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine6_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_sdram_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine6_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_233;
+reg dummy_d_220;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine6_next_state <= 4'd0;
-       vns_bankmachine6_next_state <= vns_bankmachine6_state;
-       case (vns_bankmachine6_state)
+       bankmachine6_next_state <= 4'd0;
+       bankmachine6_next_state <= bankmachine6_state;
+       case (bankmachine6_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               if (soc_sdram_bankmachine6_cmd_ready) begin
-                                       vns_bankmachine6_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               if (litedramcore_bankmachine6_cmd_ready) begin
+                                       bankmachine6_next_state <= 3'd5;
                                end
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               vns_bankmachine6_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               bankmachine6_next_state <= 3'd5;
                        end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               if (soc_sdram_bankmachine6_cmd_ready) begin
-                                       vns_bankmachine6_next_state <= 3'd7;
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               if (litedramcore_bankmachine6_cmd_ready) begin
+                                       bankmachine6_next_state <= 3'd7;
                                end
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine6_refresh_req)) begin
-                               vns_bankmachine6_next_state <= 1'd0;
+                       if ((~litedramcore_bankmachine6_refresh_req)) begin
+                               bankmachine6_next_state <= 1'd0;
                        end
                end
                3'd5: begin
-                       vns_bankmachine6_next_state <= 3'd6;
+                       bankmachine6_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine6_next_state <= 2'd3;
+                       bankmachine6_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine6_next_state <= 4'd8;
+                       bankmachine6_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine6_next_state <= 1'd0;
+                       bankmachine6_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
-                               vns_bankmachine6_next_state <= 3'd4;
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                               bankmachine6_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if ((soc_sdram_bankmachine6_cmd_ready & soc_sdram_bankmachine6_auto_precharge)) begin
-                                                               vns_bankmachine6_next_state <= 2'd2;
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+                                                               bankmachine6_next_state <= 2'd2;
                                                        end
                                                end else begin
-                                                       vns_bankmachine6_next_state <= 1'd1;
+                                                       bankmachine6_next_state <= 1'd1;
                                                end
                                        end else begin
-                                               vns_bankmachine6_next_state <= 2'd3;
+                                               bankmachine6_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_233 = dummy_s;
+       dummy_d_220 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_234;
+reg dummy_d_221;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               soc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
-                       end
                end
                2'd2: begin
                end
@@ -9520,13 +8648,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine6_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -9538,24 +8666,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_234 = dummy_s;
+       dummy_d_221 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_235;
+reg dummy_d_222;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               soc_sdram_bankmachine6_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -9568,33 +8693,41 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_235 = dummy_s;
+       dummy_d_222 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_236;
+reg dummy_d_223;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine6_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -9605,19 +8738,34 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_236 = dummy_s;
+       dummy_d_223 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_237;
+reg dummy_d_224;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
@@ -9625,6 +8773,9 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
+                       if (litedramcore_bankmachine6_twtpcon_ready) begin
+                               litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -9635,39 +8786,30 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine6_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_237 = dummy_s;
+       dummy_d_224 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_238;
+reg dummy_d_225;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_cmd_valid <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -9680,15 +8822,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine6_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       litedramcore_bankmachine6_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -9698,21 +8837,24 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_238 = dummy_s;
+       dummy_d_225 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_239;
+reg dummy_d_226;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -9725,39 +8867,27 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine6_req_wdata_ready <= soc_sdram_bankmachine6_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_239 = dummy_s;
+       dummy_d_226 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_240;
+reg dummy_d_227;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_row_open <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_row_open <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -9770,44 +8900,29 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       if (soc_sdram_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine6_req_rdata_valid <= soc_sdram_bankmachine6_cmd_ready;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_240 = dummy_s;
+       dummy_d_227 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_241;
+reg dummy_d_228;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_refresh_gnt <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_row_close <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
+                       litedramcore_bankmachine6_row_close <= 1'd1;
                end
                2'd2: begin
+                       litedramcore_bankmachine6_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine6_twtpcon_ready) begin
-                               soc_sdram_bankmachine6_refresh_gnt <= 1'd1;
-                       end
+                       litedramcore_bankmachine6_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -9821,27 +8936,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_241 = dummy_s;
+       dummy_d_228 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_242;
+reg dummy_d_229;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_valid <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               soc_sdram_bankmachine6_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               soc_sdram_bankmachine6_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -9854,12 +8963,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       soc_sdram_bankmachine6_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -9869,23 +8978,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_242 = dummy_s;
+       dummy_d_229 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_243;
+reg dummy_d_230;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_row_open <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               soc_sdram_bankmachine6_row_open <= 1'd1;
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
                        end
                end
                3'd4: begin
@@ -9902,26 +9014,26 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_243 = dummy_s;
+       dummy_d_230 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_244;
+reg dummy_d_231;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_row_close <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
-                       soc_sdram_bankmachine6_row_close <= 1'd1;
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
-                       soc_sdram_bankmachine6_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_sdram_bankmachine6_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -9932,26 +9044,48 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_244 = dummy_s;
+       dummy_d_231 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_245;
+reg dummy_d_232;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+                               litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine6_trccon_ready) begin
+                               litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                3'd4: begin
+                       litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -9962,42 +9096,24 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine6_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine6_row_opened) begin
-                                               if (soc_sdram_bankmachine6_row_hit) begin
-                                                       soc_sdram_bankmachine6_cmd_payload_cas <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_245 = dummy_s;
+       dummy_d_232 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_246;
+reg dummy_d_233;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine6_state)
+       litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+       case (bankmachine6_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine6_twtpcon_ready & soc_sdram_bankmachine6_trascon_ready)) begin
-                               soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine6_trccon_ready) begin
-                               soc_sdram_bankmachine6_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -10010,178 +9126,190 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine6_row_opened) begin
+                                               if (litedramcore_bankmachine6_row_hit) begin
+                                                       if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_246 = dummy_s;
+       dummy_d_233 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_sdram_bankmachine7_req_valid;
-assign soc_sdram_bankmachine7_req_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_sdram_bankmachine7_req_we;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_sdram_bankmachine7_req_addr;
-assign soc_sdram_bankmachine7_cmd_buffer_sink_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready = soc_sdram_bankmachine7_cmd_buffer_sink_ready;
-assign soc_sdram_bankmachine7_cmd_buffer_sink_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first;
-assign soc_sdram_bankmachine7_cmd_buffer_sink_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last;
-assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign soc_sdram_bankmachine7_cmd_buffer_source_ready = (soc_sdram_bankmachine7_req_wdata_ready | soc_sdram_bankmachine7_req_rdata_valid);
-assign soc_sdram_bankmachine7_req_lock = (soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid | soc_sdram_bankmachine7_cmd_buffer_source_valid);
-assign soc_sdram_bankmachine7_row_hit = (soc_sdram_bankmachine7_row == soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
-assign soc_sdram_bankmachine7_cmd_payload_ba = 3'd7;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
+assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
+assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
+assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
 
 // synthesis translate_off
-reg dummy_d_247;
+reg dummy_d_234;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_a <= 15'd0;
-       if (soc_sdram_bankmachine7_row_col_n_addr_sel) begin
-               soc_sdram_bankmachine7_cmd_payload_a <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+       litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
+       if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+               litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
        end else begin
-               soc_sdram_bankmachine7_cmd_payload_a <= ((soc_sdram_bankmachine7_auto_precharge <<< 4'd10) | {soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
+               litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
        end
 // synthesis translate_off
-       dummy_d_247 = dummy_s;
+       dummy_d_234 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine7_twtpcon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_cmd_payload_is_write);
-assign soc_sdram_bankmachine7_trccon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open);
-assign soc_sdram_bankmachine7_trascon_valid = ((soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_ready) & soc_sdram_bankmachine7_row_open);
+assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
+assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
+assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
 
 // synthesis translate_off
-reg dummy_d_248;
+reg dummy_d_235;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_auto_precharge <= 1'd0;
-       if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid & soc_sdram_bankmachine7_cmd_buffer_source_valid)) begin
-               if ((soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
-                       soc_sdram_bankmachine7_auto_precharge <= (soc_sdram_bankmachine7_row_close == 1'd0);
+       litedramcore_bankmachine7_auto_precharge <= 1'd0;
+       if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
+               if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
+                       litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
                end
        end
 // synthesis translate_off
-       dummy_d_248 = dummy_s;
+       dummy_d_235 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_valid = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_first = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_last = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_sdram_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_sdram_bankmachine7_cmd_buffer_lookahead_source_ready;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
 
 // synthesis translate_off
-reg dummy_d_249;
+reg dummy_d_236;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
-       if (soc_sdram_bankmachine7_cmd_buffer_lookahead_replace) begin
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
+       litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
+       if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
        end else begin
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_sdram_bankmachine7_cmd_buffer_lookahead_produce;
+               litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
        end
 // synthesis translate_off
-       dummy_d_249 = dummy_s;
+       dummy_d_236 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_sdram_bankmachine7_cmd_buffer_lookahead_replace));
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read = (soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_sdram_bankmachine7_cmd_buffer_lookahead_consume;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_sdram_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign soc_sdram_bankmachine7_cmd_buffer_sink_ready = ((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
+assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
 
 // synthesis translate_off
-reg dummy_d_250;
+reg dummy_d_237;
 // synthesis translate_on
 always @(*) begin
-       vns_bankmachine7_next_state <= 4'd0;
-       vns_bankmachine7_next_state <= vns_bankmachine7_state;
-       case (vns_bankmachine7_state)
+       bankmachine7_next_state <= 4'd0;
+       bankmachine7_next_state <= bankmachine7_state;
+       case (bankmachine7_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               if (soc_sdram_bankmachine7_cmd_ready) begin
-                                       vns_bankmachine7_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               if (litedramcore_bankmachine7_cmd_ready) begin
+                                       bankmachine7_next_state <= 3'd5;
                                end
                        end
                end
                2'd2: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               vns_bankmachine7_next_state <= 3'd5;
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               bankmachine7_next_state <= 3'd5;
                        end
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               if (soc_sdram_bankmachine7_cmd_ready) begin
-                                       vns_bankmachine7_next_state <= 3'd7;
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               if (litedramcore_bankmachine7_cmd_ready) begin
+                                       bankmachine7_next_state <= 3'd7;
                                end
                        end
                end
                3'd4: begin
-                       if ((~soc_sdram_bankmachine7_refresh_req)) begin
-                               vns_bankmachine7_next_state <= 1'd0;
+                       if ((~litedramcore_bankmachine7_refresh_req)) begin
+                               bankmachine7_next_state <= 1'd0;
                        end
                end
                3'd5: begin
-                       vns_bankmachine7_next_state <= 3'd6;
+                       bankmachine7_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_bankmachine7_next_state <= 2'd3;
+                       bankmachine7_next_state <= 2'd3;
                end
                3'd7: begin
-                       vns_bankmachine7_next_state <= 4'd8;
+                       bankmachine7_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_bankmachine7_next_state <= 1'd0;
+                       bankmachine7_next_state <= 1'd0;
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
-                               vns_bankmachine7_next_state <= 3'd4;
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                               bankmachine7_next_state <= 3'd4;
                        end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if ((soc_sdram_bankmachine7_cmd_ready & soc_sdram_bankmachine7_auto_precharge)) begin
-                                                               vns_bankmachine7_next_state <= 2'd2;
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+                                                               bankmachine7_next_state <= 2'd2;
                                                        end
                                                end else begin
-                                                       vns_bankmachine7_next_state <= 1'd1;
+                                                       bankmachine7_next_state <= 1'd1;
                                                end
                                        end else begin
-                                               vns_bankmachine7_next_state <= 2'd3;
+                                               bankmachine7_next_state <= 2'd3;
                                        end
                                end
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_250 = dummy_s;
+       dummy_d_237 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_251;
+reg dummy_d_238;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_we <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               soc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
-                       end
                end
                2'd2: begin
                end
@@ -10198,13 +9326,13 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine7_cmd_payload_we <= 1'd1;
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
                                                        end else begin
                                                        end
                                                end else begin
@@ -10216,24 +9344,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_251 = dummy_s;
+       dummy_d_238 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_252;
+reg dummy_d_239;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               soc_sdram_bankmachine7_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -10246,56 +9371,34 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_252 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_253;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd0;
-       case (vns_bankmachine7_state)
-               1'd1: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
                        end
                end
-               3'd4: begin
-                       soc_sdram_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               default: begin
-               end
        endcase
 // synthesis translate_off
-       dummy_d_253 = dummy_s;
+       dummy_d_239 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_254;
+reg dummy_d_240;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
@@ -10313,14 +9416,14 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
                                                        end else begin
-                                                               soc_sdram_bankmachine7_cmd_payload_is_read <= 1'd1;
+                                                               litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -10331,16 +9434,16 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_254 = dummy_s;
+       dummy_d_240 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_255;
+reg dummy_d_241;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
@@ -10348,6 +9451,9 @@ always @(*) begin
                2'd3: begin
                end
                3'd4: begin
+                       if (litedramcore_bankmachine7_twtpcon_ready) begin
+                               litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -10358,39 +9464,30 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine7_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_255 = dummy_s;
+       dummy_d_241 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_256;
+reg dummy_d_242;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_req_wdata_ready <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_valid <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -10403,15 +9500,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                               soc_sdram_bankmachine7_req_wdata_ready <= soc_sdram_bankmachine7_cmd_ready;
-                                                       end else begin
-                                                       end
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       litedramcore_bankmachine7_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -10421,21 +9515,24 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_256 = dummy_s;
+       dummy_d_242 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_257;
+reg dummy_d_243;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_req_rdata_valid <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_row_open <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_row_open <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -10448,44 +9545,29 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
-                       end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       if (soc_sdram_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_sdram_bankmachine7_req_rdata_valid <= soc_sdram_bankmachine7_cmd_ready;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_257 = dummy_s;
+       dummy_d_243 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_258;
+reg dummy_d_244;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_refresh_gnt <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_row_close <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
+                       litedramcore_bankmachine7_row_close <= 1'd1;
                end
                2'd2: begin
+                       litedramcore_bankmachine7_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       if (soc_sdram_bankmachine7_twtpcon_ready) begin
-                               soc_sdram_bankmachine7_refresh_gnt <= 1'd1;
-                       end
+                       litedramcore_bankmachine7_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -10499,27 +9581,21 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_258 = dummy_s;
+       dummy_d_244 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_259;
+reg dummy_d_245;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_valid <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               soc_sdram_bankmachine7_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               soc_sdram_bankmachine7_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -10532,12 +9608,12 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       soc_sdram_bankmachine7_cmd_valid <= 1'd1;
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -10547,23 +9623,23 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_259 = dummy_s;
+       dummy_d_245 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_260;
+reg dummy_d_246;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_row_open <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               soc_sdram_bankmachine7_row_open <= 1'd1;
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
                        end
                end
                3'd4: begin
@@ -10580,26 +9656,29 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_260 = dummy_s;
+       dummy_d_246 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_261;
+reg dummy_d_247;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_row_close <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
-                       soc_sdram_bankmachine7_row_close <= 1'd1;
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
-                       soc_sdram_bankmachine7_row_close <= 1'd1;
                end
                2'd3: begin
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
-                       soc_sdram_bankmachine7_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -10613,17 +9692,20 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_261 = dummy_s;
+       dummy_d_247 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_262;
+reg dummy_d_248;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_cas <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
@@ -10640,12 +9722,15 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_sdram_bankmachine7_refresh_req) begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
                        end else begin
-                               if (soc_sdram_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_sdram_bankmachine7_row_opened) begin
-                                               if (soc_sdram_bankmachine7_row_hit) begin
-                                                       soc_sdram_bankmachine7_cmd_payload_cas <= 1'd1;
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                                                       end else begin
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -10655,29 +9740,30 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_262 = dummy_s;
+       dummy_d_248 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_263;
+reg dummy_d_249;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_payload_ras <= 1'd0;
-       case (vns_bankmachine7_state)
+       litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+       case (bankmachine7_state)
                1'd1: begin
-                       if ((soc_sdram_bankmachine7_twtpcon_ready & soc_sdram_bankmachine7_trascon_ready)) begin
-                               soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
+                       if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+                               litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_sdram_bankmachine7_trccon_ready) begin
-                               soc_sdram_bankmachine7_cmd_payload_ras <= 1'd1;
+                       if (litedramcore_bankmachine7_trccon_ready) begin
+                               litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -10691,454 +9777,426 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_263 = dummy_s;
+       dummy_d_249 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_trrdcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we)));
-assign soc_sdram_tfawcon_valid = ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & ((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we)));
-assign soc_sdram_ras_allowed = (soc_sdram_trrdcon_ready & soc_sdram_tfawcon_ready);
-assign soc_sdram_tccdcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_cmd_payload_is_write | soc_sdram_choose_req_cmd_payload_is_read));
-assign soc_sdram_cas_allowed = soc_sdram_tccdcon_ready;
-assign soc_sdram_twtrcon_valid = ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
-assign soc_sdram_read_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_read) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_read)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_read)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_read)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_read)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_read)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_read)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_read));
-assign soc_sdram_write_available = ((((((((soc_sdram_bankmachine0_cmd_valid & soc_sdram_bankmachine0_cmd_payload_is_write) | (soc_sdram_bankmachine1_cmd_valid & soc_sdram_bankmachine1_cmd_payload_is_write)) | (soc_sdram_bankmachine2_cmd_valid & soc_sdram_bankmachine2_cmd_payload_is_write)) | (soc_sdram_bankmachine3_cmd_valid & soc_sdram_bankmachine3_cmd_payload_is_write)) | (soc_sdram_bankmachine4_cmd_valid & soc_sdram_bankmachine4_cmd_payload_is_write)) | (soc_sdram_bankmachine5_cmd_valid & soc_sdram_bankmachine5_cmd_payload_is_write)) | (soc_sdram_bankmachine6_cmd_valid & soc_sdram_bankmachine6_cmd_payload_is_write)) | (soc_sdram_bankmachine7_cmd_valid & soc_sdram_bankmachine7_cmd_payload_is_write));
-assign soc_sdram_max_time0 = (soc_sdram_time0 == 1'd0);
-assign soc_sdram_max_time1 = (soc_sdram_time1 == 1'd0);
-assign soc_sdram_bankmachine0_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine1_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine2_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine3_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine4_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine5_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine6_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_bankmachine7_refresh_req = soc_sdram_cmd_valid;
-assign soc_sdram_go_to_refresh = (((((((soc_sdram_bankmachine0_refresh_gnt & soc_sdram_bankmachine1_refresh_gnt) & soc_sdram_bankmachine2_refresh_gnt) & soc_sdram_bankmachine3_refresh_gnt) & soc_sdram_bankmachine4_refresh_gnt) & soc_sdram_bankmachine5_refresh_gnt) & soc_sdram_bankmachine6_refresh_gnt) & soc_sdram_bankmachine7_refresh_gnt);
-assign soc_sdram_interface_rdata = {soc_sdram_dfi_p3_rddata, soc_sdram_dfi_p2_rddata, soc_sdram_dfi_p1_rddata, soc_sdram_dfi_p0_rddata};
-assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
-assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
-assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
-assign {soc_sdram_dfi_p3_wrdata, soc_sdram_dfi_p2_wrdata, soc_sdram_dfi_p1_wrdata, soc_sdram_dfi_p0_wrdata} = soc_sdram_interface_wdata;
-assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
-assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
-assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
-assign {soc_sdram_dfi_p3_wrdata_mask, soc_sdram_dfi_p2_wrdata_mask, soc_sdram_dfi_p1_wrdata_mask, soc_sdram_dfi_p0_wrdata_mask} = (~soc_sdram_interface_wdata_we);
 
 // synthesis translate_off
-reg dummy_d_264;
+reg dummy_d_250;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_cmd_valids <= 8'd0;
-       soc_sdram_choose_cmd_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
-       soc_sdram_choose_cmd_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_cmd_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_cmd_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_cmd_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_cmd_want_writes))));
+       litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+       case (bankmachine7_state)
+               1'd1: begin
+               end
+               2'd2: begin
+               end
+               2'd3: begin
+               end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+                       if (litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (litedramcore_bankmachine7_row_opened) begin
+                                               if (litedramcore_bankmachine7_row_hit) begin
+                                                       if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
+               end
+       endcase
 // synthesis translate_off
-       dummy_d_264 = dummy_s;
+       dummy_d_250 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_choose_cmd_request = soc_sdram_choose_cmd_valids;
-assign soc_sdram_choose_cmd_cmd_valid = vns_rhs_array_muxed0;
-assign soc_sdram_choose_cmd_cmd_payload_a = vns_rhs_array_muxed1;
-assign soc_sdram_choose_cmd_cmd_payload_ba = vns_rhs_array_muxed2;
-assign soc_sdram_choose_cmd_cmd_payload_is_read = vns_rhs_array_muxed3;
-assign soc_sdram_choose_cmd_cmd_payload_is_write = vns_rhs_array_muxed4;
-assign soc_sdram_choose_cmd_cmd_payload_is_cmd = vns_rhs_array_muxed5;
+assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
+assign litedramcore_ras_allowed = (litedramcore_trrdcon_ready & litedramcore_tfawcon_ready);
+assign litedramcore_tccdcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_cmd_payload_is_write | litedramcore_choose_req_cmd_payload_is_read));
+assign litedramcore_cas_allowed = litedramcore_tccdcon_ready;
+assign litedramcore_twtrcon_valid = ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+assign litedramcore_read_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_read) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_read)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_read)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_read)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_read)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_read)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_read)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_read));
+assign litedramcore_write_available = ((((((((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_payload_is_write) | (litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_payload_is_write)) | (litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_payload_is_write)) | (litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_payload_is_write)) | (litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_payload_is_write)) | (litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_payload_is_write)) | (litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_payload_is_write)) | (litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_payload_is_write));
+assign litedramcore_max_time0 = (litedramcore_time0 == 1'd0);
+assign litedramcore_max_time1 = (litedramcore_time1 == 1'd0);
+assign litedramcore_bankmachine0_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine1_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine2_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine3_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine4_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine5_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine6_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_bankmachine7_refresh_req = litedramcore_cmd_valid;
+assign litedramcore_go_to_refresh = (((((((litedramcore_bankmachine0_refresh_gnt & litedramcore_bankmachine1_refresh_gnt) & litedramcore_bankmachine2_refresh_gnt) & litedramcore_bankmachine3_refresh_gnt) & litedramcore_bankmachine4_refresh_gnt) & litedramcore_bankmachine5_refresh_gnt) & litedramcore_bankmachine6_refresh_gnt) & litedramcore_bankmachine7_refresh_gnt);
+assign litedramcore_interface_rdata = {litedramcore_dfi_p3_rddata, litedramcore_dfi_p2_rddata, litedramcore_dfi_p1_rddata, litedramcore_dfi_p0_rddata};
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata, litedramcore_dfi_p2_wrdata, litedramcore_dfi_p1_wrdata, litedramcore_dfi_p0_wrdata} = litedramcore_interface_wdata;
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
+assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
 
 // synthesis translate_off
-reg dummy_d_265;
+reg dummy_d_251;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_cmd_cmd_payload_cas <= 1'd0;
-       if (soc_sdram_choose_cmd_cmd_valid) begin
-               soc_sdram_choose_cmd_cmd_payload_cas <= vns_t_array_muxed0;
-       end
+       litedramcore_choose_cmd_valids <= 8'd0;
+       litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+       litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
 // synthesis translate_off
-       dummy_d_265 = dummy_s;
+       dummy_d_251 = dummy_s;
 // synthesis translate_on
 end
+assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
+assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
+assign litedramcore_choose_cmd_cmd_payload_a = rhs_array_muxed1;
+assign litedramcore_choose_cmd_cmd_payload_ba = rhs_array_muxed2;
+assign litedramcore_choose_cmd_cmd_payload_is_read = rhs_array_muxed3;
+assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
+assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
 
 // synthesis translate_off
-reg dummy_d_266;
+reg dummy_d_252;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_cmd_cmd_payload_ras <= 1'd0;
-       if (soc_sdram_choose_cmd_cmd_valid) begin
-               soc_sdram_choose_cmd_cmd_payload_ras <= vns_t_array_muxed1;
+       litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+       if (litedramcore_choose_cmd_cmd_valid) begin
+               litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
        end
 // synthesis translate_off
-       dummy_d_266 = dummy_s;
+       dummy_d_252 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_267;
+reg dummy_d_253;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_cmd_cmd_payload_we <= 1'd0;
-       if (soc_sdram_choose_cmd_cmd_valid) begin
-               soc_sdram_choose_cmd_cmd_payload_we <= vns_t_array_muxed2;
+       litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+       if (litedramcore_choose_cmd_cmd_valid) begin
+               litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
        end
 // synthesis translate_off
-       dummy_d_267 = dummy_s;
+       dummy_d_253 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_268;
+reg dummy_d_254;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+       if (litedramcore_choose_cmd_cmd_valid) begin
+               litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+       end
+// synthesis translate_off
+       dummy_d_254 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_255;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine0_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd0))) begin
-               soc_sdram_bankmachine0_cmd_ready <= 1'd1;
+       litedramcore_bankmachine0_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+               litedramcore_bankmachine0_cmd_ready <= 1'd1;
        end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd0))) begin
-               soc_sdram_bankmachine0_cmd_ready <= 1'd1;
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+               litedramcore_bankmachine0_cmd_ready <= 1'd1;
        end
 // synthesis translate_off
-       dummy_d_268 = dummy_s;
+       dummy_d_255 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_269;
+reg dummy_d_256;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine1_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 1'd1))) begin
-               soc_sdram_bankmachine1_cmd_ready <= 1'd1;
+       litedramcore_bankmachine1_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+               litedramcore_bankmachine1_cmd_ready <= 1'd1;
        end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 1'd1))) begin
-               soc_sdram_bankmachine1_cmd_ready <= 1'd1;
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+               litedramcore_bankmachine1_cmd_ready <= 1'd1;
        end
 // synthesis translate_off
-       dummy_d_269 = dummy_s;
+       dummy_d_256 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_270;
+reg dummy_d_257;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine2_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd2))) begin
-               soc_sdram_bankmachine2_cmd_ready <= 1'd1;
+       litedramcore_bankmachine2_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+               litedramcore_bankmachine2_cmd_ready <= 1'd1;
        end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd2))) begin
-               soc_sdram_bankmachine2_cmd_ready <= 1'd1;
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+               litedramcore_bankmachine2_cmd_ready <= 1'd1;
        end
 // synthesis translate_off
-       dummy_d_270 = dummy_s;
+       dummy_d_257 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_271;
+reg dummy_d_258;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine3_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 2'd3))) begin
-               soc_sdram_bankmachine3_cmd_ready <= 1'd1;
+       litedramcore_bankmachine3_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+               litedramcore_bankmachine3_cmd_ready <= 1'd1;
        end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 2'd3))) begin
-               soc_sdram_bankmachine3_cmd_ready <= 1'd1;
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+               litedramcore_bankmachine3_cmd_ready <= 1'd1;
        end
 // synthesis translate_off
-       dummy_d_271 = dummy_s;
+       dummy_d_258 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_272;
+reg dummy_d_259;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine4_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd4))) begin
-               soc_sdram_bankmachine4_cmd_ready <= 1'd1;
+       litedramcore_bankmachine4_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+               litedramcore_bankmachine4_cmd_ready <= 1'd1;
        end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd4))) begin
-               soc_sdram_bankmachine4_cmd_ready <= 1'd1;
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+               litedramcore_bankmachine4_cmd_ready <= 1'd1;
        end
 // synthesis translate_off
-       dummy_d_272 = dummy_s;
+       dummy_d_259 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_273;
+reg dummy_d_260;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine5_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd5))) begin
-               soc_sdram_bankmachine5_cmd_ready <= 1'd1;
+       litedramcore_bankmachine5_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+               litedramcore_bankmachine5_cmd_ready <= 1'd1;
        end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd5))) begin
-               soc_sdram_bankmachine5_cmd_ready <= 1'd1;
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+               litedramcore_bankmachine5_cmd_ready <= 1'd1;
        end
 // synthesis translate_off
-       dummy_d_273 = dummy_s;
+       dummy_d_260 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_274;
+reg dummy_d_261;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine6_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd6))) begin
-               soc_sdram_bankmachine6_cmd_ready <= 1'd1;
+       litedramcore_bankmachine6_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+               litedramcore_bankmachine6_cmd_ready <= 1'd1;
        end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd6))) begin
-               soc_sdram_bankmachine6_cmd_ready <= 1'd1;
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+               litedramcore_bankmachine6_cmd_ready <= 1'd1;
        end
 // synthesis translate_off
-       dummy_d_274 = dummy_s;
+       dummy_d_261 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_275;
+reg dummy_d_262;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_bankmachine7_cmd_ready <= 1'd0;
-       if (((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & (soc_sdram_choose_cmd_grant == 3'd7))) begin
-               soc_sdram_bankmachine7_cmd_ready <= 1'd1;
+       litedramcore_bankmachine7_cmd_ready <= 1'd0;
+       if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+               litedramcore_bankmachine7_cmd_ready <= 1'd1;
        end
-       if (((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & (soc_sdram_choose_req_grant == 3'd7))) begin
-               soc_sdram_bankmachine7_cmd_ready <= 1'd1;
+       if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+               litedramcore_bankmachine7_cmd_ready <= 1'd1;
        end
 // synthesis translate_off
-       dummy_d_275 = dummy_s;
+       dummy_d_262 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_choose_cmd_ce = (soc_sdram_choose_cmd_cmd_ready | (~soc_sdram_choose_cmd_cmd_valid));
+assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
 
 // synthesis translate_off
-reg dummy_d_276;
+reg dummy_d_263;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_req_valids <= 8'd0;
-       soc_sdram_choose_req_valids[0] <= (soc_sdram_bankmachine0_cmd_valid & (((soc_sdram_bankmachine0_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine0_cmd_payload_ras & (~soc_sdram_bankmachine0_cmd_payload_cas)) & (~soc_sdram_bankmachine0_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine0_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine0_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[1] <= (soc_sdram_bankmachine1_cmd_valid & (((soc_sdram_bankmachine1_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine1_cmd_payload_ras & (~soc_sdram_bankmachine1_cmd_payload_cas)) & (~soc_sdram_bankmachine1_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine1_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine1_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[2] <= (soc_sdram_bankmachine2_cmd_valid & (((soc_sdram_bankmachine2_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine2_cmd_payload_ras & (~soc_sdram_bankmachine2_cmd_payload_cas)) & (~soc_sdram_bankmachine2_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine2_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine2_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[3] <= (soc_sdram_bankmachine3_cmd_valid & (((soc_sdram_bankmachine3_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine3_cmd_payload_ras & (~soc_sdram_bankmachine3_cmd_payload_cas)) & (~soc_sdram_bankmachine3_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine3_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine3_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[4] <= (soc_sdram_bankmachine4_cmd_valid & (((soc_sdram_bankmachine4_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine4_cmd_payload_ras & (~soc_sdram_bankmachine4_cmd_payload_cas)) & (~soc_sdram_bankmachine4_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine4_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine4_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[5] <= (soc_sdram_bankmachine5_cmd_valid & (((soc_sdram_bankmachine5_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine5_cmd_payload_ras & (~soc_sdram_bankmachine5_cmd_payload_cas)) & (~soc_sdram_bankmachine5_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine5_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine5_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[6] <= (soc_sdram_bankmachine6_cmd_valid & (((soc_sdram_bankmachine6_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine6_cmd_payload_ras & (~soc_sdram_bankmachine6_cmd_payload_cas)) & (~soc_sdram_bankmachine6_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine6_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine6_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
-       soc_sdram_choose_req_valids[7] <= (soc_sdram_bankmachine7_cmd_valid & (((soc_sdram_bankmachine7_cmd_payload_is_cmd & soc_sdram_choose_req_want_cmds) & ((~((soc_sdram_bankmachine7_cmd_payload_ras & (~soc_sdram_bankmachine7_cmd_payload_cas)) & (~soc_sdram_bankmachine7_cmd_payload_we))) | soc_sdram_choose_req_want_activates)) | ((soc_sdram_bankmachine7_cmd_payload_is_read == soc_sdram_choose_req_want_reads) & (soc_sdram_bankmachine7_cmd_payload_is_write == soc_sdram_choose_req_want_writes))));
+       litedramcore_choose_req_valids <= 8'd0;
+       litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+       litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
 // synthesis translate_off
-       dummy_d_276 = dummy_s;
+       dummy_d_263 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_choose_req_request = soc_sdram_choose_req_valids;
-assign soc_sdram_choose_req_cmd_valid = vns_rhs_array_muxed6;
-assign soc_sdram_choose_req_cmd_payload_a = vns_rhs_array_muxed7;
-assign soc_sdram_choose_req_cmd_payload_ba = vns_rhs_array_muxed8;
-assign soc_sdram_choose_req_cmd_payload_is_read = vns_rhs_array_muxed9;
-assign soc_sdram_choose_req_cmd_payload_is_write = vns_rhs_array_muxed10;
-assign soc_sdram_choose_req_cmd_payload_is_cmd = vns_rhs_array_muxed11;
+assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
+assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
+assign litedramcore_choose_req_cmd_payload_a = rhs_array_muxed7;
+assign litedramcore_choose_req_cmd_payload_ba = rhs_array_muxed8;
+assign litedramcore_choose_req_cmd_payload_is_read = rhs_array_muxed9;
+assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
+assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
 
 // synthesis translate_off
-reg dummy_d_277;
+reg dummy_d_264;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_req_cmd_payload_cas <= 1'd0;
-       if (soc_sdram_choose_req_cmd_valid) begin
-               soc_sdram_choose_req_cmd_payload_cas <= vns_t_array_muxed3;
+       litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+       if (litedramcore_choose_req_cmd_valid) begin
+               litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
        end
 // synthesis translate_off
-       dummy_d_277 = dummy_s;
+       dummy_d_264 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_278;
+reg dummy_d_265;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_req_cmd_payload_ras <= 1'd0;
-       if (soc_sdram_choose_req_cmd_valid) begin
-               soc_sdram_choose_req_cmd_payload_ras <= vns_t_array_muxed4;
+       litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+       if (litedramcore_choose_req_cmd_valid) begin
+               litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
        end
 // synthesis translate_off
-       dummy_d_278 = dummy_s;
+       dummy_d_265 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_279;
+reg dummy_d_266;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_req_cmd_payload_we <= 1'd0;
-       if (soc_sdram_choose_req_cmd_valid) begin
-               soc_sdram_choose_req_cmd_payload_we <= vns_t_array_muxed5;
+       litedramcore_choose_req_cmd_payload_we <= 1'd0;
+       if (litedramcore_choose_req_cmd_valid) begin
+               litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
        end
 // synthesis translate_off
-       dummy_d_279 = dummy_s;
+       dummy_d_266 = dummy_s;
 // synthesis translate_on
 end
-assign soc_sdram_choose_req_ce = (soc_sdram_choose_req_cmd_ready | (~soc_sdram_choose_req_cmd_valid));
-assign soc_sdram_dfi_p0_reset_n = 1'd1;
-assign soc_sdram_dfi_p0_cke = {1{soc_sdram_steerer0}};
-assign soc_sdram_dfi_p0_odt = {1{soc_sdram_steerer1}};
-assign soc_sdram_dfi_p1_reset_n = 1'd1;
-assign soc_sdram_dfi_p1_cke = {1{soc_sdram_steerer2}};
-assign soc_sdram_dfi_p1_odt = {1{soc_sdram_steerer3}};
-assign soc_sdram_dfi_p2_reset_n = 1'd1;
-assign soc_sdram_dfi_p2_cke = {1{soc_sdram_steerer4}};
-assign soc_sdram_dfi_p2_odt = {1{soc_sdram_steerer5}};
-assign soc_sdram_dfi_p3_reset_n = 1'd1;
-assign soc_sdram_dfi_p3_cke = {1{soc_sdram_steerer6}};
-assign soc_sdram_dfi_p3_odt = {1{soc_sdram_steerer7}};
-assign soc_sdram_tfawcon_count = ((((soc_sdram_tfawcon_window[0] + soc_sdram_tfawcon_window[1]) + soc_sdram_tfawcon_window[2]) + soc_sdram_tfawcon_window[3]) + soc_sdram_tfawcon_window[4]);
+assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
+assign litedramcore_dfi_p0_reset_n = 1'd1;
+assign litedramcore_dfi_p0_cke = {1{litedramcore_steerer0}};
+assign litedramcore_dfi_p0_odt = {1{litedramcore_steerer1}};
+assign litedramcore_dfi_p1_reset_n = 1'd1;
+assign litedramcore_dfi_p1_cke = {1{litedramcore_steerer2}};
+assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
+assign litedramcore_dfi_p2_reset_n = 1'd1;
+assign litedramcore_dfi_p2_cke = {1{litedramcore_steerer4}};
+assign litedramcore_dfi_p2_odt = {1{litedramcore_steerer5}};
+assign litedramcore_dfi_p3_reset_n = 1'd1;
+assign litedramcore_dfi_p3_cke = {1{litedramcore_steerer6}};
+assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
+assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
 
 // synthesis translate_off
-reg dummy_d_280;
+reg dummy_d_267;
 // synthesis translate_on
 always @(*) begin
-       vns_multiplexer_next_state <= 4'd0;
-       vns_multiplexer_next_state <= vns_multiplexer_state;
-       case (vns_multiplexer_state)
+       multiplexer_next_state <= 4'd0;
+       multiplexer_next_state <= multiplexer_state;
+       case (multiplexer_state)
                1'd1: begin
-                       if (soc_sdram_read_available) begin
-                               if (((~soc_sdram_write_available) | soc_sdram_max_time1)) begin
-                                       vns_multiplexer_next_state <= 2'd3;
+                       if (litedramcore_read_available) begin
+                               if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+                                       multiplexer_next_state <= 2'd3;
                                end
                        end
-                       if (soc_sdram_go_to_refresh) begin
-                               vns_multiplexer_next_state <= 2'd2;
+                       if (litedramcore_go_to_refresh) begin
+                               multiplexer_next_state <= 2'd2;
                        end
                end
                2'd2: begin
-                       if (soc_sdram_cmd_last) begin
-                               vns_multiplexer_next_state <= 1'd0;
+                       if (litedramcore_cmd_last) begin
+                               multiplexer_next_state <= 1'd0;
                        end
                end
                2'd3: begin
-                       if (soc_sdram_twtrcon_ready) begin
-                               vns_multiplexer_next_state <= 1'd0;
+                       if (litedramcore_twtrcon_ready) begin
+                               multiplexer_next_state <= 1'd0;
                        end
                end
                3'd4: begin
-                       vns_multiplexer_next_state <= 3'd5;
+                       multiplexer_next_state <= 3'd5;
                end
                3'd5: begin
-                       vns_multiplexer_next_state <= 3'd6;
+                       multiplexer_next_state <= 3'd6;
                end
                3'd6: begin
-                       vns_multiplexer_next_state <= 3'd7;
+                       multiplexer_next_state <= 3'd7;
                end
                3'd7: begin
-                       vns_multiplexer_next_state <= 4'd8;
+                       multiplexer_next_state <= 4'd8;
                end
                4'd8: begin
-                       vns_multiplexer_next_state <= 4'd9;
+                       multiplexer_next_state <= 4'd9;
                end
                4'd9: begin
-                       vns_multiplexer_next_state <= 4'd10;
+                       multiplexer_next_state <= 4'd10;
                end
                4'd10: begin
-                       vns_multiplexer_next_state <= 1'd1;
+                       multiplexer_next_state <= 1'd1;
                end
                default: begin
-                       if (soc_sdram_write_available) begin
-                               if (((~soc_sdram_read_available) | soc_sdram_max_time0)) begin
-                                       vns_multiplexer_next_state <= 3'd4;
+                       if (litedramcore_write_available) begin
+                               if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+                                       multiplexer_next_state <= 3'd4;
                                end
                        end
-                       if (soc_sdram_go_to_refresh) begin
-                               vns_multiplexer_next_state <= 2'd2;
+                       if (litedramcore_go_to_refresh) begin
+                               multiplexer_next_state <= 2'd2;
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_280 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_281;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_steerer_sel0 <= 2'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       soc_sdram_steerer_sel0 <= 1'd0;
-               end
-               2'd2: begin
-                       soc_sdram_steerer_sel0 <= 2'd3;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       soc_sdram_steerer_sel0 <= 1'd0;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_281 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_282;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_steerer_sel1 <= 2'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       soc_sdram_steerer_sel1 <= 1'd0;
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       soc_sdram_steerer_sel1 <= 1'd1;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_282 = dummy_s;
+       dummy_d_267 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_283;
+reg dummy_d_268;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_steerer_sel2 <= 2'd0;
-       case (vns_multiplexer_state)
+       litedramcore_steerer_sel2 <= 2'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       soc_sdram_steerer_sel2 <= 1'd1;
+                       litedramcore_steerer_sel2 <= 1'd1;
                end
                2'd2: begin
                end
@@ -11159,24 +10217,24 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       soc_sdram_steerer_sel2 <= 2'd2;
+                       litedramcore_steerer_sel2 <= 2'd2;
                end
        endcase
 // synthesis translate_off
-       dummy_d_283 = dummy_s;
+       dummy_d_268 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_284;
+reg dummy_d_269;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_cmd_want_activates <= 1'd0;
-       case (vns_multiplexer_state)
+       litedramcore_choose_cmd_want_activates <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
                        if (1'd0) begin
                        end else begin
-                               soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed;
+                               litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
                        end
                end
                2'd2: begin
@@ -11200,23 +10258,23 @@ always @(*) begin
                default: begin
                        if (1'd0) begin
                        end else begin
-                               soc_sdram_choose_cmd_want_activates <= soc_sdram_ras_allowed;
+                               litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
                        end
                end
        endcase
 // synthesis translate_off
-       dummy_d_284 = dummy_s;
+       dummy_d_269 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_285;
+reg dummy_d_270;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_steerer_sel3 <= 2'd0;
-       case (vns_multiplexer_state)
+       litedramcore_steerer_sel3 <= 2'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       soc_sdram_steerer_sel3 <= 2'd2;
+                       litedramcore_steerer_sel3 <= 2'd2;
                end
                2'd2: begin
                end
@@ -11237,20 +10295,20 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       soc_sdram_steerer_sel3 <= 1'd0;
+                       litedramcore_steerer_sel3 <= 1'd0;
                end
        endcase
 // synthesis translate_off
-       dummy_d_285 = dummy_s;
+       dummy_d_270 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_286;
+reg dummy_d_271;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_en0 <= 1'd0;
-       case (vns_multiplexer_state)
+       litedramcore_en0 <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
                end
                2'd2: begin
@@ -11272,24 +10330,24 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       soc_sdram_en0 <= 1'd1;
+                       litedramcore_en0 <= 1'd1;
                end
        endcase
 // synthesis translate_off
-       dummy_d_286 = dummy_s;
+       dummy_d_271 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_287;
+reg dummy_d_272;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_cmd_ready <= 1'd0;
-       case (vns_multiplexer_state)
+       litedramcore_cmd_ready <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
                end
                2'd2: begin
-                       soc_sdram_cmd_ready <= 1'd1;
+                       litedramcore_cmd_ready <= 1'd1;
                end
                2'd3: begin
                end
@@ -11311,96 +10369,22 @@ always @(*) begin
                end
        endcase
 // synthesis translate_off
-       dummy_d_287 = dummy_s;
+       dummy_d_272 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_288;
+reg dummy_d_273;
 // synthesis translate_on
 always @(*) begin
-       soc_sdram_choose_cmd_cmd_ready <= 1'd0;
-       case (vns_multiplexer_state)
+       litedramcore_choose_cmd_cmd_ready <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
                        if (1'd0) begin
                        end else begin
-                               soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed);
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       if (1'd0) begin
-                       end else begin
-                               soc_sdram_choose_cmd_cmd_ready <= ((~((soc_sdram_choose_cmd_cmd_payload_ras & (~soc_sdram_choose_cmd_cmd_payload_cas)) & (~soc_sdram_choose_cmd_cmd_payload_we))) | soc_sdram_ras_allowed);
+                               litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
                        end
                end
-       endcase
-// synthesis translate_off
-       dummy_d_288 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_289;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_req_want_reads <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       soc_sdram_choose_req_want_reads <= 1'd1;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_289 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_290;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_req_want_writes <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       soc_sdram_choose_req_want_writes <= 1'd1;
-               end
                2'd2: begin
                end
                2'd3: begin
@@ -11418,4578 +10402,3214 @@ always @(*) begin
                4'd9: begin
                end
                4'd10: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_290 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_291;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_choose_req_cmd_ready <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       if (1'd0) begin
-                               soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed));
-                       end else begin
-                               soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed;
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-                       if (1'd0) begin
-                               soc_sdram_choose_req_cmd_ready <= (soc_sdram_cas_allowed & ((~((soc_sdram_choose_req_cmd_payload_ras & (~soc_sdram_choose_req_cmd_payload_cas)) & (~soc_sdram_choose_req_cmd_payload_we))) | soc_sdram_ras_allowed));
-                       end else begin
-                               soc_sdram_choose_req_cmd_ready <= soc_sdram_cas_allowed;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_291 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_292;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_en1 <= 1'd0;
-       case (vns_multiplexer_state)
-               1'd1: begin
-                       soc_sdram_en1 <= 1'd1;
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               4'd9: begin
-               end
-               4'd10: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_292 = dummy_s;
-// synthesis translate_on
-end
-assign vns_roundrobin0_request = {(((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin0_ce = ((~soc_sdram_interface_bank0_valid) & (~soc_sdram_interface_bank0_lock));
-assign soc_sdram_interface_bank0_addr = vns_rhs_array_muxed12;
-assign soc_sdram_interface_bank0_we = vns_rhs_array_muxed13;
-assign soc_sdram_interface_bank0_valid = vns_rhs_array_muxed14;
-assign vns_roundrobin1_request = {(((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin1_ce = ((~soc_sdram_interface_bank1_valid) & (~soc_sdram_interface_bank1_lock));
-assign soc_sdram_interface_bank1_addr = vns_rhs_array_muxed15;
-assign soc_sdram_interface_bank1_we = vns_rhs_array_muxed16;
-assign soc_sdram_interface_bank1_valid = vns_rhs_array_muxed17;
-assign vns_roundrobin2_request = {(((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin2_ce = ((~soc_sdram_interface_bank2_valid) & (~soc_sdram_interface_bank2_lock));
-assign soc_sdram_interface_bank2_addr = vns_rhs_array_muxed18;
-assign soc_sdram_interface_bank2_we = vns_rhs_array_muxed19;
-assign soc_sdram_interface_bank2_valid = vns_rhs_array_muxed20;
-assign vns_roundrobin3_request = {(((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin3_ce = ((~soc_sdram_interface_bank3_valid) & (~soc_sdram_interface_bank3_lock));
-assign soc_sdram_interface_bank3_addr = vns_rhs_array_muxed21;
-assign soc_sdram_interface_bank3_we = vns_rhs_array_muxed22;
-assign soc_sdram_interface_bank3_valid = vns_rhs_array_muxed23;
-assign vns_roundrobin4_request = {(((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin4_ce = ((~soc_sdram_interface_bank4_valid) & (~soc_sdram_interface_bank4_lock));
-assign soc_sdram_interface_bank4_addr = vns_rhs_array_muxed24;
-assign soc_sdram_interface_bank4_we = vns_rhs_array_muxed25;
-assign soc_sdram_interface_bank4_valid = vns_rhs_array_muxed26;
-assign vns_roundrobin5_request = {(((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin5_ce = ((~soc_sdram_interface_bank5_valid) & (~soc_sdram_interface_bank5_lock));
-assign soc_sdram_interface_bank5_addr = vns_rhs_array_muxed27;
-assign soc_sdram_interface_bank5_we = vns_rhs_array_muxed28;
-assign soc_sdram_interface_bank5_valid = vns_rhs_array_muxed29;
-assign vns_roundrobin6_request = {(((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin6_ce = ((~soc_sdram_interface_bank6_valid) & (~soc_sdram_interface_bank6_lock));
-assign soc_sdram_interface_bank6_addr = vns_rhs_array_muxed30;
-assign soc_sdram_interface_bank6_we = vns_rhs_array_muxed31;
-assign soc_sdram_interface_bank6_valid = vns_rhs_array_muxed32;
-assign vns_roundrobin7_request = {(((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid), (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid)};
-assign vns_roundrobin7_ce = ((~soc_sdram_interface_bank7_valid) & (~soc_sdram_interface_bank7_lock));
-assign soc_sdram_interface_bank7_addr = vns_rhs_array_muxed33;
-assign soc_sdram_interface_bank7_we = vns_rhs_array_muxed34;
-assign soc_sdram_interface_bank7_valid = vns_rhs_array_muxed35;
-assign soc_port_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd0) & ((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0)))))) & soc_sdram_interface_bank7_ready));
-assign soc_cmd_ready = ((((((((1'd0 | (((vns_roundrobin0_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank0_ready)) | (((vns_roundrobin1_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank1_ready)) | (((vns_roundrobin2_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank2_ready)) | (((vns_roundrobin3_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank3_ready)) | (((vns_roundrobin4_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank4_ready)) | (((vns_roundrobin5_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank5_ready)) | (((vns_roundrobin6_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1)))))) & soc_sdram_interface_bank6_ready)) | (((vns_roundrobin7_grant == 1'd1) & ((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1)))))) & soc_sdram_interface_bank7_ready));
-assign soc_port_wdata_ready = vns_new_master_wdata_ready2;
-assign soc_wdata_ready = vns_new_master_wdata_ready5;
-assign soc_port_rdata_valid = vns_new_master_rdata_valid8;
-assign soc_rdata_valid = vns_new_master_rdata_valid17;
-
-// synthesis translate_off
-reg dummy_d_293;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_interface_wdata_we <= 16'd0;
-       case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2})
-               1'd1: begin
-                       soc_sdram_interface_wdata_we <= soc_port_wdata_payload_we;
-               end
-               2'd2: begin
-                       soc_sdram_interface_wdata_we <= soc_wdata_payload_we;
-               end
-               default: begin
-                       soc_sdram_interface_wdata_we <= 1'd0;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_293 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_294;
-// synthesis translate_on
-always @(*) begin
-       soc_sdram_interface_wdata <= 128'd0;
-       case ({vns_new_master_wdata_ready5, vns_new_master_wdata_ready2})
-               1'd1: begin
-                       soc_sdram_interface_wdata <= soc_port_wdata_payload_data;
-               end
-               2'd2: begin
-                       soc_sdram_interface_wdata <= soc_wdata_payload_data;
-               end
-               default: begin
-                       soc_sdram_interface_wdata <= 1'd0;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_294 = dummy_s;
-// synthesis translate_on
-end
-assign soc_port_rdata_payload_data = soc_sdram_interface_rdata;
-assign soc_rdata_payload_data = soc_sdram_interface_rdata;
-assign soc_address_d = soc_wb_sdram_adr;
-assign soc_counter_offset = soc_address_q;
-assign soc_counter_done = ((soc_counter + soc_counter_offset) == 2'd3);
-assign soc_end_of_burst = ((~soc_wb_sdram_cyc) | (((soc_wb_sdram_stb & soc_wb_sdram_cyc) & soc_wb_sdram_ack) & ((soc_wb_sdram_cti == 3'd7) | soc_counter_done)));
-assign soc_need_refill_reset = soc_end_of_burst;
-assign soc_need_refill_d = 1'd0;
-assign soc_litedram_wb_cti = 3'd7;
-assign soc_litedram_wb_adr = soc_address_q[29:2];
-assign soc_cached_sels_reset0 = soc_counter_reset;
-
-// synthesis translate_off
-reg dummy_d_295;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_flipflop0_d <= 32'd0;
-       if (soc_write) begin
-               soc_cached_datas_flipflop0_d <= soc_wb_sdram_dat_w;
-       end else begin
-               soc_cached_datas_flipflop0_d <= soc_litedram_wb_dat_r[31:0];
-       end
-// synthesis translate_off
-       dummy_d_295 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_flipflop0_d = soc_wb_sdram_sel;
-
-// synthesis translate_off
-reg dummy_d_296;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_sels_ce0 <= 1'd0;
-       if (((soc_write & soc_write_sel0) | soc_refill)) begin
-               soc_cached_sels_ce0 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_296 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_297;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_ce0 <= 1'd0;
-       if (((soc_write & soc_write_sel0) | soc_refill)) begin
-               soc_cached_datas_ce0 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_297 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_reset1 = soc_counter_reset;
-
-// synthesis translate_off
-reg dummy_d_298;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_flipflop1_d <= 32'd0;
-       if (soc_write) begin
-               soc_cached_datas_flipflop1_d <= soc_wb_sdram_dat_w;
-       end else begin
-               soc_cached_datas_flipflop1_d <= soc_litedram_wb_dat_r[63:32];
-       end
-// synthesis translate_off
-       dummy_d_298 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_flipflop1_d = soc_wb_sdram_sel;
-
-// synthesis translate_off
-reg dummy_d_299;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_sels_ce1 <= 1'd0;
-       if (((soc_write & soc_write_sel1) | soc_refill)) begin
-               soc_cached_sels_ce1 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_299 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_300;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_ce1 <= 1'd0;
-       if (((soc_write & soc_write_sel1) | soc_refill)) begin
-               soc_cached_datas_ce1 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_300 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_reset2 = soc_counter_reset;
-
-// synthesis translate_off
-reg dummy_d_301;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_flipflop2_d <= 32'd0;
-       if (soc_write) begin
-               soc_cached_datas_flipflop2_d <= soc_wb_sdram_dat_w;
-       end else begin
-               soc_cached_datas_flipflop2_d <= soc_litedram_wb_dat_r[95:64];
-       end
-// synthesis translate_off
-       dummy_d_301 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_flipflop2_d = soc_wb_sdram_sel;
-
-// synthesis translate_off
-reg dummy_d_302;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_sels_ce2 <= 1'd0;
-       if (((soc_write & soc_write_sel2) | soc_refill)) begin
-               soc_cached_sels_ce2 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_302 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_303;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_ce2 <= 1'd0;
-       if (((soc_write & soc_write_sel2) | soc_refill)) begin
-               soc_cached_datas_ce2 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_303 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_reset3 = soc_counter_reset;
-
-// synthesis translate_off
-reg dummy_d_304;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_flipflop3_d <= 32'd0;
-       if (soc_write) begin
-               soc_cached_datas_flipflop3_d <= soc_wb_sdram_dat_w;
-       end else begin
-               soc_cached_datas_flipflop3_d <= soc_litedram_wb_dat_r[127:96];
-       end
-// synthesis translate_off
-       dummy_d_304 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_sels_flipflop3_d = soc_wb_sdram_sel;
-
-// synthesis translate_off
-reg dummy_d_305;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_sels_ce3 <= 1'd0;
-       if (((soc_write & soc_write_sel3) | soc_refill)) begin
-               soc_cached_sels_ce3 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_305 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_306;
-// synthesis translate_on
-always @(*) begin
-       soc_cached_datas_ce3 <= 1'd0;
-       if (((soc_write & soc_write_sel3) | soc_refill)) begin
-               soc_cached_datas_ce3 <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_306 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_307;
-// synthesis translate_on
-always @(*) begin
-       soc_write_sel1 <= 1'd0;
-       case ((soc_counter + soc_counter_offset))
-               1'd0: begin
-               end
-               1'd1: begin
-                       soc_write_sel1 <= 1'd1;
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_307 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_308;
-// synthesis translate_on
-always @(*) begin
-       soc_write_sel0 <= 1'd0;
-       case ((soc_counter + soc_counter_offset))
-               1'd0: begin
-                       soc_write_sel0 <= 1'd1;
-               end
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_308 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_309;
-// synthesis translate_on
-always @(*) begin
-       soc_write_sel2 <= 1'd0;
-       case ((soc_counter + soc_counter_offset))
-               1'd0: begin
-               end
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_write_sel2 <= 1'd1;
-               end
-               2'd3: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_309 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_310;
-// synthesis translate_on
-always @(*) begin
-       soc_write_sel3 <= 1'd0;
-       case ((soc_counter + soc_counter_offset))
-               1'd0: begin
-               end
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       soc_write_sel3 <= 1'd1;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_310 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_311;
-// synthesis translate_on
-always @(*) begin
-       soc_wb_sdram_dat_r <= 32'd0;
-       case (soc_address_q[1:0])
-               1'd0: begin
-                       soc_wb_sdram_dat_r <= soc_cached_datas_flipflop0_q;
-               end
-               1'd1: begin
-                       soc_wb_sdram_dat_r <= soc_cached_datas_flipflop1_q;
-               end
-               2'd2: begin
-                       soc_wb_sdram_dat_r <= soc_cached_datas_flipflop2_q;
-               end
-               2'd3: begin
-                       soc_wb_sdram_dat_r <= soc_cached_datas_flipflop3_q;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_311 = dummy_s;
-// synthesis translate_on
-end
-assign soc_cached_data = {soc_cached_datas_flipflop3_q, soc_cached_datas_flipflop2_q, soc_cached_datas_flipflop1_q, soc_cached_datas_flipflop0_q};
-assign soc_cached_sel = {soc_cached_sels_flipflop3_q, soc_cached_sels_flipflop2_q, soc_cached_sels_flipflop1_q, soc_cached_sels_flipflop0_q};
-
-// synthesis translate_off
-reg dummy_d_312;
-// synthesis translate_on
-always @(*) begin
-       vns_converter_next_state <= 3'd0;
-       vns_converter_next_state <= vns_converter_state;
-       case (vns_converter_state)
-               1'd1: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               if (soc_counter_done) begin
-                                       vns_converter_next_state <= 2'd2;
-                               end
-                       end else begin
-                               if ((~soc_wb_sdram_cyc)) begin
-                                       vns_converter_next_state <= 2'd2;
-                               end
-                       end
-               end
-               2'd2: begin
-                       if (soc_litedram_wb_ack) begin
-                               vns_converter_next_state <= 1'd0;
-                       end
-               end
-               2'd3: begin
-                       if (soc_litedram_wb_ack) begin
-                               vns_converter_next_state <= 3'd4;
-                       end
-               end
-               3'd4: begin
-                       vns_converter_next_state <= 1'd0;
-               end
-               default: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               if (soc_wb_sdram_we) begin
-                                       vns_converter_next_state <= 1'd1;
-                               end else begin
-                                       if (soc_need_refill_q) begin
-                                               vns_converter_next_state <= 2'd3;
-                                       end else begin
-                                               vns_converter_next_state <= 3'd4;
-                                       end
-                               end
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_312 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_313;
-// synthesis translate_on
-always @(*) begin
-       soc_address_ce <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               soc_address_ce <= 1'd1;
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_313 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_314;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_dat_w <= 128'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_litedram_wb_dat_w <= soc_cached_data;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_314 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_315;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_sel <= 16'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_litedram_wb_sel <= soc_cached_sel;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_315 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_316;
-// synthesis translate_on
-always @(*) begin
-       soc_counter_ce <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               soc_counter_ce <= 1'd1;
-                       end else begin
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_316 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_317;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_cyc <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_litedram_wb_cyc <= 1'd1;
-               end
-               2'd3: begin
-                       soc_litedram_wb_cyc <= 1'd1;
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_317 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_318;
-// synthesis translate_on
-always @(*) begin
-       soc_counter_reset <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-                       soc_counter_reset <= 1'd1;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_318 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_319;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_stb <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_litedram_wb_stb <= 1'd1;
-               end
-               2'd3: begin
-                       soc_litedram_wb_stb <= 1'd1;
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_319 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_320;
-// synthesis translate_on
-always @(*) begin
-       soc_need_refill_ce <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       if (soc_litedram_wb_ack) begin
-                               soc_need_refill_ce <= 1'd1;
-                       end
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_320 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_321;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_we <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_litedram_wb_we <= 1'd1;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_321 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_322;
-// synthesis translate_on
-always @(*) begin
-       soc_write <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               soc_write <= 1'd1;
-                       end else begin
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_322 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_323;
-// synthesis translate_on
-always @(*) begin
-       soc_wb_sdram_ack <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               soc_wb_sdram_ack <= 1'd1;
-                       end else begin
-                       end
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-                       if ((soc_wb_sdram_stb & soc_wb_sdram_cyc)) begin
-                               soc_wb_sdram_ack <= 1'd1;
-                       end
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_323 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_324;
-// synthesis translate_on
-always @(*) begin
-       soc_evict <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-                       soc_evict <= 1'd1;
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_324 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_325;
-// synthesis translate_on
-always @(*) begin
-       soc_refill <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-                       soc_refill <= 1'd1;
-               end
-               3'd4: begin
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_325 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_326;
-// synthesis translate_on
-always @(*) begin
-       soc_read <= 1'd0;
-       case (vns_converter_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               2'd3: begin
-               end
-               3'd4: begin
-                       soc_read <= 1'd1;
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_326 = dummy_s;
-// synthesis translate_on
-end
-assign soc_wdata_converter_sink_valid = ((soc_litedram_wb_cyc & soc_litedram_wb_stb) & soc_litedram_wb_we);
-assign soc_wdata_converter_sink_payload_data = soc_litedram_wb_dat_w;
-assign soc_wdata_converter_sink_payload_we = soc_litedram_wb_sel;
-assign soc_port_wdata_valid = soc_wdata_converter_source_valid;
-assign soc_wdata_converter_source_ready = soc_port_wdata_ready;
-assign soc_port_wdata_first = soc_wdata_converter_source_first;
-assign soc_port_wdata_last = soc_wdata_converter_source_last;
-assign soc_port_wdata_payload_data = soc_wdata_converter_source_payload_data;
-assign soc_port_wdata_payload_we = soc_wdata_converter_source_payload_we;
-assign soc_rdata_converter_sink_valid = soc_port_rdata_valid;
-assign soc_port_rdata_ready = soc_rdata_converter_sink_ready;
-assign soc_rdata_converter_sink_first = soc_port_rdata_first;
-assign soc_rdata_converter_sink_last = soc_port_rdata_last;
-assign soc_rdata_converter_sink_payload_data = soc_port_rdata_payload_data;
-assign soc_rdata_converter_source_ready = 1'd1;
-assign soc_litedram_wb_dat_r = soc_rdata_converter_source_payload_data;
-assign soc_wdata_converter_converter_sink_valid = soc_wdata_converter_sink_valid;
-assign soc_wdata_converter_converter_sink_first = soc_wdata_converter_sink_first;
-assign soc_wdata_converter_converter_sink_last = soc_wdata_converter_sink_last;
-assign soc_wdata_converter_sink_ready = soc_wdata_converter_converter_sink_ready;
-assign soc_wdata_converter_converter_sink_payload_data = {soc_wdata_converter_sink_payload_we, soc_wdata_converter_sink_payload_data};
-assign soc_wdata_converter_source_valid = soc_wdata_converter_source_source_valid;
-assign soc_wdata_converter_source_first = soc_wdata_converter_source_source_first;
-assign soc_wdata_converter_source_last = soc_wdata_converter_source_source_last;
-assign soc_wdata_converter_source_source_ready = soc_wdata_converter_source_ready;
-assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data;
-assign {soc_wdata_converter_source_payload_we, soc_wdata_converter_source_payload_data} = soc_wdata_converter_source_source_payload_data;
-assign soc_wdata_converter_source_source_valid = soc_wdata_converter_converter_source_valid;
-assign soc_wdata_converter_converter_source_ready = soc_wdata_converter_source_source_ready;
-assign soc_wdata_converter_source_source_first = soc_wdata_converter_converter_source_first;
-assign soc_wdata_converter_source_source_last = soc_wdata_converter_converter_source_last;
-assign soc_wdata_converter_source_source_payload_data = soc_wdata_converter_converter_source_payload_data;
-assign soc_wdata_converter_converter_source_valid = soc_wdata_converter_converter_sink_valid;
-assign soc_wdata_converter_converter_sink_ready = soc_wdata_converter_converter_source_ready;
-assign soc_wdata_converter_converter_source_first = soc_wdata_converter_converter_sink_first;
-assign soc_wdata_converter_converter_source_last = soc_wdata_converter_converter_sink_last;
-assign soc_wdata_converter_converter_source_payload_data = soc_wdata_converter_converter_sink_payload_data;
-assign soc_wdata_converter_converter_source_payload_valid_token_count = 1'd1;
-assign soc_rdata_converter_converter_sink_valid = soc_rdata_converter_sink_valid;
-assign soc_rdata_converter_converter_sink_first = soc_rdata_converter_sink_first;
-assign soc_rdata_converter_converter_sink_last = soc_rdata_converter_sink_last;
-assign soc_rdata_converter_sink_ready = soc_rdata_converter_converter_sink_ready;
-assign soc_rdata_converter_converter_sink_payload_data = {soc_rdata_converter_sink_payload_data};
-assign soc_rdata_converter_source_valid = soc_rdata_converter_source_source_valid;
-assign soc_rdata_converter_source_first = soc_rdata_converter_source_source_first;
-assign soc_rdata_converter_source_last = soc_rdata_converter_source_source_last;
-assign soc_rdata_converter_source_source_ready = soc_rdata_converter_source_ready;
-assign {soc_rdata_converter_source_payload_data} = soc_rdata_converter_source_source_payload_data;
-assign soc_rdata_converter_source_source_valid = soc_rdata_converter_converter_source_valid;
-assign soc_rdata_converter_converter_source_ready = soc_rdata_converter_source_source_ready;
-assign soc_rdata_converter_source_source_first = soc_rdata_converter_converter_source_first;
-assign soc_rdata_converter_source_source_last = soc_rdata_converter_converter_source_last;
-assign soc_rdata_converter_source_source_payload_data = soc_rdata_converter_converter_source_payload_data;
-assign soc_rdata_converter_converter_source_valid = soc_rdata_converter_converter_sink_valid;
-assign soc_rdata_converter_converter_sink_ready = soc_rdata_converter_converter_source_ready;
-assign soc_rdata_converter_converter_source_first = soc_rdata_converter_converter_sink_first;
-assign soc_rdata_converter_converter_source_last = soc_rdata_converter_converter_sink_last;
-assign soc_rdata_converter_converter_source_payload_data = soc_rdata_converter_converter_sink_payload_data;
-assign soc_rdata_converter_converter_source_payload_valid_token_count = 1'd1;
-
-// synthesis translate_off
-reg dummy_d_327;
-// synthesis translate_on
-always @(*) begin
-       vns_litedramwishbone2native_next_state <= 2'd0;
-       vns_litedramwishbone2native_next_state <= vns_litedramwishbone2native_state;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-                       if (soc_wdata_converter_sink_ready) begin
-                               vns_litedramwishbone2native_next_state <= 1'd0;
-                       end
-               end
-               2'd2: begin
-                       if (soc_rdata_converter_source_valid) begin
-                               vns_litedramwishbone2native_next_state <= 1'd0;
-                       end
-               end
-               default: begin
-                       if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
-                               if ((soc_count == 1'd0)) begin
-                                       if (soc_litedram_wb_we) begin
-                                               vns_litedramwishbone2native_next_state <= 1'd1;
-                                       end else begin
-                                               vns_litedramwishbone2native_next_state <= 2'd2;
-                                       end
-                               end
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_327 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_328;
-// synthesis translate_on
-always @(*) begin
-       soc_count_next_value_ce <= 1'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               default: begin
-                       if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
-                               soc_count_next_value_ce <= 1'd1;
-                               if ((soc_count == 1'd0)) begin
-                                       soc_count_next_value_ce <= 1'd1;
-                               end
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_328 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_329;
-// synthesis translate_on
-always @(*) begin
-       soc_port_cmd_valid <= 1'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               default: begin
-                       soc_port_cmd_valid <= (soc_litedram_wb_cyc & soc_litedram_wb_stb);
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_329 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_330;
-// synthesis translate_on
-always @(*) begin
-       soc_litedram_wb_ack <= 1'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-                       if (soc_wdata_converter_sink_ready) begin
-                               soc_litedram_wb_ack <= 1'd1;
-                       end
-               end
-               2'd2: begin
-                       if (soc_rdata_converter_source_valid) begin
-                               soc_litedram_wb_ack <= 1'd1;
-                       end
-               end
-               default: begin
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_330 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_331;
-// synthesis translate_on
-always @(*) begin
-       soc_port_cmd_payload_we <= 1'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               default: begin
-                       soc_port_cmd_payload_we <= soc_litedram_wb_we;
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_331 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_332;
-// synthesis translate_on
-always @(*) begin
-       soc_port_cmd_payload_addr <= 25'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               default: begin
-                       soc_port_cmd_payload_addr <= (((soc_litedram_wb_adr * 1'd1) + soc_count) - 27'd67108864);
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_332 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_333;
-// synthesis translate_on
-always @(*) begin
-       soc_count_next_value <= 1'd0;
-       case (vns_litedramwishbone2native_state)
-               1'd1: begin
-               end
-               2'd2: begin
-               end
-               default: begin
-                       if ((soc_port_cmd_valid & soc_port_cmd_ready)) begin
-                               soc_count_next_value <= (soc_count + 1'd1);
-                               if ((soc_count == 1'd0)) begin
-                                       soc_count_next_value <= 1'd0;
-                               end
-                       end
-               end
-       endcase
-// synthesis translate_off
-       dummy_d_333 = dummy_s;
-// synthesis translate_on
-end
-assign vns_shared_adr = vns_rhs_array_muxed36;
-assign vns_shared_dat_w = vns_rhs_array_muxed37;
-assign vns_shared_sel = vns_rhs_array_muxed38;
-assign vns_shared_cyc = vns_rhs_array_muxed39;
-assign vns_shared_stb = vns_rhs_array_muxed40;
-assign vns_shared_we = vns_rhs_array_muxed41;
-assign vns_shared_cti = vns_rhs_array_muxed42;
-assign vns_shared_bte = vns_rhs_array_muxed43;
-assign soc_litedramcore_cpu_ibus_dat_r = vns_shared_dat_r;
-assign soc_litedramcore_cpu_dbus_dat_r = vns_shared_dat_r;
-assign soc_litedramcore_cpu_ibus_ack = (vns_shared_ack & (vns_grant == 1'd0));
-assign soc_litedramcore_cpu_dbus_ack = (vns_shared_ack & (vns_grant == 1'd1));
-assign soc_litedramcore_cpu_ibus_err = (vns_shared_err & (vns_grant == 1'd0));
-assign soc_litedramcore_cpu_dbus_err = (vns_shared_err & (vns_grant == 1'd1));
-assign vns_request = {soc_litedramcore_cpu_dbus_cyc, soc_litedramcore_cpu_ibus_cyc};
-
-// synthesis translate_off
-reg dummy_d_334;
-// synthesis translate_on
-always @(*) begin
-       vns_slave_sel <= 4'd0;
-       vns_slave_sel[0] <= (vns_shared_adr[29:13] == 1'd0);
-       vns_slave_sel[1] <= (vns_shared_adr[29:10] == 13'd4096);
-       vns_slave_sel[2] <= (vns_shared_adr[29:14] == 16'd33280);
-       vns_slave_sel[3] <= (vns_shared_adr[29:22] == 7'd64);
-// synthesis translate_off
-       dummy_d_334 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_litedramcore_ram_bus_adr = vns_shared_adr;
-assign soc_litedramcore_litedramcore_ram_bus_dat_w = vns_shared_dat_w;
-assign soc_litedramcore_litedramcore_ram_bus_sel = vns_shared_sel;
-assign soc_litedramcore_litedramcore_ram_bus_stb = vns_shared_stb;
-assign soc_litedramcore_litedramcore_ram_bus_we = vns_shared_we;
-assign soc_litedramcore_litedramcore_ram_bus_cti = vns_shared_cti;
-assign soc_litedramcore_litedramcore_ram_bus_bte = vns_shared_bte;
-assign soc_litedramcore_ram_bus_ram_bus_adr = vns_shared_adr;
-assign soc_litedramcore_ram_bus_ram_bus_dat_w = vns_shared_dat_w;
-assign soc_litedramcore_ram_bus_ram_bus_sel = vns_shared_sel;
-assign soc_litedramcore_ram_bus_ram_bus_stb = vns_shared_stb;
-assign soc_litedramcore_ram_bus_ram_bus_we = vns_shared_we;
-assign soc_litedramcore_ram_bus_ram_bus_cti = vns_shared_cti;
-assign soc_litedramcore_ram_bus_ram_bus_bte = vns_shared_bte;
-assign soc_litedramcore_bus_wishbone_adr = vns_shared_adr;
-assign soc_litedramcore_bus_wishbone_dat_w = vns_shared_dat_w;
-assign soc_litedramcore_bus_wishbone_sel = vns_shared_sel;
-assign soc_litedramcore_bus_wishbone_stb = vns_shared_stb;
-assign soc_litedramcore_bus_wishbone_we = vns_shared_we;
-assign soc_litedramcore_bus_wishbone_cti = vns_shared_cti;
-assign soc_litedramcore_bus_wishbone_bte = vns_shared_bte;
-assign soc_wb_sdram_adr = vns_shared_adr;
-assign soc_wb_sdram_dat_w = vns_shared_dat_w;
-assign soc_wb_sdram_sel = vns_shared_sel;
-assign soc_wb_sdram_stb = vns_shared_stb;
-assign soc_wb_sdram_we = vns_shared_we;
-assign soc_wb_sdram_cti = vns_shared_cti;
-assign soc_wb_sdram_bte = vns_shared_bte;
-assign soc_litedramcore_litedramcore_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[0]);
-assign soc_litedramcore_ram_bus_ram_bus_cyc = (vns_shared_cyc & vns_slave_sel[1]);
-assign soc_litedramcore_bus_wishbone_cyc = (vns_shared_cyc & vns_slave_sel[2]);
-assign soc_wb_sdram_cyc = (vns_shared_cyc & vns_slave_sel[3]);
-
-// synthesis translate_off
-reg dummy_d_335;
-// synthesis translate_on
-always @(*) begin
-       vns_shared_ack <= 1'd0;
-       vns_shared_ack <= (((soc_litedramcore_litedramcore_ram_bus_ack | soc_litedramcore_ram_bus_ram_bus_ack) | soc_litedramcore_bus_wishbone_ack) | soc_wb_sdram_ack);
-       if (vns_done) begin
-               vns_shared_ack <= 1'd1;
-       end
-// synthesis translate_off
-       dummy_d_335 = dummy_s;
-// synthesis translate_on
-end
-assign vns_shared_err = (((soc_litedramcore_litedramcore_ram_bus_err | soc_litedramcore_ram_bus_ram_bus_err) | soc_litedramcore_bus_wishbone_err) | soc_wb_sdram_err);
-
-// synthesis translate_off
-reg dummy_d_336;
-// synthesis translate_on
-always @(*) begin
-       vns_shared_dat_r <= 32'd0;
-       vns_shared_dat_r <= (((({32{vns_slave_sel_r[0]}} & soc_litedramcore_litedramcore_ram_bus_dat_r) | ({32{vns_slave_sel_r[1]}} & soc_litedramcore_ram_bus_ram_bus_dat_r)) | ({32{vns_slave_sel_r[2]}} & soc_litedramcore_bus_wishbone_dat_r)) | ({32{vns_slave_sel_r[3]}} & soc_wb_sdram_dat_r));
-       if (vns_done) begin
-               vns_shared_dat_r <= 32'd4294967295;
-       end
-// synthesis translate_off
-       dummy_d_336 = dummy_s;
-// synthesis translate_on
-end
-assign vns_wait = ((vns_shared_stb & vns_shared_cyc) & (~vns_shared_ack));
-
-// synthesis translate_off
-reg dummy_d_337;
-// synthesis translate_on
-always @(*) begin
-       vns_error <= 1'd0;
-       if (vns_done) begin
-               vns_error <= 1'd1;
-       end
+               end
+               default: begin
+                       if (1'd0) begin
+                       end else begin
+                               litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+                       end
+               end
+       endcase
 // synthesis translate_off
-       dummy_d_337 = dummy_s;
+       dummy_d_273 = dummy_s;
 // synthesis translate_on
 end
-assign vns_done = (vns_count == 1'd0);
-assign vns_csrbank0_sel = (vns_interface0_bank_bus_adr[13:9] == 1'd0);
-assign vns_csrbank0_reset0_r = vns_interface0_bank_bus_dat_w[0];
-assign vns_csrbank0_reset0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd0));
-assign vns_csrbank0_reset0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd0));
-assign vns_csrbank0_scratch3_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_scratch3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 1'd1));
-assign vns_csrbank0_scratch3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 1'd1));
-assign vns_csrbank0_scratch2_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_scratch2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd2));
-assign vns_csrbank0_scratch2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd2));
-assign vns_csrbank0_scratch1_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_scratch1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 2'd3));
-assign vns_csrbank0_scratch1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 2'd3));
-assign vns_csrbank0_scratch0_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_scratch0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd4));
-assign vns_csrbank0_scratch0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd4));
-assign vns_csrbank0_bus_errors3_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_bus_errors3_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd5));
-assign vns_csrbank0_bus_errors3_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd5));
-assign vns_csrbank0_bus_errors2_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_bus_errors2_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd6));
-assign vns_csrbank0_bus_errors2_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd6));
-assign vns_csrbank0_bus_errors1_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_bus_errors1_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 3'd7));
-assign vns_csrbank0_bus_errors1_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 3'd7));
-assign vns_csrbank0_bus_errors0_r = vns_interface0_bank_bus_dat_w[7:0];
-assign vns_csrbank0_bus_errors0_re = ((vns_csrbank0_sel & vns_interface0_bank_bus_we) & (vns_interface0_bank_bus_adr[3:0] == 4'd8));
-assign vns_csrbank0_bus_errors0_we = ((vns_csrbank0_sel & (~vns_interface0_bank_bus_we)) & (vns_interface0_bank_bus_adr[3:0] == 4'd8));
-assign vns_csrbank0_reset0_w = soc_litedramcore_soccontroller_reset_storage;
-assign vns_csrbank0_scratch3_w = soc_litedramcore_soccontroller_scratch_storage[31:24];
-assign vns_csrbank0_scratch2_w = soc_litedramcore_soccontroller_scratch_storage[23:16];
-assign vns_csrbank0_scratch1_w = soc_litedramcore_soccontroller_scratch_storage[15:8];
-assign vns_csrbank0_scratch0_w = soc_litedramcore_soccontroller_scratch_storage[7:0];
-assign vns_csrbank0_bus_errors3_w = soc_litedramcore_soccontroller_bus_errors_status[31:24];
-assign vns_csrbank0_bus_errors2_w = soc_litedramcore_soccontroller_bus_errors_status[23:16];
-assign vns_csrbank0_bus_errors1_w = soc_litedramcore_soccontroller_bus_errors_status[15:8];
-assign vns_csrbank0_bus_errors0_w = soc_litedramcore_soccontroller_bus_errors_status[7:0];
-assign soc_litedramcore_soccontroller_bus_errors_we = vns_csrbank0_bus_errors0_we;
-assign vns_csrbank1_sel = (vns_interface1_bank_bus_adr[13:9] == 3'd7);
-assign vns_csrbank1_init_done0_r = vns_interface1_bank_bus_dat_w[0];
-assign vns_csrbank1_init_done0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd0));
-assign vns_csrbank1_init_done0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd0));
-assign vns_csrbank1_init_error0_r = vns_interface1_bank_bus_dat_w[0];
-assign vns_csrbank1_init_error0_re = ((vns_csrbank1_sel & vns_interface1_bank_bus_we) & (vns_interface1_bank_bus_adr[0] == 1'd1));
-assign vns_csrbank1_init_error0_we = ((vns_csrbank1_sel & (~vns_interface1_bank_bus_we)) & (vns_interface1_bank_bus_adr[0] == 1'd1));
-assign vns_csrbank1_init_done0_w = soc_init_done_storage;
-assign vns_csrbank1_init_error0_w = soc_init_error_storage;
-assign vns_csrbank2_sel = (vns_interface2_bank_bus_adr[13:9] == 3'd5);
-assign vns_csrbank2_half_sys8x_taps0_r = vns_interface2_bank_bus_dat_w[4:0];
-assign vns_csrbank2_half_sys8x_taps0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd0));
-assign vns_csrbank2_half_sys8x_taps0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd0));
-assign vns_csrbank2_wlevel_en0_r = vns_interface2_bank_bus_dat_w[0];
-assign vns_csrbank2_wlevel_en0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 1'd1));
-assign vns_csrbank2_wlevel_en0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 1'd1));
-assign soc_a7ddrphy_wlevel_strobe_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_wlevel_strobe_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd2));
-assign soc_a7ddrphy_wlevel_strobe_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd2));
-assign soc_a7ddrphy_cdly_rst_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_cdly_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 2'd3));
-assign soc_a7ddrphy_cdly_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 2'd3));
-assign soc_a7ddrphy_cdly_inc_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_cdly_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd4));
-assign soc_a7ddrphy_cdly_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd4));
-assign vns_csrbank2_dly_sel0_r = vns_interface2_bank_bus_dat_w[1:0];
-assign vns_csrbank2_dly_sel0_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd5));
-assign vns_csrbank2_dly_sel0_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd5));
-assign soc_a7ddrphy_rdly_dq_rst_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd6));
-assign soc_a7ddrphy_rdly_dq_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd6));
-assign soc_a7ddrphy_rdly_dq_inc_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_inc_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 3'd7));
-assign soc_a7ddrphy_rdly_dq_inc_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 3'd7));
-assign soc_a7ddrphy_rdly_dq_bitslip_rst_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_bitslip_rst_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd8));
-assign soc_a7ddrphy_rdly_dq_bitslip_rst_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd8));
-assign soc_a7ddrphy_rdly_dq_bitslip_r = vns_interface2_bank_bus_dat_w[0];
-assign soc_a7ddrphy_rdly_dq_bitslip_re = ((vns_csrbank2_sel & vns_interface2_bank_bus_we) & (vns_interface2_bank_bus_adr[3:0] == 4'd9));
-assign soc_a7ddrphy_rdly_dq_bitslip_we = ((vns_csrbank2_sel & (~vns_interface2_bank_bus_we)) & (vns_interface2_bank_bus_adr[3:0] == 4'd9));
-assign vns_csrbank2_half_sys8x_taps0_w = soc_a7ddrphy_half_sys8x_taps_storage[4:0];
-assign vns_csrbank2_wlevel_en0_w = soc_a7ddrphy_wlevel_en_storage;
-assign vns_csrbank2_dly_sel0_w = soc_a7ddrphy_dly_sel_storage[1:0];
-assign vns_csrbank3_sel = (vns_interface3_bank_bus_adr[13:9] == 3'd6);
-assign vns_csrbank3_dfii_control0_r = vns_interface3_bank_bus_dat_w[3:0];
-assign vns_csrbank3_dfii_control0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd0));
-assign vns_csrbank3_dfii_control0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd0));
-assign vns_csrbank3_dfii_pi0_command0_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi0_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 1'd1));
-assign vns_csrbank3_dfii_pi0_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 1'd1));
-assign soc_sdram_phaseinjector0_command_issue_r = vns_interface3_bank_bus_dat_w[0];
-assign soc_sdram_phaseinjector0_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd2));
-assign soc_sdram_phaseinjector0_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd2));
-assign vns_csrbank3_dfii_pi0_address1_r = vns_interface3_bank_bus_dat_w[6:0];
-assign vns_csrbank3_dfii_pi0_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 2'd3));
-assign vns_csrbank3_dfii_pi0_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 2'd3));
-assign vns_csrbank3_dfii_pi0_address0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd4));
-assign vns_csrbank3_dfii_pi0_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd4));
-assign vns_csrbank3_dfii_pi0_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
-assign vns_csrbank3_dfii_pi0_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd5));
-assign vns_csrbank3_dfii_pi0_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd5));
-assign vns_csrbank3_dfii_pi0_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd6));
-assign vns_csrbank3_dfii_pi0_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd6));
-assign vns_csrbank3_dfii_pi0_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 3'd7));
-assign vns_csrbank3_dfii_pi0_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 3'd7));
-assign vns_csrbank3_dfii_pi0_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd8));
-assign vns_csrbank3_dfii_pi0_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd8));
-assign vns_csrbank3_dfii_pi0_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd9));
-assign vns_csrbank3_dfii_pi0_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd9));
-assign vns_csrbank3_dfii_pi0_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd10));
-assign vns_csrbank3_dfii_pi0_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd10));
-assign vns_csrbank3_dfii_pi0_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd11));
-assign vns_csrbank3_dfii_pi0_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd11));
-assign vns_csrbank3_dfii_pi0_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd12));
-assign vns_csrbank3_dfii_pi0_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd12));
-assign vns_csrbank3_dfii_pi0_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi0_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd13));
-assign vns_csrbank3_dfii_pi0_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd13));
-assign vns_csrbank3_dfii_pi1_command0_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi1_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd14));
-assign vns_csrbank3_dfii_pi1_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd14));
-assign soc_sdram_phaseinjector1_command_issue_r = vns_interface3_bank_bus_dat_w[0];
-assign soc_sdram_phaseinjector1_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 4'd15));
-assign soc_sdram_phaseinjector1_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 4'd15));
-assign vns_csrbank3_dfii_pi1_address1_r = vns_interface3_bank_bus_dat_w[6:0];
-assign vns_csrbank3_dfii_pi1_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd16));
-assign vns_csrbank3_dfii_pi1_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd16));
-assign vns_csrbank3_dfii_pi1_address0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd17));
-assign vns_csrbank3_dfii_pi1_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd17));
-assign vns_csrbank3_dfii_pi1_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
-assign vns_csrbank3_dfii_pi1_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd18));
-assign vns_csrbank3_dfii_pi1_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd18));
-assign vns_csrbank3_dfii_pi1_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd19));
-assign vns_csrbank3_dfii_pi1_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd19));
-assign vns_csrbank3_dfii_pi1_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd20));
-assign vns_csrbank3_dfii_pi1_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd20));
-assign vns_csrbank3_dfii_pi1_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd21));
-assign vns_csrbank3_dfii_pi1_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd21));
-assign vns_csrbank3_dfii_pi1_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd22));
-assign vns_csrbank3_dfii_pi1_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd22));
-assign vns_csrbank3_dfii_pi1_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd23));
-assign vns_csrbank3_dfii_pi1_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd23));
-assign vns_csrbank3_dfii_pi1_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd24));
-assign vns_csrbank3_dfii_pi1_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd24));
-assign vns_csrbank3_dfii_pi1_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd25));
-assign vns_csrbank3_dfii_pi1_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd25));
-assign vns_csrbank3_dfii_pi1_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi1_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd26));
-assign vns_csrbank3_dfii_pi1_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd26));
-assign vns_csrbank3_dfii_pi2_command0_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi2_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd27));
-assign vns_csrbank3_dfii_pi2_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd27));
-assign soc_sdram_phaseinjector2_command_issue_r = vns_interface3_bank_bus_dat_w[0];
-assign soc_sdram_phaseinjector2_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd28));
-assign soc_sdram_phaseinjector2_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd28));
-assign vns_csrbank3_dfii_pi2_address1_r = vns_interface3_bank_bus_dat_w[6:0];
-assign vns_csrbank3_dfii_pi2_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd29));
-assign vns_csrbank3_dfii_pi2_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd29));
-assign vns_csrbank3_dfii_pi2_address0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd30));
-assign vns_csrbank3_dfii_pi2_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd30));
-assign vns_csrbank3_dfii_pi2_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
-assign vns_csrbank3_dfii_pi2_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 5'd31));
-assign vns_csrbank3_dfii_pi2_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 5'd31));
-assign vns_csrbank3_dfii_pi2_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd32));
-assign vns_csrbank3_dfii_pi2_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd32));
-assign vns_csrbank3_dfii_pi2_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd33));
-assign vns_csrbank3_dfii_pi2_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd33));
-assign vns_csrbank3_dfii_pi2_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd34));
-assign vns_csrbank3_dfii_pi2_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd34));
-assign vns_csrbank3_dfii_pi2_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd35));
-assign vns_csrbank3_dfii_pi2_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd35));
-assign vns_csrbank3_dfii_pi2_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd36));
-assign vns_csrbank3_dfii_pi2_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd36));
-assign vns_csrbank3_dfii_pi2_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd37));
-assign vns_csrbank3_dfii_pi2_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd37));
-assign vns_csrbank3_dfii_pi2_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd38));
-assign vns_csrbank3_dfii_pi2_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd38));
-assign vns_csrbank3_dfii_pi2_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi2_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd39));
-assign vns_csrbank3_dfii_pi2_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd39));
-assign vns_csrbank3_dfii_pi3_command0_r = vns_interface3_bank_bus_dat_w[5:0];
-assign vns_csrbank3_dfii_pi3_command0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd40));
-assign vns_csrbank3_dfii_pi3_command0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd40));
-assign soc_sdram_phaseinjector3_command_issue_r = vns_interface3_bank_bus_dat_w[0];
-assign soc_sdram_phaseinjector3_command_issue_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd41));
-assign soc_sdram_phaseinjector3_command_issue_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd41));
-assign vns_csrbank3_dfii_pi3_address1_r = vns_interface3_bank_bus_dat_w[6:0];
-assign vns_csrbank3_dfii_pi3_address1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd42));
-assign vns_csrbank3_dfii_pi3_address1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd42));
-assign vns_csrbank3_dfii_pi3_address0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_address0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd43));
-assign vns_csrbank3_dfii_pi3_address0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd43));
-assign vns_csrbank3_dfii_pi3_baddress0_r = vns_interface3_bank_bus_dat_w[2:0];
-assign vns_csrbank3_dfii_pi3_baddress0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd44));
-assign vns_csrbank3_dfii_pi3_baddress0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd44));
-assign vns_csrbank3_dfii_pi3_wrdata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_wrdata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd45));
-assign vns_csrbank3_dfii_pi3_wrdata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd45));
-assign vns_csrbank3_dfii_pi3_wrdata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_wrdata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd46));
-assign vns_csrbank3_dfii_pi3_wrdata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd46));
-assign vns_csrbank3_dfii_pi3_wrdata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_wrdata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd47));
-assign vns_csrbank3_dfii_pi3_wrdata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd47));
-assign vns_csrbank3_dfii_pi3_wrdata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_wrdata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd48));
-assign vns_csrbank3_dfii_pi3_wrdata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd48));
-assign vns_csrbank3_dfii_pi3_rddata3_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_rddata3_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd49));
-assign vns_csrbank3_dfii_pi3_rddata3_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd49));
-assign vns_csrbank3_dfii_pi3_rddata2_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_rddata2_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd50));
-assign vns_csrbank3_dfii_pi3_rddata2_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd50));
-assign vns_csrbank3_dfii_pi3_rddata1_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_rddata1_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd51));
-assign vns_csrbank3_dfii_pi3_rddata1_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd51));
-assign vns_csrbank3_dfii_pi3_rddata0_r = vns_interface3_bank_bus_dat_w[7:0];
-assign vns_csrbank3_dfii_pi3_rddata0_re = ((vns_csrbank3_sel & vns_interface3_bank_bus_we) & (vns_interface3_bank_bus_adr[5:0] == 6'd52));
-assign vns_csrbank3_dfii_pi3_rddata0_we = ((vns_csrbank3_sel & (~vns_interface3_bank_bus_we)) & (vns_interface3_bank_bus_adr[5:0] == 6'd52));
-assign vns_csrbank3_dfii_control0_w = soc_sdram_storage[3:0];
-assign vns_csrbank3_dfii_pi0_command0_w = soc_sdram_phaseinjector0_command_storage[5:0];
-assign vns_csrbank3_dfii_pi0_address1_w = soc_sdram_phaseinjector0_address_storage[14:8];
-assign vns_csrbank3_dfii_pi0_address0_w = soc_sdram_phaseinjector0_address_storage[7:0];
-assign vns_csrbank3_dfii_pi0_baddress0_w = soc_sdram_phaseinjector0_baddress_storage[2:0];
-assign vns_csrbank3_dfii_pi0_wrdata3_w = soc_sdram_phaseinjector0_wrdata_storage[31:24];
-assign vns_csrbank3_dfii_pi0_wrdata2_w = soc_sdram_phaseinjector0_wrdata_storage[23:16];
-assign vns_csrbank3_dfii_pi0_wrdata1_w = soc_sdram_phaseinjector0_wrdata_storage[15:8];
-assign vns_csrbank3_dfii_pi0_wrdata0_w = soc_sdram_phaseinjector0_wrdata_storage[7:0];
-assign vns_csrbank3_dfii_pi0_rddata3_w = soc_sdram_phaseinjector0_status[31:24];
-assign vns_csrbank3_dfii_pi0_rddata2_w = soc_sdram_phaseinjector0_status[23:16];
-assign vns_csrbank3_dfii_pi0_rddata1_w = soc_sdram_phaseinjector0_status[15:8];
-assign vns_csrbank3_dfii_pi0_rddata0_w = soc_sdram_phaseinjector0_status[7:0];
-assign soc_sdram_phaseinjector0_we = vns_csrbank3_dfii_pi0_rddata0_we;
-assign vns_csrbank3_dfii_pi1_command0_w = soc_sdram_phaseinjector1_command_storage[5:0];
-assign vns_csrbank3_dfii_pi1_address1_w = soc_sdram_phaseinjector1_address_storage[14:8];
-assign vns_csrbank3_dfii_pi1_address0_w = soc_sdram_phaseinjector1_address_storage[7:0];
-assign vns_csrbank3_dfii_pi1_baddress0_w = soc_sdram_phaseinjector1_baddress_storage[2:0];
-assign vns_csrbank3_dfii_pi1_wrdata3_w = soc_sdram_phaseinjector1_wrdata_storage[31:24];
-assign vns_csrbank3_dfii_pi1_wrdata2_w = soc_sdram_phaseinjector1_wrdata_storage[23:16];
-assign vns_csrbank3_dfii_pi1_wrdata1_w = soc_sdram_phaseinjector1_wrdata_storage[15:8];
-assign vns_csrbank3_dfii_pi1_wrdata0_w = soc_sdram_phaseinjector1_wrdata_storage[7:0];
-assign vns_csrbank3_dfii_pi1_rddata3_w = soc_sdram_phaseinjector1_status[31:24];
-assign vns_csrbank3_dfii_pi1_rddata2_w = soc_sdram_phaseinjector1_status[23:16];
-assign vns_csrbank3_dfii_pi1_rddata1_w = soc_sdram_phaseinjector1_status[15:8];
-assign vns_csrbank3_dfii_pi1_rddata0_w = soc_sdram_phaseinjector1_status[7:0];
-assign soc_sdram_phaseinjector1_we = vns_csrbank3_dfii_pi1_rddata0_we;
-assign vns_csrbank3_dfii_pi2_command0_w = soc_sdram_phaseinjector2_command_storage[5:0];
-assign vns_csrbank3_dfii_pi2_address1_w = soc_sdram_phaseinjector2_address_storage[14:8];
-assign vns_csrbank3_dfii_pi2_address0_w = soc_sdram_phaseinjector2_address_storage[7:0];
-assign vns_csrbank3_dfii_pi2_baddress0_w = soc_sdram_phaseinjector2_baddress_storage[2:0];
-assign vns_csrbank3_dfii_pi2_wrdata3_w = soc_sdram_phaseinjector2_wrdata_storage[31:24];
-assign vns_csrbank3_dfii_pi2_wrdata2_w = soc_sdram_phaseinjector2_wrdata_storage[23:16];
-assign vns_csrbank3_dfii_pi2_wrdata1_w = soc_sdram_phaseinjector2_wrdata_storage[15:8];
-assign vns_csrbank3_dfii_pi2_wrdata0_w = soc_sdram_phaseinjector2_wrdata_storage[7:0];
-assign vns_csrbank3_dfii_pi2_rddata3_w = soc_sdram_phaseinjector2_status[31:24];
-assign vns_csrbank3_dfii_pi2_rddata2_w = soc_sdram_phaseinjector2_status[23:16];
-assign vns_csrbank3_dfii_pi2_rddata1_w = soc_sdram_phaseinjector2_status[15:8];
-assign vns_csrbank3_dfii_pi2_rddata0_w = soc_sdram_phaseinjector2_status[7:0];
-assign soc_sdram_phaseinjector2_we = vns_csrbank3_dfii_pi2_rddata0_we;
-assign vns_csrbank3_dfii_pi3_command0_w = soc_sdram_phaseinjector3_command_storage[5:0];
-assign vns_csrbank3_dfii_pi3_address1_w = soc_sdram_phaseinjector3_address_storage[14:8];
-assign vns_csrbank3_dfii_pi3_address0_w = soc_sdram_phaseinjector3_address_storage[7:0];
-assign vns_csrbank3_dfii_pi3_baddress0_w = soc_sdram_phaseinjector3_baddress_storage[2:0];
-assign vns_csrbank3_dfii_pi3_wrdata3_w = soc_sdram_phaseinjector3_wrdata_storage[31:24];
-assign vns_csrbank3_dfii_pi3_wrdata2_w = soc_sdram_phaseinjector3_wrdata_storage[23:16];
-assign vns_csrbank3_dfii_pi3_wrdata1_w = soc_sdram_phaseinjector3_wrdata_storage[15:8];
-assign vns_csrbank3_dfii_pi3_wrdata0_w = soc_sdram_phaseinjector3_wrdata_storage[7:0];
-assign vns_csrbank3_dfii_pi3_rddata3_w = soc_sdram_phaseinjector3_status[31:24];
-assign vns_csrbank3_dfii_pi3_rddata2_w = soc_sdram_phaseinjector3_status[23:16];
-assign vns_csrbank3_dfii_pi3_rddata1_w = soc_sdram_phaseinjector3_status[15:8];
-assign vns_csrbank3_dfii_pi3_rddata0_w = soc_sdram_phaseinjector3_status[7:0];
-assign soc_sdram_phaseinjector3_we = vns_csrbank3_dfii_pi3_rddata0_we;
-assign vns_csrbank4_sel = (vns_interface4_bank_bus_adr[13:9] == 3'd4);
-assign vns_csrbank4_load3_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_load3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd0));
-assign vns_csrbank4_load3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd0));
-assign vns_csrbank4_load2_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_load2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 1'd1));
-assign vns_csrbank4_load2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 1'd1));
-assign vns_csrbank4_load1_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_load1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd2));
-assign vns_csrbank4_load1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd2));
-assign vns_csrbank4_load0_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_load0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 2'd3));
-assign vns_csrbank4_load0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 2'd3));
-assign vns_csrbank4_reload3_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_reload3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd4));
-assign vns_csrbank4_reload3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd4));
-assign vns_csrbank4_reload2_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_reload2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd5));
-assign vns_csrbank4_reload2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd5));
-assign vns_csrbank4_reload1_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_reload1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd6));
-assign vns_csrbank4_reload1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd6));
-assign vns_csrbank4_reload0_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_reload0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 3'd7));
-assign vns_csrbank4_reload0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 3'd7));
-assign vns_csrbank4_en0_r = vns_interface4_bank_bus_dat_w[0];
-assign vns_csrbank4_en0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd8));
-assign vns_csrbank4_en0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd8));
-assign vns_csrbank4_update_value0_r = vns_interface4_bank_bus_dat_w[0];
-assign vns_csrbank4_update_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd9));
-assign vns_csrbank4_update_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd9));
-assign vns_csrbank4_value3_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_value3_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd10));
-assign vns_csrbank4_value3_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd10));
-assign vns_csrbank4_value2_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_value2_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd11));
-assign vns_csrbank4_value2_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd11));
-assign vns_csrbank4_value1_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_value1_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd12));
-assign vns_csrbank4_value1_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd12));
-assign vns_csrbank4_value0_r = vns_interface4_bank_bus_dat_w[7:0];
-assign vns_csrbank4_value0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd13));
-assign vns_csrbank4_value0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd13));
-assign soc_litedramcore_timer_eventmanager_status_r = vns_interface4_bank_bus_dat_w[0];
-assign soc_litedramcore_timer_eventmanager_status_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd14));
-assign soc_litedramcore_timer_eventmanager_status_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd14));
-assign soc_litedramcore_timer_eventmanager_pending_r = vns_interface4_bank_bus_dat_w[0];
-assign soc_litedramcore_timer_eventmanager_pending_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 4'd15));
-assign soc_litedramcore_timer_eventmanager_pending_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 4'd15));
-assign vns_csrbank4_ev_enable0_r = vns_interface4_bank_bus_dat_w[0];
-assign vns_csrbank4_ev_enable0_re = ((vns_csrbank4_sel & vns_interface4_bank_bus_we) & (vns_interface4_bank_bus_adr[4:0] == 5'd16));
-assign vns_csrbank4_ev_enable0_we = ((vns_csrbank4_sel & (~vns_interface4_bank_bus_we)) & (vns_interface4_bank_bus_adr[4:0] == 5'd16));
-assign vns_csrbank4_load3_w = soc_litedramcore_timer_load_storage[31:24];
-assign vns_csrbank4_load2_w = soc_litedramcore_timer_load_storage[23:16];
-assign vns_csrbank4_load1_w = soc_litedramcore_timer_load_storage[15:8];
-assign vns_csrbank4_load0_w = soc_litedramcore_timer_load_storage[7:0];
-assign vns_csrbank4_reload3_w = soc_litedramcore_timer_reload_storage[31:24];
-assign vns_csrbank4_reload2_w = soc_litedramcore_timer_reload_storage[23:16];
-assign vns_csrbank4_reload1_w = soc_litedramcore_timer_reload_storage[15:8];
-assign vns_csrbank4_reload0_w = soc_litedramcore_timer_reload_storage[7:0];
-assign vns_csrbank4_en0_w = soc_litedramcore_timer_en_storage;
-assign vns_csrbank4_update_value0_w = soc_litedramcore_timer_update_value_storage;
-assign vns_csrbank4_value3_w = soc_litedramcore_timer_value_status[31:24];
-assign vns_csrbank4_value2_w = soc_litedramcore_timer_value_status[23:16];
-assign vns_csrbank4_value1_w = soc_litedramcore_timer_value_status[15:8];
-assign vns_csrbank4_value0_w = soc_litedramcore_timer_value_status[7:0];
-assign soc_litedramcore_timer_value_we = vns_csrbank4_value0_we;
-assign vns_csrbank4_ev_enable0_w = soc_litedramcore_timer_eventmanager_storage;
-assign vns_csrbank5_sel = (vns_interface5_bank_bus_adr[13:9] == 2'd3);
-assign soc_litedramcore_uart_rxtx_r = vns_interface5_bank_bus_dat_w[7:0];
-assign soc_litedramcore_uart_rxtx_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd0));
-assign soc_litedramcore_uart_rxtx_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd0));
-assign vns_csrbank5_txfull_r = vns_interface5_bank_bus_dat_w[0];
-assign vns_csrbank5_txfull_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 1'd1));
-assign vns_csrbank5_txfull_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 1'd1));
-assign vns_csrbank5_rxempty_r = vns_interface5_bank_bus_dat_w[0];
-assign vns_csrbank5_rxempty_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd2));
-assign vns_csrbank5_rxempty_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd2));
-assign soc_litedramcore_uart_eventmanager_status_r = vns_interface5_bank_bus_dat_w[1:0];
-assign soc_litedramcore_uart_eventmanager_status_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 2'd3));
-assign soc_litedramcore_uart_eventmanager_status_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 2'd3));
-assign soc_litedramcore_uart_eventmanager_pending_r = vns_interface5_bank_bus_dat_w[1:0];
-assign soc_litedramcore_uart_eventmanager_pending_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd4));
-assign soc_litedramcore_uart_eventmanager_pending_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd4));
-assign vns_csrbank5_ev_enable0_r = vns_interface5_bank_bus_dat_w[1:0];
-assign vns_csrbank5_ev_enable0_re = ((vns_csrbank5_sel & vns_interface5_bank_bus_we) & (vns_interface5_bank_bus_adr[2:0] == 3'd5));
-assign vns_csrbank5_ev_enable0_we = ((vns_csrbank5_sel & (~vns_interface5_bank_bus_we)) & (vns_interface5_bank_bus_adr[2:0] == 3'd5));
-assign vns_csrbank5_txfull_w = soc_litedramcore_uart_txfull_status;
-assign soc_litedramcore_uart_txfull_we = vns_csrbank5_txfull_we;
-assign vns_csrbank5_rxempty_w = soc_litedramcore_uart_rxempty_status;
-assign soc_litedramcore_uart_rxempty_we = vns_csrbank5_rxempty_we;
-assign vns_csrbank5_ev_enable0_w = soc_litedramcore_uart_eventmanager_storage[1:0];
-assign vns_csrbank6_sel = (vns_interface6_bank_bus_adr[13:9] == 2'd2);
-assign vns_csrbank6_tuning_word3_r = vns_interface6_bank_bus_dat_w[7:0];
-assign vns_csrbank6_tuning_word3_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd0));
-assign vns_csrbank6_tuning_word3_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd0));
-assign vns_csrbank6_tuning_word2_r = vns_interface6_bank_bus_dat_w[7:0];
-assign vns_csrbank6_tuning_word2_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 1'd1));
-assign vns_csrbank6_tuning_word2_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 1'd1));
-assign vns_csrbank6_tuning_word1_r = vns_interface6_bank_bus_dat_w[7:0];
-assign vns_csrbank6_tuning_word1_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd2));
-assign vns_csrbank6_tuning_word1_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd2));
-assign vns_csrbank6_tuning_word0_r = vns_interface6_bank_bus_dat_w[7:0];
-assign vns_csrbank6_tuning_word0_re = ((vns_csrbank6_sel & vns_interface6_bank_bus_we) & (vns_interface6_bank_bus_adr[1:0] == 2'd3));
-assign vns_csrbank6_tuning_word0_we = ((vns_csrbank6_sel & (~vns_interface6_bank_bus_we)) & (vns_interface6_bank_bus_adr[1:0] == 2'd3));
-assign vns_csrbank6_tuning_word3_w = soc_litedramcore_storage[31:24];
-assign vns_csrbank6_tuning_word2_w = soc_litedramcore_storage[23:16];
-assign vns_csrbank6_tuning_word1_w = soc_litedramcore_storage[15:8];
-assign vns_csrbank6_tuning_word0_w = soc_litedramcore_storage[7:0];
-assign vns_adr = soc_litedramcore_interface_adr;
-assign vns_we = soc_litedramcore_interface_we;
-assign vns_dat_w = soc_litedramcore_interface_dat_w;
-assign soc_litedramcore_interface_dat_r = vns_dat_r;
-assign vns_interface0_bank_bus_adr = vns_adr;
-assign vns_interface1_bank_bus_adr = vns_adr;
-assign vns_interface2_bank_bus_adr = vns_adr;
-assign vns_interface3_bank_bus_adr = vns_adr;
-assign vns_interface4_bank_bus_adr = vns_adr;
-assign vns_interface5_bank_bus_adr = vns_adr;
-assign vns_interface6_bank_bus_adr = vns_adr;
-assign vns_interface0_bank_bus_we = vns_we;
-assign vns_interface1_bank_bus_we = vns_we;
-assign vns_interface2_bank_bus_we = vns_we;
-assign vns_interface3_bank_bus_we = vns_we;
-assign vns_interface4_bank_bus_we = vns_we;
-assign vns_interface5_bank_bus_we = vns_we;
-assign vns_interface6_bank_bus_we = vns_we;
-assign vns_interface0_bank_bus_dat_w = vns_dat_w;
-assign vns_interface1_bank_bus_dat_w = vns_dat_w;
-assign vns_interface2_bank_bus_dat_w = vns_dat_w;
-assign vns_interface3_bank_bus_dat_w = vns_dat_w;
-assign vns_interface4_bank_bus_dat_w = vns_dat_w;
-assign vns_interface5_bank_bus_dat_w = vns_dat_w;
-assign vns_interface6_bank_bus_dat_w = vns_dat_w;
-assign vns_dat_r = ((((((vns_interface0_bank_bus_dat_r | vns_interface1_bank_bus_dat_r) | vns_interface2_bank_bus_dat_r) | vns_interface3_bank_bus_dat_r) | vns_interface4_bank_bus_dat_r) | vns_interface5_bank_bus_dat_r) | vns_interface6_bank_bus_dat_r);
 
 // synthesis translate_off
-reg dummy_d_338;
+reg dummy_d_274;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed0 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[0];
-               end
+       litedramcore_choose_req_want_reads <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[1];
                end
                2'd2: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[2];
                end
                2'd3: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[3];
                end
                3'd4: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[4];
                end
                3'd5: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[5];
                end
                3'd6: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[6];
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed0 <= soc_sdram_choose_cmd_valids[7];
+                       litedramcore_choose_req_want_reads <= 1'd1;
                end
        endcase
 // synthesis translate_off
-       dummy_d_338 = dummy_s;
+       dummy_d_274 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_339;
+reg dummy_d_275;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed1 <= 15'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_a;
-               end
+       litedramcore_choose_req_want_writes <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_a;
+                       litedramcore_choose_req_want_writes <= 1'd1;
                end
                2'd2: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_a;
                end
                2'd3: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_a;
                end
                3'd4: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_a;
                end
                3'd5: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_a;
                end
                3'd6: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_a;
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_339 = dummy_s;
+       dummy_d_275 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_340;
+reg dummy_d_276;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed2 <= 3'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_ba;
-               end
+       litedramcore_choose_req_cmd_ready <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_ba;
+                       if (1'd0) begin
+                               litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+                       end else begin
+                               litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+                       end
                end
                2'd2: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_ba;
                end
                2'd3: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_ba;
                end
                3'd4: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_ba;
                end
                3'd5: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_ba;
                end
                3'd6: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_ba;
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_ba;
+                       if (1'd0) begin
+                               litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+                       end else begin
+                               litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+                       end
                end
        endcase
 // synthesis translate_off
-       dummy_d_340 = dummy_s;
+       dummy_d_276 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_341;
+reg dummy_d_277;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed3 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_is_read;
-               end
+       litedramcore_en1 <= 1'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_is_read;
+                       litedramcore_en1 <= 1'd1;
                end
                2'd2: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_is_read;
                end
                2'd3: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_is_read;
                end
                3'd4: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_is_read;
                end
                3'd5: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_is_read;
                end
                3'd6: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_is_read;
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_is_read;
                end
        endcase
 // synthesis translate_off
-       dummy_d_341 = dummy_s;
+       dummy_d_277 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_342;
+reg dummy_d_278;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed4 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_is_write;
-               end
+       litedramcore_steerer_sel0 <= 2'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_is_write;
+                       litedramcore_steerer_sel0 <= 1'd0;
                end
                2'd2: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_is_write;
+                       litedramcore_steerer_sel0 <= 2'd3;
                end
                2'd3: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_is_write;
                end
                3'd4: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_is_write;
                end
                3'd5: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_is_write;
                end
                3'd6: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_is_write;
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_is_write;
+                       litedramcore_steerer_sel0 <= 1'd0;
                end
        endcase
 // synthesis translate_off
-       dummy_d_342 = dummy_s;
+       dummy_d_278 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_343;
+reg dummy_d_279;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed5 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_is_cmd;
-               end
+       litedramcore_steerer_sel1 <= 2'd0;
+       case (multiplexer_state)
                1'd1: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_is_cmd;
+                       litedramcore_steerer_sel1 <= 1'd0;
                end
                2'd2: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_is_cmd;
                end
                2'd3: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_is_cmd;
                end
                3'd4: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_is_cmd;
                end
                3'd5: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_is_cmd;
                end
                3'd6: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_is_cmd;
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               4'd9: begin
+               end
+               4'd10: begin
                end
                default: begin
-                       vns_rhs_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_is_cmd;
+                       litedramcore_steerer_sel1 <= 1'd1;
                end
        endcase
 // synthesis translate_off
-       dummy_d_343 = dummy_s;
+       dummy_d_279 = dummy_s;
 // synthesis translate_on
 end
+assign roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
+assign litedramcore_interface_bank0_addr = rhs_array_muxed12;
+assign litedramcore_interface_bank0_we = rhs_array_muxed13;
+assign litedramcore_interface_bank0_valid = rhs_array_muxed14;
+assign roundrobin1_request = {(((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin1_ce = ((~litedramcore_interface_bank1_valid) & (~litedramcore_interface_bank1_lock));
+assign litedramcore_interface_bank1_addr = rhs_array_muxed15;
+assign litedramcore_interface_bank1_we = rhs_array_muxed16;
+assign litedramcore_interface_bank1_valid = rhs_array_muxed17;
+assign roundrobin2_request = {(((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin2_ce = ((~litedramcore_interface_bank2_valid) & (~litedramcore_interface_bank2_lock));
+assign litedramcore_interface_bank2_addr = rhs_array_muxed18;
+assign litedramcore_interface_bank2_we = rhs_array_muxed19;
+assign litedramcore_interface_bank2_valid = rhs_array_muxed20;
+assign roundrobin3_request = {(((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin3_ce = ((~litedramcore_interface_bank3_valid) & (~litedramcore_interface_bank3_lock));
+assign litedramcore_interface_bank3_addr = rhs_array_muxed21;
+assign litedramcore_interface_bank3_we = rhs_array_muxed22;
+assign litedramcore_interface_bank3_valid = rhs_array_muxed23;
+assign roundrobin4_request = {(((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin4_ce = ((~litedramcore_interface_bank4_valid) & (~litedramcore_interface_bank4_lock));
+assign litedramcore_interface_bank4_addr = rhs_array_muxed24;
+assign litedramcore_interface_bank4_we = rhs_array_muxed25;
+assign litedramcore_interface_bank4_valid = rhs_array_muxed26;
+assign roundrobin5_request = {(((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin5_ce = ((~litedramcore_interface_bank5_valid) & (~litedramcore_interface_bank5_lock));
+assign litedramcore_interface_bank5_addr = rhs_array_muxed27;
+assign litedramcore_interface_bank5_we = rhs_array_muxed28;
+assign litedramcore_interface_bank5_valid = rhs_array_muxed29;
+assign roundrobin6_request = {(((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin6_ce = ((~litedramcore_interface_bank6_valid) & (~litedramcore_interface_bank6_lock));
+assign litedramcore_interface_bank6_addr = rhs_array_muxed30;
+assign litedramcore_interface_bank6_we = rhs_array_muxed31;
+assign litedramcore_interface_bank6_valid = rhs_array_muxed32;
+assign roundrobin7_request = {(((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid)};
+assign roundrobin7_ce = ((~litedramcore_interface_bank7_valid) & (~litedramcore_interface_bank7_lock));
+assign litedramcore_interface_bank7_addr = rhs_array_muxed33;
+assign litedramcore_interface_bank7_we = rhs_array_muxed34;
+assign litedramcore_interface_bank7_valid = rhs_array_muxed35;
+assign user_port_cmd_ready = ((((((((1'd0 | (((roundrobin0_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank0_ready)) | (((roundrobin1_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank1_ready)) | (((roundrobin2_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank2_ready)) | (((roundrobin3_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank3_ready)) | (((roundrobin4_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank4_ready)) | (((roundrobin5_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank5_ready)) | (((roundrobin6_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0)))))) & litedramcore_interface_bank6_ready)) | (((roundrobin7_grant == 1'd0) & ((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0)))))) & litedramcore_interface_bank7_ready));
+assign user_port_wdata_ready = new_master_wdata_ready2;
+assign user_port_rdata_valid = new_master_rdata_valid8;
 
 // synthesis translate_off
-reg dummy_d_344;
+reg dummy_d_280;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed0 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
-               1'd0: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine0_cmd_payload_cas;
-               end
+       litedramcore_interface_wdata <= 128'd0;
+       case ({new_master_wdata_ready2})
                1'd1: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine1_cmd_payload_cas;
-               end
-               2'd2: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine2_cmd_payload_cas;
-               end
-               2'd3: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine3_cmd_payload_cas;
-               end
-               3'd4: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine4_cmd_payload_cas;
+                       litedramcore_interface_wdata <= user_port_wdata_payload_data;
                end
-               3'd5: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine5_cmd_payload_cas;
+               default: begin
+                       litedramcore_interface_wdata <= 1'd0;
                end
-               3'd6: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine6_cmd_payload_cas;
+       endcase
+// synthesis translate_off
+       dummy_d_280 = dummy_s;
+// synthesis translate_on
+end
+
+// synthesis translate_off
+reg dummy_d_281;
+// synthesis translate_on
+always @(*) begin
+       litedramcore_interface_wdata_we <= 16'd0;
+       case ({new_master_wdata_ready2})
+               1'd1: begin
+                       litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
                end
                default: begin
-                       vns_t_array_muxed0 <= soc_sdram_bankmachine7_cmd_payload_cas;
+                       litedramcore_interface_wdata_we <= 1'd0;
                end
        endcase
 // synthesis translate_off
-       dummy_d_344 = dummy_s;
+       dummy_d_281 = dummy_s;
 // synthesis translate_on
 end
+assign user_port_rdata_payload_data = litedramcore_interface_rdata;
+assign roundrobin0_grant = 1'd0;
+assign roundrobin1_grant = 1'd0;
+assign roundrobin2_grant = 1'd0;
+assign roundrobin3_grant = 1'd0;
+assign roundrobin4_grant = 1'd0;
+assign roundrobin5_grant = 1'd0;
+assign roundrobin6_grant = 1'd0;
+assign roundrobin7_grant = 1'd0;
 
 // synthesis translate_off
-reg dummy_d_345;
+reg dummy_d_282;
+// synthesis translate_on
+always @(*) begin
+       csrbank0_sel <= 1'd0;
+       csrbank0_sel <= (interface0_bank_bus_adr[13:11] == 2'd2);
+       if (interface0_bank_bus_adr[0]) begin
+               csrbank0_sel <= 1'd0;
+       end
+// synthesis translate_off
+       dummy_d_282 = dummy_s;
+// synthesis translate_on
+end
+assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_init_done0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd0));
+assign csrbank0_init_done0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd0));
+assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
+assign csrbank0_init_error0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3] == 1'd1));
+assign csrbank0_init_error0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3] == 1'd1));
+assign csrbank0_init_done0_w = init_done_storage;
+assign csrbank0_init_error0_w = init_error_storage;
+
+// synthesis translate_off
+reg dummy_d_283;
+// synthesis translate_on
+always @(*) begin
+       csrbank1_sel <= 1'd0;
+       csrbank1_sel <= (interface1_bank_bus_adr[13:11] == 1'd0);
+       if (interface1_bank_bus_adr[0]) begin
+               csrbank1_sel <= 1'd0;
+       end
+// synthesis translate_off
+       dummy_d_283 = dummy_s;
+// synthesis translate_on
+end
+assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
+assign csrbank1_half_sys8x_taps0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd0));
+assign csrbank1_half_sys8x_taps0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd0));
+assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
+assign csrbank1_wlevel_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 1'd1));
+assign csrbank1_wlevel_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 1'd1));
+assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_wlevel_strobe_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd2));
+assign a7ddrphy_wlevel_strobe_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd2));
+assign a7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_cdly_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 2'd3));
+assign a7ddrphy_cdly_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 2'd3));
+assign a7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_cdly_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd4));
+assign a7ddrphy_cdly_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd4));
+assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
+assign csrbank1_dly_sel0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd5));
+assign csrbank1_dly_sel0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd5));
+assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd6));
+assign a7ddrphy_rdly_dq_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd6));
+assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_inc_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 3'd7));
+assign a7ddrphy_rdly_dq_inc_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 3'd7));
+assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_rst_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_rst_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd8));
+assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
+assign a7ddrphy_rdly_dq_bitslip_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[6:3] == 4'd9));
+assign a7ddrphy_rdly_dq_bitslip_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[6:3] == 4'd9));
+assign csrbank1_half_sys8x_taps0_w = a7ddrphy_half_sys8x_taps_storage[4:0];
+assign csrbank1_wlevel_en0_w = a7ddrphy_wlevel_en_storage;
+assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
+
+// synthesis translate_off
+reg dummy_d_284;
+// synthesis translate_on
+always @(*) begin
+       csrbank2_sel <= 1'd0;
+       csrbank2_sel <= (interface2_bank_bus_adr[13:11] == 1'd1);
+       if (interface2_bank_bus_adr[0]) begin
+               csrbank2_sel <= 1'd0;
+       end
+// synthesis translate_off
+       dummy_d_284 = dummy_s;
+// synthesis translate_on
+end
+assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
+assign csrbank2_dfii_control0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd0));
+assign csrbank2_dfii_control0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd0));
+assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi0_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 1'd1));
+assign csrbank2_dfii_pi0_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 1'd1));
+assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector0_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd2));
+assign litedramcore_phaseinjector0_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd2));
+assign csrbank2_dfii_pi0_address1_r = interface2_bank_bus_dat_w[6:0];
+assign csrbank2_dfii_pi0_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 2'd3));
+assign csrbank2_dfii_pi0_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 2'd3));
+assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd4));
+assign csrbank2_dfii_pi0_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd4));
+assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi0_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd5));
+assign csrbank2_dfii_pi0_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd5));
+assign csrbank2_dfii_pi0_wrdata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd6));
+assign csrbank2_dfii_pi0_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd6));
+assign csrbank2_dfii_pi0_wrdata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 3'd7));
+assign csrbank2_dfii_pi0_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 3'd7));
+assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd8));
+assign csrbank2_dfii_pi0_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd8));
+assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd9));
+assign csrbank2_dfii_pi0_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd9));
+assign csrbank2_dfii_pi0_rddata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd10));
+assign csrbank2_dfii_pi0_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd10));
+assign csrbank2_dfii_pi0_rddata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd11));
+assign csrbank2_dfii_pi0_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd11));
+assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd12));
+assign csrbank2_dfii_pi0_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd12));
+assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi0_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd13));
+assign csrbank2_dfii_pi0_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd13));
+assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi1_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd14));
+assign csrbank2_dfii_pi1_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd14));
+assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector1_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 4'd15));
+assign litedramcore_phaseinjector1_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 4'd15));
+assign csrbank2_dfii_pi1_address1_r = interface2_bank_bus_dat_w[6:0];
+assign csrbank2_dfii_pi1_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd16));
+assign csrbank2_dfii_pi1_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd16));
+assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd17));
+assign csrbank2_dfii_pi1_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd17));
+assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi1_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd18));
+assign csrbank2_dfii_pi1_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd18));
+assign csrbank2_dfii_pi1_wrdata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd19));
+assign csrbank2_dfii_pi1_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd19));
+assign csrbank2_dfii_pi1_wrdata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd20));
+assign csrbank2_dfii_pi1_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd20));
+assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd21));
+assign csrbank2_dfii_pi1_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd21));
+assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd22));
+assign csrbank2_dfii_pi1_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd22));
+assign csrbank2_dfii_pi1_rddata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd23));
+assign csrbank2_dfii_pi1_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd23));
+assign csrbank2_dfii_pi1_rddata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd24));
+assign csrbank2_dfii_pi1_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd24));
+assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd25));
+assign csrbank2_dfii_pi1_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd25));
+assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi1_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd26));
+assign csrbank2_dfii_pi1_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd26));
+assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi2_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd27));
+assign csrbank2_dfii_pi2_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd27));
+assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector2_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd28));
+assign litedramcore_phaseinjector2_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd28));
+assign csrbank2_dfii_pi2_address1_r = interface2_bank_bus_dat_w[6:0];
+assign csrbank2_dfii_pi2_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd29));
+assign csrbank2_dfii_pi2_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd29));
+assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd30));
+assign csrbank2_dfii_pi2_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd30));
+assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi2_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 5'd31));
+assign csrbank2_dfii_pi2_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 5'd31));
+assign csrbank2_dfii_pi2_wrdata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd32));
+assign csrbank2_dfii_pi2_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd32));
+assign csrbank2_dfii_pi2_wrdata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd33));
+assign csrbank2_dfii_pi2_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd33));
+assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd34));
+assign csrbank2_dfii_pi2_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd34));
+assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd35));
+assign csrbank2_dfii_pi2_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd35));
+assign csrbank2_dfii_pi2_rddata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd36));
+assign csrbank2_dfii_pi2_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd36));
+assign csrbank2_dfii_pi2_rddata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd37));
+assign csrbank2_dfii_pi2_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd37));
+assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd38));
+assign csrbank2_dfii_pi2_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd38));
+assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi2_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd39));
+assign csrbank2_dfii_pi2_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd39));
+assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
+assign csrbank2_dfii_pi3_command0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd40));
+assign csrbank2_dfii_pi3_command0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd40));
+assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
+assign litedramcore_phaseinjector3_command_issue_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd41));
+assign litedramcore_phaseinjector3_command_issue_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd41));
+assign csrbank2_dfii_pi3_address1_r = interface2_bank_bus_dat_w[6:0];
+assign csrbank2_dfii_pi3_address1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd42));
+assign csrbank2_dfii_pi3_address1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd42));
+assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_address0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd43));
+assign csrbank2_dfii_pi3_address0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd43));
+assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
+assign csrbank2_dfii_pi3_baddress0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd44));
+assign csrbank2_dfii_pi3_baddress0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd44));
+assign csrbank2_dfii_pi3_wrdata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_wrdata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd45));
+assign csrbank2_dfii_pi3_wrdata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd45));
+assign csrbank2_dfii_pi3_wrdata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_wrdata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd46));
+assign csrbank2_dfii_pi3_wrdata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd46));
+assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_wrdata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd47));
+assign csrbank2_dfii_pi3_wrdata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd47));
+assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_wrdata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd48));
+assign csrbank2_dfii_pi3_wrdata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd48));
+assign csrbank2_dfii_pi3_rddata3_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_rddata3_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd49));
+assign csrbank2_dfii_pi3_rddata3_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd49));
+assign csrbank2_dfii_pi3_rddata2_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_rddata2_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd50));
+assign csrbank2_dfii_pi3_rddata2_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd50));
+assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_rddata1_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd51));
+assign csrbank2_dfii_pi3_rddata1_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd51));
+assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[7:0];
+assign csrbank2_dfii_pi3_rddata0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[8:3] == 6'd52));
+assign csrbank2_dfii_pi3_rddata0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[8:3] == 6'd52));
+assign csrbank2_dfii_control0_w = litedramcore_storage[3:0];
+assign csrbank2_dfii_pi0_command0_w = litedramcore_phaseinjector0_command_storage[5:0];
+assign csrbank2_dfii_pi0_address1_w = litedramcore_phaseinjector0_address_storage[14:8];
+assign csrbank2_dfii_pi0_address0_w = litedramcore_phaseinjector0_address_storage[7:0];
+assign csrbank2_dfii_pi0_baddress0_w = litedramcore_phaseinjector0_baddress_storage[2:0];
+assign csrbank2_dfii_pi0_wrdata3_w = litedramcore_phaseinjector0_wrdata_storage[31:24];
+assign csrbank2_dfii_pi0_wrdata2_w = litedramcore_phaseinjector0_wrdata_storage[23:16];
+assign csrbank2_dfii_pi0_wrdata1_w = litedramcore_phaseinjector0_wrdata_storage[15:8];
+assign csrbank2_dfii_pi0_wrdata0_w = litedramcore_phaseinjector0_wrdata_storage[7:0];
+assign csrbank2_dfii_pi0_rddata3_w = litedramcore_phaseinjector0_status[31:24];
+assign csrbank2_dfii_pi0_rddata2_w = litedramcore_phaseinjector0_status[23:16];
+assign csrbank2_dfii_pi0_rddata1_w = litedramcore_phaseinjector0_status[15:8];
+assign csrbank2_dfii_pi0_rddata0_w = litedramcore_phaseinjector0_status[7:0];
+assign litedramcore_phaseinjector0_we = csrbank2_dfii_pi0_rddata0_we;
+assign csrbank2_dfii_pi1_command0_w = litedramcore_phaseinjector1_command_storage[5:0];
+assign csrbank2_dfii_pi1_address1_w = litedramcore_phaseinjector1_address_storage[14:8];
+assign csrbank2_dfii_pi1_address0_w = litedramcore_phaseinjector1_address_storage[7:0];
+assign csrbank2_dfii_pi1_baddress0_w = litedramcore_phaseinjector1_baddress_storage[2:0];
+assign csrbank2_dfii_pi1_wrdata3_w = litedramcore_phaseinjector1_wrdata_storage[31:24];
+assign csrbank2_dfii_pi1_wrdata2_w = litedramcore_phaseinjector1_wrdata_storage[23:16];
+assign csrbank2_dfii_pi1_wrdata1_w = litedramcore_phaseinjector1_wrdata_storage[15:8];
+assign csrbank2_dfii_pi1_wrdata0_w = litedramcore_phaseinjector1_wrdata_storage[7:0];
+assign csrbank2_dfii_pi1_rddata3_w = litedramcore_phaseinjector1_status[31:24];
+assign csrbank2_dfii_pi1_rddata2_w = litedramcore_phaseinjector1_status[23:16];
+assign csrbank2_dfii_pi1_rddata1_w = litedramcore_phaseinjector1_status[15:8];
+assign csrbank2_dfii_pi1_rddata0_w = litedramcore_phaseinjector1_status[7:0];
+assign litedramcore_phaseinjector1_we = csrbank2_dfii_pi1_rddata0_we;
+assign csrbank2_dfii_pi2_command0_w = litedramcore_phaseinjector2_command_storage[5:0];
+assign csrbank2_dfii_pi2_address1_w = litedramcore_phaseinjector2_address_storage[14:8];
+assign csrbank2_dfii_pi2_address0_w = litedramcore_phaseinjector2_address_storage[7:0];
+assign csrbank2_dfii_pi2_baddress0_w = litedramcore_phaseinjector2_baddress_storage[2:0];
+assign csrbank2_dfii_pi2_wrdata3_w = litedramcore_phaseinjector2_wrdata_storage[31:24];
+assign csrbank2_dfii_pi2_wrdata2_w = litedramcore_phaseinjector2_wrdata_storage[23:16];
+assign csrbank2_dfii_pi2_wrdata1_w = litedramcore_phaseinjector2_wrdata_storage[15:8];
+assign csrbank2_dfii_pi2_wrdata0_w = litedramcore_phaseinjector2_wrdata_storage[7:0];
+assign csrbank2_dfii_pi2_rddata3_w = litedramcore_phaseinjector2_status[31:24];
+assign csrbank2_dfii_pi2_rddata2_w = litedramcore_phaseinjector2_status[23:16];
+assign csrbank2_dfii_pi2_rddata1_w = litedramcore_phaseinjector2_status[15:8];
+assign csrbank2_dfii_pi2_rddata0_w = litedramcore_phaseinjector2_status[7:0];
+assign litedramcore_phaseinjector2_we = csrbank2_dfii_pi2_rddata0_we;
+assign csrbank2_dfii_pi3_command0_w = litedramcore_phaseinjector3_command_storage[5:0];
+assign csrbank2_dfii_pi3_address1_w = litedramcore_phaseinjector3_address_storage[14:8];
+assign csrbank2_dfii_pi3_address0_w = litedramcore_phaseinjector3_address_storage[7:0];
+assign csrbank2_dfii_pi3_baddress0_w = litedramcore_phaseinjector3_baddress_storage[2:0];
+assign csrbank2_dfii_pi3_wrdata3_w = litedramcore_phaseinjector3_wrdata_storage[31:24];
+assign csrbank2_dfii_pi3_wrdata2_w = litedramcore_phaseinjector3_wrdata_storage[23:16];
+assign csrbank2_dfii_pi3_wrdata1_w = litedramcore_phaseinjector3_wrdata_storage[15:8];
+assign csrbank2_dfii_pi3_wrdata0_w = litedramcore_phaseinjector3_wrdata_storage[7:0];
+assign csrbank2_dfii_pi3_rddata3_w = litedramcore_phaseinjector3_status[31:24];
+assign csrbank2_dfii_pi3_rddata2_w = litedramcore_phaseinjector3_status[23:16];
+assign csrbank2_dfii_pi3_rddata1_w = litedramcore_phaseinjector3_status[15:8];
+assign csrbank2_dfii_pi3_rddata0_w = litedramcore_phaseinjector3_status[7:0];
+assign litedramcore_phaseinjector3_we = csrbank2_dfii_pi3_rddata0_we;
+assign adr = csr_port_adr;
+assign we = csr_port_we;
+assign dat_w = csr_port_dat_w;
+assign csr_port_dat_r = dat_r;
+assign interface0_bank_bus_adr = adr;
+assign interface1_bank_bus_adr = adr;
+assign interface2_bank_bus_adr = adr;
+assign interface0_bank_bus_we = we;
+assign interface1_bank_bus_we = we;
+assign interface2_bank_bus_we = we;
+assign interface0_bank_bus_dat_w = dat_w;
+assign interface1_bank_bus_dat_w = dat_w;
+assign interface2_bank_bus_dat_w = dat_w;
+assign dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
+
+// synthesis translate_off
+reg dummy_d_285;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed1 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
+       rhs_array_muxed0 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine0_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
                end
                1'd1: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine1_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
                end
                2'd2: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine2_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
                end
                2'd3: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine3_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
                end
                3'd4: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine4_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
                end
                3'd5: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine5_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
                end
                3'd6: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine6_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
                end
                default: begin
-                       vns_t_array_muxed1 <= soc_sdram_bankmachine7_cmd_payload_ras;
+                       rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_345 = dummy_s;
+       dummy_d_285 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_346;
+reg dummy_d_286;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed2 <= 1'd0;
-       case (soc_sdram_choose_cmd_grant)
+       rhs_array_muxed1 <= 15'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine0_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
                end
                1'd1: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine1_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
                end
                2'd2: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine2_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
                end
                2'd3: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine3_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
                end
                3'd4: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine4_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
                end
                3'd5: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine5_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
                end
                3'd6: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine6_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
                end
                default: begin
-                       vns_t_array_muxed2 <= soc_sdram_bankmachine7_cmd_payload_we;
+                       rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_346 = dummy_s;
+       dummy_d_286 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_347;
+reg dummy_d_287;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed6 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed2 <= 3'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[0];
+                       rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
                end
                1'd1: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[1];
+                       rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
                end
                2'd2: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[2];
+                       rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
                end
                2'd3: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[3];
+                       rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
                end
                3'd4: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[4];
+                       rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
                end
                3'd5: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[5];
+                       rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
                end
                3'd6: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[6];
+                       rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
                end
                default: begin
-                       vns_rhs_array_muxed6 <= soc_sdram_choose_req_valids[7];
+                       rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
                end
        endcase
 // synthesis translate_off
-       dummy_d_347 = dummy_s;
+       dummy_d_287 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_348;
+reg dummy_d_288;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed7 <= 15'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed3 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine0_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
                end
                1'd1: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine1_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
                end
                2'd2: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine2_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
                end
                2'd3: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine3_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
                end
                3'd4: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine4_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
                end
                3'd5: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine5_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
                end
                3'd6: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine6_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
                end
                default: begin
-                       vns_rhs_array_muxed7 <= soc_sdram_bankmachine7_cmd_payload_a;
+                       rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
                end
        endcase
 // synthesis translate_off
-       dummy_d_348 = dummy_s;
+       dummy_d_288 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_349;
+reg dummy_d_289;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed8 <= 3'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed4 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine0_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
                end
                1'd1: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine1_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
                end
                2'd2: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine2_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
                end
                2'd3: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine3_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
                end
                3'd4: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine4_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
                end
                3'd5: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine5_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
                end
                3'd6: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine6_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
                end
                default: begin
-                       vns_rhs_array_muxed8 <= soc_sdram_bankmachine7_cmd_payload_ba;
+                       rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
                end
        endcase
 // synthesis translate_off
-       dummy_d_349 = dummy_s;
+       dummy_d_289 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_350;
+reg dummy_d_290;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed9 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed5 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine0_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
                end
                1'd1: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine1_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
                end
                2'd2: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine2_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
                end
                2'd3: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine3_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
                end
                3'd4: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine4_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
                end
                3'd5: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine5_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
                end
                3'd6: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine6_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
                end
                default: begin
-                       vns_rhs_array_muxed9 <= soc_sdram_bankmachine7_cmd_payload_is_read;
+                       rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
                end
        endcase
 // synthesis translate_off
-       dummy_d_350 = dummy_s;
+       dummy_d_290 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_351;
+reg dummy_d_291;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed10 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       t_array_muxed0 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine0_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
                end
                1'd1: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine1_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
                end
                2'd2: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine2_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
                end
                2'd3: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine3_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
                end
                3'd4: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine4_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
                end
                3'd5: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine5_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
                end
                3'd6: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine6_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
                end
                default: begin
-                       vns_rhs_array_muxed10 <= soc_sdram_bankmachine7_cmd_payload_is_write;
+                       t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
                end
        endcase
 // synthesis translate_off
-       dummy_d_351 = dummy_s;
+       dummy_d_291 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_352;
+reg dummy_d_292;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed11 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       t_array_muxed1 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine0_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
                end
                1'd1: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine1_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
                end
                2'd2: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine2_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
                end
                2'd3: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine3_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
                end
                3'd4: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine4_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
                end
                3'd5: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine5_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
                end
                3'd6: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine6_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
                end
                default: begin
-                       vns_rhs_array_muxed11 <= soc_sdram_bankmachine7_cmd_payload_is_cmd;
+                       t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
                end
        endcase
 // synthesis translate_off
-       dummy_d_352 = dummy_s;
+       dummy_d_292 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_353;
+reg dummy_d_293;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed3 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       t_array_muxed2 <= 1'd0;
+       case (litedramcore_choose_cmd_grant)
                1'd0: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine0_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
                end
                1'd1: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine1_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
                end
                2'd2: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine2_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
                end
                2'd3: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine3_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
                end
                3'd4: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine4_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
                end
                3'd5: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine5_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
                end
                3'd6: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine6_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
                end
                default: begin
-                       vns_t_array_muxed3 <= soc_sdram_bankmachine7_cmd_payload_cas;
+                       t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_353 = dummy_s;
+       dummy_d_293 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_354;
+reg dummy_d_294;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed4 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed6 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine0_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
                end
                1'd1: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine1_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
                end
                2'd2: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine2_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
                end
                2'd3: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine3_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
                end
                3'd4: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine4_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
                end
                3'd5: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine5_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
                end
                3'd6: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine6_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
                end
                default: begin
-                       vns_t_array_muxed4 <= soc_sdram_bankmachine7_cmd_payload_ras;
+                       rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
                end
        endcase
 // synthesis translate_off
-       dummy_d_354 = dummy_s;
+       dummy_d_294 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_355;
+reg dummy_d_295;
 // synthesis translate_on
 always @(*) begin
-       vns_t_array_muxed5 <= 1'd0;
-       case (soc_sdram_choose_req_grant)
+       rhs_array_muxed7 <= 15'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine0_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
                end
                1'd1: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine1_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
                end
                2'd2: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine2_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
                end
                2'd3: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine3_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
                end
                3'd4: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine4_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
                end
                3'd5: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine5_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
                end
                3'd6: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine6_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
                end
                default: begin
-                       vns_t_array_muxed5 <= soc_sdram_bankmachine7_cmd_payload_we;
+                       rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_355 = dummy_s;
+       dummy_d_295 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_356;
+reg dummy_d_296;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed12 <= 22'd0;
-       case (vns_roundrobin0_grant)
+       rhs_array_muxed8 <= 3'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed12 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+                       rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
                end
-               default: begin
-                       vns_rhs_array_muxed12 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+               1'd1: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
                end
-       endcase
-// synthesis translate_off
-       dummy_d_356 = dummy_s;
-// synthesis translate_on
-end
-
-// synthesis translate_off
-reg dummy_d_357;
-// synthesis translate_on
-always @(*) begin
-       vns_rhs_array_muxed13 <= 1'd0;
-       case (vns_roundrobin0_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed13 <= soc_port_cmd_payload_we;
+               2'd2: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+               end
+               2'd3: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+               end
+               3'd4: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+               end
+               3'd5: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+               end
+               3'd6: begin
+                       rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
                end
                default: begin
-                       vns_rhs_array_muxed13 <= soc_cmd_payload_we;
+                       rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
                end
        endcase
 // synthesis translate_off
-       dummy_d_357 = dummy_s;
+       dummy_d_296 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_358;
+reg dummy_d_297;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed14 <= 1'd0;
-       case (vns_roundrobin0_grant)
+       rhs_array_muxed9 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed14 <= (((soc_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked0 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+                       rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+               end
+               1'd1: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+               end
+               2'd2: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+               end
+               2'd3: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+               end
+               3'd4: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+               end
+               3'd5: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+               end
+               3'd6: begin
+                       rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
                end
                default: begin
-                       vns_rhs_array_muxed14 <= (((soc_cmd_payload_addr[9:7] == 1'd0) & (~(((((((vns_locked1 | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
                end
        endcase
 // synthesis translate_off
-       dummy_d_358 = dummy_s;
+       dummy_d_297 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_359;
+reg dummy_d_298;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed15 <= 22'd0;
-       case (vns_roundrobin1_grant)
+       rhs_array_muxed10 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed15 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+                       rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+               end
+               1'd1: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+               end
+               2'd2: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+               end
+               2'd3: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+               end
+               3'd4: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+               end
+               3'd5: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+               end
+               3'd6: begin
+                       rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
                end
                default: begin
-                       vns_rhs_array_muxed15 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
                end
        endcase
 // synthesis translate_off
-       dummy_d_359 = dummy_s;
+       dummy_d_298 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_360;
+reg dummy_d_299;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed16 <= 1'd0;
-       case (vns_roundrobin1_grant)
+       rhs_array_muxed11 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed16 <= soc_port_cmd_payload_we;
+                       rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+               end
+               1'd1: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+               end
+               2'd2: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+               end
+               2'd3: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+               end
+               3'd4: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+               end
+               3'd5: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+               end
+               3'd6: begin
+                       rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
                end
                default: begin
-                       vns_rhs_array_muxed16 <= soc_cmd_payload_we;
+                       rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
                end
        endcase
 // synthesis translate_off
-       dummy_d_360 = dummy_s;
+       dummy_d_299 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_361;
+reg dummy_d_300;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed17 <= 1'd0;
-       case (vns_roundrobin1_grant)
+       t_array_muxed3 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed17 <= (((soc_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked2 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
+                       t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+               end
+               1'd1: begin
+                       t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+               end
+               2'd2: begin
+                       t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+               end
+               2'd3: begin
+                       t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+               end
+               3'd4: begin
+                       t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+               end
+               3'd5: begin
+                       t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+               end
+               3'd6: begin
+                       t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
                end
                default: begin
-                       vns_rhs_array_muxed17 <= (((soc_cmd_payload_addr[9:7] == 1'd1) & (~(((((((vns_locked3 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
                end
        endcase
 // synthesis translate_off
-       dummy_d_361 = dummy_s;
+       dummy_d_300 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_362;
+reg dummy_d_301;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed18 <= 22'd0;
-       case (vns_roundrobin2_grant)
+       t_array_muxed4 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed18 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
+                       t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+               end
+               1'd1: begin
+                       t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+               end
+               2'd2: begin
+                       t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+               end
+               2'd3: begin
+                       t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+               end
+               3'd4: begin
+                       t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+               end
+               3'd5: begin
+                       t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+               end
+               3'd6: begin
+                       t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
                end
                default: begin
-                       vns_rhs_array_muxed18 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+                       t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
                end
        endcase
 // synthesis translate_off
-       dummy_d_362 = dummy_s;
+       dummy_d_301 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_363;
+reg dummy_d_302;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed19 <= 1'd0;
-       case (vns_roundrobin2_grant)
+       t_array_muxed5 <= 1'd0;
+       case (litedramcore_choose_req_grant)
                1'd0: begin
-                       vns_rhs_array_muxed19 <= soc_port_cmd_payload_we;
+                       t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+               end
+               1'd1: begin
+                       t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+               end
+               2'd2: begin
+                       t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+               end
+               2'd3: begin
+                       t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+               end
+               3'd4: begin
+                       t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+               end
+               3'd5: begin
+                       t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+               end
+               3'd6: begin
+                       t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
                end
                default: begin
-                       vns_rhs_array_muxed19 <= soc_cmd_payload_we;
+                       t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_363 = dummy_s;
+       dummy_d_302 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_364;
+reg dummy_d_303;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed20 <= 1'd0;
-       case (vns_roundrobin2_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed20 <= (((soc_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked4 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed12 <= 22'd0;
+       case (roundrobin0_grant)
                default: begin
-                       vns_rhs_array_muxed20 <= (((soc_cmd_payload_addr[9:7] == 2'd2) & (~(((((((vns_locked5 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_364 = dummy_s;
+       dummy_d_303 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_365;
+reg dummy_d_304;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed21 <= 22'd0;
-       case (vns_roundrobin3_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed21 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
-               end
+       rhs_array_muxed13 <= 1'd0;
+       case (roundrobin0_grant)
                default: begin
-                       vns_rhs_array_muxed21 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed13 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_365 = dummy_s;
+       dummy_d_304 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_366;
+reg dummy_d_305;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed22 <= 1'd0;
-       case (vns_roundrobin3_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed22 <= soc_port_cmd_payload_we;
-               end
+       rhs_array_muxed14 <= 1'd0;
+       case (roundrobin0_grant)
                default: begin
-                       vns_rhs_array_muxed22 <= soc_cmd_payload_we;
+                       rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((locked0 | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_366 = dummy_s;
+       dummy_d_305 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_367;
+reg dummy_d_306;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed23 <= 1'd0;
-       case (vns_roundrobin3_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed23 <= (((soc_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked6 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed15 <= 22'd0;
+       case (roundrobin1_grant)
                default: begin
-                       vns_rhs_array_muxed23 <= (((soc_cmd_payload_addr[9:7] == 2'd3) & (~(((((((vns_locked7 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_367 = dummy_s;
+       dummy_d_306 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_368;
+reg dummy_d_307;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed24 <= 22'd0;
-       case (vns_roundrobin4_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed24 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
-               end
+       rhs_array_muxed16 <= 1'd0;
+       case (roundrobin1_grant)
                default: begin
-                       vns_rhs_array_muxed24 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed16 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_368 = dummy_s;
+       dummy_d_307 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_369;
+reg dummy_d_308;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed25 <= 1'd0;
-       case (vns_roundrobin4_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed25 <= soc_port_cmd_payload_we;
-               end
+       rhs_array_muxed17 <= 1'd0;
+       case (roundrobin1_grant)
                default: begin
-                       vns_rhs_array_muxed25 <= soc_cmd_payload_we;
+                       rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((locked1 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_369 = dummy_s;
+       dummy_d_308 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_370;
+reg dummy_d_309;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed26 <= 1'd0;
-       case (vns_roundrobin4_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed26 <= (((soc_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked8 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed18 <= 22'd0;
+       case (roundrobin2_grant)
                default: begin
-                       vns_rhs_array_muxed26 <= (((soc_cmd_payload_addr[9:7] == 3'd4) & (~(((((((vns_locked9 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_370 = dummy_s;
+       dummy_d_309 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_371;
+reg dummy_d_310;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed27 <= 22'd0;
-       case (vns_roundrobin5_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed27 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
-               end
+       rhs_array_muxed19 <= 1'd0;
+       case (roundrobin2_grant)
                default: begin
-                       vns_rhs_array_muxed27 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed19 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_371 = dummy_s;
+       dummy_d_310 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_372;
+reg dummy_d_311;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed28 <= 1'd0;
-       case (vns_roundrobin5_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed28 <= soc_port_cmd_payload_we;
-               end
+       rhs_array_muxed20 <= 1'd0;
+       case (roundrobin2_grant)
                default: begin
-                       vns_rhs_array_muxed28 <= soc_cmd_payload_we;
+                       rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((locked2 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_372 = dummy_s;
+       dummy_d_311 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_373;
+reg dummy_d_312;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed29 <= 1'd0;
-       case (vns_roundrobin5_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed29 <= (((soc_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked10 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed21 <= 22'd0;
+       case (roundrobin3_grant)
                default: begin
-                       vns_rhs_array_muxed29 <= (((soc_cmd_payload_addr[9:7] == 3'd5) & (~(((((((vns_locked11 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_373 = dummy_s;
+       dummy_d_312 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_374;
+reg dummy_d_313;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed30 <= 22'd0;
-       case (vns_roundrobin6_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed30 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
-               end
+       rhs_array_muxed22 <= 1'd0;
+       case (roundrobin3_grant)
                default: begin
-                       vns_rhs_array_muxed30 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed22 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_374 = dummy_s;
+       dummy_d_313 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_375;
+reg dummy_d_314;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed31 <= 1'd0;
-       case (vns_roundrobin6_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed31 <= soc_port_cmd_payload_we;
-               end
+       rhs_array_muxed23 <= 1'd0;
+       case (roundrobin3_grant)
                default: begin
-                       vns_rhs_array_muxed31 <= soc_cmd_payload_we;
+                       rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((locked3 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_375 = dummy_s;
+       dummy_d_314 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_376;
+reg dummy_d_315;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed32 <= 1'd0;
-       case (vns_roundrobin6_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed32 <= (((soc_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked12 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed24 <= 22'd0;
+       case (roundrobin4_grant)
                default: begin
-                       vns_rhs_array_muxed32 <= (((soc_cmd_payload_addr[9:7] == 3'd6) & (~(((((((vns_locked13 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank7_lock & (vns_roundrobin7_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_376 = dummy_s;
+       dummy_d_315 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_377;
+reg dummy_d_316;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed33 <= 22'd0;
-       case (vns_roundrobin7_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed33 <= {soc_port_cmd_payload_addr[24:10], soc_port_cmd_payload_addr[6:0]};
-               end
+       rhs_array_muxed25 <= 1'd0;
+       case (roundrobin4_grant)
                default: begin
-                       vns_rhs_array_muxed33 <= {soc_cmd_payload_addr[24:10], soc_cmd_payload_addr[6:0]};
+                       rhs_array_muxed25 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_377 = dummy_s;
+       dummy_d_316 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_378;
+reg dummy_d_317;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed34 <= 1'd0;
-       case (vns_roundrobin7_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed34 <= soc_port_cmd_payload_we;
-               end
+       rhs_array_muxed26 <= 1'd0;
+       case (roundrobin4_grant)
                default: begin
-                       vns_rhs_array_muxed34 <= soc_cmd_payload_we;
+                       rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((locked4 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_378 = dummy_s;
+       dummy_d_317 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_379;
+reg dummy_d_318;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed35 <= 1'd0;
-       case (vns_roundrobin7_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed35 <= (((soc_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked14 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd0))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd0))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd0))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd0))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd0))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd0))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd0))))) & soc_port_cmd_valid);
-               end
+       rhs_array_muxed27 <= 22'd0;
+       case (roundrobin5_grant)
                default: begin
-                       vns_rhs_array_muxed35 <= (((soc_cmd_payload_addr[9:7] == 3'd7) & (~(((((((vns_locked15 | (soc_sdram_interface_bank0_lock & (vns_roundrobin0_grant == 1'd1))) | (soc_sdram_interface_bank1_lock & (vns_roundrobin1_grant == 1'd1))) | (soc_sdram_interface_bank2_lock & (vns_roundrobin2_grant == 1'd1))) | (soc_sdram_interface_bank3_lock & (vns_roundrobin3_grant == 1'd1))) | (soc_sdram_interface_bank4_lock & (vns_roundrobin4_grant == 1'd1))) | (soc_sdram_interface_bank5_lock & (vns_roundrobin5_grant == 1'd1))) | (soc_sdram_interface_bank6_lock & (vns_roundrobin6_grant == 1'd1))))) & soc_cmd_valid);
+                       rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_379 = dummy_s;
+       dummy_d_318 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_380;
+reg dummy_d_319;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed36 <= 30'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed36 <= soc_litedramcore_cpu_ibus_adr;
-               end
+       rhs_array_muxed28 <= 1'd0;
+       case (roundrobin5_grant)
                default: begin
-                       vns_rhs_array_muxed36 <= soc_litedramcore_cpu_dbus_adr;
+                       rhs_array_muxed28 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_380 = dummy_s;
+       dummy_d_319 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_381;
+reg dummy_d_320;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed37 <= 32'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed37 <= soc_litedramcore_cpu_ibus_dat_w;
-               end
+       rhs_array_muxed29 <= 1'd0;
+       case (roundrobin5_grant)
                default: begin
-                       vns_rhs_array_muxed37 <= soc_litedramcore_cpu_dbus_dat_w;
+                       rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((locked5 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_381 = dummy_s;
+       dummy_d_320 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_382;
+reg dummy_d_321;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed38 <= 4'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed38 <= soc_litedramcore_cpu_ibus_sel;
-               end
+       rhs_array_muxed30 <= 22'd0;
+       case (roundrobin6_grant)
                default: begin
-                       vns_rhs_array_muxed38 <= soc_litedramcore_cpu_dbus_sel;
+                       rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_382 = dummy_s;
+       dummy_d_321 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_383;
+reg dummy_d_322;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed39 <= 1'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed39 <= soc_litedramcore_cpu_ibus_cyc;
-               end
+       rhs_array_muxed31 <= 1'd0;
+       case (roundrobin6_grant)
                default: begin
-                       vns_rhs_array_muxed39 <= soc_litedramcore_cpu_dbus_cyc;
+                       rhs_array_muxed31 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_383 = dummy_s;
+       dummy_d_322 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_384;
+reg dummy_d_323;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed40 <= 1'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed40 <= soc_litedramcore_cpu_ibus_stb;
-               end
+       rhs_array_muxed32 <= 1'd0;
+       case (roundrobin6_grant)
                default: begin
-                       vns_rhs_array_muxed40 <= soc_litedramcore_cpu_dbus_stb;
+                       rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((locked6 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_384 = dummy_s;
+       dummy_d_323 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_385;
+reg dummy_d_324;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed41 <= 1'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed41 <= soc_litedramcore_cpu_ibus_we;
-               end
+       rhs_array_muxed33 <= 22'd0;
+       case (roundrobin7_grant)
                default: begin
-                       vns_rhs_array_muxed41 <= soc_litedramcore_cpu_dbus_we;
+                       rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
                end
        endcase
 // synthesis translate_off
-       dummy_d_385 = dummy_s;
+       dummy_d_324 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_386;
+reg dummy_d_325;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed42 <= 3'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed42 <= soc_litedramcore_cpu_ibus_cti;
-               end
+       rhs_array_muxed34 <= 1'd0;
+       case (roundrobin7_grant)
                default: begin
-                       vns_rhs_array_muxed42 <= soc_litedramcore_cpu_dbus_cti;
+                       rhs_array_muxed34 <= user_port_cmd_payload_we;
                end
        endcase
 // synthesis translate_off
-       dummy_d_386 = dummy_s;
+       dummy_d_325 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_387;
+reg dummy_d_326;
 // synthesis translate_on
 always @(*) begin
-       vns_rhs_array_muxed43 <= 2'd0;
-       case (vns_grant)
-               1'd0: begin
-                       vns_rhs_array_muxed43 <= soc_litedramcore_cpu_ibus_bte;
-               end
+       rhs_array_muxed35 <= 1'd0;
+       case (roundrobin7_grant)
                default: begin
-                       vns_rhs_array_muxed43 <= soc_litedramcore_cpu_dbus_bte;
+                       rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((locked7 | (litedramcore_interface_bank0_lock & (roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
                end
        endcase
 // synthesis translate_off
-       dummy_d_387 = dummy_s;
+       dummy_d_326 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_388;
+reg dummy_d_327;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed0 <= 3'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed0 <= 3'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed0 <= soc_sdram_nop_ba[2:0];
+                       array_muxed0 <= litedramcore_nop_ba[2:0];
                end
                1'd1: begin
-                       vns_array_muxed0 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+                       array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
                end
                2'd2: begin
-                       vns_array_muxed0 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+                       array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
                end
                default: begin
-                       vns_array_muxed0 <= soc_sdram_cmd_payload_ba[2:0];
+                       array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
                end
        endcase
 // synthesis translate_off
-       dummy_d_388 = dummy_s;
+       dummy_d_327 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_389;
+reg dummy_d_328;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed1 <= 15'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed1 <= 15'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed1 <= soc_sdram_nop_a;
+                       array_muxed1 <= litedramcore_nop_a;
                end
                1'd1: begin
-                       vns_array_muxed1 <= soc_sdram_choose_cmd_cmd_payload_a;
+                       array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
                end
                2'd2: begin
-                       vns_array_muxed1 <= soc_sdram_choose_req_cmd_payload_a;
+                       array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
                end
                default: begin
-                       vns_array_muxed1 <= soc_sdram_cmd_payload_a;
+                       array_muxed1 <= litedramcore_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_389 = dummy_s;
+       dummy_d_328 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_390;
+reg dummy_d_329;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed2 <= 1'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed2 <= 1'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed2 <= 1'd0;
+                       array_muxed2 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed2 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+                       array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
                end
                2'd2: begin
-                       vns_array_muxed2 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+                       array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
                end
                default: begin
-                       vns_array_muxed2 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+                       array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
                end
        endcase
 // synthesis translate_off
-       dummy_d_390 = dummy_s;
+       dummy_d_329 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_391;
+reg dummy_d_330;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed3 <= 1'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed3 <= 1'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed3 <= 1'd0;
+                       array_muxed3 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed3 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+                       array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
                end
                2'd2: begin
-                       vns_array_muxed3 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+                       array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
                end
                default: begin
-                       vns_array_muxed3 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+                       array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
                end
        endcase
 // synthesis translate_off
-       dummy_d_391 = dummy_s;
+       dummy_d_330 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_392;
+reg dummy_d_331;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed4 <= 1'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed4 <= 1'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed4 <= 1'd0;
+                       array_muxed4 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed4 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+                       array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
                end
                2'd2: begin
-                       vns_array_muxed4 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+                       array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
                end
                default: begin
-                       vns_array_muxed4 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+                       array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
                end
        endcase
 // synthesis translate_off
-       dummy_d_392 = dummy_s;
+       dummy_d_331 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_393;
+reg dummy_d_332;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed5 <= 1'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed5 <= 1'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed5 <= 1'd0;
+                       array_muxed5 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed5 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+                       array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
                end
                2'd2: begin
-                       vns_array_muxed5 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+                       array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
                end
                default: begin
-                       vns_array_muxed5 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+                       array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
                end
        endcase
 // synthesis translate_off
-       dummy_d_393 = dummy_s;
+       dummy_d_332 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_394;
+reg dummy_d_333;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed6 <= 1'd0;
-       case (soc_sdram_steerer_sel0)
+       array_muxed6 <= 1'd0;
+       case (litedramcore_steerer_sel0)
                1'd0: begin
-                       vns_array_muxed6 <= 1'd0;
+                       array_muxed6 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed6 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+                       array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
                end
                2'd2: begin
-                       vns_array_muxed6 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+                       array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
                end
                default: begin
-                       vns_array_muxed6 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+                       array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
                end
        endcase
 // synthesis translate_off
-       dummy_d_394 = dummy_s;
+       dummy_d_333 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_395;
+reg dummy_d_334;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed7 <= 3'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed7 <= 3'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed7 <= soc_sdram_nop_ba[2:0];
+                       array_muxed7 <= litedramcore_nop_ba[2:0];
                end
                1'd1: begin
-                       vns_array_muxed7 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+                       array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
                end
                2'd2: begin
-                       vns_array_muxed7 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+                       array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
                end
                default: begin
-                       vns_array_muxed7 <= soc_sdram_cmd_payload_ba[2:0];
+                       array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
                end
        endcase
 // synthesis translate_off
-       dummy_d_395 = dummy_s;
+       dummy_d_334 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_396;
+reg dummy_d_335;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed8 <= 15'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed8 <= 15'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed8 <= soc_sdram_nop_a;
+                       array_muxed8 <= litedramcore_nop_a;
                end
                1'd1: begin
-                       vns_array_muxed8 <= soc_sdram_choose_cmd_cmd_payload_a;
+                       array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
                end
                2'd2: begin
-                       vns_array_muxed8 <= soc_sdram_choose_req_cmd_payload_a;
+                       array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
                end
                default: begin
-                       vns_array_muxed8 <= soc_sdram_cmd_payload_a;
+                       array_muxed8 <= litedramcore_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_396 = dummy_s;
+       dummy_d_335 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_397;
+reg dummy_d_336;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed9 <= 1'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed9 <= 1'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed9 <= 1'd0;
+                       array_muxed9 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed9 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+                       array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
                end
                2'd2: begin
-                       vns_array_muxed9 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+                       array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
                end
                default: begin
-                       vns_array_muxed9 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+                       array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
                end
        endcase
 // synthesis translate_off
-       dummy_d_397 = dummy_s;
+       dummy_d_336 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_398;
+reg dummy_d_337;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed10 <= 1'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed10 <= 1'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed10 <= 1'd0;
+                       array_muxed10 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed10 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+                       array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
                end
                2'd2: begin
-                       vns_array_muxed10 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+                       array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
                end
                default: begin
-                       vns_array_muxed10 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+                       array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
                end
        endcase
 // synthesis translate_off
-       dummy_d_398 = dummy_s;
+       dummy_d_337 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_399;
+reg dummy_d_338;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed11 <= 1'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed11 <= 1'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed11 <= 1'd0;
+                       array_muxed11 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed11 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+                       array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
                end
                2'd2: begin
-                       vns_array_muxed11 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+                       array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
                end
                default: begin
-                       vns_array_muxed11 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+                       array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
                end
        endcase
 // synthesis translate_off
-       dummy_d_399 = dummy_s;
+       dummy_d_338 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_400;
+reg dummy_d_339;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed12 <= 1'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed12 <= 1'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed12 <= 1'd0;
+                       array_muxed12 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed12 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+                       array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
                end
                2'd2: begin
-                       vns_array_muxed12 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+                       array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
                end
                default: begin
-                       vns_array_muxed12 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+                       array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
                end
        endcase
 // synthesis translate_off
-       dummy_d_400 = dummy_s;
+       dummy_d_339 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_401;
+reg dummy_d_340;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed13 <= 1'd0;
-       case (soc_sdram_steerer_sel1)
+       array_muxed13 <= 1'd0;
+       case (litedramcore_steerer_sel1)
                1'd0: begin
-                       vns_array_muxed13 <= 1'd0;
+                       array_muxed13 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed13 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+                       array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
                end
                2'd2: begin
-                       vns_array_muxed13 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+                       array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
                end
                default: begin
-                       vns_array_muxed13 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+                       array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
                end
        endcase
 // synthesis translate_off
-       dummy_d_401 = dummy_s;
+       dummy_d_340 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_402;
+reg dummy_d_341;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed14 <= 3'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed14 <= 3'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed14 <= soc_sdram_nop_ba[2:0];
+                       array_muxed14 <= litedramcore_nop_ba[2:0];
                end
                1'd1: begin
-                       vns_array_muxed14 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+                       array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
                end
                2'd2: begin
-                       vns_array_muxed14 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+                       array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
                end
                default: begin
-                       vns_array_muxed14 <= soc_sdram_cmd_payload_ba[2:0];
+                       array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
                end
        endcase
 // synthesis translate_off
-       dummy_d_402 = dummy_s;
+       dummy_d_341 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_403;
+reg dummy_d_342;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed15 <= 15'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed15 <= 15'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed15 <= soc_sdram_nop_a;
+                       array_muxed15 <= litedramcore_nop_a;
                end
                1'd1: begin
-                       vns_array_muxed15 <= soc_sdram_choose_cmd_cmd_payload_a;
+                       array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
                end
                2'd2: begin
-                       vns_array_muxed15 <= soc_sdram_choose_req_cmd_payload_a;
+                       array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
                end
                default: begin
-                       vns_array_muxed15 <= soc_sdram_cmd_payload_a;
+                       array_muxed15 <= litedramcore_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_403 = dummy_s;
+       dummy_d_342 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_404;
+reg dummy_d_343;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed16 <= 1'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed16 <= 1'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed16 <= 1'd0;
+                       array_muxed16 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed16 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+                       array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
                end
                2'd2: begin
-                       vns_array_muxed16 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+                       array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
                end
                default: begin
-                       vns_array_muxed16 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+                       array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
                end
        endcase
 // synthesis translate_off
-       dummy_d_404 = dummy_s;
+       dummy_d_343 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_405;
+reg dummy_d_344;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed17 <= 1'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed17 <= 1'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed17 <= 1'd0;
+                       array_muxed17 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed17 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+                       array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
                end
                2'd2: begin
-                       vns_array_muxed17 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+                       array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
                end
                default: begin
-                       vns_array_muxed17 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+                       array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
                end
        endcase
 // synthesis translate_off
-       dummy_d_405 = dummy_s;
+       dummy_d_344 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_406;
+reg dummy_d_345;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed18 <= 1'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed18 <= 1'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed18 <= 1'd0;
+                       array_muxed18 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed18 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+                       array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
                end
                2'd2: begin
-                       vns_array_muxed18 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+                       array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
                end
                default: begin
-                       vns_array_muxed18 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+                       array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
                end
        endcase
 // synthesis translate_off
-       dummy_d_406 = dummy_s;
+       dummy_d_345 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_407;
+reg dummy_d_346;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed19 <= 1'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed19 <= 1'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed19 <= 1'd0;
+                       array_muxed19 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed19 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+                       array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
                end
                2'd2: begin
-                       vns_array_muxed19 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+                       array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
                end
                default: begin
-                       vns_array_muxed19 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+                       array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
                end
        endcase
 // synthesis translate_off
-       dummy_d_407 = dummy_s;
+       dummy_d_346 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_408;
+reg dummy_d_347;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed20 <= 1'd0;
-       case (soc_sdram_steerer_sel2)
+       array_muxed20 <= 1'd0;
+       case (litedramcore_steerer_sel2)
                1'd0: begin
-                       vns_array_muxed20 <= 1'd0;
+                       array_muxed20 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed20 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+                       array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
                end
                2'd2: begin
-                       vns_array_muxed20 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+                       array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
                end
                default: begin
-                       vns_array_muxed20 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+                       array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
                end
        endcase
 // synthesis translate_off
-       dummy_d_408 = dummy_s;
+       dummy_d_347 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_409;
+reg dummy_d_348;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed21 <= 3'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed21 <= 3'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed21 <= soc_sdram_nop_ba[2:0];
+                       array_muxed21 <= litedramcore_nop_ba[2:0];
                end
                1'd1: begin
-                       vns_array_muxed21 <= soc_sdram_choose_cmd_cmd_payload_ba[2:0];
+                       array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
                end
                2'd2: begin
-                       vns_array_muxed21 <= soc_sdram_choose_req_cmd_payload_ba[2:0];
+                       array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
                end
                default: begin
-                       vns_array_muxed21 <= soc_sdram_cmd_payload_ba[2:0];
+                       array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
                end
        endcase
 // synthesis translate_off
-       dummy_d_409 = dummy_s;
+       dummy_d_348 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_410;
+reg dummy_d_349;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed22 <= 15'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed22 <= 15'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed22 <= soc_sdram_nop_a;
+                       array_muxed22 <= litedramcore_nop_a;
                end
                1'd1: begin
-                       vns_array_muxed22 <= soc_sdram_choose_cmd_cmd_payload_a;
+                       array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
                end
                2'd2: begin
-                       vns_array_muxed22 <= soc_sdram_choose_req_cmd_payload_a;
+                       array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
                end
                default: begin
-                       vns_array_muxed22 <= soc_sdram_cmd_payload_a;
+                       array_muxed22 <= litedramcore_cmd_payload_a;
                end
        endcase
 // synthesis translate_off
-       dummy_d_410 = dummy_s;
+       dummy_d_349 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_411;
+reg dummy_d_350;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed23 <= 1'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed23 <= 1'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed23 <= 1'd0;
+                       array_muxed23 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed23 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_cas);
+                       array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
                end
                2'd2: begin
-                       vns_array_muxed23 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_cas);
+                       array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
                end
                default: begin
-                       vns_array_muxed23 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_cas);
+                       array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
                end
        endcase
 // synthesis translate_off
-       dummy_d_411 = dummy_s;
+       dummy_d_350 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_412;
+reg dummy_d_351;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed24 <= 1'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed24 <= 1'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed24 <= 1'd0;
+                       array_muxed24 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed24 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_ras);
+                       array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
                end
                2'd2: begin
-                       vns_array_muxed24 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_ras);
+                       array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
                end
                default: begin
-                       vns_array_muxed24 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_ras);
+                       array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
                end
        endcase
 // synthesis translate_off
-       dummy_d_412 = dummy_s;
+       dummy_d_351 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_413;
+reg dummy_d_352;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed25 <= 1'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed25 <= 1'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed25 <= 1'd0;
+                       array_muxed25 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed25 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_we);
+                       array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
                end
                2'd2: begin
-                       vns_array_muxed25 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_we);
+                       array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
                end
                default: begin
-                       vns_array_muxed25 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_we);
+                       array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
                end
        endcase
 // synthesis translate_off
-       dummy_d_413 = dummy_s;
+       dummy_d_352 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_414;
+reg dummy_d_353;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed26 <= 1'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed26 <= 1'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed26 <= 1'd0;
+                       array_muxed26 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed26 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_read);
+                       array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
                end
                2'd2: begin
-                       vns_array_muxed26 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_read);
+                       array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
                end
                default: begin
-                       vns_array_muxed26 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_read);
+                       array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
                end
        endcase
 // synthesis translate_off
-       dummy_d_414 = dummy_s;
+       dummy_d_353 = dummy_s;
 // synthesis translate_on
 end
 
 // synthesis translate_off
-reg dummy_d_415;
+reg dummy_d_354;
 // synthesis translate_on
 always @(*) begin
-       vns_array_muxed27 <= 1'd0;
-       case (soc_sdram_steerer_sel3)
+       array_muxed27 <= 1'd0;
+       case (litedramcore_steerer_sel3)
                1'd0: begin
-                       vns_array_muxed27 <= 1'd0;
+                       array_muxed27 <= 1'd0;
                end
                1'd1: begin
-                       vns_array_muxed27 <= ((soc_sdram_choose_cmd_cmd_valid & soc_sdram_choose_cmd_cmd_ready) & soc_sdram_choose_cmd_cmd_payload_is_write);
+                       array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
                end
                2'd2: begin
-                       vns_array_muxed27 <= ((soc_sdram_choose_req_cmd_valid & soc_sdram_choose_req_cmd_ready) & soc_sdram_choose_req_cmd_payload_is_write);
+                       array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
                end
                default: begin
-                       vns_array_muxed27 <= ((soc_sdram_cmd_valid & soc_sdram_cmd_ready) & soc_sdram_cmd_payload_is_write);
+                       array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
                end
        endcase
 // synthesis translate_off
-       dummy_d_415 = dummy_s;
-// synthesis translate_on
-end
-assign soc_litedramcore_rx = vns_regs1;
-assign vns_xilinxasyncresetsynchronizerimpl0 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
-assign vns_xilinxasyncresetsynchronizerimpl1 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
-assign vns_xilinxasyncresetsynchronizerimpl2 = ((~soc_sys_pll_locked) | soc_sys_pll_reset);
-assign vns_xilinxasyncresetsynchronizerimpl3 = ((~soc_iodelay_pll_locked) | soc_iodelay_pll_reset);
-
-always @(posedge iodelay_clk) begin
-       if ((soc_reset_counter != 1'd0)) begin
-               soc_reset_counter <= (soc_reset_counter - 1'd1);
-       end else begin
-               soc_ic_reset <= 1'd0;
-       end
-       if (iodelay_rst) begin
-               soc_reset_counter <= 4'd15;
-               soc_ic_reset <= 1'd1;
-       end
-end
-
-always @(posedge sys_clk) begin
-       if ((soc_litedramcore_soccontroller_bus_errors != 32'd4294967295)) begin
-               if (soc_litedramcore_soccontroller_bus_error) begin
-                       soc_litedramcore_soccontroller_bus_errors <= (soc_litedramcore_soccontroller_bus_errors + 1'd1);
-               end
-       end
-       soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0;
-       if (((soc_litedramcore_litedramcore_ram_bus_cyc & soc_litedramcore_litedramcore_ram_bus_stb) & (~soc_litedramcore_litedramcore_ram_bus_ack))) begin
-               soc_litedramcore_litedramcore_ram_bus_ack <= 1'd1;
-       end
-       soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0;
-       if (((soc_litedramcore_ram_bus_ram_bus_cyc & soc_litedramcore_ram_bus_ram_bus_stb) & (~soc_litedramcore_ram_bus_ram_bus_ack))) begin
-               soc_litedramcore_ram_bus_ram_bus_ack <= 1'd1;
-       end
-       soc_litedramcore_sink_ready <= 1'd0;
-       if (((soc_litedramcore_sink_valid & (~soc_litedramcore_tx_busy)) & (~soc_litedramcore_sink_ready))) begin
-               soc_litedramcore_tx_reg <= soc_litedramcore_sink_payload_data;
-               soc_litedramcore_tx_bitcount <= 1'd0;
-               soc_litedramcore_tx_busy <= 1'd1;
-               serial_tx <= 1'd0;
-       end else begin
-               if ((soc_litedramcore_uart_clk_txen & soc_litedramcore_tx_busy)) begin
-                       soc_litedramcore_tx_bitcount <= (soc_litedramcore_tx_bitcount + 1'd1);
-                       if ((soc_litedramcore_tx_bitcount == 4'd8)) begin
-                               serial_tx <= 1'd1;
-                       end else begin
-                               if ((soc_litedramcore_tx_bitcount == 4'd9)) begin
-                                       serial_tx <= 1'd1;
-                                       soc_litedramcore_tx_busy <= 1'd0;
-                                       soc_litedramcore_sink_ready <= 1'd1;
-                               end else begin
-                                       serial_tx <= soc_litedramcore_tx_reg[0];
-                                       soc_litedramcore_tx_reg <= {1'd0, soc_litedramcore_tx_reg[7:1]};
-                               end
-                       end
-               end
-       end
-       if (soc_litedramcore_tx_busy) begin
-               {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= (soc_litedramcore_phase_accumulator_tx + soc_litedramcore_storage);
-       end else begin
-               {soc_litedramcore_uart_clk_txen, soc_litedramcore_phase_accumulator_tx} <= 1'd0;
-       end
-       soc_litedramcore_source_valid <= 1'd0;
-       soc_litedramcore_rx_r <= soc_litedramcore_rx;
-       if ((~soc_litedramcore_rx_busy)) begin
-               if (((~soc_litedramcore_rx) & soc_litedramcore_rx_r)) begin
-                       soc_litedramcore_rx_busy <= 1'd1;
-                       soc_litedramcore_rx_bitcount <= 1'd0;
-               end
-       end else begin
-               if (soc_litedramcore_uart_clk_rxen) begin
-                       soc_litedramcore_rx_bitcount <= (soc_litedramcore_rx_bitcount + 1'd1);
-                       if ((soc_litedramcore_rx_bitcount == 1'd0)) begin
-                               if (soc_litedramcore_rx) begin
-                                       soc_litedramcore_rx_busy <= 1'd0;
-                               end
-                       end else begin
-                               if ((soc_litedramcore_rx_bitcount == 4'd9)) begin
-                                       soc_litedramcore_rx_busy <= 1'd0;
-                                       if (soc_litedramcore_rx) begin
-                                               soc_litedramcore_source_payload_data <= soc_litedramcore_rx_reg;
-                                               soc_litedramcore_source_valid <= 1'd1;
-                                       end
-                               end else begin
-                                       soc_litedramcore_rx_reg <= {soc_litedramcore_rx, soc_litedramcore_rx_reg[7:1]};
-                               end
-                       end
-               end
-       end
-       if (soc_litedramcore_rx_busy) begin
-               {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= (soc_litedramcore_phase_accumulator_rx + soc_litedramcore_storage);
-       end else begin
-               {soc_litedramcore_uart_clk_rxen, soc_litedramcore_phase_accumulator_rx} <= 32'd2147483648;
-       end
-       if (soc_litedramcore_uart_tx_clear) begin
-               soc_litedramcore_uart_tx_pending <= 1'd0;
-       end
-       soc_litedramcore_uart_tx_old_trigger <= soc_litedramcore_uart_tx_trigger;
-       if (((~soc_litedramcore_uart_tx_trigger) & soc_litedramcore_uart_tx_old_trigger)) begin
-               soc_litedramcore_uart_tx_pending <= 1'd1;
-       end
-       if (soc_litedramcore_uart_rx_clear) begin
-               soc_litedramcore_uart_rx_pending <= 1'd0;
-       end
-       soc_litedramcore_uart_rx_old_trigger <= soc_litedramcore_uart_rx_trigger;
-       if (((~soc_litedramcore_uart_rx_trigger) & soc_litedramcore_uart_rx_old_trigger)) begin
-               soc_litedramcore_uart_rx_pending <= 1'd1;
-       end
-       if (soc_litedramcore_uart_tx_fifo_syncfifo_re) begin
-               soc_litedramcore_uart_tx_fifo_readable <= 1'd1;
-       end else begin
-               if (soc_litedramcore_uart_tx_fifo_re) begin
-                       soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
-               end
-       end
-       if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin
-               soc_litedramcore_uart_tx_fifo_produce <= (soc_litedramcore_uart_tx_fifo_produce + 1'd1);
-       end
-       if (soc_litedramcore_uart_tx_fifo_do_read) begin
-               soc_litedramcore_uart_tx_fifo_consume <= (soc_litedramcore_uart_tx_fifo_consume + 1'd1);
-       end
-       if (((soc_litedramcore_uart_tx_fifo_syncfifo_we & soc_litedramcore_uart_tx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_tx_fifo_replace))) begin
-               if ((~soc_litedramcore_uart_tx_fifo_do_read)) begin
-                       soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 + 1'd1);
-               end
-       end else begin
-               if (soc_litedramcore_uart_tx_fifo_do_read) begin
-                       soc_litedramcore_uart_tx_fifo_level0 <= (soc_litedramcore_uart_tx_fifo_level0 - 1'd1);
-               end
-       end
-       if (soc_litedramcore_uart_rx_fifo_syncfifo_re) begin
-               soc_litedramcore_uart_rx_fifo_readable <= 1'd1;
-       end else begin
-               if (soc_litedramcore_uart_rx_fifo_re) begin
-                       soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
-               end
-       end
-       if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin
-               soc_litedramcore_uart_rx_fifo_produce <= (soc_litedramcore_uart_rx_fifo_produce + 1'd1);
-       end
-       if (soc_litedramcore_uart_rx_fifo_do_read) begin
-               soc_litedramcore_uart_rx_fifo_consume <= (soc_litedramcore_uart_rx_fifo_consume + 1'd1);
-       end
-       if (((soc_litedramcore_uart_rx_fifo_syncfifo_we & soc_litedramcore_uart_rx_fifo_syncfifo_writable) & (~soc_litedramcore_uart_rx_fifo_replace))) begin
-               if ((~soc_litedramcore_uart_rx_fifo_do_read)) begin
-                       soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 + 1'd1);
-               end
-       end else begin
-               if (soc_litedramcore_uart_rx_fifo_do_read) begin
-                       soc_litedramcore_uart_rx_fifo_level0 <= (soc_litedramcore_uart_rx_fifo_level0 - 1'd1);
-               end
-       end
-       if (soc_litedramcore_uart_reset) begin
-               soc_litedramcore_uart_tx_pending <= 1'd0;
-               soc_litedramcore_uart_tx_old_trigger <= 1'd0;
-               soc_litedramcore_uart_rx_pending <= 1'd0;
-               soc_litedramcore_uart_rx_old_trigger <= 1'd0;
-               soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
-               soc_litedramcore_uart_tx_fifo_level0 <= 5'd0;
-               soc_litedramcore_uart_tx_fifo_produce <= 4'd0;
-               soc_litedramcore_uart_tx_fifo_consume <= 4'd0;
-               soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
-               soc_litedramcore_uart_rx_fifo_level0 <= 5'd0;
-               soc_litedramcore_uart_rx_fifo_produce <= 4'd0;
-               soc_litedramcore_uart_rx_fifo_consume <= 4'd0;
-       end
-       if (soc_litedramcore_timer_en_storage) begin
-               if ((soc_litedramcore_timer_value == 1'd0)) begin
-                       soc_litedramcore_timer_value <= soc_litedramcore_timer_reload_storage;
-               end else begin
-                       soc_litedramcore_timer_value <= (soc_litedramcore_timer_value - 1'd1);
-               end
+       dummy_d_354 = dummy_s;
+// synthesis translate_on
+end
+assign xilinxasyncresetsynchronizerimpl0 = ((~sys_pll_locked) | sys_pll_reset);
+assign xilinxasyncresetsynchronizerimpl1 = ((~sys_pll_locked) | sys_pll_reset);
+assign xilinxasyncresetsynchronizerimpl2 = ((~sys_pll_locked) | sys_pll_reset);
+assign xilinxasyncresetsynchronizerimpl3 = ((~iodelay_pll_locked) | iodelay_pll_reset);
+
+always @(posedge iodelay_clk) begin
+       if ((reset_counter != 1'd0)) begin
+               reset_counter <= (reset_counter - 1'd1);
        end else begin
-               soc_litedramcore_timer_value <= soc_litedramcore_timer_load_storage;
-       end
-       if (soc_litedramcore_timer_update_value_re) begin
-               soc_litedramcore_timer_value_status <= soc_litedramcore_timer_value;
+               ic_reset <= 1'd0;
        end
-       if (soc_litedramcore_timer_zero_clear) begin
-               soc_litedramcore_timer_zero_pending <= 1'd0;
-       end
-       soc_litedramcore_timer_zero_old_trigger <= soc_litedramcore_timer_zero_trigger;
-       if (((~soc_litedramcore_timer_zero_trigger) & soc_litedramcore_timer_zero_old_trigger)) begin
-               soc_litedramcore_timer_zero_pending <= 1'd1;
+       if (iodelay_rst) begin
+               reset_counter <= 4'd15;
+               ic_reset <= 1'd1;
        end
-       vns_wb2csr_state <= vns_wb2csr_next_state;
-       soc_a7ddrphy_dqs_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dqs_oe) | soc_a7ddrphy_dqspattern1);
-       soc_a7ddrphy_dq_oe_delayed <= ((soc_a7ddrphy_dqspattern0 | soc_a7ddrphy_dq_oe) | soc_a7ddrphy_dqspattern1);
-       soc_a7ddrphy_rddata_en_last <= soc_a7ddrphy_rddata_en;
-       soc_a7ddrphy_dfi_p0_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
-       soc_a7ddrphy_dfi_p1_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
-       soc_a7ddrphy_dfi_p2_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
-       soc_a7ddrphy_dfi_p3_rddata_valid <= (soc_a7ddrphy_rddata_en[7] | soc_a7ddrphy_wlevel_en_storage);
-       soc_a7ddrphy_wrdata_en_last <= soc_a7ddrphy_wrdata_en;
-       soc_a7ddrphy_dqspattern_o1 <= soc_a7ddrphy_dqspattern_o0;
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip0_value <= (soc_a7ddrphy_bitslip0_value + 1'd1);
+end
+
+always @(posedge sys_clk) begin
+       a7ddrphy_dqs_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dqs_oe) | a7ddrphy_dqspattern1);
+       a7ddrphy_dq_oe_delayed <= ((a7ddrphy_dqspattern0 | a7ddrphy_dq_oe) | a7ddrphy_dqspattern1);
+       a7ddrphy_rddata_en_last <= a7ddrphy_rddata_en;
+       a7ddrphy_dfi_p0_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
+       a7ddrphy_dfi_p1_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
+       a7ddrphy_dfi_p2_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
+       a7ddrphy_dfi_p3_rddata_valid <= (a7ddrphy_rddata_en[7] | a7ddrphy_wlevel_en_storage);
+       a7ddrphy_wrdata_en_last <= a7ddrphy_wrdata_en;
+       a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip0_value <= (a7ddrphy_bitslip0_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip0_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip0_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip0_r <= {soc_a7ddrphy_bitslip0_i, soc_a7ddrphy_bitslip0_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip1_value <= (soc_a7ddrphy_bitslip1_value + 1'd1);
+       a7ddrphy_bitslip0_r <= {a7ddrphy_bitslip0_i, a7ddrphy_bitslip0_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip1_value <= (a7ddrphy_bitslip1_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip1_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip1_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip1_r <= {soc_a7ddrphy_bitslip1_i, soc_a7ddrphy_bitslip1_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip2_value <= (soc_a7ddrphy_bitslip2_value + 1'd1);
+       a7ddrphy_bitslip1_r <= {a7ddrphy_bitslip1_i, a7ddrphy_bitslip1_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip2_value <= (a7ddrphy_bitslip2_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip2_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip2_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip2_r <= {soc_a7ddrphy_bitslip2_i, soc_a7ddrphy_bitslip2_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip3_value <= (soc_a7ddrphy_bitslip3_value + 1'd1);
+       a7ddrphy_bitslip2_r <= {a7ddrphy_bitslip2_i, a7ddrphy_bitslip2_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip3_value <= (a7ddrphy_bitslip3_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip3_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip3_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip3_r <= {soc_a7ddrphy_bitslip3_i, soc_a7ddrphy_bitslip3_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip4_value <= (soc_a7ddrphy_bitslip4_value + 1'd1);
+       a7ddrphy_bitslip3_r <= {a7ddrphy_bitslip3_i, a7ddrphy_bitslip3_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip4_value <= (a7ddrphy_bitslip4_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip4_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip4_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip4_r <= {soc_a7ddrphy_bitslip4_i, soc_a7ddrphy_bitslip4_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip5_value <= (soc_a7ddrphy_bitslip5_value + 1'd1);
+       a7ddrphy_bitslip4_r <= {a7ddrphy_bitslip4_i, a7ddrphy_bitslip4_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip5_value <= (a7ddrphy_bitslip5_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip5_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip5_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip5_r <= {soc_a7ddrphy_bitslip5_i, soc_a7ddrphy_bitslip5_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip6_value <= (soc_a7ddrphy_bitslip6_value + 1'd1);
+       a7ddrphy_bitslip5_r <= {a7ddrphy_bitslip5_i, a7ddrphy_bitslip5_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip6_value <= (a7ddrphy_bitslip6_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip6_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip6_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip6_r <= {soc_a7ddrphy_bitslip6_i, soc_a7ddrphy_bitslip6_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip7_value <= (soc_a7ddrphy_bitslip7_value + 1'd1);
+       a7ddrphy_bitslip6_r <= {a7ddrphy_bitslip6_i, a7ddrphy_bitslip6_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip7_value <= (a7ddrphy_bitslip7_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip7_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip7_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip7_r <= {soc_a7ddrphy_bitslip7_i, soc_a7ddrphy_bitslip7_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip8_value <= (soc_a7ddrphy_bitslip8_value + 1'd1);
+       a7ddrphy_bitslip7_r <= {a7ddrphy_bitslip7_i, a7ddrphy_bitslip7_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip8_value <= (a7ddrphy_bitslip8_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip8_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip8_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip8_r <= {soc_a7ddrphy_bitslip8_i, soc_a7ddrphy_bitslip8_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip9_value <= (soc_a7ddrphy_bitslip9_value + 1'd1);
+       a7ddrphy_bitslip8_r <= {a7ddrphy_bitslip8_i, a7ddrphy_bitslip8_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip9_value <= (a7ddrphy_bitslip9_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip9_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip9_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip9_r <= {soc_a7ddrphy_bitslip9_i, soc_a7ddrphy_bitslip9_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip10_value <= (soc_a7ddrphy_bitslip10_value + 1'd1);
+       a7ddrphy_bitslip9_r <= {a7ddrphy_bitslip9_i, a7ddrphy_bitslip9_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip10_value <= (a7ddrphy_bitslip10_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip10_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip10_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip10_r <= {soc_a7ddrphy_bitslip10_i, soc_a7ddrphy_bitslip10_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip11_value <= (soc_a7ddrphy_bitslip11_value + 1'd1);
+       a7ddrphy_bitslip10_r <= {a7ddrphy_bitslip10_i, a7ddrphy_bitslip10_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip11_value <= (a7ddrphy_bitslip11_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip11_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip11_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip11_r <= {soc_a7ddrphy_bitslip11_i, soc_a7ddrphy_bitslip11_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip12_value <= (soc_a7ddrphy_bitslip12_value + 1'd1);
+       a7ddrphy_bitslip11_r <= {a7ddrphy_bitslip11_i, a7ddrphy_bitslip11_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip12_value <= (a7ddrphy_bitslip12_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip12_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip12_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip12_r <= {soc_a7ddrphy_bitslip12_i, soc_a7ddrphy_bitslip12_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip13_value <= (soc_a7ddrphy_bitslip13_value + 1'd1);
+       a7ddrphy_bitslip12_r <= {a7ddrphy_bitslip12_i, a7ddrphy_bitslip12_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip13_value <= (a7ddrphy_bitslip13_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip13_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip13_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip13_r <= {soc_a7ddrphy_bitslip13_i, soc_a7ddrphy_bitslip13_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip14_value <= (soc_a7ddrphy_bitslip14_value + 1'd1);
+       a7ddrphy_bitslip13_r <= {a7ddrphy_bitslip13_i, a7ddrphy_bitslip13_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip14_value <= (a7ddrphy_bitslip14_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip14_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip14_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip14_r <= {soc_a7ddrphy_bitslip14_i, soc_a7ddrphy_bitslip14_r[15:8]};
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_re)) begin
-               soc_a7ddrphy_bitslip15_value <= (soc_a7ddrphy_bitslip15_value + 1'd1);
+       a7ddrphy_bitslip14_r <= {a7ddrphy_bitslip14_i, a7ddrphy_bitslip14_r[15:8]};
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+               a7ddrphy_bitslip15_value <= (a7ddrphy_bitslip15_value + 1'd1);
        end
-       if ((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_bitslip_rst_re)) begin
-               soc_a7ddrphy_bitslip15_value <= 1'd0;
+       if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re)) begin
+               a7ddrphy_bitslip15_value <= 1'd0;
        end
-       soc_a7ddrphy_bitslip15_r <= {soc_a7ddrphy_bitslip15_i, soc_a7ddrphy_bitslip15_r[15:8]};
-       if (soc_sdram_inti_p0_rddata_valid) begin
-               soc_sdram_phaseinjector0_status <= soc_sdram_inti_p0_rddata;
+       a7ddrphy_bitslip15_r <= {a7ddrphy_bitslip15_i, a7ddrphy_bitslip15_r[15:8]};
+       if (litedramcore_inti_p0_rddata_valid) begin
+               litedramcore_phaseinjector0_status <= litedramcore_inti_p0_rddata;
        end
-       if (soc_sdram_inti_p1_rddata_valid) begin
-               soc_sdram_phaseinjector1_status <= soc_sdram_inti_p1_rddata;
+       if (litedramcore_inti_p1_rddata_valid) begin
+               litedramcore_phaseinjector1_status <= litedramcore_inti_p1_rddata;
        end
-       if (soc_sdram_inti_p2_rddata_valid) begin
-               soc_sdram_phaseinjector2_status <= soc_sdram_inti_p2_rddata;
+       if (litedramcore_inti_p2_rddata_valid) begin
+               litedramcore_phaseinjector2_status <= litedramcore_inti_p2_rddata;
        end
-       if (soc_sdram_inti_p3_rddata_valid) begin
-               soc_sdram_phaseinjector3_status <= soc_sdram_inti_p3_rddata;
+       if (litedramcore_inti_p3_rddata_valid) begin
+               litedramcore_phaseinjector3_status <= litedramcore_inti_p3_rddata;
        end
-       if ((soc_sdram_timer_wait & (~soc_sdram_timer_done0))) begin
-               soc_sdram_timer_count1 <= (soc_sdram_timer_count1 - 1'd1);
+       if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+               litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
        end else begin
-               soc_sdram_timer_count1 <= 10'd781;
+               litedramcore_timer_count1 <= 10'd781;
        end
-       soc_sdram_postponer_req_o <= 1'd0;
-       if (soc_sdram_postponer_req_i) begin
-               soc_sdram_postponer_count <= (soc_sdram_postponer_count - 1'd1);
-               if ((soc_sdram_postponer_count == 1'd0)) begin
-                       soc_sdram_postponer_count <= 1'd0;
-                       soc_sdram_postponer_req_o <= 1'd1;
+       litedramcore_postponer_req_o <= 1'd0;
+       if (litedramcore_postponer_req_i) begin
+               litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+               if ((litedramcore_postponer_count == 1'd0)) begin
+                       litedramcore_postponer_count <= 1'd0;
+                       litedramcore_postponer_req_o <= 1'd1;
                end
        end
-       if (soc_sdram_sequencer_start0) begin
-               soc_sdram_sequencer_count <= 1'd0;
+       if (litedramcore_sequencer_start0) begin
+               litedramcore_sequencer_count <= 1'd0;
        end else begin
-               if (soc_sdram_sequencer_done1) begin
-                       if ((soc_sdram_sequencer_count != 1'd0)) begin
-                               soc_sdram_sequencer_count <= (soc_sdram_sequencer_count - 1'd1);
-                       end
-               end
-       end
-       soc_sdram_cmd_payload_a <= 1'd0;
-       soc_sdram_cmd_payload_ba <= 1'd0;
-       soc_sdram_cmd_payload_cas <= 1'd0;
-       soc_sdram_cmd_payload_ras <= 1'd0;
-       soc_sdram_cmd_payload_we <= 1'd0;
-       soc_sdram_sequencer_done1 <= 1'd0;
-       if ((soc_sdram_sequencer_start1 & (soc_sdram_sequencer_counter == 1'd0))) begin
-               soc_sdram_cmd_payload_a <= 11'd1024;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd0;
-               soc_sdram_cmd_payload_ras <= 1'd1;
-               soc_sdram_cmd_payload_we <= 1'd1;
-       end
-       if ((soc_sdram_sequencer_counter == 2'd3)) begin
-               soc_sdram_cmd_payload_a <= 1'd0;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd1;
-               soc_sdram_cmd_payload_ras <= 1'd1;
-               soc_sdram_cmd_payload_we <= 1'd0;
-       end
-       if ((soc_sdram_sequencer_counter == 6'd55)) begin
-               soc_sdram_cmd_payload_a <= 1'd0;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd0;
-               soc_sdram_cmd_payload_ras <= 1'd0;
-               soc_sdram_cmd_payload_we <= 1'd0;
-               soc_sdram_sequencer_done1 <= 1'd1;
-       end
-       if ((soc_sdram_sequencer_counter == 6'd55)) begin
-               soc_sdram_sequencer_counter <= 1'd0;
+               if (litedramcore_sequencer_done1) begin
+                       if ((litedramcore_sequencer_count != 1'd0)) begin
+                               litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+                       end
+               end
+       end
+       litedramcore_cmd_payload_a <= 1'd0;
+       litedramcore_cmd_payload_ba <= 1'd0;
+       litedramcore_cmd_payload_cas <= 1'd0;
+       litedramcore_cmd_payload_ras <= 1'd0;
+       litedramcore_cmd_payload_we <= 1'd0;
+       litedramcore_sequencer_done1 <= 1'd0;
+       if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+               litedramcore_cmd_payload_a <= 11'd1024;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd1;
+               litedramcore_cmd_payload_we <= 1'd1;
+       end
+       if ((litedramcore_sequencer_counter == 2'd3)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd1;
+               litedramcore_cmd_payload_ras <= 1'd1;
+               litedramcore_cmd_payload_we <= 1'd0;
+       end
+       if ((litedramcore_sequencer_counter == 6'd55)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd0;
+               litedramcore_cmd_payload_we <= 1'd0;
+               litedramcore_sequencer_done1 <= 1'd1;
+       end
+       if ((litedramcore_sequencer_counter == 6'd55)) begin
+               litedramcore_sequencer_counter <= 1'd0;
        end else begin
-               if ((soc_sdram_sequencer_counter != 1'd0)) begin
-                       soc_sdram_sequencer_counter <= (soc_sdram_sequencer_counter + 1'd1);
+               if ((litedramcore_sequencer_counter != 1'd0)) begin
+                       litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
                end else begin
-                       if (soc_sdram_sequencer_start1) begin
-                               soc_sdram_sequencer_counter <= 1'd1;
+                       if (litedramcore_sequencer_start1) begin
+                               litedramcore_sequencer_counter <= 1'd1;
                        end
                end
        end
-       if ((soc_sdram_zqcs_timer_wait & (~soc_sdram_zqcs_timer_done0))) begin
-               soc_sdram_zqcs_timer_count1 <= (soc_sdram_zqcs_timer_count1 - 1'd1);
+       if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+               litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
        end else begin
-               soc_sdram_zqcs_timer_count1 <= 27'd99999999;
-       end
-       soc_sdram_zqcs_executer_done <= 1'd0;
-       if ((soc_sdram_zqcs_executer_start & (soc_sdram_zqcs_executer_counter == 1'd0))) begin
-               soc_sdram_cmd_payload_a <= 11'd1024;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd0;
-               soc_sdram_cmd_payload_ras <= 1'd1;
-               soc_sdram_cmd_payload_we <= 1'd1;
-       end
-       if ((soc_sdram_zqcs_executer_counter == 2'd3)) begin
-               soc_sdram_cmd_payload_a <= 1'd0;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd0;
-               soc_sdram_cmd_payload_ras <= 1'd0;
-               soc_sdram_cmd_payload_we <= 1'd1;
-       end
-       if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin
-               soc_sdram_cmd_payload_a <= 1'd0;
-               soc_sdram_cmd_payload_ba <= 1'd0;
-               soc_sdram_cmd_payload_cas <= 1'd0;
-               soc_sdram_cmd_payload_ras <= 1'd0;
-               soc_sdram_cmd_payload_we <= 1'd0;
-               soc_sdram_zqcs_executer_done <= 1'd1;
-       end
-       if ((soc_sdram_zqcs_executer_counter == 5'd19)) begin
-               soc_sdram_zqcs_executer_counter <= 1'd0;
+               litedramcore_zqcs_timer_count1 <= 27'd99999999;
+       end
+       litedramcore_zqcs_executer_done <= 1'd0;
+       if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+               litedramcore_cmd_payload_a <= 11'd1024;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd1;
+               litedramcore_cmd_payload_we <= 1'd1;
+       end
+       if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd0;
+               litedramcore_cmd_payload_we <= 1'd1;
+       end
+       if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+               litedramcore_cmd_payload_a <= 1'd0;
+               litedramcore_cmd_payload_ba <= 1'd0;
+               litedramcore_cmd_payload_cas <= 1'd0;
+               litedramcore_cmd_payload_ras <= 1'd0;
+               litedramcore_cmd_payload_we <= 1'd0;
+               litedramcore_zqcs_executer_done <= 1'd1;
+       end
+       if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+               litedramcore_zqcs_executer_counter <= 1'd0;
        end else begin
-               if ((soc_sdram_zqcs_executer_counter != 1'd0)) begin
-                       soc_sdram_zqcs_executer_counter <= (soc_sdram_zqcs_executer_counter + 1'd1);
+               if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+                       litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
                end else begin
-                       if (soc_sdram_zqcs_executer_start) begin
-                               soc_sdram_zqcs_executer_counter <= 1'd1;
+                       if (litedramcore_zqcs_executer_start) begin
+                               litedramcore_zqcs_executer_counter <= 1'd1;
                        end
                end
        end
-       vns_refresher_state <= vns_refresher_next_state;
-       if (soc_sdram_bankmachine0_row_close) begin
-               soc_sdram_bankmachine0_row_opened <= 1'd0;
+       refresher_state <= refresher_next_state;
+       if (litedramcore_bankmachine0_row_close) begin
+               litedramcore_bankmachine0_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine0_row_open) begin
-                       soc_sdram_bankmachine0_row_opened <= 1'd1;
-                       soc_sdram_bankmachine0_row <= soc_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:7];
+               if (litedramcore_bankmachine0_row_open) begin
+                       litedramcore_bankmachine0_row_opened <= 1'd1;
+                       litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
                end
        end
-       if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_sdram_bankmachine0_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine0_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine0_cmd_buffer_source_valid) | soc_sdram_bankmachine0_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine0_cmd_buffer_source_valid <= soc_sdram_bankmachine0_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine0_cmd_buffer_source_first <= soc_sdram_bankmachine0_cmd_buffer_sink_first;
-               soc_sdram_bankmachine0_cmd_buffer_source_last <= soc_sdram_bankmachine0_cmd_buffer_sink_last;
-               soc_sdram_bankmachine0_cmd_buffer_source_payload_we <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine0_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine0_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
+               litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
+               litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
+               litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine0_twtpcon_valid) begin
-               soc_sdram_bankmachine0_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine0_twtpcon_valid) begin
+               litedramcore_bankmachine0_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine0_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine0_twtpcon_ready)) begin
-                       soc_sdram_bankmachine0_twtpcon_count <= (soc_sdram_bankmachine0_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine0_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+                       litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine0_trccon_valid) begin
-               soc_sdram_bankmachine0_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine0_trccon_valid) begin
+               litedramcore_bankmachine0_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine0_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine0_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine0_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine0_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine0_trccon_ready)) begin
-                       soc_sdram_bankmachine0_trccon_count <= (soc_sdram_bankmachine0_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine0_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine0_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine0_trccon_ready)) begin
+                       litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine0_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine0_trascon_valid) begin
-               soc_sdram_bankmachine0_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine0_trascon_valid) begin
+               litedramcore_bankmachine0_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine0_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine0_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine0_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine0_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine0_trascon_ready)) begin
-                       soc_sdram_bankmachine0_trascon_count <= (soc_sdram_bankmachine0_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine0_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine0_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine0_trascon_ready)) begin
+                       litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine0_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine0_state <= vns_bankmachine0_next_state;
-       if (soc_sdram_bankmachine1_row_close) begin
-               soc_sdram_bankmachine1_row_opened <= 1'd0;
+       bankmachine0_state <= bankmachine0_next_state;
+       if (litedramcore_bankmachine1_row_close) begin
+               litedramcore_bankmachine1_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine1_row_open) begin
-                       soc_sdram_bankmachine1_row_opened <= 1'd1;
-                       soc_sdram_bankmachine1_row <= soc_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:7];
+               if (litedramcore_bankmachine1_row_open) begin
+                       litedramcore_bankmachine1_row_opened <= 1'd1;
+                       litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
                end
        end
-       if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_sdram_bankmachine1_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine1_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine1_cmd_buffer_source_valid) | soc_sdram_bankmachine1_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine1_cmd_buffer_source_valid <= soc_sdram_bankmachine1_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine1_cmd_buffer_source_first <= soc_sdram_bankmachine1_cmd_buffer_sink_first;
-               soc_sdram_bankmachine1_cmd_buffer_source_last <= soc_sdram_bankmachine1_cmd_buffer_sink_last;
-               soc_sdram_bankmachine1_cmd_buffer_source_payload_we <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine1_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine1_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
+               litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
+               litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
+               litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine1_twtpcon_valid) begin
-               soc_sdram_bankmachine1_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine1_twtpcon_valid) begin
+               litedramcore_bankmachine1_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine1_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine1_twtpcon_ready)) begin
-                       soc_sdram_bankmachine1_twtpcon_count <= (soc_sdram_bankmachine1_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine1_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+                       litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine1_trccon_valid) begin
-               soc_sdram_bankmachine1_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine1_trccon_valid) begin
+               litedramcore_bankmachine1_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine1_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine1_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine1_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine1_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine1_trccon_ready)) begin
-                       soc_sdram_bankmachine1_trccon_count <= (soc_sdram_bankmachine1_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine1_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine1_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine1_trccon_ready)) begin
+                       litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine1_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine1_trascon_valid) begin
-               soc_sdram_bankmachine1_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine1_trascon_valid) begin
+               litedramcore_bankmachine1_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine1_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine1_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine1_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine1_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine1_trascon_ready)) begin
-                       soc_sdram_bankmachine1_trascon_count <= (soc_sdram_bankmachine1_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine1_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine1_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine1_trascon_ready)) begin
+                       litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine1_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine1_state <= vns_bankmachine1_next_state;
-       if (soc_sdram_bankmachine2_row_close) begin
-               soc_sdram_bankmachine2_row_opened <= 1'd0;
+       bankmachine1_state <= bankmachine1_next_state;
+       if (litedramcore_bankmachine2_row_close) begin
+               litedramcore_bankmachine2_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine2_row_open) begin
-                       soc_sdram_bankmachine2_row_opened <= 1'd1;
-                       soc_sdram_bankmachine2_row <= soc_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:7];
+               if (litedramcore_bankmachine2_row_open) begin
+                       litedramcore_bankmachine2_row_opened <= 1'd1;
+                       litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
                end
        end
-       if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_sdram_bankmachine2_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine2_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine2_cmd_buffer_source_valid) | soc_sdram_bankmachine2_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine2_cmd_buffer_source_valid <= soc_sdram_bankmachine2_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine2_cmd_buffer_source_first <= soc_sdram_bankmachine2_cmd_buffer_sink_first;
-               soc_sdram_bankmachine2_cmd_buffer_source_last <= soc_sdram_bankmachine2_cmd_buffer_sink_last;
-               soc_sdram_bankmachine2_cmd_buffer_source_payload_we <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine2_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine2_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
+               litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
+               litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
+               litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine2_twtpcon_valid) begin
-               soc_sdram_bankmachine2_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine2_twtpcon_valid) begin
+               litedramcore_bankmachine2_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine2_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine2_twtpcon_ready)) begin
-                       soc_sdram_bankmachine2_twtpcon_count <= (soc_sdram_bankmachine2_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine2_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+                       litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine2_trccon_valid) begin
-               soc_sdram_bankmachine2_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine2_trccon_valid) begin
+               litedramcore_bankmachine2_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine2_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine2_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine2_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine2_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine2_trccon_ready)) begin
-                       soc_sdram_bankmachine2_trccon_count <= (soc_sdram_bankmachine2_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine2_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine2_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine2_trccon_ready)) begin
+                       litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine2_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine2_trascon_valid) begin
-               soc_sdram_bankmachine2_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine2_trascon_valid) begin
+               litedramcore_bankmachine2_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine2_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine2_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine2_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine2_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine2_trascon_ready)) begin
-                       soc_sdram_bankmachine2_trascon_count <= (soc_sdram_bankmachine2_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine2_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine2_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine2_trascon_ready)) begin
+                       litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine2_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine2_state <= vns_bankmachine2_next_state;
-       if (soc_sdram_bankmachine3_row_close) begin
-               soc_sdram_bankmachine3_row_opened <= 1'd0;
+       bankmachine2_state <= bankmachine2_next_state;
+       if (litedramcore_bankmachine3_row_close) begin
+               litedramcore_bankmachine3_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine3_row_open) begin
-                       soc_sdram_bankmachine3_row_opened <= 1'd1;
-                       soc_sdram_bankmachine3_row <= soc_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:7];
+               if (litedramcore_bankmachine3_row_open) begin
+                       litedramcore_bankmachine3_row_opened <= 1'd1;
+                       litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
                end
        end
-       if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_sdram_bankmachine3_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine3_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine3_cmd_buffer_source_valid) | soc_sdram_bankmachine3_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine3_cmd_buffer_source_valid <= soc_sdram_bankmachine3_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine3_cmd_buffer_source_first <= soc_sdram_bankmachine3_cmd_buffer_sink_first;
-               soc_sdram_bankmachine3_cmd_buffer_source_last <= soc_sdram_bankmachine3_cmd_buffer_sink_last;
-               soc_sdram_bankmachine3_cmd_buffer_source_payload_we <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine3_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine3_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
+               litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
+               litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
+               litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine3_twtpcon_valid) begin
-               soc_sdram_bankmachine3_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine3_twtpcon_valid) begin
+               litedramcore_bankmachine3_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine3_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine3_twtpcon_ready)) begin
-                       soc_sdram_bankmachine3_twtpcon_count <= (soc_sdram_bankmachine3_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine3_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+                       litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine3_trccon_valid) begin
-               soc_sdram_bankmachine3_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine3_trccon_valid) begin
+               litedramcore_bankmachine3_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine3_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine3_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine3_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine3_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine3_trccon_ready)) begin
-                       soc_sdram_bankmachine3_trccon_count <= (soc_sdram_bankmachine3_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine3_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine3_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine3_trccon_ready)) begin
+                       litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine3_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine3_trascon_valid) begin
-               soc_sdram_bankmachine3_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine3_trascon_valid) begin
+               litedramcore_bankmachine3_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine3_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine3_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine3_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine3_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine3_trascon_ready)) begin
-                       soc_sdram_bankmachine3_trascon_count <= (soc_sdram_bankmachine3_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine3_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine3_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine3_trascon_ready)) begin
+                       litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine3_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine3_state <= vns_bankmachine3_next_state;
-       if (soc_sdram_bankmachine4_row_close) begin
-               soc_sdram_bankmachine4_row_opened <= 1'd0;
+       bankmachine3_state <= bankmachine3_next_state;
+       if (litedramcore_bankmachine4_row_close) begin
+               litedramcore_bankmachine4_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine4_row_open) begin
-                       soc_sdram_bankmachine4_row_opened <= 1'd1;
-                       soc_sdram_bankmachine4_row <= soc_sdram_bankmachine4_cmd_buffer_source_payload_addr[21:7];
+               if (litedramcore_bankmachine4_row_open) begin
+                       litedramcore_bankmachine4_row_opened <= 1'd1;
+                       litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
                end
        end
-       if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_sdram_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_sdram_bankmachine4_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine4_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine4_cmd_buffer_source_valid) | soc_sdram_bankmachine4_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine4_cmd_buffer_source_valid <= soc_sdram_bankmachine4_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine4_cmd_buffer_source_first <= soc_sdram_bankmachine4_cmd_buffer_sink_first;
-               soc_sdram_bankmachine4_cmd_buffer_source_last <= soc_sdram_bankmachine4_cmd_buffer_sink_last;
-               soc_sdram_bankmachine4_cmd_buffer_source_payload_we <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine4_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine4_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
+               litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
+               litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
+               litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine4_twtpcon_valid) begin
-               soc_sdram_bankmachine4_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine4_twtpcon_valid) begin
+               litedramcore_bankmachine4_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine4_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine4_twtpcon_ready)) begin
-                       soc_sdram_bankmachine4_twtpcon_count <= (soc_sdram_bankmachine4_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine4_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+                       litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine4_trccon_valid) begin
-               soc_sdram_bankmachine4_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine4_trccon_valid) begin
+               litedramcore_bankmachine4_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine4_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine4_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine4_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine4_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine4_trccon_ready)) begin
-                       soc_sdram_bankmachine4_trccon_count <= (soc_sdram_bankmachine4_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine4_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine4_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine4_trccon_ready)) begin
+                       litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine4_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine4_trascon_valid) begin
-               soc_sdram_bankmachine4_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine4_trascon_valid) begin
+               litedramcore_bankmachine4_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine4_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine4_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine4_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine4_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine4_trascon_ready)) begin
-                       soc_sdram_bankmachine4_trascon_count <= (soc_sdram_bankmachine4_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine4_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine4_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine4_trascon_ready)) begin
+                       litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine4_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine4_state <= vns_bankmachine4_next_state;
-       if (soc_sdram_bankmachine5_row_close) begin
-               soc_sdram_bankmachine5_row_opened <= 1'd0;
+       bankmachine4_state <= bankmachine4_next_state;
+       if (litedramcore_bankmachine5_row_close) begin
+               litedramcore_bankmachine5_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine5_row_open) begin
-                       soc_sdram_bankmachine5_row_opened <= 1'd1;
-                       soc_sdram_bankmachine5_row <= soc_sdram_bankmachine5_cmd_buffer_source_payload_addr[21:7];
+               if (litedramcore_bankmachine5_row_open) begin
+                       litedramcore_bankmachine5_row_opened <= 1'd1;
+                       litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
                end
        end
-       if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_sdram_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_sdram_bankmachine5_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine5_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine5_cmd_buffer_source_valid) | soc_sdram_bankmachine5_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine5_cmd_buffer_source_valid <= soc_sdram_bankmachine5_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine5_cmd_buffer_source_first <= soc_sdram_bankmachine5_cmd_buffer_sink_first;
-               soc_sdram_bankmachine5_cmd_buffer_source_last <= soc_sdram_bankmachine5_cmd_buffer_sink_last;
-               soc_sdram_bankmachine5_cmd_buffer_source_payload_we <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine5_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine5_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
+               litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
+               litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
+               litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine5_twtpcon_valid) begin
-               soc_sdram_bankmachine5_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine5_twtpcon_valid) begin
+               litedramcore_bankmachine5_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine5_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine5_twtpcon_ready)) begin
-                       soc_sdram_bankmachine5_twtpcon_count <= (soc_sdram_bankmachine5_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine5_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+                       litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine5_trccon_valid) begin
-               soc_sdram_bankmachine5_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine5_trccon_valid) begin
+               litedramcore_bankmachine5_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine5_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine5_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine5_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine5_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine5_trccon_ready)) begin
-                       soc_sdram_bankmachine5_trccon_count <= (soc_sdram_bankmachine5_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine5_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine5_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine5_trccon_ready)) begin
+                       litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine5_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine5_trascon_valid) begin
-               soc_sdram_bankmachine5_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine5_trascon_valid) begin
+               litedramcore_bankmachine5_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine5_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine5_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine5_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine5_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine5_trascon_ready)) begin
-                       soc_sdram_bankmachine5_trascon_count <= (soc_sdram_bankmachine5_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine5_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine5_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine5_trascon_ready)) begin
+                       litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine5_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine5_state <= vns_bankmachine5_next_state;
-       if (soc_sdram_bankmachine6_row_close) begin
-               soc_sdram_bankmachine6_row_opened <= 1'd0;
+       bankmachine5_state <= bankmachine5_next_state;
+       if (litedramcore_bankmachine6_row_close) begin
+               litedramcore_bankmachine6_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine6_row_open) begin
-                       soc_sdram_bankmachine6_row_opened <= 1'd1;
-                       soc_sdram_bankmachine6_row <= soc_sdram_bankmachine6_cmd_buffer_source_payload_addr[21:7];
+               if (litedramcore_bankmachine6_row_open) begin
+                       litedramcore_bankmachine6_row_opened <= 1'd1;
+                       litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
                end
        end
-       if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_sdram_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_sdram_bankmachine6_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine6_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine6_cmd_buffer_source_valid) | soc_sdram_bankmachine6_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine6_cmd_buffer_source_valid <= soc_sdram_bankmachine6_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine6_cmd_buffer_source_first <= soc_sdram_bankmachine6_cmd_buffer_sink_first;
-               soc_sdram_bankmachine6_cmd_buffer_source_last <= soc_sdram_bankmachine6_cmd_buffer_sink_last;
-               soc_sdram_bankmachine6_cmd_buffer_source_payload_we <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine6_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine6_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
+               litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
+               litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
+               litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine6_twtpcon_valid) begin
-               soc_sdram_bankmachine6_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine6_twtpcon_valid) begin
+               litedramcore_bankmachine6_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine6_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine6_twtpcon_ready)) begin
-                       soc_sdram_bankmachine6_twtpcon_count <= (soc_sdram_bankmachine6_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine6_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+                       litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine6_trccon_valid) begin
-               soc_sdram_bankmachine6_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine6_trccon_valid) begin
+               litedramcore_bankmachine6_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine6_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine6_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine6_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine6_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine6_trccon_ready)) begin
-                       soc_sdram_bankmachine6_trccon_count <= (soc_sdram_bankmachine6_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine6_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine6_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine6_trccon_ready)) begin
+                       litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine6_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine6_trascon_valid) begin
-               soc_sdram_bankmachine6_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine6_trascon_valid) begin
+               litedramcore_bankmachine6_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine6_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine6_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine6_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine6_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine6_trascon_ready)) begin
-                       soc_sdram_bankmachine6_trascon_count <= (soc_sdram_bankmachine6_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine6_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine6_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine6_trascon_ready)) begin
+                       litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine6_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine6_state <= vns_bankmachine6_next_state;
-       if (soc_sdram_bankmachine7_row_close) begin
-               soc_sdram_bankmachine7_row_opened <= 1'd0;
+       bankmachine6_state <= bankmachine6_next_state;
+       if (litedramcore_bankmachine7_row_close) begin
+               litedramcore_bankmachine7_row_opened <= 1'd0;
        end else begin
-               if (soc_sdram_bankmachine7_row_open) begin
-                       soc_sdram_bankmachine7_row_opened <= 1'd1;
-                       soc_sdram_bankmachine7_row <= soc_sdram_bankmachine7_cmd_buffer_source_payload_addr[21:7];
+               if (litedramcore_bankmachine7_row_open) begin
+                       litedramcore_bankmachine7_row_opened <= 1'd1;
+                       litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
                end
        end
-       if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
+       if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
        end
-       if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
+       if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+               litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
        end
-       if (((soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_sdram_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_sdram_bankmachine7_cmd_buffer_lookahead_replace))) begin
-               if ((~soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read)) begin
-                       soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
+       if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
+               if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
+                       litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
                end
        end else begin
-               if (soc_sdram_bankmachine7_cmd_buffer_lookahead_do_read) begin
-                       soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= (soc_sdram_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
+               if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
+                       litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
                end
        end
-       if (((~soc_sdram_bankmachine7_cmd_buffer_source_valid) | soc_sdram_bankmachine7_cmd_buffer_source_ready)) begin
-               soc_sdram_bankmachine7_cmd_buffer_source_valid <= soc_sdram_bankmachine7_cmd_buffer_sink_valid;
-               soc_sdram_bankmachine7_cmd_buffer_source_first <= soc_sdram_bankmachine7_cmd_buffer_sink_first;
-               soc_sdram_bankmachine7_cmd_buffer_source_last <= soc_sdram_bankmachine7_cmd_buffer_sink_last;
-               soc_sdram_bankmachine7_cmd_buffer_source_payload_we <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_we;
-               soc_sdram_bankmachine7_cmd_buffer_source_payload_addr <= soc_sdram_bankmachine7_cmd_buffer_sink_payload_addr;
+       if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
+               litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
+               litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
+               litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
+               litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
+               litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
        end
-       if (soc_sdram_bankmachine7_twtpcon_valid) begin
-               soc_sdram_bankmachine7_twtpcon_count <= 3'd5;
+       if (litedramcore_bankmachine7_twtpcon_valid) begin
+               litedramcore_bankmachine7_twtpcon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
+                       litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine7_twtpcon_ready <= 1'd0;
+                       litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine7_twtpcon_ready)) begin
-                       soc_sdram_bankmachine7_twtpcon_count <= (soc_sdram_bankmachine7_twtpcon_count - 1'd1);
-                       if ((soc_sdram_bankmachine7_twtpcon_count == 1'd1)) begin
-                               soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+                       litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+                       if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+                               litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine7_trccon_valid) begin
-               soc_sdram_bankmachine7_trccon_count <= 3'd5;
+       if (litedramcore_bankmachine7_trccon_valid) begin
+               litedramcore_bankmachine7_trccon_count <= 3'd5;
                if (1'd0) begin
-                       soc_sdram_bankmachine7_trccon_ready <= 1'd1;
+                       litedramcore_bankmachine7_trccon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine7_trccon_ready <= 1'd0;
+                       litedramcore_bankmachine7_trccon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine7_trccon_ready)) begin
-                       soc_sdram_bankmachine7_trccon_count <= (soc_sdram_bankmachine7_trccon_count - 1'd1);
-                       if ((soc_sdram_bankmachine7_trccon_count == 1'd1)) begin
-                               soc_sdram_bankmachine7_trccon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine7_trccon_ready)) begin
+                       litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+                       if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+                               litedramcore_bankmachine7_trccon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_bankmachine7_trascon_valid) begin
-               soc_sdram_bankmachine7_trascon_count <= 3'd4;
+       if (litedramcore_bankmachine7_trascon_valid) begin
+               litedramcore_bankmachine7_trascon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_bankmachine7_trascon_ready <= 1'd1;
+                       litedramcore_bankmachine7_trascon_ready <= 1'd1;
                end else begin
-                       soc_sdram_bankmachine7_trascon_ready <= 1'd0;
+                       litedramcore_bankmachine7_trascon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_bankmachine7_trascon_ready)) begin
-                       soc_sdram_bankmachine7_trascon_count <= (soc_sdram_bankmachine7_trascon_count - 1'd1);
-                       if ((soc_sdram_bankmachine7_trascon_count == 1'd1)) begin
-                               soc_sdram_bankmachine7_trascon_ready <= 1'd1;
+               if ((~litedramcore_bankmachine7_trascon_ready)) begin
+                       litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+                       if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+                               litedramcore_bankmachine7_trascon_ready <= 1'd1;
                        end
                end
        end
-       vns_bankmachine7_state <= vns_bankmachine7_next_state;
-       if ((~soc_sdram_en0)) begin
-               soc_sdram_time0 <= 5'd31;
+       bankmachine7_state <= bankmachine7_next_state;
+       if ((~litedramcore_en0)) begin
+               litedramcore_time0 <= 5'd31;
        end else begin
-               if ((~soc_sdram_max_time0)) begin
-                       soc_sdram_time0 <= (soc_sdram_time0 - 1'd1);
+               if ((~litedramcore_max_time0)) begin
+                       litedramcore_time0 <= (litedramcore_time0 - 1'd1);
                end
        end
-       if ((~soc_sdram_en1)) begin
-               soc_sdram_time1 <= 4'd15;
+       if ((~litedramcore_en1)) begin
+               litedramcore_time1 <= 4'd15;
        end else begin
-               if ((~soc_sdram_max_time1)) begin
-                       soc_sdram_time1 <= (soc_sdram_time1 - 1'd1);
+               if ((~litedramcore_max_time1)) begin
+                       litedramcore_time1 <= (litedramcore_time1 - 1'd1);
                end
        end
-       if (soc_sdram_choose_cmd_ce) begin
-               case (soc_sdram_choose_cmd_grant)
+       if (litedramcore_choose_cmd_ce) begin
+               case (litedramcore_choose_cmd_grant)
                        1'd0: begin
-                               if (soc_sdram_choose_cmd_request[1]) begin
-                                       soc_sdram_choose_cmd_grant <= 1'd1;
+                               if (litedramcore_choose_cmd_request[1]) begin
+                                       litedramcore_choose_cmd_grant <= 1'd1;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[2]) begin
-                                               soc_sdram_choose_cmd_grant <= 2'd2;
+                                       if (litedramcore_choose_cmd_request[2]) begin
+                                               litedramcore_choose_cmd_grant <= 2'd2;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[3]) begin
-                                                       soc_sdram_choose_cmd_grant <= 2'd3;
+                                               if (litedramcore_choose_cmd_request[3]) begin
+                                                       litedramcore_choose_cmd_grant <= 2'd3;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[4]) begin
-                                                               soc_sdram_choose_cmd_grant <= 3'd4;
+                                                       if (litedramcore_choose_cmd_request[4]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd4;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[5]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 3'd5;
+                                                               if (litedramcore_choose_cmd_request[5]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd5;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[6]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 3'd6;
+                                                                       if (litedramcore_choose_cmd_request[6]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd6;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[7]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 3'd7;
+                                                                               if (litedramcore_choose_cmd_request[7]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd7;
                                                                                end
                                                                        end
                                                                end
@@ -15999,26 +13619,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        1'd1: begin
-                               if (soc_sdram_choose_cmd_request[2]) begin
-                                       soc_sdram_choose_cmd_grant <= 2'd2;
+                               if (litedramcore_choose_cmd_request[2]) begin
+                                       litedramcore_choose_cmd_grant <= 2'd2;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[3]) begin
-                                               soc_sdram_choose_cmd_grant <= 2'd3;
+                                       if (litedramcore_choose_cmd_request[3]) begin
+                                               litedramcore_choose_cmd_grant <= 2'd3;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[4]) begin
-                                                       soc_sdram_choose_cmd_grant <= 3'd4;
+                                               if (litedramcore_choose_cmd_request[4]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd4;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[5]) begin
-                                                               soc_sdram_choose_cmd_grant <= 3'd5;
+                                                       if (litedramcore_choose_cmd_request[5]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd5;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[6]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 3'd6;
+                                                               if (litedramcore_choose_cmd_request[6]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd6;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[7]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 3'd7;
+                                                                       if (litedramcore_choose_cmd_request[7]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd7;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[0]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 1'd0;
+                                                                               if (litedramcore_choose_cmd_request[0]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 1'd0;
                                                                                end
                                                                        end
                                                                end
@@ -16028,26 +13648,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        2'd2: begin
-                               if (soc_sdram_choose_cmd_request[3]) begin
-                                       soc_sdram_choose_cmd_grant <= 2'd3;
+                               if (litedramcore_choose_cmd_request[3]) begin
+                                       litedramcore_choose_cmd_grant <= 2'd3;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[4]) begin
-                                               soc_sdram_choose_cmd_grant <= 3'd4;
+                                       if (litedramcore_choose_cmd_request[4]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd4;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[5]) begin
-                                                       soc_sdram_choose_cmd_grant <= 3'd5;
+                                               if (litedramcore_choose_cmd_request[5]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd5;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[6]) begin
-                                                               soc_sdram_choose_cmd_grant <= 3'd6;
+                                                       if (litedramcore_choose_cmd_request[6]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd6;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[7]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 3'd7;
+                                                               if (litedramcore_choose_cmd_request[7]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd7;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[0]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 1'd0;
+                                                                       if (litedramcore_choose_cmd_request[0]) begin
+                                                                               litedramcore_choose_cmd_grant <= 1'd0;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[1]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 1'd1;
+                                                                               if (litedramcore_choose_cmd_request[1]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 1'd1;
                                                                                end
                                                                        end
                                                                end
@@ -16057,26 +13677,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        2'd3: begin
-                               if (soc_sdram_choose_cmd_request[4]) begin
-                                       soc_sdram_choose_cmd_grant <= 3'd4;
+                               if (litedramcore_choose_cmd_request[4]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd4;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[5]) begin
-                                               soc_sdram_choose_cmd_grant <= 3'd5;
+                                       if (litedramcore_choose_cmd_request[5]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd5;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[6]) begin
-                                                       soc_sdram_choose_cmd_grant <= 3'd6;
+                                               if (litedramcore_choose_cmd_request[6]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd6;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[7]) begin
-                                                               soc_sdram_choose_cmd_grant <= 3'd7;
+                                                       if (litedramcore_choose_cmd_request[7]) begin
+                                                               litedramcore_choose_cmd_grant <= 3'd7;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[0]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 1'd0;
+                                                               if (litedramcore_choose_cmd_request[0]) begin
+                                                                       litedramcore_choose_cmd_grant <= 1'd0;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[1]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 1'd1;
+                                                                       if (litedramcore_choose_cmd_request[1]) begin
+                                                                               litedramcore_choose_cmd_grant <= 1'd1;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[2]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 2'd2;
+                                                                               if (litedramcore_choose_cmd_request[2]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 2'd2;
                                                                                end
                                                                        end
                                                                end
@@ -16086,26 +13706,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd4: begin
-                               if (soc_sdram_choose_cmd_request[5]) begin
-                                       soc_sdram_choose_cmd_grant <= 3'd5;
+                               if (litedramcore_choose_cmd_request[5]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd5;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[6]) begin
-                                               soc_sdram_choose_cmd_grant <= 3'd6;
+                                       if (litedramcore_choose_cmd_request[6]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd6;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[7]) begin
-                                                       soc_sdram_choose_cmd_grant <= 3'd7;
+                                               if (litedramcore_choose_cmd_request[7]) begin
+                                                       litedramcore_choose_cmd_grant <= 3'd7;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[0]) begin
-                                                               soc_sdram_choose_cmd_grant <= 1'd0;
+                                                       if (litedramcore_choose_cmd_request[0]) begin
+                                                               litedramcore_choose_cmd_grant <= 1'd0;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[1]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 1'd1;
+                                                               if (litedramcore_choose_cmd_request[1]) begin
+                                                                       litedramcore_choose_cmd_grant <= 1'd1;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[2]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 2'd2;
+                                                                       if (litedramcore_choose_cmd_request[2]) begin
+                                                                               litedramcore_choose_cmd_grant <= 2'd2;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[3]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 2'd3;
+                                                                               if (litedramcore_choose_cmd_request[3]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 2'd3;
                                                                                end
                                                                        end
                                                                end
@@ -16115,26 +13735,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd5: begin
-                               if (soc_sdram_choose_cmd_request[6]) begin
-                                       soc_sdram_choose_cmd_grant <= 3'd6;
+                               if (litedramcore_choose_cmd_request[6]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd6;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[7]) begin
-                                               soc_sdram_choose_cmd_grant <= 3'd7;
+                                       if (litedramcore_choose_cmd_request[7]) begin
+                                               litedramcore_choose_cmd_grant <= 3'd7;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[0]) begin
-                                                       soc_sdram_choose_cmd_grant <= 1'd0;
+                                               if (litedramcore_choose_cmd_request[0]) begin
+                                                       litedramcore_choose_cmd_grant <= 1'd0;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[1]) begin
-                                                               soc_sdram_choose_cmd_grant <= 1'd1;
+                                                       if (litedramcore_choose_cmd_request[1]) begin
+                                                               litedramcore_choose_cmd_grant <= 1'd1;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[2]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 2'd2;
+                                                               if (litedramcore_choose_cmd_request[2]) begin
+                                                                       litedramcore_choose_cmd_grant <= 2'd2;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[3]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 2'd3;
+                                                                       if (litedramcore_choose_cmd_request[3]) begin
+                                                                               litedramcore_choose_cmd_grant <= 2'd3;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[4]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 3'd4;
+                                                                               if (litedramcore_choose_cmd_request[4]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd4;
                                                                                end
                                                                        end
                                                                end
@@ -16144,26 +13764,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd6: begin
-                               if (soc_sdram_choose_cmd_request[7]) begin
-                                       soc_sdram_choose_cmd_grant <= 3'd7;
+                               if (litedramcore_choose_cmd_request[7]) begin
+                                       litedramcore_choose_cmd_grant <= 3'd7;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[0]) begin
-                                               soc_sdram_choose_cmd_grant <= 1'd0;
+                                       if (litedramcore_choose_cmd_request[0]) begin
+                                               litedramcore_choose_cmd_grant <= 1'd0;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[1]) begin
-                                                       soc_sdram_choose_cmd_grant <= 1'd1;
+                                               if (litedramcore_choose_cmd_request[1]) begin
+                                                       litedramcore_choose_cmd_grant <= 1'd1;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[2]) begin
-                                                               soc_sdram_choose_cmd_grant <= 2'd2;
+                                                       if (litedramcore_choose_cmd_request[2]) begin
+                                                               litedramcore_choose_cmd_grant <= 2'd2;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[3]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 2'd3;
+                                                               if (litedramcore_choose_cmd_request[3]) begin
+                                                                       litedramcore_choose_cmd_grant <= 2'd3;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[4]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 3'd4;
+                                                                       if (litedramcore_choose_cmd_request[4]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd4;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[5]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 3'd5;
+                                                                               if (litedramcore_choose_cmd_request[5]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd5;
                                                                                end
                                                                        end
                                                                end
@@ -16173,26 +13793,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd7: begin
-                               if (soc_sdram_choose_cmd_request[0]) begin
-                                       soc_sdram_choose_cmd_grant <= 1'd0;
+                               if (litedramcore_choose_cmd_request[0]) begin
+                                       litedramcore_choose_cmd_grant <= 1'd0;
                                end else begin
-                                       if (soc_sdram_choose_cmd_request[1]) begin
-                                               soc_sdram_choose_cmd_grant <= 1'd1;
+                                       if (litedramcore_choose_cmd_request[1]) begin
+                                               litedramcore_choose_cmd_grant <= 1'd1;
                                        end else begin
-                                               if (soc_sdram_choose_cmd_request[2]) begin
-                                                       soc_sdram_choose_cmd_grant <= 2'd2;
+                                               if (litedramcore_choose_cmd_request[2]) begin
+                                                       litedramcore_choose_cmd_grant <= 2'd2;
                                                end else begin
-                                                       if (soc_sdram_choose_cmd_request[3]) begin
-                                                               soc_sdram_choose_cmd_grant <= 2'd3;
+                                                       if (litedramcore_choose_cmd_request[3]) begin
+                                                               litedramcore_choose_cmd_grant <= 2'd3;
                                                        end else begin
-                                                               if (soc_sdram_choose_cmd_request[4]) begin
-                                                                       soc_sdram_choose_cmd_grant <= 3'd4;
+                                                               if (litedramcore_choose_cmd_request[4]) begin
+                                                                       litedramcore_choose_cmd_grant <= 3'd4;
                                                                end else begin
-                                                                       if (soc_sdram_choose_cmd_request[5]) begin
-                                                                               soc_sdram_choose_cmd_grant <= 3'd5;
+                                                                       if (litedramcore_choose_cmd_request[5]) begin
+                                                                               litedramcore_choose_cmd_grant <= 3'd5;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_cmd_request[6]) begin
-                                                                                       soc_sdram_choose_cmd_grant <= 3'd6;
+                                                                               if (litedramcore_choose_cmd_request[6]) begin
+                                                                                       litedramcore_choose_cmd_grant <= 3'd6;
                                                                                end
                                                                        end
                                                                end
@@ -16203,29 +13823,29 @@ always @(posedge sys_clk) begin
                        end
                endcase
        end
-       if (soc_sdram_choose_req_ce) begin
-               case (soc_sdram_choose_req_grant)
+       if (litedramcore_choose_req_ce) begin
+               case (litedramcore_choose_req_grant)
                        1'd0: begin
-                               if (soc_sdram_choose_req_request[1]) begin
-                                       soc_sdram_choose_req_grant <= 1'd1;
+                               if (litedramcore_choose_req_request[1]) begin
+                                       litedramcore_choose_req_grant <= 1'd1;
                                end else begin
-                                       if (soc_sdram_choose_req_request[2]) begin
-                                               soc_sdram_choose_req_grant <= 2'd2;
+                                       if (litedramcore_choose_req_request[2]) begin
+                                               litedramcore_choose_req_grant <= 2'd2;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[3]) begin
-                                                       soc_sdram_choose_req_grant <= 2'd3;
+                                               if (litedramcore_choose_req_request[3]) begin
+                                                       litedramcore_choose_req_grant <= 2'd3;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[4]) begin
-                                                               soc_sdram_choose_req_grant <= 3'd4;
+                                                       if (litedramcore_choose_req_request[4]) begin
+                                                               litedramcore_choose_req_grant <= 3'd4;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[5]) begin
-                                                                       soc_sdram_choose_req_grant <= 3'd5;
+                                                               if (litedramcore_choose_req_request[5]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd5;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[6]) begin
-                                                                               soc_sdram_choose_req_grant <= 3'd6;
+                                                                       if (litedramcore_choose_req_request[6]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd6;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[7]) begin
-                                                                                       soc_sdram_choose_req_grant <= 3'd7;
+                                                                               if (litedramcore_choose_req_request[7]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd7;
                                                                                end
                                                                        end
                                                                end
@@ -16235,26 +13855,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        1'd1: begin
-                               if (soc_sdram_choose_req_request[2]) begin
-                                       soc_sdram_choose_req_grant <= 2'd2;
+                               if (litedramcore_choose_req_request[2]) begin
+                                       litedramcore_choose_req_grant <= 2'd2;
                                end else begin
-                                       if (soc_sdram_choose_req_request[3]) begin
-                                               soc_sdram_choose_req_grant <= 2'd3;
+                                       if (litedramcore_choose_req_request[3]) begin
+                                               litedramcore_choose_req_grant <= 2'd3;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[4]) begin
-                                                       soc_sdram_choose_req_grant <= 3'd4;
+                                               if (litedramcore_choose_req_request[4]) begin
+                                                       litedramcore_choose_req_grant <= 3'd4;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[5]) begin
-                                                               soc_sdram_choose_req_grant <= 3'd5;
+                                                       if (litedramcore_choose_req_request[5]) begin
+                                                               litedramcore_choose_req_grant <= 3'd5;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[6]) begin
-                                                                       soc_sdram_choose_req_grant <= 3'd6;
+                                                               if (litedramcore_choose_req_request[6]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd6;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[7]) begin
-                                                                               soc_sdram_choose_req_grant <= 3'd7;
+                                                                       if (litedramcore_choose_req_request[7]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd7;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[0]) begin
-                                                                                       soc_sdram_choose_req_grant <= 1'd0;
+                                                                               if (litedramcore_choose_req_request[0]) begin
+                                                                                       litedramcore_choose_req_grant <= 1'd0;
                                                                                end
                                                                        end
                                                                end
@@ -16264,26 +13884,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        2'd2: begin
-                               if (soc_sdram_choose_req_request[3]) begin
-                                       soc_sdram_choose_req_grant <= 2'd3;
+                               if (litedramcore_choose_req_request[3]) begin
+                                       litedramcore_choose_req_grant <= 2'd3;
                                end else begin
-                                       if (soc_sdram_choose_req_request[4]) begin
-                                               soc_sdram_choose_req_grant <= 3'd4;
+                                       if (litedramcore_choose_req_request[4]) begin
+                                               litedramcore_choose_req_grant <= 3'd4;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[5]) begin
-                                                       soc_sdram_choose_req_grant <= 3'd5;
+                                               if (litedramcore_choose_req_request[5]) begin
+                                                       litedramcore_choose_req_grant <= 3'd5;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[6]) begin
-                                                               soc_sdram_choose_req_grant <= 3'd6;
+                                                       if (litedramcore_choose_req_request[6]) begin
+                                                               litedramcore_choose_req_grant <= 3'd6;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[7]) begin
-                                                                       soc_sdram_choose_req_grant <= 3'd7;
+                                                               if (litedramcore_choose_req_request[7]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd7;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[0]) begin
-                                                                               soc_sdram_choose_req_grant <= 1'd0;
+                                                                       if (litedramcore_choose_req_request[0]) begin
+                                                                               litedramcore_choose_req_grant <= 1'd0;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[1]) begin
-                                                                                       soc_sdram_choose_req_grant <= 1'd1;
+                                                                               if (litedramcore_choose_req_request[1]) begin
+                                                                                       litedramcore_choose_req_grant <= 1'd1;
                                                                                end
                                                                        end
                                                                end
@@ -16293,26 +13913,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        2'd3: begin
-                               if (soc_sdram_choose_req_request[4]) begin
-                                       soc_sdram_choose_req_grant <= 3'd4;
+                               if (litedramcore_choose_req_request[4]) begin
+                                       litedramcore_choose_req_grant <= 3'd4;
                                end else begin
-                                       if (soc_sdram_choose_req_request[5]) begin
-                                               soc_sdram_choose_req_grant <= 3'd5;
+                                       if (litedramcore_choose_req_request[5]) begin
+                                               litedramcore_choose_req_grant <= 3'd5;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[6]) begin
-                                                       soc_sdram_choose_req_grant <= 3'd6;
+                                               if (litedramcore_choose_req_request[6]) begin
+                                                       litedramcore_choose_req_grant <= 3'd6;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[7]) begin
-                                                               soc_sdram_choose_req_grant <= 3'd7;
+                                                       if (litedramcore_choose_req_request[7]) begin
+                                                               litedramcore_choose_req_grant <= 3'd7;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[0]) begin
-                                                                       soc_sdram_choose_req_grant <= 1'd0;
+                                                               if (litedramcore_choose_req_request[0]) begin
+                                                                       litedramcore_choose_req_grant <= 1'd0;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[1]) begin
-                                                                               soc_sdram_choose_req_grant <= 1'd1;
+                                                                       if (litedramcore_choose_req_request[1]) begin
+                                                                               litedramcore_choose_req_grant <= 1'd1;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[2]) begin
-                                                                                       soc_sdram_choose_req_grant <= 2'd2;
+                                                                               if (litedramcore_choose_req_request[2]) begin
+                                                                                       litedramcore_choose_req_grant <= 2'd2;
                                                                                end
                                                                        end
                                                                end
@@ -16322,26 +13942,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd4: begin
-                               if (soc_sdram_choose_req_request[5]) begin
-                                       soc_sdram_choose_req_grant <= 3'd5;
+                               if (litedramcore_choose_req_request[5]) begin
+                                       litedramcore_choose_req_grant <= 3'd5;
                                end else begin
-                                       if (soc_sdram_choose_req_request[6]) begin
-                                               soc_sdram_choose_req_grant <= 3'd6;
+                                       if (litedramcore_choose_req_request[6]) begin
+                                               litedramcore_choose_req_grant <= 3'd6;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[7]) begin
-                                                       soc_sdram_choose_req_grant <= 3'd7;
+                                               if (litedramcore_choose_req_request[7]) begin
+                                                       litedramcore_choose_req_grant <= 3'd7;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[0]) begin
-                                                               soc_sdram_choose_req_grant <= 1'd0;
+                                                       if (litedramcore_choose_req_request[0]) begin
+                                                               litedramcore_choose_req_grant <= 1'd0;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[1]) begin
-                                                                       soc_sdram_choose_req_grant <= 1'd1;
+                                                               if (litedramcore_choose_req_request[1]) begin
+                                                                       litedramcore_choose_req_grant <= 1'd1;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[2]) begin
-                                                                               soc_sdram_choose_req_grant <= 2'd2;
+                                                                       if (litedramcore_choose_req_request[2]) begin
+                                                                               litedramcore_choose_req_grant <= 2'd2;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[3]) begin
-                                                                                       soc_sdram_choose_req_grant <= 2'd3;
+                                                                               if (litedramcore_choose_req_request[3]) begin
+                                                                                       litedramcore_choose_req_grant <= 2'd3;
                                                                                end
                                                                        end
                                                                end
@@ -16351,26 +13971,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd5: begin
-                               if (soc_sdram_choose_req_request[6]) begin
-                                       soc_sdram_choose_req_grant <= 3'd6;
+                               if (litedramcore_choose_req_request[6]) begin
+                                       litedramcore_choose_req_grant <= 3'd6;
                                end else begin
-                                       if (soc_sdram_choose_req_request[7]) begin
-                                               soc_sdram_choose_req_grant <= 3'd7;
+                                       if (litedramcore_choose_req_request[7]) begin
+                                               litedramcore_choose_req_grant <= 3'd7;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[0]) begin
-                                                       soc_sdram_choose_req_grant <= 1'd0;
+                                               if (litedramcore_choose_req_request[0]) begin
+                                                       litedramcore_choose_req_grant <= 1'd0;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[1]) begin
-                                                               soc_sdram_choose_req_grant <= 1'd1;
+                                                       if (litedramcore_choose_req_request[1]) begin
+                                                               litedramcore_choose_req_grant <= 1'd1;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[2]) begin
-                                                                       soc_sdram_choose_req_grant <= 2'd2;
+                                                               if (litedramcore_choose_req_request[2]) begin
+                                                                       litedramcore_choose_req_grant <= 2'd2;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[3]) begin
-                                                                               soc_sdram_choose_req_grant <= 2'd3;
+                                                                       if (litedramcore_choose_req_request[3]) begin
+                                                                               litedramcore_choose_req_grant <= 2'd3;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[4]) begin
-                                                                                       soc_sdram_choose_req_grant <= 3'd4;
+                                                                               if (litedramcore_choose_req_request[4]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd4;
                                                                                end
                                                                        end
                                                                end
@@ -16380,26 +14000,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd6: begin
-                               if (soc_sdram_choose_req_request[7]) begin
-                                       soc_sdram_choose_req_grant <= 3'd7;
+                               if (litedramcore_choose_req_request[7]) begin
+                                       litedramcore_choose_req_grant <= 3'd7;
                                end else begin
-                                       if (soc_sdram_choose_req_request[0]) begin
-                                               soc_sdram_choose_req_grant <= 1'd0;
+                                       if (litedramcore_choose_req_request[0]) begin
+                                               litedramcore_choose_req_grant <= 1'd0;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[1]) begin
-                                                       soc_sdram_choose_req_grant <= 1'd1;
+                                               if (litedramcore_choose_req_request[1]) begin
+                                                       litedramcore_choose_req_grant <= 1'd1;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[2]) begin
-                                                               soc_sdram_choose_req_grant <= 2'd2;
+                                                       if (litedramcore_choose_req_request[2]) begin
+                                                               litedramcore_choose_req_grant <= 2'd2;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[3]) begin
-                                                                       soc_sdram_choose_req_grant <= 2'd3;
+                                                               if (litedramcore_choose_req_request[3]) begin
+                                                                       litedramcore_choose_req_grant <= 2'd3;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[4]) begin
-                                                                               soc_sdram_choose_req_grant <= 3'd4;
+                                                                       if (litedramcore_choose_req_request[4]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd4;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[5]) begin
-                                                                                       soc_sdram_choose_req_grant <= 3'd5;
+                                                                               if (litedramcore_choose_req_request[5]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd5;
                                                                                end
                                                                        end
                                                                end
@@ -16409,26 +14029,26 @@ always @(posedge sys_clk) begin
                                end
                        end
                        3'd7: begin
-                               if (soc_sdram_choose_req_request[0]) begin
-                                       soc_sdram_choose_req_grant <= 1'd0;
+                               if (litedramcore_choose_req_request[0]) begin
+                                       litedramcore_choose_req_grant <= 1'd0;
                                end else begin
-                                       if (soc_sdram_choose_req_request[1]) begin
-                                               soc_sdram_choose_req_grant <= 1'd1;
+                                       if (litedramcore_choose_req_request[1]) begin
+                                               litedramcore_choose_req_grant <= 1'd1;
                                        end else begin
-                                               if (soc_sdram_choose_req_request[2]) begin
-                                                       soc_sdram_choose_req_grant <= 2'd2;
+                                               if (litedramcore_choose_req_request[2]) begin
+                                                       litedramcore_choose_req_grant <= 2'd2;
                                                end else begin
-                                                       if (soc_sdram_choose_req_request[3]) begin
-                                                               soc_sdram_choose_req_grant <= 2'd3;
+                                                       if (litedramcore_choose_req_request[3]) begin
+                                                               litedramcore_choose_req_grant <= 2'd3;
                                                        end else begin
-                                                               if (soc_sdram_choose_req_request[4]) begin
-                                                                       soc_sdram_choose_req_grant <= 3'd4;
+                                                               if (litedramcore_choose_req_request[4]) begin
+                                                                       litedramcore_choose_req_grant <= 3'd4;
                                                                end else begin
-                                                                       if (soc_sdram_choose_req_request[5]) begin
-                                                                               soc_sdram_choose_req_grant <= 3'd5;
+                                                                       if (litedramcore_choose_req_request[5]) begin
+                                                                               litedramcore_choose_req_grant <= 3'd5;
                                                                        end else begin
-                                                                               if (soc_sdram_choose_req_request[6]) begin
-                                                                                       soc_sdram_choose_req_grant <= 3'd6;
+                                                                               if (litedramcore_choose_req_request[6]) begin
+                                                                                       litedramcore_choose_req_grant <= 3'd6;
                                                                                end
                                                                        end
                                                                end
@@ -16439,1280 +14059,709 @@ always @(posedge sys_clk) begin
                        end
                endcase
        end
-       soc_sdram_dfi_p0_cs_n <= 1'd0;
-       soc_sdram_dfi_p0_bank <= vns_array_muxed0;
-       soc_sdram_dfi_p0_address <= vns_array_muxed1;
-       soc_sdram_dfi_p0_cas_n <= (~vns_array_muxed2);
-       soc_sdram_dfi_p0_ras_n <= (~vns_array_muxed3);
-       soc_sdram_dfi_p0_we_n <= (~vns_array_muxed4);
-       soc_sdram_dfi_p0_rddata_en <= vns_array_muxed5;
-       soc_sdram_dfi_p0_wrdata_en <= vns_array_muxed6;
-       soc_sdram_dfi_p1_cs_n <= 1'd0;
-       soc_sdram_dfi_p1_bank <= vns_array_muxed7;
-       soc_sdram_dfi_p1_address <= vns_array_muxed8;
-       soc_sdram_dfi_p1_cas_n <= (~vns_array_muxed9);
-       soc_sdram_dfi_p1_ras_n <= (~vns_array_muxed10);
-       soc_sdram_dfi_p1_we_n <= (~vns_array_muxed11);
-       soc_sdram_dfi_p1_rddata_en <= vns_array_muxed12;
-       soc_sdram_dfi_p1_wrdata_en <= vns_array_muxed13;
-       soc_sdram_dfi_p2_cs_n <= 1'd0;
-       soc_sdram_dfi_p2_bank <= vns_array_muxed14;
-       soc_sdram_dfi_p2_address <= vns_array_muxed15;
-       soc_sdram_dfi_p2_cas_n <= (~vns_array_muxed16);
-       soc_sdram_dfi_p2_ras_n <= (~vns_array_muxed17);
-       soc_sdram_dfi_p2_we_n <= (~vns_array_muxed18);
-       soc_sdram_dfi_p2_rddata_en <= vns_array_muxed19;
-       soc_sdram_dfi_p2_wrdata_en <= vns_array_muxed20;
-       soc_sdram_dfi_p3_cs_n <= 1'd0;
-       soc_sdram_dfi_p3_bank <= vns_array_muxed21;
-       soc_sdram_dfi_p3_address <= vns_array_muxed22;
-       soc_sdram_dfi_p3_cas_n <= (~vns_array_muxed23);
-       soc_sdram_dfi_p3_ras_n <= (~vns_array_muxed24);
-       soc_sdram_dfi_p3_we_n <= (~vns_array_muxed25);
-       soc_sdram_dfi_p3_rddata_en <= vns_array_muxed26;
-       soc_sdram_dfi_p3_wrdata_en <= vns_array_muxed27;
-       if (soc_sdram_trrdcon_valid) begin
-               soc_sdram_trrdcon_count <= 1'd1;
+       litedramcore_dfi_p0_cs_n <= 1'd0;
+       litedramcore_dfi_p0_bank <= array_muxed0;
+       litedramcore_dfi_p0_address <= array_muxed1;
+       litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+       litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+       litedramcore_dfi_p0_we_n <= (~array_muxed4);
+       litedramcore_dfi_p0_rddata_en <= array_muxed5;
+       litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+       litedramcore_dfi_p1_cs_n <= 1'd0;
+       litedramcore_dfi_p1_bank <= array_muxed7;
+       litedramcore_dfi_p1_address <= array_muxed8;
+       litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+       litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+       litedramcore_dfi_p1_we_n <= (~array_muxed11);
+       litedramcore_dfi_p1_rddata_en <= array_muxed12;
+       litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+       litedramcore_dfi_p2_cs_n <= 1'd0;
+       litedramcore_dfi_p2_bank <= array_muxed14;
+       litedramcore_dfi_p2_address <= array_muxed15;
+       litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+       litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+       litedramcore_dfi_p2_we_n <= (~array_muxed18);
+       litedramcore_dfi_p2_rddata_en <= array_muxed19;
+       litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+       litedramcore_dfi_p3_cs_n <= 1'd0;
+       litedramcore_dfi_p3_bank <= array_muxed21;
+       litedramcore_dfi_p3_address <= array_muxed22;
+       litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+       litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+       litedramcore_dfi_p3_we_n <= (~array_muxed25);
+       litedramcore_dfi_p3_rddata_en <= array_muxed26;
+       litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+       if (litedramcore_trrdcon_valid) begin
+               litedramcore_trrdcon_count <= 1'd1;
                if (1'd0) begin
-                       soc_sdram_trrdcon_ready <= 1'd1;
+                       litedramcore_trrdcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_trrdcon_ready <= 1'd0;
+                       litedramcore_trrdcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_trrdcon_ready)) begin
-                       soc_sdram_trrdcon_count <= (soc_sdram_trrdcon_count - 1'd1);
-                       if ((soc_sdram_trrdcon_count == 1'd1)) begin
-                               soc_sdram_trrdcon_ready <= 1'd1;
+               if ((~litedramcore_trrdcon_ready)) begin
+                       litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+                       if ((litedramcore_trrdcon_count == 1'd1)) begin
+                               litedramcore_trrdcon_ready <= 1'd1;
                        end
                end
        end
-       soc_sdram_tfawcon_window <= {soc_sdram_tfawcon_window, soc_sdram_tfawcon_valid};
-       if ((soc_sdram_tfawcon_count < 3'd4)) begin
-               if ((soc_sdram_tfawcon_count == 2'd3)) begin
-                       soc_sdram_tfawcon_ready <= (~soc_sdram_tfawcon_valid);
+       litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+       if ((litedramcore_tfawcon_count < 3'd4)) begin
+               if ((litedramcore_tfawcon_count == 2'd3)) begin
+                       litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
                end else begin
-                       soc_sdram_tfawcon_ready <= 1'd1;
+                       litedramcore_tfawcon_ready <= 1'd1;
                end
        end
-       if (soc_sdram_tccdcon_valid) begin
-               soc_sdram_tccdcon_count <= 1'd0;
+       if (litedramcore_tccdcon_valid) begin
+               litedramcore_tccdcon_count <= 1'd0;
                if (1'd1) begin
-                       soc_sdram_tccdcon_ready <= 1'd1;
+                       litedramcore_tccdcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_tccdcon_ready <= 1'd0;
+                       litedramcore_tccdcon_ready <= 1'd0;
                end
        end else begin
-               if ((~soc_sdram_tccdcon_ready)) begin
-                       soc_sdram_tccdcon_count <= (soc_sdram_tccdcon_count - 1'd1);
-                       if ((soc_sdram_tccdcon_count == 1'd1)) begin
-                               soc_sdram_tccdcon_ready <= 1'd1;
+               if ((~litedramcore_tccdcon_ready)) begin
+                       litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+                       if ((litedramcore_tccdcon_count == 1'd1)) begin
+                               litedramcore_tccdcon_ready <= 1'd1;
                        end
                end
        end
-       if (soc_sdram_twtrcon_valid) begin
-               soc_sdram_twtrcon_count <= 3'd4;
+       if (litedramcore_twtrcon_valid) begin
+               litedramcore_twtrcon_count <= 3'd4;
                if (1'd0) begin
-                       soc_sdram_twtrcon_ready <= 1'd1;
+                       litedramcore_twtrcon_ready <= 1'd1;
                end else begin
-                       soc_sdram_twtrcon_ready <= 1'd0;
-               end
-       end else begin
-               if ((~soc_sdram_twtrcon_ready)) begin
-                       soc_sdram_twtrcon_count <= (soc_sdram_twtrcon_count - 1'd1);
-                       if ((soc_sdram_twtrcon_count == 1'd1)) begin
-                               soc_sdram_twtrcon_ready <= 1'd1;
-                       end
-               end
-       end
-       vns_multiplexer_state <= vns_multiplexer_next_state;
-       vns_new_master_wdata_ready0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_wdata_ready));
-       vns_new_master_wdata_ready1 <= vns_new_master_wdata_ready0;
-       vns_new_master_wdata_ready2 <= vns_new_master_wdata_ready1;
-       vns_new_master_wdata_ready3 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_wdata_ready)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_wdata_ready)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_wdata_ready)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_wdata_ready)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_wdata_ready)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_wdata_ready)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_wdata_ready)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_wdata_ready));
-       vns_new_master_wdata_ready4 <= vns_new_master_wdata_ready3;
-       vns_new_master_wdata_ready5 <= vns_new_master_wdata_ready4;
-       vns_new_master_rdata_valid0 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd0) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd0) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd0) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd0) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd0) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd0) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd0) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd0) & soc_sdram_interface_bank7_rdata_valid));
-       vns_new_master_rdata_valid1 <= vns_new_master_rdata_valid0;
-       vns_new_master_rdata_valid2 <= vns_new_master_rdata_valid1;
-       vns_new_master_rdata_valid3 <= vns_new_master_rdata_valid2;
-       vns_new_master_rdata_valid4 <= vns_new_master_rdata_valid3;
-       vns_new_master_rdata_valid5 <= vns_new_master_rdata_valid4;
-       vns_new_master_rdata_valid6 <= vns_new_master_rdata_valid5;
-       vns_new_master_rdata_valid7 <= vns_new_master_rdata_valid6;
-       vns_new_master_rdata_valid8 <= vns_new_master_rdata_valid7;
-       vns_new_master_rdata_valid9 <= ((((((((1'd0 | ((vns_roundrobin0_grant == 1'd1) & soc_sdram_interface_bank0_rdata_valid)) | ((vns_roundrobin1_grant == 1'd1) & soc_sdram_interface_bank1_rdata_valid)) | ((vns_roundrobin2_grant == 1'd1) & soc_sdram_interface_bank2_rdata_valid)) | ((vns_roundrobin3_grant == 1'd1) & soc_sdram_interface_bank3_rdata_valid)) | ((vns_roundrobin4_grant == 1'd1) & soc_sdram_interface_bank4_rdata_valid)) | ((vns_roundrobin5_grant == 1'd1) & soc_sdram_interface_bank5_rdata_valid)) | ((vns_roundrobin6_grant == 1'd1) & soc_sdram_interface_bank6_rdata_valid)) | ((vns_roundrobin7_grant == 1'd1) & soc_sdram_interface_bank7_rdata_valid));
-       vns_new_master_rdata_valid10 <= vns_new_master_rdata_valid9;
-       vns_new_master_rdata_valid11 <= vns_new_master_rdata_valid10;
-       vns_new_master_rdata_valid12 <= vns_new_master_rdata_valid11;
-       vns_new_master_rdata_valid13 <= vns_new_master_rdata_valid12;
-       vns_new_master_rdata_valid14 <= vns_new_master_rdata_valid13;
-       vns_new_master_rdata_valid15 <= vns_new_master_rdata_valid14;
-       vns_new_master_rdata_valid16 <= vns_new_master_rdata_valid15;
-       vns_new_master_rdata_valid17 <= vns_new_master_rdata_valid16;
-       if (vns_roundrobin0_ce) begin
-               case (vns_roundrobin0_grant)
-                       1'd0: begin
-                               if (vns_roundrobin0_request[1]) begin
-                                       vns_roundrobin0_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin0_request[0]) begin
-                                       vns_roundrobin0_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin1_ce) begin
-               case (vns_roundrobin1_grant)
-                       1'd0: begin
-                               if (vns_roundrobin1_request[1]) begin
-                                       vns_roundrobin1_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin1_request[0]) begin
-                                       vns_roundrobin1_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin2_ce) begin
-               case (vns_roundrobin2_grant)
-                       1'd0: begin
-                               if (vns_roundrobin2_request[1]) begin
-                                       vns_roundrobin2_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin2_request[0]) begin
-                                       vns_roundrobin2_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin3_ce) begin
-               case (vns_roundrobin3_grant)
-                       1'd0: begin
-                               if (vns_roundrobin3_request[1]) begin
-                                       vns_roundrobin3_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin3_request[0]) begin
-                                       vns_roundrobin3_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin4_ce) begin
-               case (vns_roundrobin4_grant)
-                       1'd0: begin
-                               if (vns_roundrobin4_request[1]) begin
-                                       vns_roundrobin4_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin4_request[0]) begin
-                                       vns_roundrobin4_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin5_ce) begin
-               case (vns_roundrobin5_grant)
-                       1'd0: begin
-                               if (vns_roundrobin5_request[1]) begin
-                                       vns_roundrobin5_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin5_request[0]) begin
-                                       vns_roundrobin5_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin6_ce) begin
-               case (vns_roundrobin6_grant)
-                       1'd0: begin
-                               if (vns_roundrobin6_request[1]) begin
-                                       vns_roundrobin6_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin6_request[0]) begin
-                                       vns_roundrobin6_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (vns_roundrobin7_ce) begin
-               case (vns_roundrobin7_grant)
-                       1'd0: begin
-                               if (vns_roundrobin7_request[1]) begin
-                                       vns_roundrobin7_grant <= 1'd1;
-                               end
-                       end
-                       1'd1: begin
-                               if (vns_roundrobin7_request[0]) begin
-                                       vns_roundrobin7_grant <= 1'd0;
-                               end
-                       end
-               endcase
-       end
-       if (soc_counter_reset) begin
-               soc_counter <= 1'd0;
-       end else begin
-               if (soc_counter_ce) begin
-                       soc_counter <= (soc_counter + 1'd1);
-               end
-       end
-       if (soc_address_ce) begin
-               soc_address_q <= soc_address_d;
-       end
-       if (soc_address_reset) begin
-               soc_address_q <= 30'd0;
-       end
-       if (soc_need_refill_ce) begin
-               soc_need_refill_q <= soc_need_refill_d;
-       end
-       if (soc_need_refill_reset) begin
-               soc_need_refill_q <= 1'd1;
-       end
-       vns_converter_state <= vns_converter_next_state;
-       if (soc_cached_datas_ce0) begin
-               soc_cached_datas_flipflop0_q <= soc_cached_datas_flipflop0_d;
-       end
-       if (soc_cached_datas_reset0) begin
-               soc_cached_datas_flipflop0_q <= 32'd0;
-       end
-       if (soc_cached_datas_ce1) begin
-               soc_cached_datas_flipflop1_q <= soc_cached_datas_flipflop1_d;
-       end
-       if (soc_cached_datas_reset1) begin
-               soc_cached_datas_flipflop1_q <= 32'd0;
-       end
-       if (soc_cached_datas_ce2) begin
-               soc_cached_datas_flipflop2_q <= soc_cached_datas_flipflop2_d;
-       end
-       if (soc_cached_datas_reset2) begin
-               soc_cached_datas_flipflop2_q <= 32'd0;
-       end
-       if (soc_cached_datas_ce3) begin
-               soc_cached_datas_flipflop3_q <= soc_cached_datas_flipflop3_d;
-       end
-       if (soc_cached_datas_reset3) begin
-               soc_cached_datas_flipflop3_q <= 32'd0;
-       end
-       if (soc_cached_sels_ce0) begin
-               soc_cached_sels_flipflop0_q <= soc_cached_sels_flipflop0_d;
-       end
-       if (soc_cached_sels_reset0) begin
-               soc_cached_sels_flipflop0_q <= 4'd0;
-       end
-       if (soc_cached_sels_ce1) begin
-               soc_cached_sels_flipflop1_q <= soc_cached_sels_flipflop1_d;
-       end
-       if (soc_cached_sels_reset1) begin
-               soc_cached_sels_flipflop1_q <= 4'd0;
-       end
-       if (soc_cached_sels_ce2) begin
-               soc_cached_sels_flipflop2_q <= soc_cached_sels_flipflop2_d;
-       end
-       if (soc_cached_sels_reset2) begin
-               soc_cached_sels_flipflop2_q <= 4'd0;
-       end
-       if (soc_cached_sels_ce3) begin
-               soc_cached_sels_flipflop3_q <= soc_cached_sels_flipflop3_d;
-       end
-       if (soc_cached_sels_reset3) begin
-               soc_cached_sels_flipflop3_q <= 4'd0;
-       end
-       vns_litedramwishbone2native_state <= vns_litedramwishbone2native_next_state;
-       if (soc_count_next_value_ce) begin
-               soc_count <= soc_count_next_value;
-       end
-       case (vns_grant)
-               1'd0: begin
-                       if ((~vns_request[0])) begin
-                               if (vns_request[1]) begin
-                                       vns_grant <= 1'd1;
-                               end
-                       end
-               end
-               1'd1: begin
-                       if ((~vns_request[1])) begin
-                               if (vns_request[0]) begin
-                                       vns_grant <= 1'd0;
-                               end
-                       end
-               end
-       endcase
-       vns_slave_sel_r <= vns_slave_sel;
-       if (vns_wait) begin
-               if ((~vns_done)) begin
-                       vns_count <= (vns_count - 1'd1);
+                       litedramcore_twtrcon_ready <= 1'd0;
                end
        end else begin
-               vns_count <= 20'd1000000;
-       end
-       vns_interface0_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank0_sel) begin
-               case (vns_interface0_bank_bus_adr[3:0])
-                       1'd0: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_reset0_w;
-                       end
-                       1'd1: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch3_w;
-                       end
-                       2'd2: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch2_w;
-                       end
-                       2'd3: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch1_w;
-                       end
-                       3'd4: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_scratch0_w;
-                       end
-                       3'd5: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors3_w;
-                       end
-                       3'd6: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors2_w;
-                       end
-                       3'd7: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors1_w;
-                       end
-                       4'd8: begin
-                               vns_interface0_bank_bus_dat_r <= vns_csrbank0_bus_errors0_w;
-                       end
-               endcase
-       end
-       if (vns_csrbank0_reset0_re) begin
-               soc_litedramcore_soccontroller_reset_storage <= vns_csrbank0_reset0_r;
-       end
-       soc_litedramcore_soccontroller_reset_re <= vns_csrbank0_reset0_re;
-       if (vns_csrbank0_scratch3_re) begin
-               soc_litedramcore_soccontroller_scratch_storage[31:24] <= vns_csrbank0_scratch3_r;
-       end
-       if (vns_csrbank0_scratch2_re) begin
-               soc_litedramcore_soccontroller_scratch_storage[23:16] <= vns_csrbank0_scratch2_r;
-       end
-       if (vns_csrbank0_scratch1_re) begin
-               soc_litedramcore_soccontroller_scratch_storage[15:8] <= vns_csrbank0_scratch1_r;
-       end
-       if (vns_csrbank0_scratch0_re) begin
-               soc_litedramcore_soccontroller_scratch_storage[7:0] <= vns_csrbank0_scratch0_r;
-       end
-       soc_litedramcore_soccontroller_scratch_re <= vns_csrbank0_scratch0_re;
-       vns_interface1_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank1_sel) begin
-               case (vns_interface1_bank_bus_adr[0])
+               if ((~litedramcore_twtrcon_ready)) begin
+                       litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+                       if ((litedramcore_twtrcon_count == 1'd1)) begin
+                               litedramcore_twtrcon_ready <= 1'd1;
+                       end
+               end
+       end
+       multiplexer_state <= multiplexer_next_state;
+       new_master_wdata_ready0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+       new_master_wdata_ready1 <= new_master_wdata_ready0;
+       new_master_wdata_ready2 <= new_master_wdata_ready1;
+       new_master_rdata_valid0 <= ((((((((1'd0 | ((roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+       new_master_rdata_valid1 <= new_master_rdata_valid0;
+       new_master_rdata_valid2 <= new_master_rdata_valid1;
+       new_master_rdata_valid3 <= new_master_rdata_valid2;
+       new_master_rdata_valid4 <= new_master_rdata_valid3;
+       new_master_rdata_valid5 <= new_master_rdata_valid4;
+       new_master_rdata_valid6 <= new_master_rdata_valid5;
+       new_master_rdata_valid7 <= new_master_rdata_valid6;
+       new_master_rdata_valid8 <= new_master_rdata_valid7;
+       interface0_bank_bus_dat_r <= 1'd0;
+       if (csrbank0_sel) begin
+               case (interface0_bank_bus_adr[3])
                        1'd0: begin
-                               vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_done0_w;
+                               interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
                        end
                        1'd1: begin
-                               vns_interface1_bank_bus_dat_r <= vns_csrbank1_init_error0_w;
+                               interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
                        end
                endcase
        end
-       if (vns_csrbank1_init_done0_re) begin
-               soc_init_done_storage <= vns_csrbank1_init_done0_r;
+       if (csrbank0_init_done0_re) begin
+               init_done_storage <= csrbank0_init_done0_r;
        end
-       soc_init_done_re <= vns_csrbank1_init_done0_re;
-       if (vns_csrbank1_init_error0_re) begin
-               soc_init_error_storage <= vns_csrbank1_init_error0_r;
+       init_done_re <= csrbank0_init_done0_re;
+       if (csrbank0_init_error0_re) begin
+               init_error_storage <= csrbank0_init_error0_r;
        end
-       soc_init_error_re <= vns_csrbank1_init_error0_re;
-       vns_interface2_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank2_sel) begin
-               case (vns_interface2_bank_bus_adr[3:0])
+       init_error_re <= csrbank0_init_error0_re;
+       interface1_bank_bus_dat_r <= 1'd0;
+       if (csrbank1_sel) begin
+               case (interface1_bank_bus_adr[6:3])
                        1'd0: begin
-                               vns_interface2_bank_bus_dat_r <= vns_csrbank2_half_sys8x_taps0_w;
+                               interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
                        end
                        1'd1: begin
-                               vns_interface2_bank_bus_dat_r <= vns_csrbank2_wlevel_en0_w;
+                               interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
                        end
                        2'd2: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_wlevel_strobe_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
                        end
                        2'd3: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_rst_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_cdly_rst_w;
                        end
                        3'd4: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_cdly_inc_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_cdly_inc_w;
                        end
                        3'd5: begin
-                               vns_interface2_bank_bus_dat_r <= vns_csrbank2_dly_sel0_w;
+                               interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
                        end
                        3'd6: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_rst_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
                        end
                        3'd7: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_inc_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
                        end
                        4'd8: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_rst_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
                        end
                        4'd9: begin
-                               vns_interface2_bank_bus_dat_r <= soc_a7ddrphy_rdly_dq_bitslip_w;
+                               interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
                        end
                endcase
        end
-       if (vns_csrbank2_half_sys8x_taps0_re) begin
-               soc_a7ddrphy_half_sys8x_taps_storage[4:0] <= vns_csrbank2_half_sys8x_taps0_r;
+       if (csrbank1_half_sys8x_taps0_re) begin
+               a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
        end
-       soc_a7ddrphy_half_sys8x_taps_re <= vns_csrbank2_half_sys8x_taps0_re;
-       if (vns_csrbank2_wlevel_en0_re) begin
-               soc_a7ddrphy_wlevel_en_storage <= vns_csrbank2_wlevel_en0_r;
+       a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+       if (csrbank1_wlevel_en0_re) begin
+               a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
        end
-       soc_a7ddrphy_wlevel_en_re <= vns_csrbank2_wlevel_en0_re;
-       if (vns_csrbank2_dly_sel0_re) begin
-               soc_a7ddrphy_dly_sel_storage[1:0] <= vns_csrbank2_dly_sel0_r;
+       a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+       if (csrbank1_dly_sel0_re) begin
+               a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
        end
-       soc_a7ddrphy_dly_sel_re <= vns_csrbank2_dly_sel0_re;
-       vns_interface3_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank3_sel) begin
-               case (vns_interface3_bank_bus_adr[5:0])
+       a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+       interface2_bank_bus_dat_r <= 1'd0;
+       if (csrbank2_sel) begin
+               case (interface2_bank_bus_adr[8:3])
                        1'd0: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_control0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
                        end
                        1'd1: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_command0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
                        end
                        2'd2: begin
-                               vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector0_command_issue_w;
+                               interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
                        end
                        2'd3: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address1_w;
                        end
                        3'd4: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_address0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
                        end
                        3'd5: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_baddress0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
                        end
                        3'd6: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata3_w;
                        end
                        3'd7: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata2_w;
                        end
                        4'd8: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
                        end
                        4'd9: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_wrdata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
                        end
                        4'd10: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata3_w;
                        end
                        4'd11: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata2_w;
                        end
                        4'd12: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
                        end
                        4'd13: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi0_rddata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
                        end
                        4'd14: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_command0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
                        end
                        4'd15: begin
-                               vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector1_command_issue_w;
+                               interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
                        end
                        5'd16: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address1_w;
                        end
                        5'd17: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_address0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
                        end
                        5'd18: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_baddress0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
                        end
                        5'd19: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata3_w;
                        end
                        5'd20: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata2_w;
                        end
                        5'd21: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
                        end
                        5'd22: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_wrdata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
                        end
                        5'd23: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata3_w;
                        end
                        5'd24: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata2_w;
                        end
                        5'd25: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
                        end
                        5'd26: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi1_rddata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
                        end
                        5'd27: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_command0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
                        end
                        5'd28: begin
-                               vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector2_command_issue_w;
+                               interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
                        end
                        5'd29: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address1_w;
                        end
                        5'd30: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_address0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
                        end
                        5'd31: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_baddress0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
                        end
                        6'd32: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata3_w;
                        end
                        6'd33: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata2_w;
                        end
                        6'd34: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w;
                        end
                        6'd35: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_wrdata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
                        end
                        6'd36: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata3_w;
                        end
                        6'd37: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata2_w;
                        end
                        6'd38: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w;
                        end
                        6'd39: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi2_rddata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w;
                        end
                        6'd40: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_command0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
                        end
                        6'd41: begin
-                               vns_interface3_bank_bus_dat_r <= soc_sdram_phaseinjector3_command_issue_w;
+                               interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
                        end
                        6'd42: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address1_w;
                        end
                        6'd43: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_address0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
                        end
                        6'd44: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_baddress0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
                        end
                        6'd45: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata3_w;
                        end
                        6'd46: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata2_w;
                        end
                        6'd47: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w;
                        end
                        6'd48: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_wrdata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
                        end
                        6'd49: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata3_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata3_w;
                        end
                        6'd50: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata2_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata2_w;
                        end
                        6'd51: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata1_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w;
                        end
                        6'd52: begin
-                               vns_interface3_bank_bus_dat_r <= vns_csrbank3_dfii_pi3_rddata0_w;
+                               interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w;
                        end
                endcase
        end
-       if (vns_csrbank3_dfii_control0_re) begin
-               soc_sdram_storage[3:0] <= vns_csrbank3_dfii_control0_r;
-       end
-       soc_sdram_re <= vns_csrbank3_dfii_control0_re;
-       if (vns_csrbank3_dfii_pi0_command0_re) begin
-               soc_sdram_phaseinjector0_command_storage[5:0] <= vns_csrbank3_dfii_pi0_command0_r;
-       end
-       soc_sdram_phaseinjector0_command_re <= vns_csrbank3_dfii_pi0_command0_re;
-       if (vns_csrbank3_dfii_pi0_address1_re) begin
-               soc_sdram_phaseinjector0_address_storage[14:8] <= vns_csrbank3_dfii_pi0_address1_r;
-       end
-       if (vns_csrbank3_dfii_pi0_address0_re) begin
-               soc_sdram_phaseinjector0_address_storage[7:0] <= vns_csrbank3_dfii_pi0_address0_r;
-       end
-       soc_sdram_phaseinjector0_address_re <= vns_csrbank3_dfii_pi0_address0_re;
-       if (vns_csrbank3_dfii_pi0_baddress0_re) begin
-               soc_sdram_phaseinjector0_baddress_storage[2:0] <= vns_csrbank3_dfii_pi0_baddress0_r;
-       end
-       soc_sdram_phaseinjector0_baddress_re <= vns_csrbank3_dfii_pi0_baddress0_re;
-       if (vns_csrbank3_dfii_pi0_wrdata3_re) begin
-               soc_sdram_phaseinjector0_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi0_wrdata3_r;
-       end
-       if (vns_csrbank3_dfii_pi0_wrdata2_re) begin
-               soc_sdram_phaseinjector0_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi0_wrdata2_r;
-       end
-       if (vns_csrbank3_dfii_pi0_wrdata1_re) begin
-               soc_sdram_phaseinjector0_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi0_wrdata1_r;
-       end
-       if (vns_csrbank3_dfii_pi0_wrdata0_re) begin
-               soc_sdram_phaseinjector0_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi0_wrdata0_r;
+       if (csrbank2_dfii_control0_re) begin
+               litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
        end
-       soc_sdram_phaseinjector0_wrdata_re <= vns_csrbank3_dfii_pi0_wrdata0_re;
-       if (vns_csrbank3_dfii_pi1_command0_re) begin
-               soc_sdram_phaseinjector1_command_storage[5:0] <= vns_csrbank3_dfii_pi1_command0_r;
+       litedramcore_re <= csrbank2_dfii_control0_re;
+       if (csrbank2_dfii_pi0_command0_re) begin
+               litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
        end
-       soc_sdram_phaseinjector1_command_re <= vns_csrbank3_dfii_pi1_command0_re;
-       if (vns_csrbank3_dfii_pi1_address1_re) begin
-               soc_sdram_phaseinjector1_address_storage[14:8] <= vns_csrbank3_dfii_pi1_address1_r;
+       litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+       if (csrbank2_dfii_pi0_address1_re) begin
+               litedramcore_phaseinjector0_address_storage[14:8] <= csrbank2_dfii_pi0_address1_r;
        end
-       if (vns_csrbank3_dfii_pi1_address0_re) begin
-               soc_sdram_phaseinjector1_address_storage[7:0] <= vns_csrbank3_dfii_pi1_address0_r;
+       if (csrbank2_dfii_pi0_address0_re) begin
+               litedramcore_phaseinjector0_address_storage[7:0] <= csrbank2_dfii_pi0_address0_r;
        end
-       soc_sdram_phaseinjector1_address_re <= vns_csrbank3_dfii_pi1_address0_re;
-       if (vns_csrbank3_dfii_pi1_baddress0_re) begin
-               soc_sdram_phaseinjector1_baddress_storage[2:0] <= vns_csrbank3_dfii_pi1_baddress0_r;
+       litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+       if (csrbank2_dfii_pi0_baddress0_re) begin
+               litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
        end
-       soc_sdram_phaseinjector1_baddress_re <= vns_csrbank3_dfii_pi1_baddress0_re;
-       if (vns_csrbank3_dfii_pi1_wrdata3_re) begin
-               soc_sdram_phaseinjector1_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi1_wrdata3_r;
+       litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+       if (csrbank2_dfii_pi0_wrdata3_re) begin
+               litedramcore_phaseinjector0_wrdata_storage[31:24] <= csrbank2_dfii_pi0_wrdata3_r;
        end
-       if (vns_csrbank3_dfii_pi1_wrdata2_re) begin
-               soc_sdram_phaseinjector1_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi1_wrdata2_r;
+       if (csrbank2_dfii_pi0_wrdata2_re) begin
+               litedramcore_phaseinjector0_wrdata_storage[23:16] <= csrbank2_dfii_pi0_wrdata2_r;
        end
-       if (vns_csrbank3_dfii_pi1_wrdata1_re) begin
-               soc_sdram_phaseinjector1_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi1_wrdata1_r;
+       if (csrbank2_dfii_pi0_wrdata1_re) begin
+               litedramcore_phaseinjector0_wrdata_storage[15:8] <= csrbank2_dfii_pi0_wrdata1_r;
        end
-       if (vns_csrbank3_dfii_pi1_wrdata0_re) begin
-               soc_sdram_phaseinjector1_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi1_wrdata0_r;
+       if (csrbank2_dfii_pi0_wrdata0_re) begin
+               litedramcore_phaseinjector0_wrdata_storage[7:0] <= csrbank2_dfii_pi0_wrdata0_r;
        end
-       soc_sdram_phaseinjector1_wrdata_re <= vns_csrbank3_dfii_pi1_wrdata0_re;
-       if (vns_csrbank3_dfii_pi2_command0_re) begin
-               soc_sdram_phaseinjector2_command_storage[5:0] <= vns_csrbank3_dfii_pi2_command0_r;
+       litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+       if (csrbank2_dfii_pi1_command0_re) begin
+               litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
        end
-       soc_sdram_phaseinjector2_command_re <= vns_csrbank3_dfii_pi2_command0_re;
-       if (vns_csrbank3_dfii_pi2_address1_re) begin
-               soc_sdram_phaseinjector2_address_storage[14:8] <= vns_csrbank3_dfii_pi2_address1_r;
+       litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+       if (csrbank2_dfii_pi1_address1_re) begin
+               litedramcore_phaseinjector1_address_storage[14:8] <= csrbank2_dfii_pi1_address1_r;
        end
-       if (vns_csrbank3_dfii_pi2_address0_re) begin
-               soc_sdram_phaseinjector2_address_storage[7:0] <= vns_csrbank3_dfii_pi2_address0_r;
+       if (csrbank2_dfii_pi1_address0_re) begin
+               litedramcore_phaseinjector1_address_storage[7:0] <= csrbank2_dfii_pi1_address0_r;
        end
-       soc_sdram_phaseinjector2_address_re <= vns_csrbank3_dfii_pi2_address0_re;
-       if (vns_csrbank3_dfii_pi2_baddress0_re) begin
-               soc_sdram_phaseinjector2_baddress_storage[2:0] <= vns_csrbank3_dfii_pi2_baddress0_r;
+       litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+       if (csrbank2_dfii_pi1_baddress0_re) begin
+               litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
        end
-       soc_sdram_phaseinjector2_baddress_re <= vns_csrbank3_dfii_pi2_baddress0_re;
-       if (vns_csrbank3_dfii_pi2_wrdata3_re) begin
-               soc_sdram_phaseinjector2_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi2_wrdata3_r;
+       litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+       if (csrbank2_dfii_pi1_wrdata3_re) begin
+               litedramcore_phaseinjector1_wrdata_storage[31:24] <= csrbank2_dfii_pi1_wrdata3_r;
        end
-       if (vns_csrbank3_dfii_pi2_wrdata2_re) begin
-               soc_sdram_phaseinjector2_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi2_wrdata2_r;
-       end
-       if (vns_csrbank3_dfii_pi2_wrdata1_re) begin
-               soc_sdram_phaseinjector2_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi2_wrdata1_r;
-       end
-       if (vns_csrbank3_dfii_pi2_wrdata0_re) begin
-               soc_sdram_phaseinjector2_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi2_wrdata0_r;
-       end
-       soc_sdram_phaseinjector2_wrdata_re <= vns_csrbank3_dfii_pi2_wrdata0_re;
-       if (vns_csrbank3_dfii_pi3_command0_re) begin
-               soc_sdram_phaseinjector3_command_storage[5:0] <= vns_csrbank3_dfii_pi3_command0_r;
-       end
-       soc_sdram_phaseinjector3_command_re <= vns_csrbank3_dfii_pi3_command0_re;
-       if (vns_csrbank3_dfii_pi3_address1_re) begin
-               soc_sdram_phaseinjector3_address_storage[14:8] <= vns_csrbank3_dfii_pi3_address1_r;
-       end
-       if (vns_csrbank3_dfii_pi3_address0_re) begin
-               soc_sdram_phaseinjector3_address_storage[7:0] <= vns_csrbank3_dfii_pi3_address0_r;
-       end
-       soc_sdram_phaseinjector3_address_re <= vns_csrbank3_dfii_pi3_address0_re;
-       if (vns_csrbank3_dfii_pi3_baddress0_re) begin
-               soc_sdram_phaseinjector3_baddress_storage[2:0] <= vns_csrbank3_dfii_pi3_baddress0_r;
-       end
-       soc_sdram_phaseinjector3_baddress_re <= vns_csrbank3_dfii_pi3_baddress0_re;
-       if (vns_csrbank3_dfii_pi3_wrdata3_re) begin
-               soc_sdram_phaseinjector3_wrdata_storage[31:24] <= vns_csrbank3_dfii_pi3_wrdata3_r;
-       end
-       if (vns_csrbank3_dfii_pi3_wrdata2_re) begin
-               soc_sdram_phaseinjector3_wrdata_storage[23:16] <= vns_csrbank3_dfii_pi3_wrdata2_r;
-       end
-       if (vns_csrbank3_dfii_pi3_wrdata1_re) begin
-               soc_sdram_phaseinjector3_wrdata_storage[15:8] <= vns_csrbank3_dfii_pi3_wrdata1_r;
-       end
-       if (vns_csrbank3_dfii_pi3_wrdata0_re) begin
-               soc_sdram_phaseinjector3_wrdata_storage[7:0] <= vns_csrbank3_dfii_pi3_wrdata0_r;
-       end
-       soc_sdram_phaseinjector3_wrdata_re <= vns_csrbank3_dfii_pi3_wrdata0_re;
-       vns_interface4_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank4_sel) begin
-               case (vns_interface4_bank_bus_adr[4:0])
-                       1'd0: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_load3_w;
-                       end
-                       1'd1: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_load2_w;
-                       end
-                       2'd2: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_load1_w;
-                       end
-                       2'd3: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_load0_w;
-                       end
-                       3'd4: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload3_w;
-                       end
-                       3'd5: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload2_w;
-                       end
-                       3'd6: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload1_w;
-                       end
-                       3'd7: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_reload0_w;
-                       end
-                       4'd8: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_en0_w;
-                       end
-                       4'd9: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_update_value0_w;
-                       end
-                       4'd10: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_value3_w;
-                       end
-                       4'd11: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_value2_w;
-                       end
-                       4'd12: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_value1_w;
-                       end
-                       4'd13: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_value0_w;
-                       end
-                       4'd14: begin
-                               vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_status_w;
-                       end
-                       4'd15: begin
-                               vns_interface4_bank_bus_dat_r <= soc_litedramcore_timer_eventmanager_pending_w;
-                       end
-                       5'd16: begin
-                               vns_interface4_bank_bus_dat_r <= vns_csrbank4_ev_enable0_w;
-                       end
-               endcase
+       if (csrbank2_dfii_pi1_wrdata2_re) begin
+               litedramcore_phaseinjector1_wrdata_storage[23:16] <= csrbank2_dfii_pi1_wrdata2_r;
        end
-       if (vns_csrbank4_load3_re) begin
-               soc_litedramcore_timer_load_storage[31:24] <= vns_csrbank4_load3_r;
+       if (csrbank2_dfii_pi1_wrdata1_re) begin
+               litedramcore_phaseinjector1_wrdata_storage[15:8] <= csrbank2_dfii_pi1_wrdata1_r;
        end
-       if (vns_csrbank4_load2_re) begin
-               soc_litedramcore_timer_load_storage[23:16] <= vns_csrbank4_load2_r;
+       if (csrbank2_dfii_pi1_wrdata0_re) begin
+               litedramcore_phaseinjector1_wrdata_storage[7:0] <= csrbank2_dfii_pi1_wrdata0_r;
        end
-       if (vns_csrbank4_load1_re) begin
-               soc_litedramcore_timer_load_storage[15:8] <= vns_csrbank4_load1_r;
+       litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+       if (csrbank2_dfii_pi2_command0_re) begin
+               litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
        end
-       if (vns_csrbank4_load0_re) begin
-               soc_litedramcore_timer_load_storage[7:0] <= vns_csrbank4_load0_r;
+       litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+       if (csrbank2_dfii_pi2_address1_re) begin
+               litedramcore_phaseinjector2_address_storage[14:8] <= csrbank2_dfii_pi2_address1_r;
        end
-       soc_litedramcore_timer_load_re <= vns_csrbank4_load0_re;
-       if (vns_csrbank4_reload3_re) begin
-               soc_litedramcore_timer_reload_storage[31:24] <= vns_csrbank4_reload3_r;
+       if (csrbank2_dfii_pi2_address0_re) begin
+               litedramcore_phaseinjector2_address_storage[7:0] <= csrbank2_dfii_pi2_address0_r;
        end
-       if (vns_csrbank4_reload2_re) begin
-               soc_litedramcore_timer_reload_storage[23:16] <= vns_csrbank4_reload2_r;
+       litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+       if (csrbank2_dfii_pi2_baddress0_re) begin
+               litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
        end
-       if (vns_csrbank4_reload1_re) begin
-               soc_litedramcore_timer_reload_storage[15:8] <= vns_csrbank4_reload1_r;
+       litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+       if (csrbank2_dfii_pi2_wrdata3_re) begin
+               litedramcore_phaseinjector2_wrdata_storage[31:24] <= csrbank2_dfii_pi2_wrdata3_r;
        end
-       if (vns_csrbank4_reload0_re) begin
-               soc_litedramcore_timer_reload_storage[7:0] <= vns_csrbank4_reload0_r;
+       if (csrbank2_dfii_pi2_wrdata2_re) begin
+               litedramcore_phaseinjector2_wrdata_storage[23:16] <= csrbank2_dfii_pi2_wrdata2_r;
        end
-       soc_litedramcore_timer_reload_re <= vns_csrbank4_reload0_re;
-       if (vns_csrbank4_en0_re) begin
-               soc_litedramcore_timer_en_storage <= vns_csrbank4_en0_r;
+       if (csrbank2_dfii_pi2_wrdata1_re) begin
+               litedramcore_phaseinjector2_wrdata_storage[15:8] <= csrbank2_dfii_pi2_wrdata1_r;
        end
-       soc_litedramcore_timer_en_re <= vns_csrbank4_en0_re;
-       if (vns_csrbank4_update_value0_re) begin
-               soc_litedramcore_timer_update_value_storage <= vns_csrbank4_update_value0_r;
+       if (csrbank2_dfii_pi2_wrdata0_re) begin
+               litedramcore_phaseinjector2_wrdata_storage[7:0] <= csrbank2_dfii_pi2_wrdata0_r;
        end
-       soc_litedramcore_timer_update_value_re <= vns_csrbank4_update_value0_re;
-       if (vns_csrbank4_ev_enable0_re) begin
-               soc_litedramcore_timer_eventmanager_storage <= vns_csrbank4_ev_enable0_r;
+       litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+       if (csrbank2_dfii_pi3_command0_re) begin
+               litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
        end
-       soc_litedramcore_timer_eventmanager_re <= vns_csrbank4_ev_enable0_re;
-       vns_interface5_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank5_sel) begin
-               case (vns_interface5_bank_bus_adr[2:0])
-                       1'd0: begin
-                               vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_rxtx_w;
-                       end
-                       1'd1: begin
-                               vns_interface5_bank_bus_dat_r <= vns_csrbank5_txfull_w;
-                       end
-                       2'd2: begin
-                               vns_interface5_bank_bus_dat_r <= vns_csrbank5_rxempty_w;
-                       end
-                       2'd3: begin
-                               vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_status_w;
-                       end
-                       3'd4: begin
-                               vns_interface5_bank_bus_dat_r <= soc_litedramcore_uart_eventmanager_pending_w;
-                       end
-                       3'd5: begin
-                               vns_interface5_bank_bus_dat_r <= vns_csrbank5_ev_enable0_w;
-                       end
-               endcase
+       litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+       if (csrbank2_dfii_pi3_address1_re) begin
+               litedramcore_phaseinjector3_address_storage[14:8] <= csrbank2_dfii_pi3_address1_r;
        end
-       if (vns_csrbank5_ev_enable0_re) begin
-               soc_litedramcore_uart_eventmanager_storage[1:0] <= vns_csrbank5_ev_enable0_r;
+       if (csrbank2_dfii_pi3_address0_re) begin
+               litedramcore_phaseinjector3_address_storage[7:0] <= csrbank2_dfii_pi3_address0_r;
        end
-       soc_litedramcore_uart_eventmanager_re <= vns_csrbank5_ev_enable0_re;
-       vns_interface6_bank_bus_dat_r <= 1'd0;
-       if (vns_csrbank6_sel) begin
-               case (vns_interface6_bank_bus_adr[1:0])
-                       1'd0: begin
-                               vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word3_w;
-                       end
-                       1'd1: begin
-                               vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word2_w;
-                       end
-                       2'd2: begin
-                               vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word1_w;
-                       end
-                       2'd3: begin
-                               vns_interface6_bank_bus_dat_r <= vns_csrbank6_tuning_word0_w;
-                       end
-               endcase
+       litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+       if (csrbank2_dfii_pi3_baddress0_re) begin
+               litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
        end
-       if (vns_csrbank6_tuning_word3_re) begin
-               soc_litedramcore_storage[31:24] <= vns_csrbank6_tuning_word3_r;
+       litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+       if (csrbank2_dfii_pi3_wrdata3_re) begin
+               litedramcore_phaseinjector3_wrdata_storage[31:24] <= csrbank2_dfii_pi3_wrdata3_r;
        end
-       if (vns_csrbank6_tuning_word2_re) begin
-               soc_litedramcore_storage[23:16] <= vns_csrbank6_tuning_word2_r;
+       if (csrbank2_dfii_pi3_wrdata2_re) begin
+               litedramcore_phaseinjector3_wrdata_storage[23:16] <= csrbank2_dfii_pi3_wrdata2_r;
        end
-       if (vns_csrbank6_tuning_word1_re) begin
-               soc_litedramcore_storage[15:8] <= vns_csrbank6_tuning_word1_r;
+       if (csrbank2_dfii_pi3_wrdata1_re) begin
+               litedramcore_phaseinjector3_wrdata_storage[15:8] <= csrbank2_dfii_pi3_wrdata1_r;
        end
-       if (vns_csrbank6_tuning_word0_re) begin
-               soc_litedramcore_storage[7:0] <= vns_csrbank6_tuning_word0_r;
+       if (csrbank2_dfii_pi3_wrdata0_re) begin
+               litedramcore_phaseinjector3_wrdata_storage[7:0] <= csrbank2_dfii_pi3_wrdata0_r;
        end
-       soc_litedramcore_re <= vns_csrbank6_tuning_word0_re;
+       litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
        if (sys_rst) begin
-               soc_litedramcore_soccontroller_reset_storage <= 1'd0;
-               soc_litedramcore_soccontroller_reset_re <= 1'd0;
-               soc_litedramcore_soccontroller_scratch_storage <= 32'd305419896;
-               soc_litedramcore_soccontroller_scratch_re <= 1'd0;
-               soc_litedramcore_soccontroller_bus_errors <= 32'd0;
-               soc_litedramcore_litedramcore_ram_bus_ack <= 1'd0;
-               soc_litedramcore_ram_bus_ram_bus_ack <= 1'd0;
-               serial_tx <= 1'd1;
-               soc_litedramcore_storage <= 32'd4947802;
-               soc_litedramcore_re <= 1'd0;
-               soc_litedramcore_sink_ready <= 1'd0;
-               soc_litedramcore_uart_clk_txen <= 1'd0;
-               soc_litedramcore_tx_busy <= 1'd0;
-               soc_litedramcore_source_valid <= 1'd0;
-               soc_litedramcore_uart_clk_rxen <= 1'd0;
-               soc_litedramcore_rx_r <= 1'd0;
-               soc_litedramcore_rx_busy <= 1'd0;
-               soc_litedramcore_uart_tx_pending <= 1'd0;
-               soc_litedramcore_uart_tx_old_trigger <= 1'd0;
-               soc_litedramcore_uart_rx_pending <= 1'd0;
-               soc_litedramcore_uart_rx_old_trigger <= 1'd0;
-               soc_litedramcore_uart_eventmanager_storage <= 2'd0;
-               soc_litedramcore_uart_eventmanager_re <= 1'd0;
-               soc_litedramcore_uart_tx_fifo_readable <= 1'd0;
-               soc_litedramcore_uart_tx_fifo_level0 <= 5'd0;
-               soc_litedramcore_uart_tx_fifo_produce <= 4'd0;
-               soc_litedramcore_uart_tx_fifo_consume <= 4'd0;
-               soc_litedramcore_uart_rx_fifo_readable <= 1'd0;
-               soc_litedramcore_uart_rx_fifo_level0 <= 5'd0;
-               soc_litedramcore_uart_rx_fifo_produce <= 4'd0;
-               soc_litedramcore_uart_rx_fifo_consume <= 4'd0;
-               soc_litedramcore_timer_load_storage <= 32'd0;
-               soc_litedramcore_timer_load_re <= 1'd0;
-               soc_litedramcore_timer_reload_storage <= 32'd0;
-               soc_litedramcore_timer_reload_re <= 1'd0;
-               soc_litedramcore_timer_en_storage <= 1'd0;
-               soc_litedramcore_timer_en_re <= 1'd0;
-               soc_litedramcore_timer_update_value_storage <= 1'd0;
-               soc_litedramcore_timer_update_value_re <= 1'd0;
-               soc_litedramcore_timer_value_status <= 32'd0;
-               soc_litedramcore_timer_zero_pending <= 1'd0;
-               soc_litedramcore_timer_zero_old_trigger <= 1'd0;
-               soc_litedramcore_timer_eventmanager_storage <= 1'd0;
-               soc_litedramcore_timer_eventmanager_re <= 1'd0;
-               soc_litedramcore_timer_value <= 32'd0;
-               soc_a7ddrphy_half_sys8x_taps_storage <= 5'd8;
-               soc_a7ddrphy_half_sys8x_taps_re <= 1'd0;
-               soc_a7ddrphy_wlevel_en_storage <= 1'd0;
-               soc_a7ddrphy_wlevel_en_re <= 1'd0;
-               soc_a7ddrphy_dly_sel_storage <= 2'd0;
-               soc_a7ddrphy_dly_sel_re <= 1'd0;
-               soc_a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
-               soc_a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
-               soc_a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
-               soc_a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
-               soc_a7ddrphy_dqs_oe_delayed <= 1'd0;
-               soc_a7ddrphy_dqspattern_o1 <= 8'd0;
-               soc_a7ddrphy_dq_oe_delayed <= 1'd0;
-               soc_a7ddrphy_bitslip0_value <= 3'd0;
-               soc_a7ddrphy_bitslip1_value <= 3'd0;
-               soc_a7ddrphy_bitslip2_value <= 3'd0;
-               soc_a7ddrphy_bitslip3_value <= 3'd0;
-               soc_a7ddrphy_bitslip4_value <= 3'd0;
-               soc_a7ddrphy_bitslip5_value <= 3'd0;
-               soc_a7ddrphy_bitslip6_value <= 3'd0;
-               soc_a7ddrphy_bitslip7_value <= 3'd0;
-               soc_a7ddrphy_bitslip8_value <= 3'd0;
-               soc_a7ddrphy_bitslip9_value <= 3'd0;
-               soc_a7ddrphy_bitslip10_value <= 3'd0;
-               soc_a7ddrphy_bitslip11_value <= 3'd0;
-               soc_a7ddrphy_bitslip12_value <= 3'd0;
-               soc_a7ddrphy_bitslip13_value <= 3'd0;
-               soc_a7ddrphy_bitslip14_value <= 3'd0;
-               soc_a7ddrphy_bitslip15_value <= 3'd0;
-               soc_a7ddrphy_rddata_en_last <= 8'd0;
-               soc_a7ddrphy_wrdata_en_last <= 4'd0;
-               soc_sdram_storage <= 4'd0;
-               soc_sdram_re <= 1'd0;
-               soc_sdram_phaseinjector0_command_storage <= 6'd0;
-               soc_sdram_phaseinjector0_command_re <= 1'd0;
-               soc_sdram_phaseinjector0_address_re <= 1'd0;
-               soc_sdram_phaseinjector0_baddress_re <= 1'd0;
-               soc_sdram_phaseinjector0_wrdata_re <= 1'd0;
-               soc_sdram_phaseinjector0_status <= 32'd0;
-               soc_sdram_phaseinjector1_command_storage <= 6'd0;
-               soc_sdram_phaseinjector1_command_re <= 1'd0;
-               soc_sdram_phaseinjector1_address_re <= 1'd0;
-               soc_sdram_phaseinjector1_baddress_re <= 1'd0;
-               soc_sdram_phaseinjector1_wrdata_re <= 1'd0;
-               soc_sdram_phaseinjector1_status <= 32'd0;
-               soc_sdram_phaseinjector2_command_storage <= 6'd0;
-               soc_sdram_phaseinjector2_command_re <= 1'd0;
-               soc_sdram_phaseinjector2_address_re <= 1'd0;
-               soc_sdram_phaseinjector2_baddress_re <= 1'd0;
-               soc_sdram_phaseinjector2_wrdata_re <= 1'd0;
-               soc_sdram_phaseinjector2_status <= 32'd0;
-               soc_sdram_phaseinjector3_command_storage <= 6'd0;
-               soc_sdram_phaseinjector3_command_re <= 1'd0;
-               soc_sdram_phaseinjector3_address_re <= 1'd0;
-               soc_sdram_phaseinjector3_baddress_re <= 1'd0;
-               soc_sdram_phaseinjector3_wrdata_re <= 1'd0;
-               soc_sdram_phaseinjector3_status <= 32'd0;
-               soc_sdram_dfi_p0_address <= 15'd0;
-               soc_sdram_dfi_p0_bank <= 3'd0;
-               soc_sdram_dfi_p0_cas_n <= 1'd1;
-               soc_sdram_dfi_p0_cs_n <= 1'd1;
-               soc_sdram_dfi_p0_ras_n <= 1'd1;
-               soc_sdram_dfi_p0_we_n <= 1'd1;
-               soc_sdram_dfi_p0_wrdata_en <= 1'd0;
-               soc_sdram_dfi_p0_rddata_en <= 1'd0;
-               soc_sdram_dfi_p1_address <= 15'd0;
-               soc_sdram_dfi_p1_bank <= 3'd0;
-               soc_sdram_dfi_p1_cas_n <= 1'd1;
-               soc_sdram_dfi_p1_cs_n <= 1'd1;
-               soc_sdram_dfi_p1_ras_n <= 1'd1;
-               soc_sdram_dfi_p1_we_n <= 1'd1;
-               soc_sdram_dfi_p1_wrdata_en <= 1'd0;
-               soc_sdram_dfi_p1_rddata_en <= 1'd0;
-               soc_sdram_dfi_p2_address <= 15'd0;
-               soc_sdram_dfi_p2_bank <= 3'd0;
-               soc_sdram_dfi_p2_cas_n <= 1'd1;
-               soc_sdram_dfi_p2_cs_n <= 1'd1;
-               soc_sdram_dfi_p2_ras_n <= 1'd1;
-               soc_sdram_dfi_p2_we_n <= 1'd1;
-               soc_sdram_dfi_p2_wrdata_en <= 1'd0;
-               soc_sdram_dfi_p2_rddata_en <= 1'd0;
-               soc_sdram_dfi_p3_address <= 15'd0;
-               soc_sdram_dfi_p3_bank <= 3'd0;
-               soc_sdram_dfi_p3_cas_n <= 1'd1;
-               soc_sdram_dfi_p3_cs_n <= 1'd1;
-               soc_sdram_dfi_p3_ras_n <= 1'd1;
-               soc_sdram_dfi_p3_we_n <= 1'd1;
-               soc_sdram_dfi_p3_wrdata_en <= 1'd0;
-               soc_sdram_dfi_p3_rddata_en <= 1'd0;
-               soc_sdram_timer_count1 <= 10'd781;
-               soc_sdram_postponer_req_o <= 1'd0;
-               soc_sdram_postponer_count <= 1'd0;
-               soc_sdram_sequencer_done1 <= 1'd0;
-               soc_sdram_sequencer_counter <= 6'd0;
-               soc_sdram_sequencer_count <= 1'd0;
-               soc_sdram_zqcs_timer_count1 <= 27'd99999999;
-               soc_sdram_zqcs_executer_done <= 1'd0;
-               soc_sdram_zqcs_executer_counter <= 5'd0;
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine0_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine0_row <= 15'd0;
-               soc_sdram_bankmachine0_row_opened <= 1'd0;
-               soc_sdram_bankmachine0_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine0_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine0_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine0_trccon_count <= 3'd0;
-               soc_sdram_bankmachine0_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine0_trascon_count <= 3'd0;
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine1_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine1_row <= 15'd0;
-               soc_sdram_bankmachine1_row_opened <= 1'd0;
-               soc_sdram_bankmachine1_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine1_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine1_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine1_trccon_count <= 3'd0;
-               soc_sdram_bankmachine1_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine1_trascon_count <= 3'd0;
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine2_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine2_row <= 15'd0;
-               soc_sdram_bankmachine2_row_opened <= 1'd0;
-               soc_sdram_bankmachine2_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine2_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine2_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine2_trccon_count <= 3'd0;
-               soc_sdram_bankmachine2_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine2_trascon_count <= 3'd0;
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine3_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine3_row <= 15'd0;
-               soc_sdram_bankmachine3_row_opened <= 1'd0;
-               soc_sdram_bankmachine3_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine3_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine3_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine3_trccon_count <= 3'd0;
-               soc_sdram_bankmachine3_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine3_trascon_count <= 3'd0;
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine4_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine4_row <= 15'd0;
-               soc_sdram_bankmachine4_row_opened <= 1'd0;
-               soc_sdram_bankmachine4_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine4_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine4_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine4_trccon_count <= 3'd0;
-               soc_sdram_bankmachine4_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine4_trascon_count <= 3'd0;
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine5_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine5_row <= 15'd0;
-               soc_sdram_bankmachine5_row_opened <= 1'd0;
-               soc_sdram_bankmachine5_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine5_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine5_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine5_trccon_count <= 3'd0;
-               soc_sdram_bankmachine5_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine5_trascon_count <= 3'd0;
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine6_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine6_row <= 15'd0;
-               soc_sdram_bankmachine6_row_opened <= 1'd0;
-               soc_sdram_bankmachine6_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine6_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine6_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine6_trccon_count <= 3'd0;
-               soc_sdram_bankmachine6_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine6_trascon_count <= 3'd0;
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
-               soc_sdram_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
-               soc_sdram_bankmachine7_cmd_buffer_source_valid <= 1'd0;
-               soc_sdram_bankmachine7_row <= 15'd0;
-               soc_sdram_bankmachine7_row_opened <= 1'd0;
-               soc_sdram_bankmachine7_twtpcon_ready <= 1'd1;
-               soc_sdram_bankmachine7_twtpcon_count <= 3'd0;
-               soc_sdram_bankmachine7_trccon_ready <= 1'd1;
-               soc_sdram_bankmachine7_trccon_count <= 3'd0;
-               soc_sdram_bankmachine7_trascon_ready <= 1'd1;
-               soc_sdram_bankmachine7_trascon_count <= 3'd0;
-               soc_sdram_choose_cmd_grant <= 3'd0;
-               soc_sdram_choose_req_grant <= 3'd0;
-               soc_sdram_trrdcon_ready <= 1'd1;
-               soc_sdram_trrdcon_count <= 1'd0;
-               soc_sdram_tfawcon_ready <= 1'd1;
-               soc_sdram_tfawcon_window <= 5'd0;
-               soc_sdram_tccdcon_ready <= 1'd1;
-               soc_sdram_tccdcon_count <= 1'd0;
-               soc_sdram_twtrcon_ready <= 1'd1;
-               soc_sdram_twtrcon_count <= 3'd0;
-               soc_sdram_time0 <= 5'd0;
-               soc_sdram_time1 <= 4'd0;
-               soc_address_q <= 30'd0;
-               soc_counter <= 2'd0;
-               soc_need_refill_q <= 1'd1;
-               soc_cached_datas_flipflop0_q <= 32'd0;
-               soc_cached_datas_flipflop1_q <= 32'd0;
-               soc_cached_datas_flipflop2_q <= 32'd0;
-               soc_cached_datas_flipflop3_q <= 32'd0;
-               soc_cached_sels_flipflop0_q <= 4'd0;
-               soc_cached_sels_flipflop1_q <= 4'd0;
-               soc_cached_sels_flipflop2_q <= 4'd0;
-               soc_cached_sels_flipflop3_q <= 4'd0;
-               soc_count <= 1'd0;
-               soc_init_done_storage <= 1'd0;
-               soc_init_done_re <= 1'd0;
-               soc_init_error_storage <= 1'd0;
-               soc_init_error_re <= 1'd0;
-               vns_wb2csr_state <= 1'd0;
-               vns_refresher_state <= 2'd0;
-               vns_bankmachine0_state <= 4'd0;
-               vns_bankmachine1_state <= 4'd0;
-               vns_bankmachine2_state <= 4'd0;
-               vns_bankmachine3_state <= 4'd0;
-               vns_bankmachine4_state <= 4'd0;
-               vns_bankmachine5_state <= 4'd0;
-               vns_bankmachine6_state <= 4'd0;
-               vns_bankmachine7_state <= 4'd0;
-               vns_multiplexer_state <= 4'd0;
-               vns_roundrobin0_grant <= 1'd0;
-               vns_roundrobin1_grant <= 1'd0;
-               vns_roundrobin2_grant <= 1'd0;
-               vns_roundrobin3_grant <= 1'd0;
-               vns_roundrobin4_grant <= 1'd0;
-               vns_roundrobin5_grant <= 1'd0;
-               vns_roundrobin6_grant <= 1'd0;
-               vns_roundrobin7_grant <= 1'd0;
-               vns_new_master_wdata_ready0 <= 1'd0;
-               vns_new_master_wdata_ready1 <= 1'd0;
-               vns_new_master_wdata_ready2 <= 1'd0;
-               vns_new_master_wdata_ready3 <= 1'd0;
-               vns_new_master_wdata_ready4 <= 1'd0;
-               vns_new_master_wdata_ready5 <= 1'd0;
-               vns_new_master_rdata_valid0 <= 1'd0;
-               vns_new_master_rdata_valid1 <= 1'd0;
-               vns_new_master_rdata_valid2 <= 1'd0;
-               vns_new_master_rdata_valid3 <= 1'd0;
-               vns_new_master_rdata_valid4 <= 1'd0;
-               vns_new_master_rdata_valid5 <= 1'd0;
-               vns_new_master_rdata_valid6 <= 1'd0;
-               vns_new_master_rdata_valid7 <= 1'd0;
-               vns_new_master_rdata_valid8 <= 1'd0;
-               vns_new_master_rdata_valid9 <= 1'd0;
-               vns_new_master_rdata_valid10 <= 1'd0;
-               vns_new_master_rdata_valid11 <= 1'd0;
-               vns_new_master_rdata_valid12 <= 1'd0;
-               vns_new_master_rdata_valid13 <= 1'd0;
-               vns_new_master_rdata_valid14 <= 1'd0;
-               vns_new_master_rdata_valid15 <= 1'd0;
-               vns_new_master_rdata_valid16 <= 1'd0;
-               vns_new_master_rdata_valid17 <= 1'd0;
-               vns_converter_state <= 3'd0;
-               vns_litedramwishbone2native_state <= 2'd0;
-               vns_grant <= 1'd0;
-               vns_slave_sel_r <= 4'd0;
-               vns_count <= 20'd1000000;
-       end
-       vns_regs0 <= serial_rx;
-       vns_regs1 <= vns_regs0;
-end
-
-reg [31:0] mem[0:6143];
-reg [31:0] memdat;
-always @(posedge sys_clk) begin
-       memdat <= mem[soc_litedramcore_litedramcore_adr];
-end
-
-assign soc_litedramcore_litedramcore_dat_r = memdat;
-
-initial begin
-       $readmemh("litedram_core.init", mem);
-end
-
-reg [31:0] mem_1[0:1023];
-reg [9:0] memadr;
-always @(posedge sys_clk) begin
-       if (soc_litedramcore_ram_we[0])
-               mem_1[soc_litedramcore_ram_adr][7:0] <= soc_litedramcore_ram_dat_w[7:0];
-       if (soc_litedramcore_ram_we[1])
-               mem_1[soc_litedramcore_ram_adr][15:8] <= soc_litedramcore_ram_dat_w[15:8];
-       if (soc_litedramcore_ram_we[2])
-               mem_1[soc_litedramcore_ram_adr][23:16] <= soc_litedramcore_ram_dat_w[23:16];
-       if (soc_litedramcore_ram_we[3])
-               mem_1[soc_litedramcore_ram_adr][31:24] <= soc_litedramcore_ram_dat_w[31:24];
-       memadr <= soc_litedramcore_ram_adr;
-end
-
-assign soc_litedramcore_ram_dat_r = mem_1[memadr];
-
-initial begin
-       $readmemh("mem_1.init", mem_1);
-end
-
-reg [9:0] storage[0:15];
-reg [9:0] memdat_1;
-reg [9:0] memdat_2;
-always @(posedge sys_clk) begin
-       if (soc_litedramcore_uart_tx_fifo_wrport_we)
-               storage[soc_litedramcore_uart_tx_fifo_wrport_adr] <= soc_litedramcore_uart_tx_fifo_wrport_dat_w;
-       memdat_1 <= storage[soc_litedramcore_uart_tx_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-       if (soc_litedramcore_uart_tx_fifo_rdport_re)
-               memdat_2 <= storage[soc_litedramcore_uart_tx_fifo_rdport_adr];
-end
-
-assign soc_litedramcore_uart_tx_fifo_wrport_dat_r = memdat_1;
-assign soc_litedramcore_uart_tx_fifo_rdport_dat_r = memdat_2;
-
-reg [9:0] storage_1[0:15];
-reg [9:0] memdat_3;
-reg [9:0] memdat_4;
-always @(posedge sys_clk) begin
-       if (soc_litedramcore_uart_rx_fifo_wrport_we)
-               storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr] <= soc_litedramcore_uart_rx_fifo_wrport_dat_w;
-       memdat_3 <= storage_1[soc_litedramcore_uart_rx_fifo_wrport_adr];
-end
-
-always @(posedge sys_clk) begin
-       if (soc_litedramcore_uart_rx_fifo_rdport_re)
-               memdat_4 <= storage_1[soc_litedramcore_uart_rx_fifo_rdport_adr];
+               a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+               a7ddrphy_half_sys8x_taps_re <= 1'd0;
+               a7ddrphy_wlevel_en_storage <= 1'd0;
+               a7ddrphy_wlevel_en_re <= 1'd0;
+               a7ddrphy_dly_sel_storage <= 2'd0;
+               a7ddrphy_dly_sel_re <= 1'd0;
+               a7ddrphy_dfi_p0_rddata_valid <= 1'd0;
+               a7ddrphy_dfi_p1_rddata_valid <= 1'd0;
+               a7ddrphy_dfi_p2_rddata_valid <= 1'd0;
+               a7ddrphy_dfi_p3_rddata_valid <= 1'd0;
+               a7ddrphy_dqs_oe_delayed <= 1'd0;
+               a7ddrphy_dqspattern_o1 <= 8'd0;
+               a7ddrphy_dq_oe_delayed <= 1'd0;
+               a7ddrphy_bitslip0_value <= 3'd0;
+               a7ddrphy_bitslip1_value <= 3'd0;
+               a7ddrphy_bitslip2_value <= 3'd0;
+               a7ddrphy_bitslip3_value <= 3'd0;
+               a7ddrphy_bitslip4_value <= 3'd0;
+               a7ddrphy_bitslip5_value <= 3'd0;
+               a7ddrphy_bitslip6_value <= 3'd0;
+               a7ddrphy_bitslip7_value <= 3'd0;
+               a7ddrphy_bitslip8_value <= 3'd0;
+               a7ddrphy_bitslip9_value <= 3'd0;
+               a7ddrphy_bitslip10_value <= 3'd0;
+               a7ddrphy_bitslip11_value <= 3'd0;
+               a7ddrphy_bitslip12_value <= 3'd0;
+               a7ddrphy_bitslip13_value <= 3'd0;
+               a7ddrphy_bitslip14_value <= 3'd0;
+               a7ddrphy_bitslip15_value <= 3'd0;
+               a7ddrphy_rddata_en_last <= 8'd0;
+               a7ddrphy_wrdata_en_last <= 4'd0;
+               litedramcore_storage <= 4'd0;
+               litedramcore_re <= 1'd0;
+               litedramcore_phaseinjector0_command_storage <= 6'd0;
+               litedramcore_phaseinjector0_command_re <= 1'd0;
+               litedramcore_phaseinjector0_address_re <= 1'd0;
+               litedramcore_phaseinjector0_baddress_re <= 1'd0;
+               litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector0_status <= 32'd0;
+               litedramcore_phaseinjector1_command_storage <= 6'd0;
+               litedramcore_phaseinjector1_command_re <= 1'd0;
+               litedramcore_phaseinjector1_address_re <= 1'd0;
+               litedramcore_phaseinjector1_baddress_re <= 1'd0;
+               litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector1_status <= 32'd0;
+               litedramcore_phaseinjector2_command_storage <= 6'd0;
+               litedramcore_phaseinjector2_command_re <= 1'd0;
+               litedramcore_phaseinjector2_address_re <= 1'd0;
+               litedramcore_phaseinjector2_baddress_re <= 1'd0;
+               litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector2_status <= 32'd0;
+               litedramcore_phaseinjector3_command_storage <= 6'd0;
+               litedramcore_phaseinjector3_command_re <= 1'd0;
+               litedramcore_phaseinjector3_address_re <= 1'd0;
+               litedramcore_phaseinjector3_baddress_re <= 1'd0;
+               litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+               litedramcore_phaseinjector3_status <= 32'd0;
+               litedramcore_dfi_p0_address <= 15'd0;
+               litedramcore_dfi_p0_bank <= 3'd0;
+               litedramcore_dfi_p0_cas_n <= 1'd1;
+               litedramcore_dfi_p0_cs_n <= 1'd1;
+               litedramcore_dfi_p0_ras_n <= 1'd1;
+               litedramcore_dfi_p0_we_n <= 1'd1;
+               litedramcore_dfi_p0_wrdata_en <= 1'd0;
+               litedramcore_dfi_p0_rddata_en <= 1'd0;
+               litedramcore_dfi_p1_address <= 15'd0;
+               litedramcore_dfi_p1_bank <= 3'd0;
+               litedramcore_dfi_p1_cas_n <= 1'd1;
+               litedramcore_dfi_p1_cs_n <= 1'd1;
+               litedramcore_dfi_p1_ras_n <= 1'd1;
+               litedramcore_dfi_p1_we_n <= 1'd1;
+               litedramcore_dfi_p1_wrdata_en <= 1'd0;
+               litedramcore_dfi_p1_rddata_en <= 1'd0;
+               litedramcore_dfi_p2_address <= 15'd0;
+               litedramcore_dfi_p2_bank <= 3'd0;
+               litedramcore_dfi_p2_cas_n <= 1'd1;
+               litedramcore_dfi_p2_cs_n <= 1'd1;
+               litedramcore_dfi_p2_ras_n <= 1'd1;
+               litedramcore_dfi_p2_we_n <= 1'd1;
+               litedramcore_dfi_p2_wrdata_en <= 1'd0;
+               litedramcore_dfi_p2_rddata_en <= 1'd0;
+               litedramcore_dfi_p3_address <= 15'd0;
+               litedramcore_dfi_p3_bank <= 3'd0;
+               litedramcore_dfi_p3_cas_n <= 1'd1;
+               litedramcore_dfi_p3_cs_n <= 1'd1;
+               litedramcore_dfi_p3_ras_n <= 1'd1;
+               litedramcore_dfi_p3_we_n <= 1'd1;
+               litedramcore_dfi_p3_wrdata_en <= 1'd0;
+               litedramcore_dfi_p3_rddata_en <= 1'd0;
+               litedramcore_timer_count1 <= 10'd781;
+               litedramcore_postponer_req_o <= 1'd0;
+               litedramcore_postponer_count <= 1'd0;
+               litedramcore_sequencer_done1 <= 1'd0;
+               litedramcore_sequencer_counter <= 6'd0;
+               litedramcore_sequencer_count <= 1'd0;
+               litedramcore_zqcs_timer_count1 <= 27'd99999999;
+               litedramcore_zqcs_executer_done <= 1'd0;
+               litedramcore_zqcs_executer_counter <= 5'd0;
+               litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine0_row <= 15'd0;
+               litedramcore_bankmachine0_row_opened <= 1'd0;
+               litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine0_trccon_ready <= 1'd1;
+               litedramcore_bankmachine0_trccon_count <= 3'd0;
+               litedramcore_bankmachine0_trascon_ready <= 1'd1;
+               litedramcore_bankmachine0_trascon_count <= 3'd0;
+               litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine1_row <= 15'd0;
+               litedramcore_bankmachine1_row_opened <= 1'd0;
+               litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine1_trccon_ready <= 1'd1;
+               litedramcore_bankmachine1_trccon_count <= 3'd0;
+               litedramcore_bankmachine1_trascon_ready <= 1'd1;
+               litedramcore_bankmachine1_trascon_count <= 3'd0;
+               litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine2_row <= 15'd0;
+               litedramcore_bankmachine2_row_opened <= 1'd0;
+               litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine2_trccon_ready <= 1'd1;
+               litedramcore_bankmachine2_trccon_count <= 3'd0;
+               litedramcore_bankmachine2_trascon_ready <= 1'd1;
+               litedramcore_bankmachine2_trascon_count <= 3'd0;
+               litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine3_row <= 15'd0;
+               litedramcore_bankmachine3_row_opened <= 1'd0;
+               litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine3_trccon_ready <= 1'd1;
+               litedramcore_bankmachine3_trccon_count <= 3'd0;
+               litedramcore_bankmachine3_trascon_ready <= 1'd1;
+               litedramcore_bankmachine3_trascon_count <= 3'd0;
+               litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine4_row <= 15'd0;
+               litedramcore_bankmachine4_row_opened <= 1'd0;
+               litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine4_trccon_ready <= 1'd1;
+               litedramcore_bankmachine4_trccon_count <= 3'd0;
+               litedramcore_bankmachine4_trascon_ready <= 1'd1;
+               litedramcore_bankmachine4_trascon_count <= 3'd0;
+               litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine5_row <= 15'd0;
+               litedramcore_bankmachine5_row_opened <= 1'd0;
+               litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine5_trccon_ready <= 1'd1;
+               litedramcore_bankmachine5_trccon_count <= 3'd0;
+               litedramcore_bankmachine5_trascon_ready <= 1'd1;
+               litedramcore_bankmachine5_trascon_count <= 3'd0;
+               litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine6_row <= 15'd0;
+               litedramcore_bankmachine6_row_opened <= 1'd0;
+               litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine6_trccon_ready <= 1'd1;
+               litedramcore_bankmachine6_trccon_count <= 3'd0;
+               litedramcore_bankmachine6_trascon_ready <= 1'd1;
+               litedramcore_bankmachine6_trascon_count <= 3'd0;
+               litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
+               litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
+               litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
+               litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
+               litedramcore_bankmachine7_row <= 15'd0;
+               litedramcore_bankmachine7_row_opened <= 1'd0;
+               litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+               litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+               litedramcore_bankmachine7_trccon_ready <= 1'd1;
+               litedramcore_bankmachine7_trccon_count <= 3'd0;
+               litedramcore_bankmachine7_trascon_ready <= 1'd1;
+               litedramcore_bankmachine7_trascon_count <= 3'd0;
+               litedramcore_choose_cmd_grant <= 3'd0;
+               litedramcore_choose_req_grant <= 3'd0;
+               litedramcore_trrdcon_ready <= 1'd1;
+               litedramcore_trrdcon_count <= 1'd0;
+               litedramcore_tfawcon_ready <= 1'd1;
+               litedramcore_tfawcon_window <= 5'd0;
+               litedramcore_tccdcon_ready <= 1'd1;
+               litedramcore_tccdcon_count <= 1'd0;
+               litedramcore_twtrcon_ready <= 1'd1;
+               litedramcore_twtrcon_count <= 3'd0;
+               litedramcore_time0 <= 5'd0;
+               litedramcore_time1 <= 4'd0;
+               init_done_storage <= 1'd0;
+               init_done_re <= 1'd0;
+               init_error_storage <= 1'd0;
+               init_error_re <= 1'd0;
+               refresher_state <= 2'd0;
+               bankmachine0_state <= 4'd0;
+               bankmachine1_state <= 4'd0;
+               bankmachine2_state <= 4'd0;
+               bankmachine3_state <= 4'd0;
+               bankmachine4_state <= 4'd0;
+               bankmachine5_state <= 4'd0;
+               bankmachine6_state <= 4'd0;
+               bankmachine7_state <= 4'd0;
+               multiplexer_state <= 4'd0;
+               new_master_wdata_ready0 <= 1'd0;
+               new_master_wdata_ready1 <= 1'd0;
+               new_master_wdata_ready2 <= 1'd0;
+               new_master_rdata_valid0 <= 1'd0;
+               new_master_rdata_valid1 <= 1'd0;
+               new_master_rdata_valid2 <= 1'd0;
+               new_master_rdata_valid3 <= 1'd0;
+               new_master_rdata_valid4 <= 1'd0;
+               new_master_rdata_valid5 <= 1'd0;
+               new_master_rdata_valid6 <= 1'd0;
+               new_master_rdata_valid7 <= 1'd0;
+               new_master_rdata_valid8 <= 1'd0;
+       end
 end
 
-assign soc_litedramcore_uart_rx_fifo_wrport_dat_r = memdat_3;
-assign soc_litedramcore_uart_rx_fifo_rdport_dat_r = memdat_4;
-
 BUFG BUFG(
-       .I(soc_s7pll0_clkout0),
-       .O(soc_s7pll0_clkout_buf0)
+       .I(s7pll0_clkout0),
+       .O(s7pll0_clkout_buf0)
 );
 
 BUFG BUFG_1(
-       .I(soc_s7pll0_clkout1),
-       .O(soc_s7pll0_clkout_buf1)
+       .I(s7pll0_clkout1),
+       .O(s7pll0_clkout_buf1)
 );
 
 BUFG BUFG_2(
-       .I(soc_s7pll0_clkout2),
-       .O(soc_s7pll0_clkout_buf2)
+       .I(s7pll0_clkout2),
+       .O(s7pll0_clkout_buf2)
 );
 
 BUFG BUFG_3(
-       .I(soc_s7pll1_clkout),
-       .O(soc_s7pll1_clkout_buf)
+       .I(s7pll1_clkout),
+       .O(s7pll1_clkout_buf)
 );
 
 IDELAYCTRL IDELAYCTRL(
        .REFCLK(iodelay_clk),
-       .RST(soc_ic_reset)
+       .RST(ic_reset)
 );
 
 OSERDESE2 #(
@@ -17734,11 +14783,11 @@ OSERDESE2 #(
        .D8(1'd1),
        .OCE(1'd1),
        .RST(sys_rst),
-       .OQ(soc_a7ddrphy_sd_clk_se_nodelay)
+       .OQ(a7ddrphy_sd_clk_se_nodelay)
 );
 
 OBUFDS OBUFDS(
-       .I(soc_a7ddrphy_sd_clk_se_nodelay),
+       .I(a7ddrphy_sd_clk_se_nodelay),
        .O(ddram_clk_p),
        .OB(ddram_clk_n)
 );
@@ -17752,14 +14801,14 @@ OSERDESE2 #(
 ) OSERDESE2_1 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[0]),
-       .D2(soc_a7ddrphy_dfi_p0_address[0]),
-       .D3(soc_a7ddrphy_dfi_p1_address[0]),
-       .D4(soc_a7ddrphy_dfi_p1_address[0]),
-       .D5(soc_a7ddrphy_dfi_p2_address[0]),
-       .D6(soc_a7ddrphy_dfi_p2_address[0]),
-       .D7(soc_a7ddrphy_dfi_p3_address[0]),
-       .D8(soc_a7ddrphy_dfi_p3_address[0]),
+       .D1(a7ddrphy_dfi_p0_address[0]),
+       .D2(a7ddrphy_dfi_p0_address[0]),
+       .D3(a7ddrphy_dfi_p1_address[0]),
+       .D4(a7ddrphy_dfi_p1_address[0]),
+       .D5(a7ddrphy_dfi_p2_address[0]),
+       .D6(a7ddrphy_dfi_p2_address[0]),
+       .D7(a7ddrphy_dfi_p3_address[0]),
+       .D8(a7ddrphy_dfi_p3_address[0]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[0])
@@ -17774,14 +14823,14 @@ OSERDESE2 #(
 ) OSERDESE2_2 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[1]),
-       .D2(soc_a7ddrphy_dfi_p0_address[1]),
-       .D3(soc_a7ddrphy_dfi_p1_address[1]),
-       .D4(soc_a7ddrphy_dfi_p1_address[1]),
-       .D5(soc_a7ddrphy_dfi_p2_address[1]),
-       .D6(soc_a7ddrphy_dfi_p2_address[1]),
-       .D7(soc_a7ddrphy_dfi_p3_address[1]),
-       .D8(soc_a7ddrphy_dfi_p3_address[1]),
+       .D1(a7ddrphy_dfi_p0_address[1]),
+       .D2(a7ddrphy_dfi_p0_address[1]),
+       .D3(a7ddrphy_dfi_p1_address[1]),
+       .D4(a7ddrphy_dfi_p1_address[1]),
+       .D5(a7ddrphy_dfi_p2_address[1]),
+       .D6(a7ddrphy_dfi_p2_address[1]),
+       .D7(a7ddrphy_dfi_p3_address[1]),
+       .D8(a7ddrphy_dfi_p3_address[1]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[1])
@@ -17796,14 +14845,14 @@ OSERDESE2 #(
 ) OSERDESE2_3 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[2]),
-       .D2(soc_a7ddrphy_dfi_p0_address[2]),
-       .D3(soc_a7ddrphy_dfi_p1_address[2]),
-       .D4(soc_a7ddrphy_dfi_p1_address[2]),
-       .D5(soc_a7ddrphy_dfi_p2_address[2]),
-       .D6(soc_a7ddrphy_dfi_p2_address[2]),
-       .D7(soc_a7ddrphy_dfi_p3_address[2]),
-       .D8(soc_a7ddrphy_dfi_p3_address[2]),
+       .D1(a7ddrphy_dfi_p0_address[2]),
+       .D2(a7ddrphy_dfi_p0_address[2]),
+       .D3(a7ddrphy_dfi_p1_address[2]),
+       .D4(a7ddrphy_dfi_p1_address[2]),
+       .D5(a7ddrphy_dfi_p2_address[2]),
+       .D6(a7ddrphy_dfi_p2_address[2]),
+       .D7(a7ddrphy_dfi_p3_address[2]),
+       .D8(a7ddrphy_dfi_p3_address[2]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[2])
@@ -17818,14 +14867,14 @@ OSERDESE2 #(
 ) OSERDESE2_4 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[3]),
-       .D2(soc_a7ddrphy_dfi_p0_address[3]),
-       .D3(soc_a7ddrphy_dfi_p1_address[3]),
-       .D4(soc_a7ddrphy_dfi_p1_address[3]),
-       .D5(soc_a7ddrphy_dfi_p2_address[3]),
-       .D6(soc_a7ddrphy_dfi_p2_address[3]),
-       .D7(soc_a7ddrphy_dfi_p3_address[3]),
-       .D8(soc_a7ddrphy_dfi_p3_address[3]),
+       .D1(a7ddrphy_dfi_p0_address[3]),
+       .D2(a7ddrphy_dfi_p0_address[3]),
+       .D3(a7ddrphy_dfi_p1_address[3]),
+       .D4(a7ddrphy_dfi_p1_address[3]),
+       .D5(a7ddrphy_dfi_p2_address[3]),
+       .D6(a7ddrphy_dfi_p2_address[3]),
+       .D7(a7ddrphy_dfi_p3_address[3]),
+       .D8(a7ddrphy_dfi_p3_address[3]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[3])
@@ -17840,14 +14889,14 @@ OSERDESE2 #(
 ) OSERDESE2_5 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[4]),
-       .D2(soc_a7ddrphy_dfi_p0_address[4]),
-       .D3(soc_a7ddrphy_dfi_p1_address[4]),
-       .D4(soc_a7ddrphy_dfi_p1_address[4]),
-       .D5(soc_a7ddrphy_dfi_p2_address[4]),
-       .D6(soc_a7ddrphy_dfi_p2_address[4]),
-       .D7(soc_a7ddrphy_dfi_p3_address[4]),
-       .D8(soc_a7ddrphy_dfi_p3_address[4]),
+       .D1(a7ddrphy_dfi_p0_address[4]),
+       .D2(a7ddrphy_dfi_p0_address[4]),
+       .D3(a7ddrphy_dfi_p1_address[4]),
+       .D4(a7ddrphy_dfi_p1_address[4]),
+       .D5(a7ddrphy_dfi_p2_address[4]),
+       .D6(a7ddrphy_dfi_p2_address[4]),
+       .D7(a7ddrphy_dfi_p3_address[4]),
+       .D8(a7ddrphy_dfi_p3_address[4]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[4])
@@ -17862,14 +14911,14 @@ OSERDESE2 #(
 ) OSERDESE2_6 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[5]),
-       .D2(soc_a7ddrphy_dfi_p0_address[5]),
-       .D3(soc_a7ddrphy_dfi_p1_address[5]),
-       .D4(soc_a7ddrphy_dfi_p1_address[5]),
-       .D5(soc_a7ddrphy_dfi_p2_address[5]),
-       .D6(soc_a7ddrphy_dfi_p2_address[5]),
-       .D7(soc_a7ddrphy_dfi_p3_address[5]),
-       .D8(soc_a7ddrphy_dfi_p3_address[5]),
+       .D1(a7ddrphy_dfi_p0_address[5]),
+       .D2(a7ddrphy_dfi_p0_address[5]),
+       .D3(a7ddrphy_dfi_p1_address[5]),
+       .D4(a7ddrphy_dfi_p1_address[5]),
+       .D5(a7ddrphy_dfi_p2_address[5]),
+       .D6(a7ddrphy_dfi_p2_address[5]),
+       .D7(a7ddrphy_dfi_p3_address[5]),
+       .D8(a7ddrphy_dfi_p3_address[5]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[5])
@@ -17884,14 +14933,14 @@ OSERDESE2 #(
 ) OSERDESE2_7 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[6]),
-       .D2(soc_a7ddrphy_dfi_p0_address[6]),
-       .D3(soc_a7ddrphy_dfi_p1_address[6]),
-       .D4(soc_a7ddrphy_dfi_p1_address[6]),
-       .D5(soc_a7ddrphy_dfi_p2_address[6]),
-       .D6(soc_a7ddrphy_dfi_p2_address[6]),
-       .D7(soc_a7ddrphy_dfi_p3_address[6]),
-       .D8(soc_a7ddrphy_dfi_p3_address[6]),
+       .D1(a7ddrphy_dfi_p0_address[6]),
+       .D2(a7ddrphy_dfi_p0_address[6]),
+       .D3(a7ddrphy_dfi_p1_address[6]),
+       .D4(a7ddrphy_dfi_p1_address[6]),
+       .D5(a7ddrphy_dfi_p2_address[6]),
+       .D6(a7ddrphy_dfi_p2_address[6]),
+       .D7(a7ddrphy_dfi_p3_address[6]),
+       .D8(a7ddrphy_dfi_p3_address[6]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[6])
@@ -17906,14 +14955,14 @@ OSERDESE2 #(
 ) OSERDESE2_8 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[7]),
-       .D2(soc_a7ddrphy_dfi_p0_address[7]),
-       .D3(soc_a7ddrphy_dfi_p1_address[7]),
-       .D4(soc_a7ddrphy_dfi_p1_address[7]),
-       .D5(soc_a7ddrphy_dfi_p2_address[7]),
-       .D6(soc_a7ddrphy_dfi_p2_address[7]),
-       .D7(soc_a7ddrphy_dfi_p3_address[7]),
-       .D8(soc_a7ddrphy_dfi_p3_address[7]),
+       .D1(a7ddrphy_dfi_p0_address[7]),
+       .D2(a7ddrphy_dfi_p0_address[7]),
+       .D3(a7ddrphy_dfi_p1_address[7]),
+       .D4(a7ddrphy_dfi_p1_address[7]),
+       .D5(a7ddrphy_dfi_p2_address[7]),
+       .D6(a7ddrphy_dfi_p2_address[7]),
+       .D7(a7ddrphy_dfi_p3_address[7]),
+       .D8(a7ddrphy_dfi_p3_address[7]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[7])
@@ -17928,14 +14977,14 @@ OSERDESE2 #(
 ) OSERDESE2_9 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[8]),
-       .D2(soc_a7ddrphy_dfi_p0_address[8]),
-       .D3(soc_a7ddrphy_dfi_p1_address[8]),
-       .D4(soc_a7ddrphy_dfi_p1_address[8]),
-       .D5(soc_a7ddrphy_dfi_p2_address[8]),
-       .D6(soc_a7ddrphy_dfi_p2_address[8]),
-       .D7(soc_a7ddrphy_dfi_p3_address[8]),
-       .D8(soc_a7ddrphy_dfi_p3_address[8]),
+       .D1(a7ddrphy_dfi_p0_address[8]),
+       .D2(a7ddrphy_dfi_p0_address[8]),
+       .D3(a7ddrphy_dfi_p1_address[8]),
+       .D4(a7ddrphy_dfi_p1_address[8]),
+       .D5(a7ddrphy_dfi_p2_address[8]),
+       .D6(a7ddrphy_dfi_p2_address[8]),
+       .D7(a7ddrphy_dfi_p3_address[8]),
+       .D8(a7ddrphy_dfi_p3_address[8]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[8])
@@ -17950,14 +14999,14 @@ OSERDESE2 #(
 ) OSERDESE2_10 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[9]),
-       .D2(soc_a7ddrphy_dfi_p0_address[9]),
-       .D3(soc_a7ddrphy_dfi_p1_address[9]),
-       .D4(soc_a7ddrphy_dfi_p1_address[9]),
-       .D5(soc_a7ddrphy_dfi_p2_address[9]),
-       .D6(soc_a7ddrphy_dfi_p2_address[9]),
-       .D7(soc_a7ddrphy_dfi_p3_address[9]),
-       .D8(soc_a7ddrphy_dfi_p3_address[9]),
+       .D1(a7ddrphy_dfi_p0_address[9]),
+       .D2(a7ddrphy_dfi_p0_address[9]),
+       .D3(a7ddrphy_dfi_p1_address[9]),
+       .D4(a7ddrphy_dfi_p1_address[9]),
+       .D5(a7ddrphy_dfi_p2_address[9]),
+       .D6(a7ddrphy_dfi_p2_address[9]),
+       .D7(a7ddrphy_dfi_p3_address[9]),
+       .D8(a7ddrphy_dfi_p3_address[9]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[9])
@@ -17972,14 +15021,14 @@ OSERDESE2 #(
 ) OSERDESE2_11 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[10]),
-       .D2(soc_a7ddrphy_dfi_p0_address[10]),
-       .D3(soc_a7ddrphy_dfi_p1_address[10]),
-       .D4(soc_a7ddrphy_dfi_p1_address[10]),
-       .D5(soc_a7ddrphy_dfi_p2_address[10]),
-       .D6(soc_a7ddrphy_dfi_p2_address[10]),
-       .D7(soc_a7ddrphy_dfi_p3_address[10]),
-       .D8(soc_a7ddrphy_dfi_p3_address[10]),
+       .D1(a7ddrphy_dfi_p0_address[10]),
+       .D2(a7ddrphy_dfi_p0_address[10]),
+       .D3(a7ddrphy_dfi_p1_address[10]),
+       .D4(a7ddrphy_dfi_p1_address[10]),
+       .D5(a7ddrphy_dfi_p2_address[10]),
+       .D6(a7ddrphy_dfi_p2_address[10]),
+       .D7(a7ddrphy_dfi_p3_address[10]),
+       .D8(a7ddrphy_dfi_p3_address[10]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[10])
@@ -17994,14 +15043,14 @@ OSERDESE2 #(
 ) OSERDESE2_12 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[11]),
-       .D2(soc_a7ddrphy_dfi_p0_address[11]),
-       .D3(soc_a7ddrphy_dfi_p1_address[11]),
-       .D4(soc_a7ddrphy_dfi_p1_address[11]),
-       .D5(soc_a7ddrphy_dfi_p2_address[11]),
-       .D6(soc_a7ddrphy_dfi_p2_address[11]),
-       .D7(soc_a7ddrphy_dfi_p3_address[11]),
-       .D8(soc_a7ddrphy_dfi_p3_address[11]),
+       .D1(a7ddrphy_dfi_p0_address[11]),
+       .D2(a7ddrphy_dfi_p0_address[11]),
+       .D3(a7ddrphy_dfi_p1_address[11]),
+       .D4(a7ddrphy_dfi_p1_address[11]),
+       .D5(a7ddrphy_dfi_p2_address[11]),
+       .D6(a7ddrphy_dfi_p2_address[11]),
+       .D7(a7ddrphy_dfi_p3_address[11]),
+       .D8(a7ddrphy_dfi_p3_address[11]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[11])
@@ -18016,14 +15065,14 @@ OSERDESE2 #(
 ) OSERDESE2_13 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[12]),
-       .D2(soc_a7ddrphy_dfi_p0_address[12]),
-       .D3(soc_a7ddrphy_dfi_p1_address[12]),
-       .D4(soc_a7ddrphy_dfi_p1_address[12]),
-       .D5(soc_a7ddrphy_dfi_p2_address[12]),
-       .D6(soc_a7ddrphy_dfi_p2_address[12]),
-       .D7(soc_a7ddrphy_dfi_p3_address[12]),
-       .D8(soc_a7ddrphy_dfi_p3_address[12]),
+       .D1(a7ddrphy_dfi_p0_address[12]),
+       .D2(a7ddrphy_dfi_p0_address[12]),
+       .D3(a7ddrphy_dfi_p1_address[12]),
+       .D4(a7ddrphy_dfi_p1_address[12]),
+       .D5(a7ddrphy_dfi_p2_address[12]),
+       .D6(a7ddrphy_dfi_p2_address[12]),
+       .D7(a7ddrphy_dfi_p3_address[12]),
+       .D8(a7ddrphy_dfi_p3_address[12]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[12])
@@ -18038,14 +15087,14 @@ OSERDESE2 #(
 ) OSERDESE2_14 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[13]),
-       .D2(soc_a7ddrphy_dfi_p0_address[13]),
-       .D3(soc_a7ddrphy_dfi_p1_address[13]),
-       .D4(soc_a7ddrphy_dfi_p1_address[13]),
-       .D5(soc_a7ddrphy_dfi_p2_address[13]),
-       .D6(soc_a7ddrphy_dfi_p2_address[13]),
-       .D7(soc_a7ddrphy_dfi_p3_address[13]),
-       .D8(soc_a7ddrphy_dfi_p3_address[13]),
+       .D1(a7ddrphy_dfi_p0_address[13]),
+       .D2(a7ddrphy_dfi_p0_address[13]),
+       .D3(a7ddrphy_dfi_p1_address[13]),
+       .D4(a7ddrphy_dfi_p1_address[13]),
+       .D5(a7ddrphy_dfi_p2_address[13]),
+       .D6(a7ddrphy_dfi_p2_address[13]),
+       .D7(a7ddrphy_dfi_p3_address[13]),
+       .D8(a7ddrphy_dfi_p3_address[13]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[13])
@@ -18060,14 +15109,14 @@ OSERDESE2 #(
 ) OSERDESE2_15 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_address[14]),
-       .D2(soc_a7ddrphy_dfi_p0_address[14]),
-       .D3(soc_a7ddrphy_dfi_p1_address[14]),
-       .D4(soc_a7ddrphy_dfi_p1_address[14]),
-       .D5(soc_a7ddrphy_dfi_p2_address[14]),
-       .D6(soc_a7ddrphy_dfi_p2_address[14]),
-       .D7(soc_a7ddrphy_dfi_p3_address[14]),
-       .D8(soc_a7ddrphy_dfi_p3_address[14]),
+       .D1(a7ddrphy_dfi_p0_address[14]),
+       .D2(a7ddrphy_dfi_p0_address[14]),
+       .D3(a7ddrphy_dfi_p1_address[14]),
+       .D4(a7ddrphy_dfi_p1_address[14]),
+       .D5(a7ddrphy_dfi_p2_address[14]),
+       .D6(a7ddrphy_dfi_p2_address[14]),
+       .D7(a7ddrphy_dfi_p3_address[14]),
+       .D8(a7ddrphy_dfi_p3_address[14]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_a[14])
@@ -18082,14 +15131,14 @@ OSERDESE2 #(
 ) OSERDESE2_16 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_bank[0]),
-       .D2(soc_a7ddrphy_dfi_p0_bank[0]),
-       .D3(soc_a7ddrphy_dfi_p1_bank[0]),
-       .D4(soc_a7ddrphy_dfi_p1_bank[0]),
-       .D5(soc_a7ddrphy_dfi_p2_bank[0]),
-       .D6(soc_a7ddrphy_dfi_p2_bank[0]),
-       .D7(soc_a7ddrphy_dfi_p3_bank[0]),
-       .D8(soc_a7ddrphy_dfi_p3_bank[0]),
+       .D1(a7ddrphy_dfi_p0_bank[0]),
+       .D2(a7ddrphy_dfi_p0_bank[0]),
+       .D3(a7ddrphy_dfi_p1_bank[0]),
+       .D4(a7ddrphy_dfi_p1_bank[0]),
+       .D5(a7ddrphy_dfi_p2_bank[0]),
+       .D6(a7ddrphy_dfi_p2_bank[0]),
+       .D7(a7ddrphy_dfi_p3_bank[0]),
+       .D8(a7ddrphy_dfi_p3_bank[0]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_ba[0])
@@ -18104,14 +15153,14 @@ OSERDESE2 #(
 ) OSERDESE2_17 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_bank[1]),
-       .D2(soc_a7ddrphy_dfi_p0_bank[1]),
-       .D3(soc_a7ddrphy_dfi_p1_bank[1]),
-       .D4(soc_a7ddrphy_dfi_p1_bank[1]),
-       .D5(soc_a7ddrphy_dfi_p2_bank[1]),
-       .D6(soc_a7ddrphy_dfi_p2_bank[1]),
-       .D7(soc_a7ddrphy_dfi_p3_bank[1]),
-       .D8(soc_a7ddrphy_dfi_p3_bank[1]),
+       .D1(a7ddrphy_dfi_p0_bank[1]),
+       .D2(a7ddrphy_dfi_p0_bank[1]),
+       .D3(a7ddrphy_dfi_p1_bank[1]),
+       .D4(a7ddrphy_dfi_p1_bank[1]),
+       .D5(a7ddrphy_dfi_p2_bank[1]),
+       .D6(a7ddrphy_dfi_p2_bank[1]),
+       .D7(a7ddrphy_dfi_p3_bank[1]),
+       .D8(a7ddrphy_dfi_p3_bank[1]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_ba[1])
@@ -18126,14 +15175,14 @@ OSERDESE2 #(
 ) OSERDESE2_18 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_bank[2]),
-       .D2(soc_a7ddrphy_dfi_p0_bank[2]),
-       .D3(soc_a7ddrphy_dfi_p1_bank[2]),
-       .D4(soc_a7ddrphy_dfi_p1_bank[2]),
-       .D5(soc_a7ddrphy_dfi_p2_bank[2]),
-       .D6(soc_a7ddrphy_dfi_p2_bank[2]),
-       .D7(soc_a7ddrphy_dfi_p3_bank[2]),
-       .D8(soc_a7ddrphy_dfi_p3_bank[2]),
+       .D1(a7ddrphy_dfi_p0_bank[2]),
+       .D2(a7ddrphy_dfi_p0_bank[2]),
+       .D3(a7ddrphy_dfi_p1_bank[2]),
+       .D4(a7ddrphy_dfi_p1_bank[2]),
+       .D5(a7ddrphy_dfi_p2_bank[2]),
+       .D6(a7ddrphy_dfi_p2_bank[2]),
+       .D7(a7ddrphy_dfi_p3_bank[2]),
+       .D8(a7ddrphy_dfi_p3_bank[2]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_ba[2])
@@ -18148,14 +15197,14 @@ OSERDESE2 #(
 ) OSERDESE2_19 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_ras_n),
-       .D2(soc_a7ddrphy_dfi_p0_ras_n),
-       .D3(soc_a7ddrphy_dfi_p1_ras_n),
-       .D4(soc_a7ddrphy_dfi_p1_ras_n),
-       .D5(soc_a7ddrphy_dfi_p2_ras_n),
-       .D6(soc_a7ddrphy_dfi_p2_ras_n),
-       .D7(soc_a7ddrphy_dfi_p3_ras_n),
-       .D8(soc_a7ddrphy_dfi_p3_ras_n),
+       .D1(a7ddrphy_dfi_p0_ras_n),
+       .D2(a7ddrphy_dfi_p0_ras_n),
+       .D3(a7ddrphy_dfi_p1_ras_n),
+       .D4(a7ddrphy_dfi_p1_ras_n),
+       .D5(a7ddrphy_dfi_p2_ras_n),
+       .D6(a7ddrphy_dfi_p2_ras_n),
+       .D7(a7ddrphy_dfi_p3_ras_n),
+       .D8(a7ddrphy_dfi_p3_ras_n),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_ras_n)
@@ -18170,14 +15219,14 @@ OSERDESE2 #(
 ) OSERDESE2_20 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_cas_n),
-       .D2(soc_a7ddrphy_dfi_p0_cas_n),
-       .D3(soc_a7ddrphy_dfi_p1_cas_n),
-       .D4(soc_a7ddrphy_dfi_p1_cas_n),
-       .D5(soc_a7ddrphy_dfi_p2_cas_n),
-       .D6(soc_a7ddrphy_dfi_p2_cas_n),
-       .D7(soc_a7ddrphy_dfi_p3_cas_n),
-       .D8(soc_a7ddrphy_dfi_p3_cas_n),
+       .D1(a7ddrphy_dfi_p0_cas_n),
+       .D2(a7ddrphy_dfi_p0_cas_n),
+       .D3(a7ddrphy_dfi_p1_cas_n),
+       .D4(a7ddrphy_dfi_p1_cas_n),
+       .D5(a7ddrphy_dfi_p2_cas_n),
+       .D6(a7ddrphy_dfi_p2_cas_n),
+       .D7(a7ddrphy_dfi_p3_cas_n),
+       .D8(a7ddrphy_dfi_p3_cas_n),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_cas_n)
@@ -18192,14 +15241,14 @@ OSERDESE2 #(
 ) OSERDESE2_21 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_we_n),
-       .D2(soc_a7ddrphy_dfi_p0_we_n),
-       .D3(soc_a7ddrphy_dfi_p1_we_n),
-       .D4(soc_a7ddrphy_dfi_p1_we_n),
-       .D5(soc_a7ddrphy_dfi_p2_we_n),
-       .D6(soc_a7ddrphy_dfi_p2_we_n),
-       .D7(soc_a7ddrphy_dfi_p3_we_n),
-       .D8(soc_a7ddrphy_dfi_p3_we_n),
+       .D1(a7ddrphy_dfi_p0_we_n),
+       .D2(a7ddrphy_dfi_p0_we_n),
+       .D3(a7ddrphy_dfi_p1_we_n),
+       .D4(a7ddrphy_dfi_p1_we_n),
+       .D5(a7ddrphy_dfi_p2_we_n),
+       .D6(a7ddrphy_dfi_p2_we_n),
+       .D7(a7ddrphy_dfi_p3_we_n),
+       .D8(a7ddrphy_dfi_p3_we_n),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_we_n)
@@ -18214,14 +15263,14 @@ OSERDESE2 #(
 ) OSERDESE2_22 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_cke),
-       .D2(soc_a7ddrphy_dfi_p0_cke),
-       .D3(soc_a7ddrphy_dfi_p1_cke),
-       .D4(soc_a7ddrphy_dfi_p1_cke),
-       .D5(soc_a7ddrphy_dfi_p2_cke),
-       .D6(soc_a7ddrphy_dfi_p2_cke),
-       .D7(soc_a7ddrphy_dfi_p3_cke),
-       .D8(soc_a7ddrphy_dfi_p3_cke),
+       .D1(a7ddrphy_dfi_p0_cke),
+       .D2(a7ddrphy_dfi_p0_cke),
+       .D3(a7ddrphy_dfi_p1_cke),
+       .D4(a7ddrphy_dfi_p1_cke),
+       .D5(a7ddrphy_dfi_p2_cke),
+       .D6(a7ddrphy_dfi_p2_cke),
+       .D7(a7ddrphy_dfi_p3_cke),
+       .D8(a7ddrphy_dfi_p3_cke),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_cke)
@@ -18236,14 +15285,14 @@ OSERDESE2 #(
 ) OSERDESE2_23 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_odt),
-       .D2(soc_a7ddrphy_dfi_p0_odt),
-       .D3(soc_a7ddrphy_dfi_p1_odt),
-       .D4(soc_a7ddrphy_dfi_p1_odt),
-       .D5(soc_a7ddrphy_dfi_p2_odt),
-       .D6(soc_a7ddrphy_dfi_p2_odt),
-       .D7(soc_a7ddrphy_dfi_p3_odt),
-       .D8(soc_a7ddrphy_dfi_p3_odt),
+       .D1(a7ddrphy_dfi_p0_odt),
+       .D2(a7ddrphy_dfi_p0_odt),
+       .D3(a7ddrphy_dfi_p1_odt),
+       .D4(a7ddrphy_dfi_p1_odt),
+       .D5(a7ddrphy_dfi_p2_odt),
+       .D6(a7ddrphy_dfi_p2_odt),
+       .D7(a7ddrphy_dfi_p3_odt),
+       .D8(a7ddrphy_dfi_p3_odt),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_odt)
@@ -18258,14 +15307,14 @@ OSERDESE2 #(
 ) OSERDESE2_24 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_reset_n),
-       .D2(soc_a7ddrphy_dfi_p0_reset_n),
-       .D3(soc_a7ddrphy_dfi_p1_reset_n),
-       .D4(soc_a7ddrphy_dfi_p1_reset_n),
-       .D5(soc_a7ddrphy_dfi_p2_reset_n),
-       .D6(soc_a7ddrphy_dfi_p2_reset_n),
-       .D7(soc_a7ddrphy_dfi_p3_reset_n),
-       .D8(soc_a7ddrphy_dfi_p3_reset_n),
+       .D1(a7ddrphy_dfi_p0_reset_n),
+       .D2(a7ddrphy_dfi_p0_reset_n),
+       .D3(a7ddrphy_dfi_p1_reset_n),
+       .D4(a7ddrphy_dfi_p1_reset_n),
+       .D5(a7ddrphy_dfi_p2_reset_n),
+       .D6(a7ddrphy_dfi_p2_reset_n),
+       .D7(a7ddrphy_dfi_p3_reset_n),
+       .D8(a7ddrphy_dfi_p3_reset_n),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_reset_n)
@@ -18280,14 +15329,14 @@ OSERDESE2 #(
 ) OSERDESE2_25 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_cs_n),
-       .D2(soc_a7ddrphy_dfi_p0_cs_n),
-       .D3(soc_a7ddrphy_dfi_p1_cs_n),
-       .D4(soc_a7ddrphy_dfi_p1_cs_n),
-       .D5(soc_a7ddrphy_dfi_p2_cs_n),
-       .D6(soc_a7ddrphy_dfi_p2_cs_n),
-       .D7(soc_a7ddrphy_dfi_p3_cs_n),
-       .D8(soc_a7ddrphy_dfi_p3_cs_n),
+       .D1(a7ddrphy_dfi_p0_cs_n),
+       .D2(a7ddrphy_dfi_p0_cs_n),
+       .D3(a7ddrphy_dfi_p1_cs_n),
+       .D4(a7ddrphy_dfi_p1_cs_n),
+       .D5(a7ddrphy_dfi_p2_cs_n),
+       .D6(a7ddrphy_dfi_p2_cs_n),
+       .D7(a7ddrphy_dfi_p3_cs_n),
+       .D8(a7ddrphy_dfi_p3_cs_n),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_cs_n)
@@ -18302,14 +15351,14 @@ OSERDESE2 #(
 ) OSERDESE2_26 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[0]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[2]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[0]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[2]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[0]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[2]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[0]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[2]),
+       .D1(a7ddrphy_dfi_p0_wrdata_mask[0]),
+       .D2(a7ddrphy_dfi_p0_wrdata_mask[2]),
+       .D3(a7ddrphy_dfi_p1_wrdata_mask[0]),
+       .D4(a7ddrphy_dfi_p1_wrdata_mask[2]),
+       .D5(a7ddrphy_dfi_p2_wrdata_mask[0]),
+       .D6(a7ddrphy_dfi_p2_wrdata_mask[2]),
+       .D7(a7ddrphy_dfi_p3_wrdata_mask[0]),
+       .D8(a7ddrphy_dfi_p3_wrdata_mask[2]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_dm[0])
@@ -18324,14 +15373,14 @@ OSERDESE2 #(
 ) OSERDESE2_27 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata_mask[1]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata_mask[3]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata_mask[1]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata_mask[3]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata_mask[1]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata_mask[3]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata_mask[1]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata_mask[3]),
+       .D1(a7ddrphy_dfi_p0_wrdata_mask[1]),
+       .D2(a7ddrphy_dfi_p0_wrdata_mask[3]),
+       .D3(a7ddrphy_dfi_p1_wrdata_mask[1]),
+       .D4(a7ddrphy_dfi_p1_wrdata_mask[3]),
+       .D5(a7ddrphy_dfi_p2_wrdata_mask[1]),
+       .D6(a7ddrphy_dfi_p2_wrdata_mask[3]),
+       .D7(a7ddrphy_dfi_p3_wrdata_mask[1]),
+       .D8(a7ddrphy_dfi_p3_wrdata_mask[3]),
        .OCE(1'd1),
        .RST(sys_rst),
        .OQ(ddram_dm[1])
@@ -18346,21 +15395,21 @@ OSERDESE2 #(
 ) OSERDESE2_28 (
        .CLK(sys4x_dqs_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dqspattern_o1[0]),
-       .D2(soc_a7ddrphy_dqspattern_o1[1]),
-       .D3(soc_a7ddrphy_dqspattern_o1[2]),
-       .D4(soc_a7ddrphy_dqspattern_o1[3]),
-       .D5(soc_a7ddrphy_dqspattern_o1[4]),
-       .D6(soc_a7ddrphy_dqspattern_o1[5]),
-       .D7(soc_a7ddrphy_dqspattern_o1[6]),
-       .D8(soc_a7ddrphy_dqspattern_o1[7]),
+       .D1(a7ddrphy_dqspattern_o1[0]),
+       .D2(a7ddrphy_dqspattern_o1[1]),
+       .D3(a7ddrphy_dqspattern_o1[2]),
+       .D4(a7ddrphy_dqspattern_o1[3]),
+       .D5(a7ddrphy_dqspattern_o1[4]),
+       .D6(a7ddrphy_dqspattern_o1[5]),
+       .D7(a7ddrphy_dqspattern_o1[6]),
+       .D8(a7ddrphy_dqspattern_o1[7]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dqs_oe_delayed)),
+       .T1((~a7ddrphy_dqs_oe_delayed)),
        .TCE(1'd1),
-       .OFB(soc_a7ddrphy0),
-       .OQ(soc_a7ddrphy_dqs_o_no_delay0),
-       .TQ(soc_a7ddrphy_dqs_t0)
+       .OFB(a7ddrphy0),
+       .OQ(a7ddrphy_dqs_o_no_delay0),
+       .TQ(a7ddrphy_dqs_t0)
 );
 
 IDELAYE2 #(
@@ -18373,16 +15422,16 @@ IDELAYE2 #(
        .REFCLK_FREQUENCY(200.0),
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2 (
-       .IDATAIN(soc_a7ddrphy_dqs_i[0]),
-       .DATAOUT(soc_a7ddrphy_dqs_i_delayed[0])
+       .IDATAIN(a7ddrphy_dqs_i[0]),
+       .DATAOUT(a7ddrphy_dqs_i_delayed[0])
 );
 
 IOBUFDS IOBUFDS(
-       .I(soc_a7ddrphy_dqs_o_no_delay0),
-       .T(soc_a7ddrphy_dqs_t0),
+       .I(a7ddrphy_dqs_o_no_delay0),
+       .T(a7ddrphy_dqs_t0),
        .IO(ddram_dqs_p[0]),
        .IOB(ddram_dqs_n[0]),
-       .O(soc_a7ddrphy_dqs_i[0])
+       .O(a7ddrphy_dqs_i[0])
 );
 
 OSERDESE2 #(
@@ -18394,21 +15443,21 @@ OSERDESE2 #(
 ) OSERDESE2_29 (
        .CLK(sys4x_dqs_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dqspattern_o1[0]),
-       .D2(soc_a7ddrphy_dqspattern_o1[1]),
-       .D3(soc_a7ddrphy_dqspattern_o1[2]),
-       .D4(soc_a7ddrphy_dqspattern_o1[3]),
-       .D5(soc_a7ddrphy_dqspattern_o1[4]),
-       .D6(soc_a7ddrphy_dqspattern_o1[5]),
-       .D7(soc_a7ddrphy_dqspattern_o1[6]),
-       .D8(soc_a7ddrphy_dqspattern_o1[7]),
+       .D1(a7ddrphy_dqspattern_o1[0]),
+       .D2(a7ddrphy_dqspattern_o1[1]),
+       .D3(a7ddrphy_dqspattern_o1[2]),
+       .D4(a7ddrphy_dqspattern_o1[3]),
+       .D5(a7ddrphy_dqspattern_o1[4]),
+       .D6(a7ddrphy_dqspattern_o1[5]),
+       .D7(a7ddrphy_dqspattern_o1[6]),
+       .D8(a7ddrphy_dqspattern_o1[7]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dqs_oe_delayed)),
+       .T1((~a7ddrphy_dqs_oe_delayed)),
        .TCE(1'd1),
-       .OFB(soc_a7ddrphy1),
-       .OQ(soc_a7ddrphy_dqs_o_no_delay1),
-       .TQ(soc_a7ddrphy_dqs_t1)
+       .OFB(a7ddrphy1),
+       .OQ(a7ddrphy_dqs_o_no_delay1),
+       .TQ(a7ddrphy_dqs_t1)
 );
 
 IDELAYE2 #(
@@ -18421,16 +15470,16 @@ IDELAYE2 #(
        .REFCLK_FREQUENCY(200.0),
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_1 (
-       .IDATAIN(soc_a7ddrphy_dqs_i[1]),
-       .DATAOUT(soc_a7ddrphy_dqs_i_delayed[1])
+       .IDATAIN(a7ddrphy_dqs_i[1]),
+       .DATAOUT(a7ddrphy_dqs_i_delayed[1])
 );
 
 IOBUFDS IOBUFDS_1(
-       .I(soc_a7ddrphy_dqs_o_no_delay1),
-       .T(soc_a7ddrphy_dqs_t1),
+       .I(a7ddrphy_dqs_o_no_delay1),
+       .T(a7ddrphy_dqs_t1),
        .IO(ddram_dqs_p[1]),
        .IOB(ddram_dqs_n[1]),
-       .O(soc_a7ddrphy_dqs_i[1])
+       .O(a7ddrphy_dqs_i[1])
 );
 
 OSERDESE2 #(
@@ -18442,20 +15491,20 @@ OSERDESE2 #(
 ) OSERDESE2_30 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[0]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[16]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[0]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[16]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[0]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[16]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[0]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[16]),
+       .D1(a7ddrphy_dfi_p0_wrdata[0]),
+       .D2(a7ddrphy_dfi_p0_wrdata[16]),
+       .D3(a7ddrphy_dfi_p1_wrdata[0]),
+       .D4(a7ddrphy_dfi_p1_wrdata[16]),
+       .D5(a7ddrphy_dfi_p2_wrdata[0]),
+       .D6(a7ddrphy_dfi_p2_wrdata[16]),
+       .D7(a7ddrphy_dfi_p3_wrdata[0]),
+       .D8(a7ddrphy_dfi_p3_wrdata[16]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay0),
-       .TQ(soc_a7ddrphy_dq_t0)
+       .OQ(a7ddrphy_dq_o_nodelay0),
+       .TQ(a7ddrphy_dq_t0)
 );
 
 ISERDESE2 #(
@@ -18471,16 +15520,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed0),
+       .DDLY(a7ddrphy_dq_i_delayed0),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data0[7]),
-       .Q2(soc_a7ddrphy_dq_i_data0[6]),
-       .Q3(soc_a7ddrphy_dq_i_data0[5]),
-       .Q4(soc_a7ddrphy_dq_i_data0[4]),
-       .Q5(soc_a7ddrphy_dq_i_data0[3]),
-       .Q6(soc_a7ddrphy_dq_i_data0[2]),
-       .Q7(soc_a7ddrphy_dq_i_data0[1]),
-       .Q8(soc_a7ddrphy_dq_i_data0[0])
+       .Q1(a7ddrphy_dq_i_data0[7]),
+       .Q2(a7ddrphy_dq_i_data0[6]),
+       .Q3(a7ddrphy_dq_i_data0[5]),
+       .Q4(a7ddrphy_dq_i_data0[4]),
+       .Q5(a7ddrphy_dq_i_data0[3]),
+       .Q6(a7ddrphy_dq_i_data0[2]),
+       .Q7(a7ddrphy_dq_i_data0[1]),
+       .Q8(a7ddrphy_dq_i_data0[0])
 );
 
 IDELAYE2 #(
@@ -18494,19 +15543,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_2 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay0),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay0),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed0)
+       .DATAOUT(a7ddrphy_dq_i_delayed0)
 );
 
 IOBUF IOBUF(
-       .I(soc_a7ddrphy_dq_o_nodelay0),
-       .T(soc_a7ddrphy_dq_t0),
+       .I(a7ddrphy_dq_o_nodelay0),
+       .T(a7ddrphy_dq_t0),
        .IO(ddram_dq[0]),
-       .O(soc_a7ddrphy_dq_i_nodelay0)
+       .O(a7ddrphy_dq_i_nodelay0)
 );
 
 OSERDESE2 #(
@@ -18518,20 +15567,20 @@ OSERDESE2 #(
 ) OSERDESE2_31 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[1]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[17]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[1]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[17]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[1]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[17]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[1]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[17]),
+       .D1(a7ddrphy_dfi_p0_wrdata[1]),
+       .D2(a7ddrphy_dfi_p0_wrdata[17]),
+       .D3(a7ddrphy_dfi_p1_wrdata[1]),
+       .D4(a7ddrphy_dfi_p1_wrdata[17]),
+       .D5(a7ddrphy_dfi_p2_wrdata[1]),
+       .D6(a7ddrphy_dfi_p2_wrdata[17]),
+       .D7(a7ddrphy_dfi_p3_wrdata[1]),
+       .D8(a7ddrphy_dfi_p3_wrdata[17]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay1),
-       .TQ(soc_a7ddrphy_dq_t1)
+       .OQ(a7ddrphy_dq_o_nodelay1),
+       .TQ(a7ddrphy_dq_t1)
 );
 
 ISERDESE2 #(
@@ -18547,16 +15596,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed1),
+       .DDLY(a7ddrphy_dq_i_delayed1),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data1[7]),
-       .Q2(soc_a7ddrphy_dq_i_data1[6]),
-       .Q3(soc_a7ddrphy_dq_i_data1[5]),
-       .Q4(soc_a7ddrphy_dq_i_data1[4]),
-       .Q5(soc_a7ddrphy_dq_i_data1[3]),
-       .Q6(soc_a7ddrphy_dq_i_data1[2]),
-       .Q7(soc_a7ddrphy_dq_i_data1[1]),
-       .Q8(soc_a7ddrphy_dq_i_data1[0])
+       .Q1(a7ddrphy_dq_i_data1[7]),
+       .Q2(a7ddrphy_dq_i_data1[6]),
+       .Q3(a7ddrphy_dq_i_data1[5]),
+       .Q4(a7ddrphy_dq_i_data1[4]),
+       .Q5(a7ddrphy_dq_i_data1[3]),
+       .Q6(a7ddrphy_dq_i_data1[2]),
+       .Q7(a7ddrphy_dq_i_data1[1]),
+       .Q8(a7ddrphy_dq_i_data1[0])
 );
 
 IDELAYE2 #(
@@ -18570,19 +15619,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_3 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay1),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay1),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed1)
+       .DATAOUT(a7ddrphy_dq_i_delayed1)
 );
 
 IOBUF IOBUF_1(
-       .I(soc_a7ddrphy_dq_o_nodelay1),
-       .T(soc_a7ddrphy_dq_t1),
+       .I(a7ddrphy_dq_o_nodelay1),
+       .T(a7ddrphy_dq_t1),
        .IO(ddram_dq[1]),
-       .O(soc_a7ddrphy_dq_i_nodelay1)
+       .O(a7ddrphy_dq_i_nodelay1)
 );
 
 OSERDESE2 #(
@@ -18594,20 +15643,20 @@ OSERDESE2 #(
 ) OSERDESE2_32 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[2]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[18]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[2]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[18]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[2]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[18]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[2]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[18]),
+       .D1(a7ddrphy_dfi_p0_wrdata[2]),
+       .D2(a7ddrphy_dfi_p0_wrdata[18]),
+       .D3(a7ddrphy_dfi_p1_wrdata[2]),
+       .D4(a7ddrphy_dfi_p1_wrdata[18]),
+       .D5(a7ddrphy_dfi_p2_wrdata[2]),
+       .D6(a7ddrphy_dfi_p2_wrdata[18]),
+       .D7(a7ddrphy_dfi_p3_wrdata[2]),
+       .D8(a7ddrphy_dfi_p3_wrdata[18]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay2),
-       .TQ(soc_a7ddrphy_dq_t2)
+       .OQ(a7ddrphy_dq_o_nodelay2),
+       .TQ(a7ddrphy_dq_t2)
 );
 
 ISERDESE2 #(
@@ -18623,16 +15672,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed2),
+       .DDLY(a7ddrphy_dq_i_delayed2),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data2[7]),
-       .Q2(soc_a7ddrphy_dq_i_data2[6]),
-       .Q3(soc_a7ddrphy_dq_i_data2[5]),
-       .Q4(soc_a7ddrphy_dq_i_data2[4]),
-       .Q5(soc_a7ddrphy_dq_i_data2[3]),
-       .Q6(soc_a7ddrphy_dq_i_data2[2]),
-       .Q7(soc_a7ddrphy_dq_i_data2[1]),
-       .Q8(soc_a7ddrphy_dq_i_data2[0])
+       .Q1(a7ddrphy_dq_i_data2[7]),
+       .Q2(a7ddrphy_dq_i_data2[6]),
+       .Q3(a7ddrphy_dq_i_data2[5]),
+       .Q4(a7ddrphy_dq_i_data2[4]),
+       .Q5(a7ddrphy_dq_i_data2[3]),
+       .Q6(a7ddrphy_dq_i_data2[2]),
+       .Q7(a7ddrphy_dq_i_data2[1]),
+       .Q8(a7ddrphy_dq_i_data2[0])
 );
 
 IDELAYE2 #(
@@ -18646,19 +15695,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_4 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay2),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay2),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed2)
+       .DATAOUT(a7ddrphy_dq_i_delayed2)
 );
 
 IOBUF IOBUF_2(
-       .I(soc_a7ddrphy_dq_o_nodelay2),
-       .T(soc_a7ddrphy_dq_t2),
+       .I(a7ddrphy_dq_o_nodelay2),
+       .T(a7ddrphy_dq_t2),
        .IO(ddram_dq[2]),
-       .O(soc_a7ddrphy_dq_i_nodelay2)
+       .O(a7ddrphy_dq_i_nodelay2)
 );
 
 OSERDESE2 #(
@@ -18670,20 +15719,20 @@ OSERDESE2 #(
 ) OSERDESE2_33 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[3]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[19]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[3]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[19]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[3]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[19]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[3]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[19]),
+       .D1(a7ddrphy_dfi_p0_wrdata[3]),
+       .D2(a7ddrphy_dfi_p0_wrdata[19]),
+       .D3(a7ddrphy_dfi_p1_wrdata[3]),
+       .D4(a7ddrphy_dfi_p1_wrdata[19]),
+       .D5(a7ddrphy_dfi_p2_wrdata[3]),
+       .D6(a7ddrphy_dfi_p2_wrdata[19]),
+       .D7(a7ddrphy_dfi_p3_wrdata[3]),
+       .D8(a7ddrphy_dfi_p3_wrdata[19]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay3),
-       .TQ(soc_a7ddrphy_dq_t3)
+       .OQ(a7ddrphy_dq_o_nodelay3),
+       .TQ(a7ddrphy_dq_t3)
 );
 
 ISERDESE2 #(
@@ -18699,16 +15748,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed3),
+       .DDLY(a7ddrphy_dq_i_delayed3),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data3[7]),
-       .Q2(soc_a7ddrphy_dq_i_data3[6]),
-       .Q3(soc_a7ddrphy_dq_i_data3[5]),
-       .Q4(soc_a7ddrphy_dq_i_data3[4]),
-       .Q5(soc_a7ddrphy_dq_i_data3[3]),
-       .Q6(soc_a7ddrphy_dq_i_data3[2]),
-       .Q7(soc_a7ddrphy_dq_i_data3[1]),
-       .Q8(soc_a7ddrphy_dq_i_data3[0])
+       .Q1(a7ddrphy_dq_i_data3[7]),
+       .Q2(a7ddrphy_dq_i_data3[6]),
+       .Q3(a7ddrphy_dq_i_data3[5]),
+       .Q4(a7ddrphy_dq_i_data3[4]),
+       .Q5(a7ddrphy_dq_i_data3[3]),
+       .Q6(a7ddrphy_dq_i_data3[2]),
+       .Q7(a7ddrphy_dq_i_data3[1]),
+       .Q8(a7ddrphy_dq_i_data3[0])
 );
 
 IDELAYE2 #(
@@ -18722,19 +15771,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_5 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay3),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay3),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed3)
+       .DATAOUT(a7ddrphy_dq_i_delayed3)
 );
 
 IOBUF IOBUF_3(
-       .I(soc_a7ddrphy_dq_o_nodelay3),
-       .T(soc_a7ddrphy_dq_t3),
+       .I(a7ddrphy_dq_o_nodelay3),
+       .T(a7ddrphy_dq_t3),
        .IO(ddram_dq[3]),
-       .O(soc_a7ddrphy_dq_i_nodelay3)
+       .O(a7ddrphy_dq_i_nodelay3)
 );
 
 OSERDESE2 #(
@@ -18746,20 +15795,20 @@ OSERDESE2 #(
 ) OSERDESE2_34 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[4]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[20]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[4]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[20]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[4]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[20]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[4]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[20]),
+       .D1(a7ddrphy_dfi_p0_wrdata[4]),
+       .D2(a7ddrphy_dfi_p0_wrdata[20]),
+       .D3(a7ddrphy_dfi_p1_wrdata[4]),
+       .D4(a7ddrphy_dfi_p1_wrdata[20]),
+       .D5(a7ddrphy_dfi_p2_wrdata[4]),
+       .D6(a7ddrphy_dfi_p2_wrdata[20]),
+       .D7(a7ddrphy_dfi_p3_wrdata[4]),
+       .D8(a7ddrphy_dfi_p3_wrdata[20]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay4),
-       .TQ(soc_a7ddrphy_dq_t4)
+       .OQ(a7ddrphy_dq_o_nodelay4),
+       .TQ(a7ddrphy_dq_t4)
 );
 
 ISERDESE2 #(
@@ -18775,16 +15824,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed4),
+       .DDLY(a7ddrphy_dq_i_delayed4),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data4[7]),
-       .Q2(soc_a7ddrphy_dq_i_data4[6]),
-       .Q3(soc_a7ddrphy_dq_i_data4[5]),
-       .Q4(soc_a7ddrphy_dq_i_data4[4]),
-       .Q5(soc_a7ddrphy_dq_i_data4[3]),
-       .Q6(soc_a7ddrphy_dq_i_data4[2]),
-       .Q7(soc_a7ddrphy_dq_i_data4[1]),
-       .Q8(soc_a7ddrphy_dq_i_data4[0])
+       .Q1(a7ddrphy_dq_i_data4[7]),
+       .Q2(a7ddrphy_dq_i_data4[6]),
+       .Q3(a7ddrphy_dq_i_data4[5]),
+       .Q4(a7ddrphy_dq_i_data4[4]),
+       .Q5(a7ddrphy_dq_i_data4[3]),
+       .Q6(a7ddrphy_dq_i_data4[2]),
+       .Q7(a7ddrphy_dq_i_data4[1]),
+       .Q8(a7ddrphy_dq_i_data4[0])
 );
 
 IDELAYE2 #(
@@ -18798,19 +15847,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_6 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay4),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay4),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed4)
+       .DATAOUT(a7ddrphy_dq_i_delayed4)
 );
 
 IOBUF IOBUF_4(
-       .I(soc_a7ddrphy_dq_o_nodelay4),
-       .T(soc_a7ddrphy_dq_t4),
+       .I(a7ddrphy_dq_o_nodelay4),
+       .T(a7ddrphy_dq_t4),
        .IO(ddram_dq[4]),
-       .O(soc_a7ddrphy_dq_i_nodelay4)
+       .O(a7ddrphy_dq_i_nodelay4)
 );
 
 OSERDESE2 #(
@@ -18822,20 +15871,20 @@ OSERDESE2 #(
 ) OSERDESE2_35 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[5]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[21]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[5]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[21]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[5]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[21]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[5]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[21]),
+       .D1(a7ddrphy_dfi_p0_wrdata[5]),
+       .D2(a7ddrphy_dfi_p0_wrdata[21]),
+       .D3(a7ddrphy_dfi_p1_wrdata[5]),
+       .D4(a7ddrphy_dfi_p1_wrdata[21]),
+       .D5(a7ddrphy_dfi_p2_wrdata[5]),
+       .D6(a7ddrphy_dfi_p2_wrdata[21]),
+       .D7(a7ddrphy_dfi_p3_wrdata[5]),
+       .D8(a7ddrphy_dfi_p3_wrdata[21]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay5),
-       .TQ(soc_a7ddrphy_dq_t5)
+       .OQ(a7ddrphy_dq_o_nodelay5),
+       .TQ(a7ddrphy_dq_t5)
 );
 
 ISERDESE2 #(
@@ -18851,16 +15900,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed5),
+       .DDLY(a7ddrphy_dq_i_delayed5),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data5[7]),
-       .Q2(soc_a7ddrphy_dq_i_data5[6]),
-       .Q3(soc_a7ddrphy_dq_i_data5[5]),
-       .Q4(soc_a7ddrphy_dq_i_data5[4]),
-       .Q5(soc_a7ddrphy_dq_i_data5[3]),
-       .Q6(soc_a7ddrphy_dq_i_data5[2]),
-       .Q7(soc_a7ddrphy_dq_i_data5[1]),
-       .Q8(soc_a7ddrphy_dq_i_data5[0])
+       .Q1(a7ddrphy_dq_i_data5[7]),
+       .Q2(a7ddrphy_dq_i_data5[6]),
+       .Q3(a7ddrphy_dq_i_data5[5]),
+       .Q4(a7ddrphy_dq_i_data5[4]),
+       .Q5(a7ddrphy_dq_i_data5[3]),
+       .Q6(a7ddrphy_dq_i_data5[2]),
+       .Q7(a7ddrphy_dq_i_data5[1]),
+       .Q8(a7ddrphy_dq_i_data5[0])
 );
 
 IDELAYE2 #(
@@ -18874,19 +15923,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_7 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay5),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay5),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed5)
+       .DATAOUT(a7ddrphy_dq_i_delayed5)
 );
 
 IOBUF IOBUF_5(
-       .I(soc_a7ddrphy_dq_o_nodelay5),
-       .T(soc_a7ddrphy_dq_t5),
+       .I(a7ddrphy_dq_o_nodelay5),
+       .T(a7ddrphy_dq_t5),
        .IO(ddram_dq[5]),
-       .O(soc_a7ddrphy_dq_i_nodelay5)
+       .O(a7ddrphy_dq_i_nodelay5)
 );
 
 OSERDESE2 #(
@@ -18898,20 +15947,20 @@ OSERDESE2 #(
 ) OSERDESE2_36 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[6]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[22]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[6]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[22]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[6]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[22]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[6]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[22]),
+       .D1(a7ddrphy_dfi_p0_wrdata[6]),
+       .D2(a7ddrphy_dfi_p0_wrdata[22]),
+       .D3(a7ddrphy_dfi_p1_wrdata[6]),
+       .D4(a7ddrphy_dfi_p1_wrdata[22]),
+       .D5(a7ddrphy_dfi_p2_wrdata[6]),
+       .D6(a7ddrphy_dfi_p2_wrdata[22]),
+       .D7(a7ddrphy_dfi_p3_wrdata[6]),
+       .D8(a7ddrphy_dfi_p3_wrdata[22]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay6),
-       .TQ(soc_a7ddrphy_dq_t6)
+       .OQ(a7ddrphy_dq_o_nodelay6),
+       .TQ(a7ddrphy_dq_t6)
 );
 
 ISERDESE2 #(
@@ -18927,16 +15976,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed6),
+       .DDLY(a7ddrphy_dq_i_delayed6),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data6[7]),
-       .Q2(soc_a7ddrphy_dq_i_data6[6]),
-       .Q3(soc_a7ddrphy_dq_i_data6[5]),
-       .Q4(soc_a7ddrphy_dq_i_data6[4]),
-       .Q5(soc_a7ddrphy_dq_i_data6[3]),
-       .Q6(soc_a7ddrphy_dq_i_data6[2]),
-       .Q7(soc_a7ddrphy_dq_i_data6[1]),
-       .Q8(soc_a7ddrphy_dq_i_data6[0])
+       .Q1(a7ddrphy_dq_i_data6[7]),
+       .Q2(a7ddrphy_dq_i_data6[6]),
+       .Q3(a7ddrphy_dq_i_data6[5]),
+       .Q4(a7ddrphy_dq_i_data6[4]),
+       .Q5(a7ddrphy_dq_i_data6[3]),
+       .Q6(a7ddrphy_dq_i_data6[2]),
+       .Q7(a7ddrphy_dq_i_data6[1]),
+       .Q8(a7ddrphy_dq_i_data6[0])
 );
 
 IDELAYE2 #(
@@ -18950,19 +15999,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_8 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay6),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay6),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed6)
+       .DATAOUT(a7ddrphy_dq_i_delayed6)
 );
 
 IOBUF IOBUF_6(
-       .I(soc_a7ddrphy_dq_o_nodelay6),
-       .T(soc_a7ddrphy_dq_t6),
+       .I(a7ddrphy_dq_o_nodelay6),
+       .T(a7ddrphy_dq_t6),
        .IO(ddram_dq[6]),
-       .O(soc_a7ddrphy_dq_i_nodelay6)
+       .O(a7ddrphy_dq_i_nodelay6)
 );
 
 OSERDESE2 #(
@@ -18974,20 +16023,20 @@ OSERDESE2 #(
 ) OSERDESE2_37 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[7]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[23]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[7]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[23]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[7]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[23]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[7]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[23]),
+       .D1(a7ddrphy_dfi_p0_wrdata[7]),
+       .D2(a7ddrphy_dfi_p0_wrdata[23]),
+       .D3(a7ddrphy_dfi_p1_wrdata[7]),
+       .D4(a7ddrphy_dfi_p1_wrdata[23]),
+       .D5(a7ddrphy_dfi_p2_wrdata[7]),
+       .D6(a7ddrphy_dfi_p2_wrdata[23]),
+       .D7(a7ddrphy_dfi_p3_wrdata[7]),
+       .D8(a7ddrphy_dfi_p3_wrdata[23]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay7),
-       .TQ(soc_a7ddrphy_dq_t7)
+       .OQ(a7ddrphy_dq_o_nodelay7),
+       .TQ(a7ddrphy_dq_t7)
 );
 
 ISERDESE2 #(
@@ -19003,16 +16052,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed7),
+       .DDLY(a7ddrphy_dq_i_delayed7),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data7[7]),
-       .Q2(soc_a7ddrphy_dq_i_data7[6]),
-       .Q3(soc_a7ddrphy_dq_i_data7[5]),
-       .Q4(soc_a7ddrphy_dq_i_data7[4]),
-       .Q5(soc_a7ddrphy_dq_i_data7[3]),
-       .Q6(soc_a7ddrphy_dq_i_data7[2]),
-       .Q7(soc_a7ddrphy_dq_i_data7[1]),
-       .Q8(soc_a7ddrphy_dq_i_data7[0])
+       .Q1(a7ddrphy_dq_i_data7[7]),
+       .Q2(a7ddrphy_dq_i_data7[6]),
+       .Q3(a7ddrphy_dq_i_data7[5]),
+       .Q4(a7ddrphy_dq_i_data7[4]),
+       .Q5(a7ddrphy_dq_i_data7[3]),
+       .Q6(a7ddrphy_dq_i_data7[2]),
+       .Q7(a7ddrphy_dq_i_data7[1]),
+       .Q8(a7ddrphy_dq_i_data7[0])
 );
 
 IDELAYE2 #(
@@ -19026,19 +16075,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_9 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay7),
+       .CE((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay7),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[0] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed7)
+       .DATAOUT(a7ddrphy_dq_i_delayed7)
 );
 
 IOBUF IOBUF_7(
-       .I(soc_a7ddrphy_dq_o_nodelay7),
-       .T(soc_a7ddrphy_dq_t7),
+       .I(a7ddrphy_dq_o_nodelay7),
+       .T(a7ddrphy_dq_t7),
        .IO(ddram_dq[7]),
-       .O(soc_a7ddrphy_dq_i_nodelay7)
+       .O(a7ddrphy_dq_i_nodelay7)
 );
 
 OSERDESE2 #(
@@ -19050,20 +16099,20 @@ OSERDESE2 #(
 ) OSERDESE2_38 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[8]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[24]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[8]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[24]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[8]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[24]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[8]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[24]),
+       .D1(a7ddrphy_dfi_p0_wrdata[8]),
+       .D2(a7ddrphy_dfi_p0_wrdata[24]),
+       .D3(a7ddrphy_dfi_p1_wrdata[8]),
+       .D4(a7ddrphy_dfi_p1_wrdata[24]),
+       .D5(a7ddrphy_dfi_p2_wrdata[8]),
+       .D6(a7ddrphy_dfi_p2_wrdata[24]),
+       .D7(a7ddrphy_dfi_p3_wrdata[8]),
+       .D8(a7ddrphy_dfi_p3_wrdata[24]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay8),
-       .TQ(soc_a7ddrphy_dq_t8)
+       .OQ(a7ddrphy_dq_o_nodelay8),
+       .TQ(a7ddrphy_dq_t8)
 );
 
 ISERDESE2 #(
@@ -19079,16 +16128,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed8),
+       .DDLY(a7ddrphy_dq_i_delayed8),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data8[7]),
-       .Q2(soc_a7ddrphy_dq_i_data8[6]),
-       .Q3(soc_a7ddrphy_dq_i_data8[5]),
-       .Q4(soc_a7ddrphy_dq_i_data8[4]),
-       .Q5(soc_a7ddrphy_dq_i_data8[3]),
-       .Q6(soc_a7ddrphy_dq_i_data8[2]),
-       .Q7(soc_a7ddrphy_dq_i_data8[1]),
-       .Q8(soc_a7ddrphy_dq_i_data8[0])
+       .Q1(a7ddrphy_dq_i_data8[7]),
+       .Q2(a7ddrphy_dq_i_data8[6]),
+       .Q3(a7ddrphy_dq_i_data8[5]),
+       .Q4(a7ddrphy_dq_i_data8[4]),
+       .Q5(a7ddrphy_dq_i_data8[3]),
+       .Q6(a7ddrphy_dq_i_data8[2]),
+       .Q7(a7ddrphy_dq_i_data8[1]),
+       .Q8(a7ddrphy_dq_i_data8[0])
 );
 
 IDELAYE2 #(
@@ -19102,19 +16151,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_10 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay8),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay8),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed8)
+       .DATAOUT(a7ddrphy_dq_i_delayed8)
 );
 
 IOBUF IOBUF_8(
-       .I(soc_a7ddrphy_dq_o_nodelay8),
-       .T(soc_a7ddrphy_dq_t8),
+       .I(a7ddrphy_dq_o_nodelay8),
+       .T(a7ddrphy_dq_t8),
        .IO(ddram_dq[8]),
-       .O(soc_a7ddrphy_dq_i_nodelay8)
+       .O(a7ddrphy_dq_i_nodelay8)
 );
 
 OSERDESE2 #(
@@ -19126,20 +16175,20 @@ OSERDESE2 #(
 ) OSERDESE2_39 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[9]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[25]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[9]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[25]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[9]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[25]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[9]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[25]),
+       .D1(a7ddrphy_dfi_p0_wrdata[9]),
+       .D2(a7ddrphy_dfi_p0_wrdata[25]),
+       .D3(a7ddrphy_dfi_p1_wrdata[9]),
+       .D4(a7ddrphy_dfi_p1_wrdata[25]),
+       .D5(a7ddrphy_dfi_p2_wrdata[9]),
+       .D6(a7ddrphy_dfi_p2_wrdata[25]),
+       .D7(a7ddrphy_dfi_p3_wrdata[9]),
+       .D8(a7ddrphy_dfi_p3_wrdata[25]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay9),
-       .TQ(soc_a7ddrphy_dq_t9)
+       .OQ(a7ddrphy_dq_o_nodelay9),
+       .TQ(a7ddrphy_dq_t9)
 );
 
 ISERDESE2 #(
@@ -19155,16 +16204,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed9),
+       .DDLY(a7ddrphy_dq_i_delayed9),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data9[7]),
-       .Q2(soc_a7ddrphy_dq_i_data9[6]),
-       .Q3(soc_a7ddrphy_dq_i_data9[5]),
-       .Q4(soc_a7ddrphy_dq_i_data9[4]),
-       .Q5(soc_a7ddrphy_dq_i_data9[3]),
-       .Q6(soc_a7ddrphy_dq_i_data9[2]),
-       .Q7(soc_a7ddrphy_dq_i_data9[1]),
-       .Q8(soc_a7ddrphy_dq_i_data9[0])
+       .Q1(a7ddrphy_dq_i_data9[7]),
+       .Q2(a7ddrphy_dq_i_data9[6]),
+       .Q3(a7ddrphy_dq_i_data9[5]),
+       .Q4(a7ddrphy_dq_i_data9[4]),
+       .Q5(a7ddrphy_dq_i_data9[3]),
+       .Q6(a7ddrphy_dq_i_data9[2]),
+       .Q7(a7ddrphy_dq_i_data9[1]),
+       .Q8(a7ddrphy_dq_i_data9[0])
 );
 
 IDELAYE2 #(
@@ -19178,19 +16227,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_11 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay9),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay9),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed9)
+       .DATAOUT(a7ddrphy_dq_i_delayed9)
 );
 
 IOBUF IOBUF_9(
-       .I(soc_a7ddrphy_dq_o_nodelay9),
-       .T(soc_a7ddrphy_dq_t9),
+       .I(a7ddrphy_dq_o_nodelay9),
+       .T(a7ddrphy_dq_t9),
        .IO(ddram_dq[9]),
-       .O(soc_a7ddrphy_dq_i_nodelay9)
+       .O(a7ddrphy_dq_i_nodelay9)
 );
 
 OSERDESE2 #(
@@ -19202,20 +16251,20 @@ OSERDESE2 #(
 ) OSERDESE2_40 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[10]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[26]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[10]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[26]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[10]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[26]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[10]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[26]),
+       .D1(a7ddrphy_dfi_p0_wrdata[10]),
+       .D2(a7ddrphy_dfi_p0_wrdata[26]),
+       .D3(a7ddrphy_dfi_p1_wrdata[10]),
+       .D4(a7ddrphy_dfi_p1_wrdata[26]),
+       .D5(a7ddrphy_dfi_p2_wrdata[10]),
+       .D6(a7ddrphy_dfi_p2_wrdata[26]),
+       .D7(a7ddrphy_dfi_p3_wrdata[10]),
+       .D8(a7ddrphy_dfi_p3_wrdata[26]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay10),
-       .TQ(soc_a7ddrphy_dq_t10)
+       .OQ(a7ddrphy_dq_o_nodelay10),
+       .TQ(a7ddrphy_dq_t10)
 );
 
 ISERDESE2 #(
@@ -19231,16 +16280,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed10),
+       .DDLY(a7ddrphy_dq_i_delayed10),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data10[7]),
-       .Q2(soc_a7ddrphy_dq_i_data10[6]),
-       .Q3(soc_a7ddrphy_dq_i_data10[5]),
-       .Q4(soc_a7ddrphy_dq_i_data10[4]),
-       .Q5(soc_a7ddrphy_dq_i_data10[3]),
-       .Q6(soc_a7ddrphy_dq_i_data10[2]),
-       .Q7(soc_a7ddrphy_dq_i_data10[1]),
-       .Q8(soc_a7ddrphy_dq_i_data10[0])
+       .Q1(a7ddrphy_dq_i_data10[7]),
+       .Q2(a7ddrphy_dq_i_data10[6]),
+       .Q3(a7ddrphy_dq_i_data10[5]),
+       .Q4(a7ddrphy_dq_i_data10[4]),
+       .Q5(a7ddrphy_dq_i_data10[3]),
+       .Q6(a7ddrphy_dq_i_data10[2]),
+       .Q7(a7ddrphy_dq_i_data10[1]),
+       .Q8(a7ddrphy_dq_i_data10[0])
 );
 
 IDELAYE2 #(
@@ -19254,19 +16303,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_12 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay10),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay10),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed10)
+       .DATAOUT(a7ddrphy_dq_i_delayed10)
 );
 
 IOBUF IOBUF_10(
-       .I(soc_a7ddrphy_dq_o_nodelay10),
-       .T(soc_a7ddrphy_dq_t10),
+       .I(a7ddrphy_dq_o_nodelay10),
+       .T(a7ddrphy_dq_t10),
        .IO(ddram_dq[10]),
-       .O(soc_a7ddrphy_dq_i_nodelay10)
+       .O(a7ddrphy_dq_i_nodelay10)
 );
 
 OSERDESE2 #(
@@ -19278,20 +16327,20 @@ OSERDESE2 #(
 ) OSERDESE2_41 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[11]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[27]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[11]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[27]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[11]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[27]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[11]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[27]),
+       .D1(a7ddrphy_dfi_p0_wrdata[11]),
+       .D2(a7ddrphy_dfi_p0_wrdata[27]),
+       .D3(a7ddrphy_dfi_p1_wrdata[11]),
+       .D4(a7ddrphy_dfi_p1_wrdata[27]),
+       .D5(a7ddrphy_dfi_p2_wrdata[11]),
+       .D6(a7ddrphy_dfi_p2_wrdata[27]),
+       .D7(a7ddrphy_dfi_p3_wrdata[11]),
+       .D8(a7ddrphy_dfi_p3_wrdata[27]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay11),
-       .TQ(soc_a7ddrphy_dq_t11)
+       .OQ(a7ddrphy_dq_o_nodelay11),
+       .TQ(a7ddrphy_dq_t11)
 );
 
 ISERDESE2 #(
@@ -19307,16 +16356,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed11),
+       .DDLY(a7ddrphy_dq_i_delayed11),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data11[7]),
-       .Q2(soc_a7ddrphy_dq_i_data11[6]),
-       .Q3(soc_a7ddrphy_dq_i_data11[5]),
-       .Q4(soc_a7ddrphy_dq_i_data11[4]),
-       .Q5(soc_a7ddrphy_dq_i_data11[3]),
-       .Q6(soc_a7ddrphy_dq_i_data11[2]),
-       .Q7(soc_a7ddrphy_dq_i_data11[1]),
-       .Q8(soc_a7ddrphy_dq_i_data11[0])
+       .Q1(a7ddrphy_dq_i_data11[7]),
+       .Q2(a7ddrphy_dq_i_data11[6]),
+       .Q3(a7ddrphy_dq_i_data11[5]),
+       .Q4(a7ddrphy_dq_i_data11[4]),
+       .Q5(a7ddrphy_dq_i_data11[3]),
+       .Q6(a7ddrphy_dq_i_data11[2]),
+       .Q7(a7ddrphy_dq_i_data11[1]),
+       .Q8(a7ddrphy_dq_i_data11[0])
 );
 
 IDELAYE2 #(
@@ -19330,19 +16379,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_13 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay11),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay11),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed11)
+       .DATAOUT(a7ddrphy_dq_i_delayed11)
 );
 
 IOBUF IOBUF_11(
-       .I(soc_a7ddrphy_dq_o_nodelay11),
-       .T(soc_a7ddrphy_dq_t11),
+       .I(a7ddrphy_dq_o_nodelay11),
+       .T(a7ddrphy_dq_t11),
        .IO(ddram_dq[11]),
-       .O(soc_a7ddrphy_dq_i_nodelay11)
+       .O(a7ddrphy_dq_i_nodelay11)
 );
 
 OSERDESE2 #(
@@ -19354,20 +16403,20 @@ OSERDESE2 #(
 ) OSERDESE2_42 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[12]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[28]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[12]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[28]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[12]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[28]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[12]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[28]),
+       .D1(a7ddrphy_dfi_p0_wrdata[12]),
+       .D2(a7ddrphy_dfi_p0_wrdata[28]),
+       .D3(a7ddrphy_dfi_p1_wrdata[12]),
+       .D4(a7ddrphy_dfi_p1_wrdata[28]),
+       .D5(a7ddrphy_dfi_p2_wrdata[12]),
+       .D6(a7ddrphy_dfi_p2_wrdata[28]),
+       .D7(a7ddrphy_dfi_p3_wrdata[12]),
+       .D8(a7ddrphy_dfi_p3_wrdata[28]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay12),
-       .TQ(soc_a7ddrphy_dq_t12)
+       .OQ(a7ddrphy_dq_o_nodelay12),
+       .TQ(a7ddrphy_dq_t12)
 );
 
 ISERDESE2 #(
@@ -19383,16 +16432,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed12),
+       .DDLY(a7ddrphy_dq_i_delayed12),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data12[7]),
-       .Q2(soc_a7ddrphy_dq_i_data12[6]),
-       .Q3(soc_a7ddrphy_dq_i_data12[5]),
-       .Q4(soc_a7ddrphy_dq_i_data12[4]),
-       .Q5(soc_a7ddrphy_dq_i_data12[3]),
-       .Q6(soc_a7ddrphy_dq_i_data12[2]),
-       .Q7(soc_a7ddrphy_dq_i_data12[1]),
-       .Q8(soc_a7ddrphy_dq_i_data12[0])
+       .Q1(a7ddrphy_dq_i_data12[7]),
+       .Q2(a7ddrphy_dq_i_data12[6]),
+       .Q3(a7ddrphy_dq_i_data12[5]),
+       .Q4(a7ddrphy_dq_i_data12[4]),
+       .Q5(a7ddrphy_dq_i_data12[3]),
+       .Q6(a7ddrphy_dq_i_data12[2]),
+       .Q7(a7ddrphy_dq_i_data12[1]),
+       .Q8(a7ddrphy_dq_i_data12[0])
 );
 
 IDELAYE2 #(
@@ -19406,19 +16455,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_14 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay12),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay12),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed12)
+       .DATAOUT(a7ddrphy_dq_i_delayed12)
 );
 
 IOBUF IOBUF_12(
-       .I(soc_a7ddrphy_dq_o_nodelay12),
-       .T(soc_a7ddrphy_dq_t12),
+       .I(a7ddrphy_dq_o_nodelay12),
+       .T(a7ddrphy_dq_t12),
        .IO(ddram_dq[12]),
-       .O(soc_a7ddrphy_dq_i_nodelay12)
+       .O(a7ddrphy_dq_i_nodelay12)
 );
 
 OSERDESE2 #(
@@ -19430,20 +16479,20 @@ OSERDESE2 #(
 ) OSERDESE2_43 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[13]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[29]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[13]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[29]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[13]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[29]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[13]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[29]),
+       .D1(a7ddrphy_dfi_p0_wrdata[13]),
+       .D2(a7ddrphy_dfi_p0_wrdata[29]),
+       .D3(a7ddrphy_dfi_p1_wrdata[13]),
+       .D4(a7ddrphy_dfi_p1_wrdata[29]),
+       .D5(a7ddrphy_dfi_p2_wrdata[13]),
+       .D6(a7ddrphy_dfi_p2_wrdata[29]),
+       .D7(a7ddrphy_dfi_p3_wrdata[13]),
+       .D8(a7ddrphy_dfi_p3_wrdata[29]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay13),
-       .TQ(soc_a7ddrphy_dq_t13)
+       .OQ(a7ddrphy_dq_o_nodelay13),
+       .TQ(a7ddrphy_dq_t13)
 );
 
 ISERDESE2 #(
@@ -19459,16 +16508,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed13),
+       .DDLY(a7ddrphy_dq_i_delayed13),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data13[7]),
-       .Q2(soc_a7ddrphy_dq_i_data13[6]),
-       .Q3(soc_a7ddrphy_dq_i_data13[5]),
-       .Q4(soc_a7ddrphy_dq_i_data13[4]),
-       .Q5(soc_a7ddrphy_dq_i_data13[3]),
-       .Q6(soc_a7ddrphy_dq_i_data13[2]),
-       .Q7(soc_a7ddrphy_dq_i_data13[1]),
-       .Q8(soc_a7ddrphy_dq_i_data13[0])
+       .Q1(a7ddrphy_dq_i_data13[7]),
+       .Q2(a7ddrphy_dq_i_data13[6]),
+       .Q3(a7ddrphy_dq_i_data13[5]),
+       .Q4(a7ddrphy_dq_i_data13[4]),
+       .Q5(a7ddrphy_dq_i_data13[3]),
+       .Q6(a7ddrphy_dq_i_data13[2]),
+       .Q7(a7ddrphy_dq_i_data13[1]),
+       .Q8(a7ddrphy_dq_i_data13[0])
 );
 
 IDELAYE2 #(
@@ -19482,19 +16531,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_15 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay13),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay13),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed13)
+       .DATAOUT(a7ddrphy_dq_i_delayed13)
 );
 
 IOBUF IOBUF_13(
-       .I(soc_a7ddrphy_dq_o_nodelay13),
-       .T(soc_a7ddrphy_dq_t13),
+       .I(a7ddrphy_dq_o_nodelay13),
+       .T(a7ddrphy_dq_t13),
        .IO(ddram_dq[13]),
-       .O(soc_a7ddrphy_dq_i_nodelay13)
+       .O(a7ddrphy_dq_i_nodelay13)
 );
 
 OSERDESE2 #(
@@ -19506,20 +16555,20 @@ OSERDESE2 #(
 ) OSERDESE2_44 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[14]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[30]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[14]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[30]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[14]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[30]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[14]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[30]),
+       .D1(a7ddrphy_dfi_p0_wrdata[14]),
+       .D2(a7ddrphy_dfi_p0_wrdata[30]),
+       .D3(a7ddrphy_dfi_p1_wrdata[14]),
+       .D4(a7ddrphy_dfi_p1_wrdata[30]),
+       .D5(a7ddrphy_dfi_p2_wrdata[14]),
+       .D6(a7ddrphy_dfi_p2_wrdata[30]),
+       .D7(a7ddrphy_dfi_p3_wrdata[14]),
+       .D8(a7ddrphy_dfi_p3_wrdata[30]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay14),
-       .TQ(soc_a7ddrphy_dq_t14)
+       .OQ(a7ddrphy_dq_o_nodelay14),
+       .TQ(a7ddrphy_dq_t14)
 );
 
 ISERDESE2 #(
@@ -19535,16 +16584,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed14),
+       .DDLY(a7ddrphy_dq_i_delayed14),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data14[7]),
-       .Q2(soc_a7ddrphy_dq_i_data14[6]),
-       .Q3(soc_a7ddrphy_dq_i_data14[5]),
-       .Q4(soc_a7ddrphy_dq_i_data14[4]),
-       .Q5(soc_a7ddrphy_dq_i_data14[3]),
-       .Q6(soc_a7ddrphy_dq_i_data14[2]),
-       .Q7(soc_a7ddrphy_dq_i_data14[1]),
-       .Q8(soc_a7ddrphy_dq_i_data14[0])
+       .Q1(a7ddrphy_dq_i_data14[7]),
+       .Q2(a7ddrphy_dq_i_data14[6]),
+       .Q3(a7ddrphy_dq_i_data14[5]),
+       .Q4(a7ddrphy_dq_i_data14[4]),
+       .Q5(a7ddrphy_dq_i_data14[3]),
+       .Q6(a7ddrphy_dq_i_data14[2]),
+       .Q7(a7ddrphy_dq_i_data14[1]),
+       .Q8(a7ddrphy_dq_i_data14[0])
 );
 
 IDELAYE2 #(
@@ -19558,19 +16607,19 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_16 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay14),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay14),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed14)
+       .DATAOUT(a7ddrphy_dq_i_delayed14)
 );
 
 IOBUF IOBUF_14(
-       .I(soc_a7ddrphy_dq_o_nodelay14),
-       .T(soc_a7ddrphy_dq_t14),
+       .I(a7ddrphy_dq_o_nodelay14),
+       .T(a7ddrphy_dq_t14),
        .IO(ddram_dq[14]),
-       .O(soc_a7ddrphy_dq_i_nodelay14)
+       .O(a7ddrphy_dq_i_nodelay14)
 );
 
 OSERDESE2 #(
@@ -19582,20 +16631,20 @@ OSERDESE2 #(
 ) OSERDESE2_45 (
        .CLK(sys4x_clk),
        .CLKDIV(sys_clk),
-       .D1(soc_a7ddrphy_dfi_p0_wrdata[15]),
-       .D2(soc_a7ddrphy_dfi_p0_wrdata[31]),
-       .D3(soc_a7ddrphy_dfi_p1_wrdata[15]),
-       .D4(soc_a7ddrphy_dfi_p1_wrdata[31]),
-       .D5(soc_a7ddrphy_dfi_p2_wrdata[15]),
-       .D6(soc_a7ddrphy_dfi_p2_wrdata[31]),
-       .D7(soc_a7ddrphy_dfi_p3_wrdata[15]),
-       .D8(soc_a7ddrphy_dfi_p3_wrdata[31]),
+       .D1(a7ddrphy_dfi_p0_wrdata[15]),
+       .D2(a7ddrphy_dfi_p0_wrdata[31]),
+       .D3(a7ddrphy_dfi_p1_wrdata[15]),
+       .D4(a7ddrphy_dfi_p1_wrdata[31]),
+       .D5(a7ddrphy_dfi_p2_wrdata[15]),
+       .D6(a7ddrphy_dfi_p2_wrdata[31]),
+       .D7(a7ddrphy_dfi_p3_wrdata[15]),
+       .D8(a7ddrphy_dfi_p3_wrdata[31]),
        .OCE(1'd1),
        .RST(sys_rst),
-       .T1((~soc_a7ddrphy_dq_oe_delayed)),
+       .T1((~a7ddrphy_dq_oe_delayed)),
        .TCE(1'd1),
-       .OQ(soc_a7ddrphy_dq_o_nodelay15),
-       .TQ(soc_a7ddrphy_dq_t15)
+       .OQ(a7ddrphy_dq_o_nodelay15),
+       .TQ(a7ddrphy_dq_t15)
 );
 
 ISERDESE2 #(
@@ -19611,16 +16660,16 @@ ISERDESE2 #(
        .CLK(sys4x_clk),
        .CLKB((~sys4x_clk)),
        .CLKDIV(sys_clk),
-       .DDLY(soc_a7ddrphy_dq_i_delayed15),
+       .DDLY(a7ddrphy_dq_i_delayed15),
        .RST(sys_rst),
-       .Q1(soc_a7ddrphy_dq_i_data15[7]),
-       .Q2(soc_a7ddrphy_dq_i_data15[6]),
-       .Q3(soc_a7ddrphy_dq_i_data15[5]),
-       .Q4(soc_a7ddrphy_dq_i_data15[4]),
-       .Q5(soc_a7ddrphy_dq_i_data15[3]),
-       .Q6(soc_a7ddrphy_dq_i_data15[2]),
-       .Q7(soc_a7ddrphy_dq_i_data15[1]),
-       .Q8(soc_a7ddrphy_dq_i_data15[0])
+       .Q1(a7ddrphy_dq_i_data15[7]),
+       .Q2(a7ddrphy_dq_i_data15[6]),
+       .Q3(a7ddrphy_dq_i_data15[5]),
+       .Q4(a7ddrphy_dq_i_data15[4]),
+       .Q5(a7ddrphy_dq_i_data15[3]),
+       .Q6(a7ddrphy_dq_i_data15[2]),
+       .Q7(a7ddrphy_dq_i_data15[1]),
+       .Q8(a7ddrphy_dq_i_data15[0])
 );
 
 IDELAYE2 #(
@@ -19634,163 +16683,132 @@ IDELAYE2 #(
        .SIGNAL_PATTERN("DATA")
 ) IDELAYE2_17 (
        .C(sys_clk),
-       .CE((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_inc_re)),
-       .IDATAIN(soc_a7ddrphy_dq_i_nodelay15),
+       .CE((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_inc_re)),
+       .IDATAIN(a7ddrphy_dq_i_nodelay15),
        .INC(1'd1),
-       .LD((soc_a7ddrphy_dly_sel_storage[1] & soc_a7ddrphy_rdly_dq_rst_re)),
+       .LD((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_rst_re)),
        .LDPIPEEN(1'd0),
-       .DATAOUT(soc_a7ddrphy_dq_i_delayed15)
+       .DATAOUT(a7ddrphy_dq_i_delayed15)
 );
 
 IOBUF IOBUF_15(
-       .I(soc_a7ddrphy_dq_o_nodelay15),
-       .T(soc_a7ddrphy_dq_t15),
+       .I(a7ddrphy_dq_o_nodelay15),
+       .T(a7ddrphy_dq_t15),
        .IO(ddram_dq[15]),
-       .O(soc_a7ddrphy_dq_i_nodelay15)
+       .O(a7ddrphy_dq_i_nodelay15)
 );
 
-reg [24:0] storage_2[0:15];
-reg [24:0] memdat_5;
+reg [24:0] storage[0:15];
+reg [24:0] memdat;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we)
-               storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_5 <= storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
+               storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
+       memdat <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
-assign soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = memdat;
+assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
 
-reg [24:0] storage_3[0:15];
-reg [24:0] memdat_6;
+reg [24:0] storage_1[0:15];
+reg [24:0] memdat_1;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we)
-               storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_6 <= storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
+               storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_1 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
-assign soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = memdat_1;
+assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
 
-reg [24:0] storage_4[0:15];
-reg [24:0] memdat_7;
+reg [24:0] storage_2[0:15];
+reg [24:0] memdat_2;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we)
-               storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_7 <= storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
+               storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_2 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
-assign soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = memdat_2;
+assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
 
-reg [24:0] storage_5[0:15];
-reg [24:0] memdat_8;
+reg [24:0] storage_3[0:15];
+reg [24:0] memdat_3;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we)
-               storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_8 <= storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
+               storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_3 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_8;
-assign soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = memdat_3;
+assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
 
-reg [24:0] storage_6[0:15];
-reg [24:0] memdat_9;
+reg [24:0] storage_4[0:15];
+reg [24:0] memdat_4;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_we)
-               storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_9 <= storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
+               storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_4 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_9;
-assign soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_sdram_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = memdat_4;
+assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
 
-reg [24:0] storage_7[0:15];
-reg [24:0] memdat_10;
+reg [24:0] storage_5[0:15];
+reg [24:0] memdat_5;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_we)
-               storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_10 <= storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
+               storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_5 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_10;
-assign soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_sdram_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = memdat_5;
+assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
 
-reg [24:0] storage_8[0:15];
-reg [24:0] memdat_11;
+reg [24:0] storage_6[0:15];
+reg [24:0] memdat_6;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_we)
-               storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_11 <= storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
+               storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_6 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_11;
-assign soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_8[soc_sdram_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = memdat_6;
+assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
 
-reg [24:0] storage_9[0:15];
-reg [24:0] memdat_12;
+reg [24:0] storage_7[0:15];
+reg [24:0] memdat_7;
 always @(posedge sys_clk) begin
-       if (soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_we)
-               storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-       memdat_12 <= storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+       if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
+               storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
+       memdat_7 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
 end
 
 always @(posedge sys_clk) begin
 end
 
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_12;
-assign soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_9[soc_sdram_bankmachine7_cmd_buffer_lookahead_rdport_adr];
-
-VexRiscv VexRiscv(
-       .clk(sys_clk),
-       .dBusWishbone_ACK(soc_litedramcore_cpu_dbus_ack),
-       .dBusWishbone_DAT_MISO(soc_litedramcore_cpu_dbus_dat_r),
-       .dBusWishbone_ERR(soc_litedramcore_cpu_dbus_err),
-       .externalInterruptArray(soc_litedramcore_cpu_interrupt),
-       .externalResetVector(soc_litedramcore_vexriscv),
-       .iBusWishbone_ACK(soc_litedramcore_cpu_ibus_ack),
-       .iBusWishbone_DAT_MISO(soc_litedramcore_cpu_ibus_dat_r),
-       .iBusWishbone_ERR(soc_litedramcore_cpu_ibus_err),
-       .reset((sys_rst | soc_litedramcore_cpu_reset)),
-       .softwareInterrupt(1'd0),
-       .timerInterrupt(1'd0),
-       .dBusWishbone_ADR(soc_litedramcore_cpu_dbus_adr),
-       .dBusWishbone_BTE(soc_litedramcore_cpu_dbus_bte),
-       .dBusWishbone_CTI(soc_litedramcore_cpu_dbus_cti),
-       .dBusWishbone_CYC(soc_litedramcore_cpu_dbus_cyc),
-       .dBusWishbone_DAT_MOSI(soc_litedramcore_cpu_dbus_dat_w),
-       .dBusWishbone_SEL(soc_litedramcore_cpu_dbus_sel),
-       .dBusWishbone_STB(soc_litedramcore_cpu_dbus_stb),
-       .dBusWishbone_WE(soc_litedramcore_cpu_dbus_we),
-       .iBusWishbone_ADR(soc_litedramcore_cpu_ibus_adr),
-       .iBusWishbone_BTE(soc_litedramcore_cpu_ibus_bte),
-       .iBusWishbone_CTI(soc_litedramcore_cpu_ibus_cti),
-       .iBusWishbone_CYC(soc_litedramcore_cpu_ibus_cyc),
-       .iBusWishbone_DAT_MOSI(soc_litedramcore_cpu_ibus_dat_w),
-       .iBusWishbone_SEL(soc_litedramcore_cpu_ibus_sel),
-       .iBusWishbone_STB(soc_litedramcore_cpu_ibus_stb),
-       .iBusWishbone_WE(soc_litedramcore_cpu_ibus_we)
-);
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = memdat_7;
+assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
 
 PLLE2_ADV #(
        .CLKFBOUT_MULT(5'd16),
@@ -19805,14 +16823,14 @@ PLLE2_ADV #(
        .REF_JITTER1(0.01),
        .STARTUP_WAIT("FALSE")
 ) PLLE2_ADV (
-       .CLKFBIN(vns_pll_fb0),
-       .CLKIN1(soc_s7pll0_clkin),
-       .RST(soc_sys_pll_reset),
-       .CLKFBOUT(vns_pll_fb0),
-       .CLKOUT0(soc_s7pll0_clkout0),
-       .CLKOUT1(soc_s7pll0_clkout1),
-       .CLKOUT2(soc_s7pll0_clkout2),
-       .LOCKED(soc_sys_pll_locked)
+       .CLKFBIN(pll_fb0),
+       .CLKIN1(s7pll0_clkin),
+       .RST(sys_pll_reset),
+       .CLKFBOUT(pll_fb0),
+       .CLKOUT0(s7pll0_clkout0),
+       .CLKOUT1(s7pll0_clkout1),
+       .CLKOUT2(s7pll0_clkout2),
+       .LOCKED(sys_pll_locked)
 );
 
 PLLE2_ADV #(
@@ -19824,12 +16842,12 @@ PLLE2_ADV #(
        .REF_JITTER1(0.01),
        .STARTUP_WAIT("FALSE")
 ) PLLE2_ADV_1 (
-       .CLKFBIN(vns_pll_fb1),
-       .CLKIN1(soc_s7pll1_clkin),
-       .RST(soc_iodelay_pll_reset),
-       .CLKFBOUT(vns_pll_fb1),
-       .CLKOUT0(soc_s7pll1_clkout),
-       .LOCKED(soc_iodelay_pll_locked)
+       .CLKFBIN(pll_fb1),
+       .CLKIN1(s7pll1_clkin),
+       .RST(iodelay_pll_reset),
+       .CLKFBOUT(pll_fb1),
+       .CLKOUT0(s7pll1_clkout),
+       .LOCKED(iodelay_pll_locked)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -19838,8 +16856,8 @@ PLLE2_ADV #(
        .C(sys_clk),
        .CE(1'd1),
        .D(1'd0),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl0),
-       .Q(vns_xilinxasyncresetsynchronizerimpl0_rst_meta)
+       .PRE(xilinxasyncresetsynchronizerimpl0),
+       .Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -19847,8 +16865,8 @@ PLLE2_ADV #(
 ) FDPE_1 (
        .C(sys_clk),
        .CE(1'd1),
-       .D(vns_xilinxasyncresetsynchronizerimpl0_rst_meta),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl0),
+       .D(xilinxasyncresetsynchronizerimpl0_rst_meta),
+       .PRE(xilinxasyncresetsynchronizerimpl0),
        .Q(sys_rst)
 );
 
@@ -19858,8 +16876,8 @@ PLLE2_ADV #(
        .C(sys4x_clk),
        .CE(1'd1),
        .D(1'd0),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl1),
-       .Q(vns_xilinxasyncresetsynchronizerimpl1_rst_meta)
+       .PRE(xilinxasyncresetsynchronizerimpl1),
+       .Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -19867,9 +16885,9 @@ PLLE2_ADV #(
 ) FDPE_3 (
        .C(sys4x_clk),
        .CE(1'd1),
-       .D(vns_xilinxasyncresetsynchronizerimpl1_rst_meta),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl1),
-       .Q(vns_xilinxasyncresetsynchronizerimpl1_expr)
+       .D(xilinxasyncresetsynchronizerimpl1_rst_meta),
+       .PRE(xilinxasyncresetsynchronizerimpl1),
+       .Q(xilinxasyncresetsynchronizerimpl1_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -19878,8 +16896,8 @@ PLLE2_ADV #(
        .C(sys4x_dqs_clk),
        .CE(1'd1),
        .D(1'd0),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl2),
-       .Q(vns_xilinxasyncresetsynchronizerimpl2_rst_meta)
+       .PRE(xilinxasyncresetsynchronizerimpl2),
+       .Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -19887,9 +16905,9 @@ PLLE2_ADV #(
 ) FDPE_5 (
        .C(sys4x_dqs_clk),
        .CE(1'd1),
-       .D(vns_xilinxasyncresetsynchronizerimpl2_rst_meta),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl2),
-       .Q(vns_xilinxasyncresetsynchronizerimpl2_expr)
+       .D(xilinxasyncresetsynchronizerimpl2_rst_meta),
+       .PRE(xilinxasyncresetsynchronizerimpl2),
+       .Q(xilinxasyncresetsynchronizerimpl2_expr)
 );
 
 (* ars_ff1 = "true", async_reg = "true" *) FDPE #(
@@ -19898,8 +16916,8 @@ PLLE2_ADV #(
        .C(iodelay_clk),
        .CE(1'd1),
        .D(1'd0),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl3),
-       .Q(vns_xilinxasyncresetsynchronizerimpl3_rst_meta)
+       .PRE(xilinxasyncresetsynchronizerimpl3),
+       .Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
 );
 
 (* ars_ff2 = "true", async_reg = "true" *) FDPE #(
@@ -19907,8 +16925,8 @@ PLLE2_ADV #(
 ) FDPE_7 (
        .C(iodelay_clk),
        .CE(1'd1),
-       .D(vns_xilinxasyncresetsynchronizerimpl3_rst_meta),
-       .PRE(vns_xilinxasyncresetsynchronizerimpl3),
+       .D(xilinxasyncresetsynchronizerimpl3_rst_meta),
+       .PRE(xilinxasyncresetsynchronizerimpl3),
        .Q(iodelay_rst)
 );
 

diff --git a/soc.vhdl b/soc.vhdl
index db52db3408335ada16134eccb4642f44d6b6d163..a8ae3c9e9a883f85dc13ca5e440c980eea9f7d2c 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -17,6 +17,7 @@ use work.wishbone_types.all;
 -- 0xc0000000: SYSCON
 -- 0xc0002000: UART0
 -- 0xc0004000: XICS ICP
+-- 0xc0100000: DRAM CSRs
 -- 0xf0000000: Block RAM (aliased & repeated)
 -- 0xffff0000: DRAM init code (if any)