x86: implements emms instruction

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 711be0bd58c469d0ccca09c5fe23b6b82aa3c494..294509df3c20238854dea9ef5e3d0a1280a3b9d5 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -604,7 +604,7 @@
                         0x4: Inst::PCMPEQB(Pq,Qq);
                         0x5: Inst::PCMPEQW(Pq,Qq);
                         0x6: Inst::PCMPEQD(Pq,Qq);
-                        0x7: WarnUnimpl::emms();
+                        0x7: Inst::EMMS();
                     }
                     // repe (0xF3)
                     0x4: decode OPCODE_OP_BOTTOM3 {

diff --git a/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py b/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py
index 3b2252a302f09a3445c6fa3e625a04bc85e5a0df..7f666ab7d8b1f1add10fdf7b1fb8efb27508b104 100644 (file)
--- a/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py
+++ b/src/arch/x86/isa/insts/simd64/integer/exit_media_state.py
@@ -36,6 +36,9 @@
 # Authors: Gabe Black
 
 microcode = '''
-# EMMS
+def macroop EMMS {
+    emms
+};
+
 # FEMMS
 '''

diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index b1fdfb54c46cf5d291d5181ee4e3f138a50b50c2..3ceaf9b28dd90bc1d0ee30c05afa037c3a6aaecf 100644 (file)
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -212,6 +212,7 @@ let {{
 
     assembler.symbols["fsw"] = readFpReg("FSW")
     assembler.symbols["fcw"] = readFpReg("FCW")
+    assembler.symbols["ftw"] = readFpReg("FTW")
 
     macroopDict = assembler.assemble(microcode)
 

diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index 7178f1f52528e3c9ae0277feff6c37f5fb06e527..20e09507eaeff42bc2fb837714a7624dcca4c13e 100644 (file)
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -1502,4 +1502,10 @@ let {{
             else if(arg1 == arg2)
                 ccFlagBits = ccFlagBits | ZFBit;
         '''
+
+    class Emms(MediaOp):
+        def __init__(self):
+            super(Emms, self).__init__('InstRegIndex(MISCREG_FTW)',
+                    'InstRegIndex(0)', 'InstRegIndex(0)', 0)
+        code = 'FTW = 0xFFFF;'
 }};

diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index bc6d1886cb959826a8ff2cc6a32bcfcead137aa5..b3607417b67495d570fad1d9b4d94fe910fcd525 100644 (file)
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -162,6 +162,7 @@ def operands {{
         # Registers related to the state of x87 floating point unit.
         'TOP':           controlReg('MISCREG_X87_TOP', 66, ctype='ub'),
         'FSW':           controlReg('MISCREG_FSW', 67, ctype='uw'),
+        'FTW':           controlReg('MISCREG_FTW', 68, ctype='uw'),
 
         # The segment base as used by memory instructions.
         'SegBase':       controlReg('MISCREG_SEG_EFF_BASE(segment)', 70),