sim: bfin: se_all32bitopcodes: skip debug insns under the sim

Since the sim has a few fake debug insns that the hardware does not, we
need to check for those before attempting to run them.  Otherwise we'll
randomly trigger the sim debug asserts/aborts/halts insns.  On the
hardware, these are proper invalid insns, and the table catches that.

diff --git a/sim/testsuite/sim/bfin/ChangeLog b/sim/testsuite/sim/bfin/ChangeLog
index 11a307285f0da6eaf9fe02dcaf61c2fe82fd2718..81cedaf5dcdb354785924db7096982e7f2b905d4 100644 (file)
--- a/sim/testsuite/sim/bfin/ChangeLog
+++ b/sim/testsuite/sim/bfin/ChangeLog
@@ -1,3 +1,7 @@
+2013-06-23  Mike Frysinger  <vapier@gentoo.org>
+
+       * se_all32bitopcodes.S (se_all_next_insn): Skip debug insn opcodes.
+
 2013-06-23  Mike Frysinger  <vapier@gentoo.org>
 
        * se_allopcodes.h (_match): Simplify register test to one less insn.

diff --git a/sim/testsuite/sim/bfin/se_all32bitopcodes.S b/sim/testsuite/sim/bfin/se_all32bitopcodes.S
index f8664e6d9b4942448a7afeefbbbd8e8043c8714c..6ffe6d1c5cfc5437c9ad7546984435003955b967 100644 (file)
--- a/sim/testsuite/sim/bfin/se_all32bitopcodes.S
+++ b/sim/testsuite/sim/bfin/se_all32bitopcodes.S
@@ -64,6 +64,19 @@
        R0 = R0 + R1;
 1:
 
+.ifndef BFIN_JTAG
+       /* Skip debug insns when running in the sim.  */
+       R1.L = 0xff00;
+       R1.H = 0x0000;
+       R2 = R0 & R1;
+       R1.L = 0xf000;
+       CC = R1 == R2;
+       IF !CC jump 1f (bp);
+       R0.L = 0xf100;
+       R0.H = 0x0000;
+1:
+.endif
+
        [P5] = R0;
 .endm
 
@@ -34164,7 +34177,7 @@
        .dw 0x0000, 0xe5c0,     0xffff, 0xe5ff,         0x21, 0
        .dw 0x0000, 0xe6c0,     0xffff, 0xe6ff,         0x21, 0
        .dw 0x0000, 0xe740,     0xffff, 0xe7ff,         0x21, 0
-       .dw 0x0000, 0xf001, 0xffff, 0xffff,             0x21, 0
+       .dw 0x0000, 0xf001,     0xffff, 0xffff,         0x21, 0
        .dw 0x0000, 0x0000,     0x0000, 0x0000,         0x00, 0
 .endm