i965: Disable register spilling on Ivybridge for now.

The data port messages for this are rather different.  For now, fail to
compile rather than hanging the GPU.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 1e2cf9171163034e01663be7e431c78954676156..f88b131677559390c9381d3d53f131196fd85c4f 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -244,6 +244,8 @@ fs_visitor::assign_regs()
 
       if (reg == -1) {
         fail("no register to spill\n");
+      } else if (intel->gen >= 7) {
+        fail("no spilling support on gen7 yet\n");
       } else if (c->dispatch_width == 16) {
         fail("no spilling support on 16-wide yet\n");
       } else {